Semiconductor structure and method of forming the same, method of measuring overlay error

Abstract

A semiconductor structure and a method for forming the same, and a method for measuring overlay error, the structure comprising: a wafer to be measured, the wafer to be measured comprising a measurement region; a first measurement mark located in the measurement region, the first measurement mark comprising first strip structures extending along a first direction and being opposite to each other, and second strip structures extending along a second direction and being opposite to each other, the first direction being perpendicular to the second direction, and the first strip structures opposite to each other and the second strip structures opposite to each other forming a shape of a rectangle; and a second measurement mark located in the measurement region, the second measurement mark surrounding the first measurement mark, the second measurement mark forming a shape of a rectangle, and a height difference being present between a top of the second measurement mark and a top of the first measurement mark. The precision of the overlay error monitoring of the first layer pattern of the wafer is improved, and the product yield of the wafer is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and its formation method, and a method for measuring overlay errors. Background Technology

[0002] Overlay error is a critical parameter in the photolithography process. It describes the relative positional deviation between the current layer (photoresist pattern) and the reference layer (substrate pattern) in a multilayer photolithography process. Ideally, these two patterns should perfectly overlap, but in reality, due to systematic and random errors, their positions deviate, resulting in overlay error. In integrated circuit manufacturing, overlay error is a key indicator for monitoring the quality of the photolithography process, affecting the reliable connection of circuits.

[0003] To ensure accurate overlay between process layers, signal alignment is performed first during photolithography. However, the first layer of the wafer lacks reference coordinates and cannot be aligned directly; it can only be positioned using wafer notches. The accuracy of this process depends entirely on the performance of the photolithography machine, and there is a risk of misalignment. Misalignment in the first layer will affect the overlay accuracy of subsequent layers, increase the difficulty of the process, and in severe cases, lead to the scrapping of the entire product.

[0004] Currently, the accuracy of overlay error monitoring for the first layer of wafers still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and its formation method, and a method for measuring overlay error, which is beneficial to improving the accuracy of monitoring the overlay error of the first layer pattern of the wafer and improving the product yield of the wafer.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure suitable for measuring the overlay error of the first layer pattern of a wafer, comprising: a wafer to be measured, the wafer to be measured including a measurement area; a first measurement mark located in the measurement area, the first measurement mark including a first strip structure extending along a first direction and facing each other and a second strip structure extending along a second direction and facing each other, the first direction being perpendicular to the second direction, and the shape formed by the facing first strip structure and the facing second strip structure being rectangular; and a second measurement mark located in the measurement area, the second measurement mark surrounding the first measurement mark, the shape formed by the second measurement mark being rectangular, and a height difference between the top of the second measurement mark and the top of the first measurement mark.

[0007] Optionally, the first measurement mark includes an opening.

[0008] Optionally, the end of the first strip structure is in contact with the end of the second strip structure; or, the end of the first strip structure is separated from the end of the second strip structure.

[0009] Optionally, the second measurement mark includes a third strip structure extending along the first direction and facing each other, and a fourth strip structure extending along the second direction and facing each other, wherein the end of the third strip structure is in contact with the end of the fourth strip structure.

[0010] Optionally, the distance between the outer boundary of the third strip structure and the first strip structure is between 4 micrometers and 10 micrometers; the distance between the outer boundary of the fourth strip structure and the second strip structure is between 4 micrometers and 10 micrometers.

[0011] Optionally, the semiconductor structure further includes: a first filling layer located in the region enclosed by the first strip structure and the second strip structure facing each other, the top of the first filling layer being flush with the top of the second measurement mark, and the first filling layer and the second measurement mark being an integral structure.

[0012] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, suitable for measuring the overlay error of the first layer pattern of a wafer, comprising: providing a wafer to be tested, the wafer to be tested including a measurement area; forming a first measurement mark in the measurement area, the first measurement mark including a first strip structure extending along a first direction and facing each other and a second strip structure extending along a second direction and facing each other, the first direction being perpendicular to the second direction, and the shape formed by the facing first strip structure and the facing second strip structure being rectangular; forming a second measurement mark surrounding the first measurement mark in the measurement area, the shape formed by the second measurement mark being rectangular, and a height difference between the top of the second measurement mark and the top of the first measurement mark.

[0013] Optionally, the first measurement mark and the second measurement mark are formed in the same step.

[0014] Optionally, the step of forming the first measurement mark and the second measurement mark includes: forming a measurement mark material layer in the measurement area of ​​the first layer of the wafer; performing patterning processing on the measurement mark material layer to form a first opening extending along a first direction and facing each other, and a second opening extending along a second direction and facing each other, wherein the first direction is perpendicular to the second direction, the shape formed by the facing first opening and the facing second opening is rectangular, and the first opening and the second opening are used as the first measurement mark, and the remaining measurement mark material layer surrounding the first measurement mark is used as the second measurement mark.

[0015] Optionally, in the step of forming the first measurement mark and the second measurement mark, the remaining measurement mark material layer located in the area enclosed by the first opening and the second opening facing each other is used as the first filling layer. The top of the first filling layer is flush with the top of the second measurement mark, and the first filling layer and the second measurement mark are an integral structure.

[0016] Optionally, the distance between the outer boundary of the second measurement mark and the first strip structure in the first direction is between 4 micrometers and 10 micrometers; the distance between the outer boundary of the second measurement mark and the second strip structure in the second direction is between 4 micrometers and 10 micrometers.

[0017] Accordingly, embodiments of the present invention also provide a method for measuring overlay error, comprising: providing a semiconductor structure provided in the embodiments of the present invention; obtaining the signal wave center point of the second measurement mark and the signal wave center point of the first measurement mark based on the height difference between the top of the second measurement mark and the top of the first measurement mark; and obtaining the overlay error between the second measurement mark and the first measurement mark based on the signal wave center point of the second measurement mark and the signal wave center point of the first measurement mark.

[0018] Optionally, the step of obtaining the signal wave center point of the second measurement mark and the signal wave center point of the first measurement mark includes: scanning the first measurement mark and the second measurement mark with an electron beam emitted by a scanning electron microscope; obtaining images of the first measurement mark and the second measurement mark after electron beam scanning; and obtaining the signal wave center point of the second measurement mark and the signal wave center point of the first measurement mark based on the images of the first measurement mark and the second measurement mark.

[0019] Optionally, the step of obtaining the overprinting error between the second measurement mark and the first measurement mark based on the signal wave center point of the second measurement mark and the signal wave center point of the first measurement mark includes: establishing an XY coordinate system; determining the coordinates of the signal wave center point of the second measurement mark and the coordinates of the signal wave center point of the first measurement mark in the XY coordinate system; and obtaining the overprinting error between the second measurement mark and the first measurement mark based on the coordinates of the signal wave center point of the second measurement mark and the coordinates of the signal wave center point of the first measurement mark in the XY coordinate system.

[0020] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0021] This invention provides a semiconductor structure suitable for measuring the overlay error of the first layer pattern of a wafer. The wafer under test includes a measurement area, and a first measurement mark is located in the measurement area. The first measurement mark includes a first strip-shaped structure extending along a first direction and facing each other, and a second strip-shaped structure extending along a second direction and facing each other. The first direction and the second direction are perpendicular, and the shape formed by the facing first strip-shaped structure and the facing second strip-shaped structure is rectangular. A second measurement mark is located in the measurement area and surrounds the first measurement mark. The shape formed by the second measurement mark is also rectangular, and there is a height difference between the top of the second measurement mark and the top of the first measurement mark. Compared with the existing method of judging the first layer pattern of a wafer by visual inspection, this method provides a more comprehensive measurement method. To determine whether an overlay error has occurred, this embodiment of the invention establishes a height difference between the top of the second measurement mark and the top of the first measurement mark. During subsequent measurement of overlay error, when the signal wave passes through the second and first measurement marks, a phase difference is generated due to the different path lengths caused by the height difference. This phase difference allows for the differentiation of the center positions of the signal waves from the second and first measurement marks. Consequently, the overlay error between the second and first measurement marks can be obtained based on the center positions of their respective signal waves, thereby determining whether an overlay error has occurred in the first layer pattern of the wafer. This improves the accuracy of monitoring overlay errors in the first layer pattern of the wafer and increases the product yield of the wafer. Attached Figure Description

[0022] Figures 1 to 2 This is a schematic diagram of a corresponding embodiment of the semiconductor structure of the present invention;

[0023] Figures 3 to 5 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0024] Figure 6 This is a flowchart of the steps corresponding to one embodiment of the method for measuring overlay error of the present invention. Detailed Implementation

[0025] As can be seen from the background technology, the accuracy of overlay error monitoring for the first layer of a wafer still needs to be improved.

[0026] To address the technical problem, this invention provides a semiconductor structure suitable for measuring the overlay error of the first layer pattern of a wafer, comprising: a wafer to be measured, the wafer including a measurement area; a first measurement mark located in the measurement area, the first measurement mark including a first strip structure extending along a first direction and facing each other and a second strip structure extending along a second direction and facing each other, the first direction being perpendicular to the second direction, and the shape formed by the facing first strip structure and the facing second strip structure being rectangular; and a second measurement mark located in the measurement area, the second measurement mark surrounding the first measurement mark, the shape formed by the second measurement mark being rectangular, and a height difference between the top of the second measurement mark and the top of the first measurement mark.

[0027] In the semiconductor structure provided by this invention, there is a height difference between the top of the second measurement mark and the top of the first measurement mark. Compared with the existing method of judging whether there is an overlay error in the first layer pattern of the wafer by visual inspection, this invention creates a height difference between the top of the second measurement mark and the top of the first measurement mark. During the subsequent measurement of overlay error, when the signal wave passes through the second and first measurement marks, a phase difference will be generated due to the different path lengths caused by the height difference. The phase difference can be used to distinguish the center position of the signal wave of the second measurement mark and the center position of the signal wave of the first measurement mark. Therefore, the overlay error between the second and first measurement marks can be obtained based on the center positions of the signal waves of the second and first measurement marks, thereby determining whether there is an overlay error in the first layer pattern of the wafer. This improves the accuracy of monitoring the overlay error of the first layer pattern of the wafer and increases the product yield of the wafer.

[0028] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] Figure 1 To the end Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 1 This is a top view of the wafer under test; Figure 2 yes Figure 1 Enlarged view of reference number 201.

[0030] The semiconductor structure includes: a wafer under test 100, the wafer under test 100 including a measurement region 101; and a first measurement mark 130 located in the measurement region 101, the first measurement mark 130 including a measurement mark along a first direction (e.g., along a first direction). Figure 2 The first strip structure 121 extending and facing each other in the X direction and along the second direction (as shown in the X direction) and the second strip structure 121 extending and facing each other in the X direction ...) and the second strip structure 121 extending and facing each other in the X direction. Figure 2 A second strip structure 120 extending and facing each other (as shown in the Y direction) is perpendicular to the first direction and the second direction, and the shape formed by the first strip structure 121 and the second strip structure 120 facing each other is rectangular; a second measurement mark 150 is located in the measurement area 101, the second measurement mark 150 surrounds the first measurement mark 130, the shape formed by the second measurement mark 150 is rectangular, and there is a height difference between the top of the second measurement mark 150 and the top of the first measurement mark 130.

[0031] Specifically, there is a height difference between the top of the second measurement mark 150 and the top of the first measurement mark 130. During the subsequent measurement of overlay error, when the signal wave passes through the second measurement mark 150 and the first measurement mark 130, a phase difference will be generated due to the different path lengths caused by the height difference. The phase difference can be used to distinguish the center position of the signal wave of the second measurement mark 150 and the center position of the signal wave of the first measurement mark 130. Therefore, the overlay error between the second measurement mark 150 and the first measurement mark 130 can be obtained based on the center positions of the signal waves of the second measurement mark 150 and the first measurement mark 130, thereby determining whether there is an overlay error in the first layer pattern of the wafer. This improves the accuracy of monitoring the overlay error of the first layer pattern of the wafer and improves the product yield of the wafer.

[0032] It should be noted that in the semiconductor structure formation process, multiple stacked patterns are formed on the wafer. The overlay error of the first layer pattern will affect the overlay accuracy of subsequent stacked layers and affect the product yield of the wafer. Therefore, it is extremely important to measure the overlay error of the first layer pattern.

[0033] Specifically, the wafer to be tested 100 is used as a wafer for subsequent measurement of overlay error.

[0034] In this embodiment, the wafer to be tested 100 includes a measurement area 101.

[0035] Specifically, the measurement area 101 is the area where the first measurement mark 130 and the second measurement mark 150 are set.

[0036] As an example, the measurement region 101 is typically located in the dicing channel of the wafer 100 under test. In other embodiments, the measurement region 101 is also located in the effective chip region of the wafer 100 under test.

[0037] It should be noted that setting the first measurement mark 130 facilitates the subsequent acquisition of the signal wave center point of the first measurement mark 130.

[0038] In this embodiment, the first measurement mark 130 includes a first strip structure 121 extending along a first direction and facing each other, and a second strip structure 120 extending along a second direction and facing each other. The first direction is perpendicular to the second direction, and the shape formed by the first strip structure 121 and the second strip structure 120 facing each other is rectangular.

[0039] Specifically, by setting up a first strip structure 121 and a second strip structure 120 that are directly opposite each other, the influence of system errors and environmental interference can be effectively eliminated during the acquisition of the center point of the signal wave, thereby improving the accuracy of the measurement results.

[0040] It should be noted that the first strip structure 121 extends along the first direction, and the second strip structure 120 extends along the second direction. The first direction and the second direction are perpendicular to each other. In the subsequent measurement of overlay error, the offset of the first measurement mark 130 and the second measurement mark 150 in the first direction and the offset of the first measurement mark 130 and the second measurement mark 150 in the second direction can be obtained.

[0041] In this embodiment, the first measurement mark 130 includes an opening.

[0042] It should be noted that the bottom of the opening exposes the top of the solid film layer. Since the second measurement mark 150 surrounds the first measurement mark 130, there is a height difference between the top of the second measurement mark 150 and the top of the first measurement mark 130. That is, there is a height difference between the top of the second measurement mark 150 and the top of the solid film layer exposed at the bottom of the opening. When the signal wave passes through the second measurement mark 150 and the first measurement mark 130, a phase difference will be generated due to the different path lengths caused by the height difference. The center position of the signal wave of the second measurement mark 150 and the center position of the signal wave of the first measurement mark 130 can be distinguished by the phase difference.

[0043] In this embodiment, the end of the first strip structure 121 is separated from the end of the second strip structure 120.

[0044] Specifically, the end of the first strip structure 121 is separated from the end of the second strip structure 120. In the process of forming the first strip structure 121 and the second strip structure 120, the process difficulty of forming the first strip structure 121 and the second strip structure 120 is reduced, and the risk of over-etching of the end of the first strip structure 121 and the end of the second strip structure 120 in their extension direction is avoided, thereby reducing the impact on the waveform accuracy of the signal wave.

[0045] In other embodiments, the end of the first strip structure 121 is in contact with the end of the second strip structure 120.

[0046] It should be noted that by setting the second measurement mark 150, it is convenient to obtain the center point of the signal wave of the second measurement mark 150. Furthermore, by utilizing the height difference between the top of the second measurement mark 150 and the top of the first measurement mark 130, during the subsequent measurement of overlay error, when the signal wave passes through the second measurement mark 150 and the first measurement mark 130, a phase difference will be generated due to the different path lengths caused by the height difference. The phase difference can be used to distinguish the center position of the signal wave of the second measurement mark 150 and the center position of the signal wave of the first measurement mark 130. Thus, the overlay error between the second measurement mark 150 and the first measurement mark 130 can be obtained based on the center positions of the signal waves of the second measurement mark 150 and the first measurement mark 130.

[0047] In this embodiment, the second measurement mark 150 includes a third strip structure 151 extending along the first direction and facing each other, and a fourth strip structure 152 extending along the second direction and facing each other, wherein the end of the third strip structure 151 is in contact with the end of the fourth strip structure 152.

[0048] It should be noted that the third strip structure 151 extends along the first direction and the fourth strip structure 152 extends along the second direction. The first direction is perpendicular to the second direction. In the subsequent measurement of overlay error, the offset of the third measurement mark and the fourth measurement mark in the first direction and the offset of the third measurement mark and the fourth measurement mark in the second direction can be obtained.

[0049] It should also be noted that the distance between the outer boundary of the third strip structure 151 and the first strip structure 121 should not be too large or too small. If the distance between the outer boundary of the third strip structure 151 and the first strip structure 121 is too large, given a fixed area of ​​the wafer 100 under test, the area around the measurement area 101 will easily become smaller, resulting in a smaller effective chip formation area, thus affecting the wafer formation quality. If the distance between the outer boundary of the third strip structure 151 and the first strip structure 121 is too small, during the subsequent acquisition of the signal wave center point of the first measurement mark 130 and the signal wave center point of the second measurement mark 150, the probability of mutual interference between the signal waves passing through the first measurement mark 130 and the signal waves passing through the second measurement mark 150 will increase, thereby reducing the accuracy of acquiring the signal wave center point of the first measurement mark 130 and the signal wave center point of the second measurement mark 150, and thus affecting the wafer product yield. Therefore, in this embodiment, the distance between the outer boundary of the third strip structure 151 and the first strip structure 121 is between 4 micrometers and 10 micrometers.

[0050] Specifically, the distance between the outer boundary of the fourth strip structure 152 and the second strip structure 120 should not be too large or too small. If the distance between the outer boundary of the fourth strip structure 152 and the second strip structure 120 is too large, given a fixed area of ​​the wafer 100 under test, the area around the measurement area 101 will easily become smaller, resulting in a smaller effective chip formation area, thus affecting the wafer formation quality. If the distance between the outer boundary of the fourth strip structure 152 and the second strip structure 120 is too small, during the subsequent acquisition of the signal wave center point position of the first measurement mark 130 and the signal wave center position of the second measurement mark 150, the probability of mutual interference between the signal waves passing through the first measurement mark 130 and the signal waves passing through the second measurement mark 150 will increase, thereby reducing the accuracy of acquiring the signal wave center point of the first measurement mark 130 and the signal wave center of the second measurement mark 150, and thus affecting the wafer product yield. Therefore, in this embodiment, the distance between the outer boundary of the fourth strip structure 152 and the second strip structure 120 is between 4 micrometers and 10 micrometers.

[0051] In this embodiment, the semiconductor structure further includes a first filling layer 199 located in the area enclosed by the first strip structure 121 and the second strip structure 120 facing each other. The top of the first filling layer 199 is flush with the top of the second measurement mark 150, and the first filling layer 199 and the second measurement mark 150 are an integral structure.

[0052] Specifically, the top of the first filling layer 199 is flush with the top of the second measurement mark 150, and the first filling layer 199 and the second measurement mark 150 are an integral structure, so that the first filling layer 199 fills the area enclosed by the first strip structure 121 and the opposite second strip structure 120, so that the waveform of the signal wave passing through the first filling layer 199 is close to the waveform passing through the top surface of the second measurement mark 150, and can be distinguished from the waveform passing through the first measurement mark 130, thereby accurately obtaining the center point of the signal wave of the first measurement mark 130.

[0053] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure. Wherein, Figures 3 to 5 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0054] refer to Figure 3 A wafer 200 to be tested is provided, the wafer 200 to be tested including a measurement area 201.

[0055] It should be noted that in the semiconductor structure formation process, multiple stacked patterns are formed on the wafer. The overlay error of the first layer pattern will affect the overlay accuracy of subsequent stacked layers and affect the product yield of the wafer. Therefore, it is extremely important to measure the overlay error of the first layer pattern.

[0056] Specifically, the wafer under test 200 is used as a wafer for subsequent measurement of overlay error.

[0057] In this embodiment, the wafer to be tested 200 includes a measurement area 201.

[0058] Specifically, measurement area 201 is the area where the first measurement mark and the second measurement mark are subsequently formed.

[0059] As an example, the measurement region 201 is typically located in the dicing channel of the wafer 200 under test. In other embodiments, the measurement region 201 is also located in the effective chip region of the wafer 200 under test.

[0060] refer to Figures 4 to 5 ,in, Figure 4 Tie Figure 3 Enlarged top view of citation number 201 Figure 5 Tie Figure 4 A cross-sectional view along the AA direction. A first measurement mark 230 is formed in the measurement area 201, the first measurement mark 230 including measurements along a first direction (e.g., ...). Figure 4 The first strip structure 297 extending and facing each other in the X direction and along the second direction (as shown in the X direction) and the second strip structure 297 extending and facing each other in the X direction ...) and the second strip structure 297 extending and facing each other in the X direction. Figure 4A second strip structure 296 extending and facing each other (as shown in the Y direction) is perpendicular to the first direction and the second direction, and the shape formed by the first strip structure 297 and the second strip structure 296 facing each other is rectangular; a second measurement mark 250 is formed around the first measurement mark 230 in the measurement area 201, the shape formed by the second measurement mark 250 is rectangular, and there is a height difference between the top of the second measurement mark 250 and the top of the first measurement mark 230.

[0061] It should be noted that there is a height difference between the top of the second measurement mark 250 and the top of the first measurement mark 230. Compared with the existing method of judging whether there is an overlay error in the first layer pattern of the wafer by visual inspection, the embodiment of the present invention, by creating a height difference between the top of the second measurement mark 250 and the top of the first measurement mark 230, will generate a phase difference when the signal wave passes through the second measurement mark 250 and the first measurement mark 230 due to the different path lengths caused by the height difference. The phase difference can be used to distinguish the center position of the signal wave of the second measurement mark 250 and the center position of the signal wave of the first measurement mark 230. Therefore, the overlay error between the second measurement mark 250 and the first measurement mark 230 can be obtained based on the center positions of the signal waves of the second measurement mark 250 and the first measurement mark 230, thereby judging whether there is an overlay error in the first layer pattern of the wafer. This improves the accuracy of monitoring the overlay error of the first layer pattern of the wafer and improves the product yield of the wafer.

[0062] In this embodiment, the first measurement mark 230 and the second measurement mark 250 are formed in the same step.

[0063] Specifically, the first measurement mark 230 and the second measurement mark 250 are formed in the same step, reducing the number of process steps and lowering process costs.

[0064] In this embodiment, the steps of forming the first measurement mark 230 and the second measurement mark 250 include: forming a measurement mark material layer 298 in the measurement region 201 of the first layer of the wafer; performing patterning processing on the measurement mark material layer 298 to form a first opening 221 extending along a first direction and facing each other, and a second opening 220 extending along a second direction and facing each other, wherein the first direction is perpendicular to the second direction, and the shape formed by the facing first opening 221 and the facing second opening 220 is rectangular, and the first opening 221 and the second opening 220 are used as the first measurement mark 230, and the remaining measurement mark material layer 298 surrounding the first measurement mark 230 is used as the second measurement mark 250.

[0065] Specifically, by setting a first opening 221 and a second opening 220 that are directly opposite each other, the influence of system errors and environmental interference can be effectively eliminated during the acquisition of the center point of the signal wave, thereby improving the accuracy of the measurement results.

[0066] It should be noted that the first opening 221 extends along the first direction, and the second opening 220 extends along the second direction. The first direction and the second direction are perpendicular to each other. In the subsequent measurement of overlay error, the offset of the first measurement mark 230 and the second measurement mark 250 in the first direction and the offset of the first measurement mark 230 and the second measurement mark 250 in the second direction can be obtained.

[0067] In this embodiment, the first opening 221 and the second opening 220 serve as the first measurement mark 230.

[0068] It should be noted that the bottom of the first opening 221 and the second opening 220 exposes the top of the solid film layer (i.e., the measurement mark material layer 298). Since the second measurement mark 250 surrounds the first measurement mark 230, there is a height difference between the top of the second measurement mark 250 and the top of the first measurement mark 230. That is, there is a height difference between the top of the second measurement mark 250 and the top of the solid film layer exposed at the bottom of the first opening 221 and the second opening 220. When the signal wave passes through the second measurement mark 250 and the first measurement mark 230, a phase difference will be generated due to the different path lengths caused by the height difference. The center position of the signal wave of the second measurement mark 250 and the center position of the signal wave of the first measurement mark 230 can be distinguished by the phase difference.

[0069] In this embodiment, in the step of forming the first measurement mark 230 and the second measurement mark 250, the remaining measurement mark material layer 298 located in the area enclosed by the first opening 221 and the second opening 220 facing each other is used as the first filling layer 299. The top of the first filling layer 299 is flush with the top of the second measurement mark 250, and the first filling layer 299 and the second measurement mark 250 are an integral structure.

[0070] Specifically, the top of the first filling layer 299 is flush with the top of the second measurement mark 250, and the first filling layer 299 and the second measurement mark 250 are an integral structure, so that the first filling layer 299 fills the area enclosed by the first strip structure 297 and the opposite second strip structure 296, so that the waveform of the signal wave passing through the first filling layer 299 is close to the waveform passing through the top surface of the second measurement mark 250, and can be distinguished from the waveform passing through the first measurement mark 230, thereby accurately obtaining the center point of the signal wave of the first measurement mark 230.

[0071] It should be noted that the distance between the outer boundary of the second measurement mark 250 and the first strip structure 297 in the first direction should not be too large or too small. If the distance between the outer boundary of the second measurement mark 250 and the first strip structure 297 in the first direction is too large, given a fixed area of ​​the wafer under test 200, the area around the measurement area 201 will easily become smaller, resulting in a smaller effective chip formation area, thus affecting the wafer formation quality. If the distance between the outer boundary of the second measurement mark 250 and the first strip structure 297 in the first direction is too small, during the subsequent acquisition of the signal wave center point positions of the first measurement mark 230 and the second measurement mark 250, the probability of mutual interference between the signal waves passing through the first measurement mark 230 and the second measurement mark 250 will increase, thereby reducing the accuracy of acquiring the signal wave center points of the first measurement mark 230 and the second measurement mark 250, and consequently affecting the wafer product yield. Therefore, in this embodiment, the distance between the outer boundary of the second measurement mark 250 and the first strip structure 297 in the first direction is between 4 micrometers and 10 micrometers.

[0072] It should also be noted that the distance between the outer boundary of the second measurement mark 250 and the second strip structure 296 in the second direction should not be too large or too small. If the distance between the outer boundary of the second measurement mark 250 and the second strip structure 296 in the second direction is too large, given a fixed area of ​​the wafer under test 200, it can easily lead to a smaller area around the measurement area 201, which in turn leads to a smaller effective chip formation area, thus affecting the wafer formation quality. If the distance between the outer boundary of the second measurement mark 250 and the second strip structure 296 in the second direction is too small, during the subsequent acquisition of the signal wave center point positions of the first measurement mark 230 and the second measurement mark 250, the probability of mutual interference between the signal waves passing through the first measurement mark 230 and the second measurement mark 250 increases, thereby reducing the accuracy of acquiring the signal wave center points of the first measurement mark 230 and the second measurement mark 250, and consequently affecting the wafer product yield. Therefore, in this embodiment, the distance between the outer boundary of the second measurement mark 250 and the second strip structure 296 in the second direction is between 4 micrometers and 10 micrometers.

[0073] Accordingly, embodiments of the present invention also provide a method for measuring overlay error. Wherein, Figure 6 This is a flowchart of a method for measuring overlay error according to an embodiment of the present invention.

[0074] Reference Figures 1 to 2 Step S1: Provide the semiconductor structure provided in the embodiments of the present invention.

[0075] Specifically, the detailed description of the semiconductor structure will not be repeated here; please refer to the foregoing embodiments.

[0076] Reference Figures 1 to 2 Step S2: Based on the height difference between the top of the second measurement mark 150 and the top of the first measurement mark 130, obtain the signal wave center point of the second measurement mark 150 and the signal wave center point of the first measurement mark 130.

[0077] Specifically, there is a height difference between the top of the second measurement mark 150 and the top of the first measurement mark 130. During the process of acquiring the signal wave center points of the second measurement mark 150 and the first measurement mark 130, the signal waves will generate a phase difference due to the different path lengths caused by the height difference when passing through the second measurement mark 150 and the first measurement mark 130. The phase difference can be used to distinguish the center position of the signal wave of the second measurement mark 150 and the center position of the signal wave of the first measurement mark 130. Therefore, the overlay error between the second measurement mark 150 and the first measurement mark 130 can be obtained based on the center positions of the signal waves of the second measurement mark 150 and the first measurement mark 130, thereby determining whether there is an overlay error in the first layer pattern of the wafer. This improves the accuracy of monitoring the overlay error of the first layer pattern of the wafer and improves the product yield of the wafer.

[0078] In this embodiment, the steps of obtaining the signal wave center point of the second measurement mark 150 and the signal wave center point of the first measurement mark 130 include: scanning the first measurement mark 130 and the second measurement mark 150 with an electron beam emitted by a scanning electron microscope; obtaining images of the first measurement mark 130 and the second measurement mark 150 after electron beam scanning; and obtaining the signal wave center point of the second measurement mark 150 and the signal wave center point of the first measurement mark 130 based on the images of the first measurement mark 130 and the second measurement mark 150.

[0079] It should be noted that obtaining the signal wave center point of the second measurement mark 150 and the signal wave center point of the first measurement mark 130 based on the images of the first measurement mark 130 and the second measurement mark 150 can improve measurement accuracy and enhance signal recognition capability.

[0080] Reference Figures 1 to 2 Step S3: Based on the signal wave center point of the second measurement mark 150 and the signal wave center point of the first measurement mark 130, obtain the overlay error between the second measurement mark 150 and the first measurement mark 130.

[0081] Specifically, by obtaining the overlay error between the second measurement mark 150 and the first measurement mark 130, the offset of the first layer pattern of the wafer under test 100 can be determined, providing a process basis for the subsequent formation of multiple stacked film layers on the first layer pattern of the wafer under test 100.

[0082] In this embodiment, the step of obtaining the overprinting error between the second measurement mark 150 and the first measurement mark 130 based on the signal wave center point of the second measurement mark 150 and the signal wave center point of the first measurement mark 130 includes: establishing an XY coordinate system; determining the coordinates of the signal wave center point of the second measurement mark 150 and the signal wave center point of the first measurement mark 130 in the XY coordinate system; and obtaining the overprinting error between the second measurement mark 150 and the first measurement mark 130 based on the coordinates of the signal wave center point of the second measurement mark 150 and the signal wave center point of the first measurement mark 130 in the XY coordinate system.

[0083] It should be noted that in the step of determining the coordinates of the signal wave center point of the second measurement mark 150 and the signal wave center point of the first measurement mark 130 in the XY coordinate system, the coordinates of the signal wave center point of the first measurement mark 130 in the XY coordinate system are set as (X1, Y1), and the coordinates of the signal wave center point of the second measurement mark 150 in the XY coordinate system are set as (X2, Y2).

[0084] In this embodiment, obtaining the overprinting error between the second measurement mark 150 and the first measurement mark 130 includes: obtaining the overprinting error between the second measurement mark 150 and the first measurement mark 130 in the first direction (i.e., the X-axis); and obtaining the overprinting error between the second measurement mark 150 and the first measurement mark 130 in the second direction (i.e., the Y-axis).

[0085] As an example, the overlay error a = X2 - X1 between the second measurement mark 150 and the first measurement mark 130 in the first direction (i.e., the X-axis) is obtained; the overlay error b = Y2 - Y1 between the second measurement mark 150 and the first measurement mark 130 in the second direction (i.e., the Y-axis) is obtained.

[0086] Specifically, when both a and b are 0, it means that the second measurement mark 150 and the first measurement mark 130 are not offset in the first direction, and the second measurement mark 150 and the first measurement mark 130 are not offset in the second direction. This also means that the first layer pattern of the wafer 100 under test has no overlay error. Although the present invention has been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure suitable for measuring the overlay error of the first layer pattern of a wafer, characterized in that, include: The wafer to be tested includes a measurement area; A first measurement mark is located in the measurement area. The first measurement mark includes a first strip structure extending along a first direction and facing each other, and a second strip structure extending along a second direction and facing each other. The first direction is perpendicular to the second direction, and the shape formed by the first strip structure and the second strip structure is rectangular. A second measurement mark is located in the measurement area. The second measurement mark surrounds the first measurement mark. The shape formed by the second measurement mark is rectangular, and there is a height difference between the top of the second measurement mark and the top of the first measurement mark.

2. The semiconductor structure as described in claim 1, characterized in that, The first measurement mark includes an opening.

3. The semiconductor structure as described in claim 1, characterized in that, The end of the first strip structure is in contact with the end of the second strip structure; Alternatively, the ends of the first strip structure are separated from the ends of the second strip structure.

4. The semiconductor structure as described in claim 1, characterized in that, The second measurement mark includes a third strip structure extending along the first direction and facing each other, and a fourth strip structure extending along the second direction and facing each other, wherein the end of the third strip structure is in contact with the end of the fourth strip structure.

5. The semiconductor structure as described in claim 4, characterized in that, The distance between the outer boundary of the third strip structure and the first strip structure is between 4 micrometers and 10 micrometers; The distance between the outer boundary of the fourth strip structure and the second strip structure is between 4 micrometers and 10 micrometers.

6. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a first filling layer located in the region enclosed by the first strip structure and the second strip structure facing each other, the top of the first filling layer being flush with the top of the second measurement mark, and the first filling layer and the second measurement mark being an integral structure.

7. A method for forming a semiconductor structure, suitable for measuring the overlay error of the first layer pattern on a wafer, characterized in that, include: A wafer to be tested is provided, the wafer including a measurement area; A first measurement mark is formed in the measurement area. The first measurement mark includes a first strip structure extending along a first direction and facing each other, and a second strip structure extending along a second direction and facing each other. The first direction is perpendicular to the second direction, and the shape formed by the first strip structure and the second strip structure is rectangular. A second measurement mark is formed around the first measurement mark in the measurement area. The shape formed by the second measurement mark is rectangular, and there is a height difference between the top of the second measurement mark and the top of the first measurement mark.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The first measurement mark and the second measurement mark are formed in the same step.

9. The method for forming a semiconductor structure according to claim 7, characterized in that, The steps of forming the first measurement mark and the second measurement mark include: forming a measurement mark material layer in the measurement area of ​​the first layer of the wafer; performing patterning processing on the measurement mark material layer to form a first opening extending in a first direction and facing each other, and a second opening extending in a second direction and facing each other, wherein the first direction is perpendicular to the second direction, and the shape formed by the facing first opening and the facing second opening is rectangular, and the first opening and the second opening are used as the first measurement mark, and the remaining measurement mark material layer surrounding the first measurement mark is used as the second measurement mark.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, In the step of forming the first measurement mark and the second measurement mark, the remaining measurement mark material layer located in the area enclosed by the first opening and the second opening that are directly opposite each other is used as the first filling layer. The top of the first filling layer is flush with the top of the second measurement mark, and the first filling layer and the second measurement mark are an integral structure.

11. The method for forming a semiconductor structure according to claim 7, characterized in that, The distance between the outer boundary of the second measurement mark and the first strip structure in the first direction is between 4 micrometers and 10 micrometers; The distance between the outer boundary of the second measurement mark and the second strip structure in the second direction is between 4 micrometers and 10 micrometers.

12. A method for measuring overlay error, characterized in that, include: Provides a semiconductor structure as described in any one of claims 1 to 6; Based on the height difference between the top of the second measurement mark and the top of the first measurement mark, the signal wave center point of the second measurement mark and the signal wave center point of the first measurement mark are obtained. Based on the signal wave center point of the second measurement mark and the signal wave center point of the first measurement mark, the overlay error between the second measurement mark and the first measurement mark is obtained.

13. The method for measuring overlay error as described in claim 12, characterized in that, The steps of obtaining the signal wave center point of the second measurement mark and the signal wave center point of the first measurement mark include: scanning the first measurement mark and the second measurement mark with an electron beam emitted by a scanning electron microscope; obtaining images of the first measurement mark and the second measurement mark after electron beam scanning; and obtaining the signal wave center point of the second measurement mark and the signal wave center point of the first measurement mark based on the images of the first measurement mark and the second measurement mark.

14. The method for measuring overlay error as described in claim 12, characterized in that, The step of obtaining the overprinting error between the second measurement mark and the first measurement mark based on the signal wave center point of the second measurement mark and the signal wave center point of the first measurement mark includes: establishing an XY coordinate system; determining the coordinates of the signal wave center point of the second measurement mark and the coordinates of the signal wave center point of the first measurement mark in the XY coordinate system; and obtaining the overprinting error between the second measurement mark and the first measurement mark based on the coordinates of the signal wave center point of the second measurement mark and the coordinates of the signal wave center point of the first measurement mark in the XY coordinate system.

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