A continuously counting timer and its timing method

Abstract

The present invention relates to the field of timers, and discloses a continuously counting timer and its timing method, including: within the current slow clock cycle, when the clock synchronization counting module detects a change in the clock synchronization signal, the clock synchronization counting module increments the count by 1 at the falling edge of each fast clock. At the previous fast clock cycle before the rising edge of the next slow clock, the clock synchronization counting module stops counting and sends a new clock selection signal, and the clock switching module starts to perform clock switching, and completes the clock switching when the rising edge of the next slow clock arrives. When the present invention performs clock switching, the switching point is adjusted to within the previous fast clock cycle before the rising edge of the slow clock, and is accessed from a low level, thereby not only ensuring glitch-free switching, but also ensuring that there is no obvious clock stop situation.

Description

Technical Field

[0001] The present invention relates to the field of timers, and particularly to a continuously counting timer and its timing method. Background Art

[0002] The driving clock of a timer generally uses one clock, and its frequency can be set and changed according to requirements. This is a case of a homologous clock. However, when the driving clock used by the timer is different clocks, for example, a 32 MHz fast clock is used in the system working state, and a 32 KHz clock output by an on-chip low-frequency clock generation circuit is used in the sleep state. The 32 KHz slow clock and the 32 MHz fast clock are different source clocks, that is, they come from two completely independent clock sources. At this time, the two clocks are completely asynchronous clocks, and the phases of the two clocks are completely random. When the clock is switched, in addition to ensuring that the clock has a glitch-free switch, it is also necessary to ensure that the counting error of the timer during the switching process is low. Summary of the Invention

[0003] In view of this, the present invention provides a continuously counting timer and its timing method to solve the problem that the timer can still accurately count when switching between different source clocks.

[0004] In a first aspect, the present invention provides a continuously counting timer, including: a clock synchronization counting module, a clock switching module, and a timing module. Among them, the first input terminal and the second input terminal of the clock synchronization counting module input a slow clock and a fast clock, the third input terminal of the clock synchronization counting module inputs a clock synchronization signal, the first output terminal and the second output terminal of the clock synchronization counting module are connected to the first input terminal of the timing module and the third input terminal of the clock switching module; the first input terminal and the second input terminal of the clock switching module input a slow clock and a fast clock, and the output terminal of the clock switching module is connected to the second input terminal of the timing module; within the current slow clock cycle, if the clock synchronization counting module detects a change in the clock synchronization signal of the clock selection signal, the clock synchronization counting module increments the count by 1 at the falling edge of each fast clock, and at the time of the fast clock cycle before the rising edge of the next slow clock, the clock synchronization counting module stops counting and sends a new clock selection signal to the timing module and the clock switching module; when the clock switching module receives the new clock selection signal, the clock switching module starts to perform a clock switch, and before the rising edge of the next slow clock arrives, the clock switch is completed; when the timing module receives the new clock selection signal, the timing module latches the current counting method, and after the clock switch is completed, the timing module switches to the corresponding counting method.

[0005] When the present invention performs clock switching, a new clock selection signal is utilized to select the driving clock of the timer and immediately perform clock switching. The switching point is adjusted to within one fast clock cycle before the rising edge of the slow clock and is accessed from a low level, thereby not only ensuring glitch-free switching but also ensuring that there is no obvious clock stop situation.

[0006] In an alternative embodiment, the continuously counting timer further includes: a clock frequency measurement module. The first input terminal and the second input terminal of the clock frequency measurement module respectively input a fast clock and a slow clock, and the output terminal of the clock frequency measurement module is connected to the fourth input terminal of the clock synchronization counting module and the third input terminal of the timing module. The clock frequency measurement module is used to test the frequency ratio of the fast clock to the slow clock. When the frequency ratio is an integer and during the period when the slow clock switches to the fast clock, the timing module increments the timing by N at each rising edge of the slow clock, where N is the frequency ratio of the fast clock to the slow clock. During the period when the fast clock switches to the slow clock, the timing module increments the count by 1 at each rising edge of the fast clock. After the clock switching is completed and under the drive of the fast clock, the timing module increments the count by 1 at each falling edge of the fast clock. After the clock switching is completed and under the drive of the slow clock, the timing module increments the timing by N at each rising edge of the slow clock.

[0007] When the present invention is driven by the slow clock, it uses the frequency ratio of the fast clock to the slow clock for timing, thereby avoiding the situation of inaccurate timing caused by the slow clock being affected by system environmental temperature and the like.

[0008] In an alternative embodiment, the timing module includes: an addend switching module, an adder, and a register. The first input terminal of the addend switching module is connected to the output terminal of the clock frequency measurement module, the second input terminal of the addend switching module inputs the value 1, the third input terminal of the addend switching module is connected to the first output terminal of the clock synchronization counting module, and the output terminal of the addend switching module is connected to the first input terminal of the adder. The second input terminal of the adder is connected to the output terminal of the register, and the output terminal of the adder is connected to the input terminal of the register.

[0009] In an alternative embodiment, the addend switching module includes: a multiplexer. The first input terminal of the multiplexer is connected to the output terminal of the clock frequency measurement module, the second input terminal of the multiplexer inputs the value 1, the third input terminal of the multiplexer is connected to the first output terminal of the clock synchronization counting module, and the output terminal of the multiplexer is connected to the first input terminal of the adder.

[0010] In an alternative embodiment, the continuously counting timer further includes: a configuration module. The configuration module is connected to the clock frequency measurement module and the register, and the configuration module is used to configure the test time of the clock frequency measurement module and the timing time of the timing module.

[0011] Second aspect, the present invention provides a timing method for a continuously counting timer. Based on the continuously counting timer of the first aspect and any of its alternative embodiments, the timing method includes: within the current slow clock cycle, determining whether the current clock selection signal is the same as the clock selection signal of the previous slow clock cycle. When the two are different, start incrementing the count by 1 at the falling edge of each fast clock; at a fast clock cycle before the rising edge of the next slow clock, stop counting and generate a new clock selection signal, and start clock switching, and complete the clock switching before the rising edge of the next slow clock arrives; latch the current counting mode, and after the clock switching is completed, switch to the corresponding counting mode.

[0012] In an alternative embodiment, the timing method of the continuously counting timer further includes: testing the frequency ratio of the fast clock to the slow clock; when incrementing the count driven by the fast clock, increment the timing by 1 at the rising edge of each fast clock; when incrementing the count driven by the slow clock, increment the timing by N at the rising edge of each slow clock, where N is the frequency ratio of the fast clock to the slow clock.

[0013] In an alternative embodiment, the new clock selection signal is latched as a comparison signal with the clock selection signal of the next slow clock cycle.

[0014] Third aspect, the present invention provides a computer device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to execute the timing method of the continuously counting timer according to the second aspect or any of its corresponding embodiments.

[0015] Fourth aspect, the present invention provides a computer-readable storage medium, on which computer instructions are stored. The computer instructions are used to cause a computer to execute the timing method of the continuously counting timer according to the second aspect or any of its corresponding embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 is the specific circuit structure diagram of the clock signal switching circuit of the related art

[0018] Figure 2 is the composition diagram of the continuously counting timer according to the embodiment of the present invention;

[0019] Figure 3 It is a component diagram of another continuously counting timer according to an embodiment of the present invention;

[0020] Figure 4 It is a schematic diagram of the internal structure of the system;

[0021] Figure 5 It is a component diagram of another continuously counting timer according to an embodiment of the present invention;

[0022] Figure 6 It is a waveform diagram of the slow clock switching to the fast clock according to an embodiment of the present invention;

[0023] Figure 7 It is a waveform diagram of the fast clock switching to the slow clock according to an embodiment of the present invention;

[0024] Figure 8 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed implementation manners

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0026] In related technologies, for the switching of different source clocks, because the switching time points are random and the phases of the two clocks are random, generally Figure 1 a switching circuit or a similar circuit in

[0027] 1) The important principle of clock switching: First, turn off the currently selected clock, and then enable the newly selected clock.

[0028] 2) It is a relatively safe practice to switch when the current clock is at a low level.

[0029] If the driving clock of the timer is a multi-clock, a clock disappearance phenomenon will occur during clock switching. For example, Figure 1 in a common clock switching circuit, this type of switching circuit will cause the clock after switching to have a clockless state for multiple target clock cycles, that is, the final clock output will continuously be at a low level. After the clock switching is completed, the clock resumes and switches to the target clock. This will cause serious consequences for application scenarios with very high requirements for timing accuracy.

[0030] Based on this, in this embodiment, a continuously counting timer is provided, such as Figure 2As shown in the figure, it includes: a clock synchronization counting module, a clock switching module, and a timing module.

[0031] As Figure 2 shown, the first input terminal and the second input terminal of the clock synchronization counting module input a slow clock and a fast clock, the third input terminal of the clock synchronization counting module inputs a clock synchronization signal, and the output terminal of the clock synchronization counting module is connected to the first input terminal of the timing module and the third input terminal of the clock switching module.

[0032] Specifically, when the system receives a clock selection signal, the system will synchronize the clock selection signal to the fast clock domain, and the synchronization time is approximately two fast clock cycles. Among them, the system can be an MCU chip or an SoC chip.

[0033] Specifically, the clock synchronization counting module will detect in real time whether the clock synchronization signal of the clock selection signal changes after delaying a preset synchronization time at each falling edge of the slow clock. When it detects that the clock synchronization signal of the clock selection signal changes, the clock synchronization counting module starts timing. The preset synchronization time is the time for the slow clock to be synchronized as a signal to the fast clock domain. Optionally, the preset synchronization time is at least two fast clock cycles.

[0034] Exemplarily, when the system receives a clock selection signal at the high level of the current slow clock, the clock synchronization counting module detects whether there is a change in the clock synchronization signal of the clock selection signal at two fast clock cycles after the falling edge of the current slow clock; when the system receives a clock selection signal at the low level of the current slow clock, the clock synchronization counting module detects whether there is a change in the clock synchronization signal of the clock selection signal at two fast clock cycles after the falling edge of the next slow clock.

[0035] Specifically, when the clock synchronization counting module does not detect a change in the clock synchronization signal of the clock selection signal, it saves the clock synchronization signal of the clock selection signal in the current slow clock cycle as a reference signal for the next slow clock cycle. This reference signal is used to compare with the clock synchronization signal of the clock selection signal in the next slow clock cycle. If the levels of the two are the same, the clock synchronization counting module does not start. If the levels of the two are different, the clock synchronization counting module starts counting.

[0036] Specifically, when it detects a change in the clock synchronization signal of the clock selection signal, the clock synchronization counting module increments the count by 1 at each falling edge of the fast clock, and stops counting at one fast clock cycle before the rising edge of the next slow clock.

[0037] It should be noted that the clock synchronization counting module stops counting at one fast clock cycle before the rising edge of the next slow clock, and one fast clock cycle refers to a complete fast clock cycle.

[0038] AsFigure 2 As shown, the first input terminal and the second input terminal of the clock switching module receive a slow clock and a fast clock respectively, and the output terminal of the clock switching module is connected to the second input terminal of the timing module.

[0039] To achieve glitch-free and continuous counting, when the clock switching module receives a new clock selection signal, it starts clock switching. When the high level of the next slow clock arrives, the clock switching is completed. When the timing module receives the new clock selection signal, the timing module latches the current counting mode. After the clock switching is completed, the timing module switches to the corresponding counting mode. That is, during the process of switching from the slow clock to the fast clock, the timing module still maintains the counting mode driven by the slow clock, and during the process of switching from the fast clock to the slow clock, the timing module still maintains the counting mode driven by the fast clock.

[0040] Specifically, for the counting mode, it involves two cases: when the clock switching is completed and during the clock switching.

[0041] (1) During the process of switching from the slow clock to the fast clock, the timing module accumulates the count driven by the slow clock, and during the process of switching from the fast clock to the slow clock, the timing module accumulates the count driven by the fast clock.

[0042] Specifically, to ensure that when driven by the slow clock, the timing module still accumulates the count driven by the slow clock, even when a fast clock cycle arrives before the next slow clock and clock switching starts, the timing module still accumulates the count driven by the slow clock. At this time, the added value driven by the slow clock needs to be latched.

[0043] Similarly, to ensure that when driven by the fast clock, the timing module still accumulates the count driven by the fast clock, even when a fast clock arrives before the next slow clock and clock switching starts, the timing module still accumulates the count driven by the fast clock. At this time, the added value driven by the fast clock needs to be latched.

[0044] (2) When the clock switching is completed, the timing module switches to the corresponding counting mode.

[0045] Specifically, when the clock switching is completed, when it is the slow clock, the timing module accumulates the count driven by the slow clock, and when it is the fast clock, the timing module accumulates the count driven by the fast clock.

[0046] In some alternative embodiments, as Figure 3 shown, the continuous counting timer further includes: a clock frequency measurement module.

[0047] As Figure 3As shown in the figure, the first input terminal and the second input terminal of the clock frequency measurement module respectively receive a fast clock and a slow clock. The output terminal of the clock frequency measurement module is connected to the fourth input terminal of the clock synchronization counting module and the third input terminal of the timing module. The clock frequency measurement module is used to measure the frequency ratio of the fast clock and the slow clock before the fast clock switches to the slow clock. The frequency ratio is an integer. Optionally, the clock frequency measurement module can set the time and number of measurements of the frequency ratio as required, which is not limited here.

[0048] Specifically, within the current slow clock cycle, if the clock synchronization counting module detects a change in the clock synchronization signal of the clock selection signal, the clock synchronization counting module increments the count by 1 at the falling edge of each fast clock. Before the rising edge of the next slow clock in the previous fast clock cycle, the clock synchronization counting module stops counting and sends a new clock selection signal to the timing module and the clock switching module.

[0049] As Figure 4 shown, an MCU chip or an SoC chip generally integrates a low-frequency clock generation circuit (RCOSC), a CPU module (i.e., the CPU Sub-System), and a sleep timer (SleepTimer) internally. The typical frequency of the low-frequency clock generation circuit is 32 KHz, which is mainly used as the working clock of the MCU system in the sleep state, such as the clock of the sleep timer (SleepTimer), the working clock of always-on modules such as system wake-up (WakeUp), etc.

[0050] As Figure 4 shown, there is at least one high-speed clock inside the MCU chip. This clock is input from an external crystal oscillator (i.e., Crystal Osc) into the chip and is directly used or further processed by an on-chip PLL to generate a higher-frequency clock. The accuracy of this type of clock is very high, and the frequency deviation is generally below 10 ppm. This type of clock can be regarded as a precise clock and is mainly used as the working clock of the MCU chip in the working state. For an MCU chip, the high-speed precise clock frequency is generally between 1 MHz and 100 MHz.

[0051] Based on this, in order to enable the timer to accurately measure time when the system is in the sleep state, that is, driven by the slow clock, in this embodiment, when the system is in the sleep state, within one slow clock cycle, the number of fast clock cycles is calculated. That is, at each rising edge of the slow clock, the timing module accumulates N, where N is the number of fast clock cycles included in one slow clock cycle, that is, the frequency ratio. When the count reaches the preset threshold, the system is awakened. At the same time, when the system is in the working state, the timing module increments the count by 1 at the rising edge of each fast clock.

[0052] Based Figure 3 on the structure shown, the counting method is as follows:

[0053] During the slow clock switching to the fast clock, the timing module increments the count by N at each rising edge of the slow clock; during the fast clock switching to the slow clock, the timing module increments the count by 1 at each rising edge of the fast clock.

[0054] (2) After the clock switching is completed and driven by the fast clock, the timing module increments the count by 1 at each rising edge of the fast clock; after the clock switching is completed and driven by the slow clock, the timing module increments the count by N at each rising edge of the slow clock.

[0055] Based on the above counting method, it is determined whether the current clock selection signal is the same as the clock selection signal in the previous slow clock cycle. When the two are different, the count starts to increment by 1 at each falling edge of the fast clock; when the count reaches When N is even, the counting stops when the count reaches When N is odd, the stop count value is The value rounded down.

[0056] In some alternative embodiments, as Figure 5 shown, the timing module includes: an addend switching module, an adder, and a register.

[0057] As Figure 5 shown, the first input terminal of the addend switching module is connected to the first output terminal of the clock frequency measurement module, the second input terminal of the addend switching module inputs the value 1, the third input terminal of the addend switching module is connected to the first output terminal of the clock synchronous counting module, and the output terminal of the addend switching module is connected to the first input terminal of the adder; the second input terminal of the adder is connected to the output terminal of the register, and the output terminal of the adder is connected to the input terminal of the register.

[0058] Specifically, referring to Figure 5 , the timing method is as follows:

[0059] (1) When the slow clock switches to the fast clock, the addend switching module outputs the frequency ratio to the adder; during the fast clock switching to the slow clock, the addend switching module outputs the value 1 ratio to the adder;

[0060] (2) After the clock switching is completed and driven by the fast clock, the addend switching module outputs the value 1 ratio to the adder; after the clock switching is completed and driven by the slow clock, the addend switching module outputs the frequency ratio to the adder.

[0061] In some alternative embodiments, the adder switching module includes: a multiplexer, wherein a first input end of the multiplexer is connected to an output end of the clock frequency measurement module, a value 1 is input to a second input end of the multiplexer, a third input end of the multiplexer is connected to a first output end of the clock synchronization counting module, and an output end of the multiplexer is connected to a first input end of the adder.

[0062] In some alternative embodiments, the continuously counting timer further includes: a configuration module, wherein the configuration module is connected to the clock frequency measurement module and the timer, and the configuration module is configured to configure a test time of the clock frequency measurement module, a timing time of the timing module, and the like.

[0063] Based on the above method, the waveforms of switching from a slow clock to a fast clock and from a fast clock to a slow clock are respectively as Figure 6 , Figure 7 shown, Figure 6 in which the waveforms from top to bottom are a fast clock waveform, a slow clock waveform, a clock selection signal waveform, a clock synchronization signal waveform of the clock selection signal, a counting waveform of the clock synchronization counting module, a new clock selection signal waveform, an output waveform of the clock switching module, and a counting waveform of the timer, Figure 7 in which the waveforms from top to bottom are a fast clock waveform, a slow clock waveform, a clock selection signal waveform, a clock synchronization signal waveform of the clock selection signal, a counting waveform of the clock synchronization counting module, a new clock selection signal waveform, an output waveform of the clock switching module, and a counting waveform of the timer.

[0064] In the present embodiment, a timing method for a continuously counting timer is provided. Based on the continuously counting timer of the above embodiment and any of its alternative embodiments, the timing method includes:

[0065] (1) During the current slow clock cycle, determine whether the current clock selection signal is the same as the clock selection signal in the previous slow clock cycle. When they are different, start incrementing the count by 1 at the falling edge of each fast clock.

[0066] (2) At a fast clock cycle before the rising edge of the next slow clock, stop counting and generate a new clock selection signal, and start clock switching, and complete the clock switching before the rising edge of the next slow clock arrives.

[0067] (3) Latch the current counting mode, and after the clock switching is completed, switch to the corresponding counting mode.

[0068] In some alternative embodiments, the timing method for the continuously counting timer further includes:

[0069] Test the frequency ratio of the fast clock and the slow clock; when accumulating and counting under the drive of the fast clock, at the rising edge of each fast clock, the timing is incremented by 1; when accumulating and counting under the drive of the slow clock, at the rising edge of each slow clock, the timing is incremented by N, where N is the frequency ratio of the fast clock to the slow clock.

[0070] In some alternative embodiments, the new clock selection signal is registered as a comparison signal with the clock selection signal of the next slow clock cycle.

[0071] Specifically, the timing method has been detailed in the embodiments and implementation manners of the continuous counting timer, and will not be elaborated here.

[0072] The embodiment of the present invention further provides a computer device having the above-mentioned continuous counting timer.

[0073] Please refer to Figure 8 , Figure 8 is a schematic structural diagram of a computer device provided by an alternative embodiment of the present invention. As Figure 8 shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including a high-speed interface and a low-speed interface. Each component communicates with each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a set of blade servers, or a multi-processor system). Figure 8 Take one processor 10 as an example in

[0074] The processor 10 can be a central processing unit, a network processor, or a combination thereof. Among them, the processor 10 can further include a hardware chip. The above-mentioned hardware chip can be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The above-mentioned programmable logic device can be a complex programmable logic device, a field programmable gate array, a general array logic, or any combination thereof.

[0075] Among them, the memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiments.

[0076] The memory 20 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created according to the use of a computer device for the display of a kind of mini-program landing page, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 may optionally include a memory remotely disposed relative to the processor 10, and these remote memories may be connected to the computer device through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0077] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, a hard disk, or a solid-state drive; the memory 20 may further include a combination of the above types of memory.

[0078] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0079] The embodiments of the present invention also provide a computer-readable storage medium. The methods according to the embodiments of the present invention may be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code originally stored in a remote storage medium or a non-transitory machine-readable storage medium and to be downloaded through a network and stored in a local storage medium, so that the methods described herein may be stored in such software processes on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium may be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium may further include a combination of the above types of memory. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods shown in the above embodiments are implemented.

[0080] Although the embodiments of the present invention are described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A continuous counting timer, characterized in that: include: Clock synchronization counting module, clock switching module and timing module, wherein: The first input terminal and the second input terminal of the clock synchronization counting module input the slow clock and the fast clock, the third input terminal of the clock synchronization counting module inputs the clock synchronization signal, and the first output terminal and the second output terminal of the clock synchronization counting module are connected to the first input terminal of the timing module and the third input terminal of the clock switching module; The first input terminal and the second input terminal of the clock switching module input the slow clock and the fast clock, and the output terminal of the clock switching module is connected to the second input terminal of the timing module; In the current slow clock cycle, if the clock synchronization counting module detects that the clock synchronization signal of the clock selection signal changes, the clock synchronization counting module counts by 1 at the falling edge of each fast clock, and in the fast clock cycle before the rising edge of the next slow clock, the clock synchronization counting module stops counting and sends a new clock selection signal to the timing module and the clock switching module; When the clock switching module receives the new clock selection signal, the clock switching module starts clock switching and completes the clock switching before the rising edge of the next slow clock arrives; When the timing module receives the new clock selection signal, the timing module latches the current counting mode, and after the clock switching is completed, the timing module switches to the corresponding counting mode.

2. The continuous counting timer according to claim 1, characterized in that: Also includes: Clock frequency measurement module, where The first input terminal and the second input terminal of the clock frequency measurement module are respectively input with the fast clock and the slow clock, and the output terminal of the clock frequency measurement module is connected with the fourth input terminal of the clock synchronization counting module and the third input terminal of the timing module; the clock frequency measurement module is used to test the frequency ratio of the fast clock to the slow clock, and the frequency ratio is an integer. During the period when the slow clock switches to the fast clock, the timing module increases the timing by N at each rising edge of the slow clock; during the period when the fast clock switches to the slow clock, the timing module increases the count by 1 at each rising edge of the fast clock, where N is the frequency ratio of the fast clock to the slow clock; After the clock switching is completed and the fast clock is driven, the timing module counts up by 1 at each rising edge of the fast clock; after the clock switching is completed and the slow clock is driven, the timing module counts up by N at each rising edge of the slow clock.

3. The continuous counting timer according to claim 2, characterized in that: The timing module includes: an addend switching module, an adder and a register, wherein: The first input end of the addend switching module is connected to the output end of the clock frequency measurement module, the second input end of the addend switching module inputs a value 1, the third input end of the addend switching module is connected to the first output end of the clock synchronization counting module, and the output end of the addend switching module is connected to the first input end of the adder; The second input terminal of the adder is connected to the output terminal of the register, and the output terminal of the adder is connected to the input terminal of the register.

4. The continuous counting timer according to claim 3, characterized in that: The addend switching module includes: a multiplexer, wherein: The first input end of the multiplexer is connected to the output end of the clock frequency measurement module, the second input end of the multiplexer inputs a value of 1, the third input end of the multiplexer is connected to the first output end of the clock synchronization counting module, and the output end of the multiplexer is connected to the first input end of the adder.

5. The continuous counting timer according to claim 3, characterized in that: Also includes: Configuration module, where The configuration module is connected to the clock frequency measurement module and the register, and is used to configure the test time of the clock frequency measurement module and the timing time of the timing module.

6. A timing method for a continuous counting timer, characterized in that: Based on the continuous counting timer according to any one of claims 1 to 5, the timing method comprises: In the current slow clock cycle, determine whether the current clock selection signal is the same as the clock selection signal of the previous slow clock cycle. If the two are different, start counting by 1 at the falling edge of each fast clock. At the fast clock cycle before the rising edge of the next slow clock, stop counting and generate a new clock selection signal, start clock switching, and complete clock switching before the rising edge of the next slow clock arrives; Latch the current counting mode, and switch to the corresponding counting mode after the clock switching is completed.

7. The timing method of a continuous counting timer according to claim 6, characterized in that: Also includes: Testing the frequency ratio of the fast clock to the slow clock; When the count is accumulated under the fast clock drive, the timing is increased by 1 at each rising edge of the fast clock; When the count is accumulated under the driving of the slow clock, the timing increases by N at each rising edge of the slow clock, where N is the frequency ratio of the fast clock to the slow clock.

8. The timing method of a continuous counting timer according to claim 6, characterized in that: The new clock selection signal is stored as a comparison signal with the clock selection signal of the next slow clock cycle.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the timing method of the continuous counting timer according to any one of claims 6 to 8 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the timing method of the continuous counting timer according to any one of claims 6 to 8.

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