Flash memory controller, memory device and related control method

Abstract

The invention relates to a flash memory controller, a memory device and a related control method. The memory device comprises a flash memory module, the flash memory module comprises a plurality of blocks, and the control method comprises the following steps of: updating wear average related data temporarily stored in a buffer memory; obtaining a plurality of parameters; determining a write frequency according to the plurality of parameters; and copying the wear average related data from the buffer memory to the flash memory module according to the write frequency.

Description

Technical Field

[0001] The present invention relates to flash memory. Background Art

[0002] In current flash memory devices, wear leveling technology is widely used. Its biggest function is to write data evenly to each block of the flash memory module to avoid permanent damage caused by excessive erase and write times of a single block, which in turn leads to data quality degradation or data loss. Therefore, wear leveling technology can improve the durability and stability of the flash memory module.

[0003] In the wear leveling technique, the flash memory controller needs to use some relevant data to determine a source block and a target block in the flash memory module, and move all the data in the source block to the target block, wherein the source block is a block with a lower erase count, and the target block is a block with a higher erase count. Therefore, in order to determine the source block and the target block, the flash memory controller will establish an erase count comparison table, which records the erase count (cumulative erase count) of each block in the flash memory module for reference when executing the wear leveling technique. In addition, since the erase count comparison table is continuously updated due to the erasure of the block, the erase count comparison table will be temporarily stored in the buffer memory of the flash memory controller and written to the flash memory module at an appropriate time. However, since the buffer memory is a volatile memory, if the flash memory controller encounters a sudden power failure, the erase count comparison table will be lost, so that after power is restored, the flash memory controller needs to read the old erase count comparison table from the flash memory module to continue using it. As a result, the erase count comparison table will not be able to reflect the actual erase count of each block in the flash memory module. In addition, if the flash memory controller often encounters sudden power failures, the distortion of the erase count comparison table will be more serious.

[0004] In order to solve the problem that the erase count comparison table cannot reflect the actual erase count of each block due to the sudden power failure, a common method is to periodically and frequently write the erase count comparison table temporarily stored in the buffer memory into the flash memory module. However, frequently writing the erase count comparison table into the flash memory module will affect the overall performance of the memory device. Therefore, how to determine the frequency of writing the erase count comparison table into the flash memory module is an important issue. Summary of the invention

[0005] Therefore, one of the objectives of the present invention is to provide a control method for a memory device, which can dynamically determine the frequency of writing the erase count table to the flash memory module according to multiple parameters recorded by the flash memory controller to solve the problems described in the prior art.

[0006] In one embodiment of the present invention, a control method for a memory device is disclosed, wherein the memory device includes a flash memory module, the flash memory module includes a plurality of blocks, and the control method includes: updating a wear leveling related data temporarily stored in a buffer memory; obtaining a plurality of parameters; determining a write frequency based on the plurality of parameters; and copying the wear leveling related data from the buffer memory to the flash memory module based on the write frequency.

[0007] In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of blocks, and the flash memory controller includes a read-only memory, a buffer memory, and a microprocessor. The microprocessor is used to perform the following operations: update a wear leveling related data temporarily stored in the buffer memory; obtain a plurality of parameters; determine a write frequency according to the plurality of parameters; and copy the wear leveling related data from the buffer memory to the flash memory module according to the write frequency.

[0008] In one embodiment of the present invention, a memory device is disclosed, which includes a flash memory module and a flash memory controller. The flash memory controller performs the following operations: updating a wear leveling related data temporarily stored in a buffer memory of the flash memory controller; obtaining a plurality of parameters; determining a write frequency according to the plurality of parameters; and copying the wear leveling related data from the buffer memory to the flash memory module according to the write frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 4 is a schematic diagram of a memory device according to an embodiment of the present invention.

[0010] Figure 2 is a schematic diagram of a flash memory module.

[0011] Figure 3 A schematic diagram of an erase count comparison table.

[0012] Figure 4 It is a schematic diagram of a comparison table of average times of wear.

[0013] Figure 5 The figure is a flow chart of updating the average wear times comparison table according to an embodiment of the present invention.

[0014] Figure 6 A schematic diagram for updating the power-on times of a memory device.

[0015] Figure 7 FIG. 4 is a flow chart of a control method of a memory device according to an embodiment of the present invention.

[0016]

Explanation of symbols

[0017] 100: Memory device

[0018] 110: Flash memory controller

[0019] 112: Microprocessor

[0020] 112M: Read-only memory

[0021] 112C: Program code

[0022] 114: Control Logic

[0023] 116: Buffer memory

[0024] 118: Interface Logic

[0025] 120: Flash memory module

[0026] 130: Main device

[0027] 132: Encoder

[0028] 134:Decoder

[0029] 136: Randomizer

[0030] 138:De-Randomizer

[0031] 300: Erase times comparison table

[0032] 400: Average number of wear and tear comparison table

[0033] 500~510: Steps

[0034] 600~604: Steps

[0035] 700~706: Steps

[0036] B1~BN: Block

[0037] P1~PA: Data page DETAILED DESCRIPTION

[0038] Figure 11 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The ROM 112M is used to store a program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access to the flash memory module 120. The control logic 114 includes an encoder 132, a decoder 134, a randomizer 136, and a de-randomizer 138, wherein the encoder 132 is used to encode the data written into the flash memory module 120 to generate a corresponding check code (or error correction code, ECC), the decoder 134 is used to decode the data read from the flash memory module 120, the randomizer 136 is used to perform a randomization operation on the data written into the flash memory module 120, and the de-randomizer 138 is used to perform a de-randomization operation on the data read from the flash memory module 120.

[0039] In a typical case, the flash memory module 120 includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks. The flash memory controller 110 performs operations such as copying, erasing, and merging data on the flash memory module 120 in units of blocks. In addition, a block can record a specific number of data pages, and the flash memory controller 110 performs operations such as writing data to the flash memory module 120 in units of data pages. In other words, a block is a minimum erase unit in the flash memory module 120, and a data page is a minimum write unit in the flash memory module 120.

[0040] In practice, the flash memory controller 110 that executes the program code 112C through the microprocessor 112 can use its own internal components to perform a variety of control operations, such as: using the control logic 114 to control the access operation of the flash memory module 120 (especially the access operation to at least one block or at least one data page), using the buffer memory 116 to perform the required buffer processing, and using the interface logic 118 to communicate with a host device 130.

[0041] In one embodiment, the memory device 100 may be a portable memory device (e.g., a memory card that complies with SD / MMC, CF, MS, or XD standards), and the host device 130 is an electronic device that can be connected to the memory device, such as a mobile phone, a notebook computer, a desktop computer, etc. In another embodiment, the memory device 100 may be a solid state drive or an embedded storage device that complies with Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, and is disposed in an electronic device, such as a mobile phone, a watch, a portable medical detection device (e.g., a medical bracelet), a notebook computer, or a desktop computer, and the host device 130 may be a processor of the electronic device.

[0042] In the present embodiment, the flash memory module 120 is a 3D NAND-type flash memory module, wherein each block is composed of a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Since the 3D NAND-type flash memory architecture is well known to those skilled in the art, no further explanation is given in the specification.

[0043] Figure 2 FIG. 1 is a schematic diagram of a flash memory module 120. Figure 2 As shown, the flash memory module 120 includes a plurality of blocks B1-BN, wherein the blocks B1-BN may include at least one type of block, for example, the blocks B1-BN may include a single-level cell (SLC) block, a multi-level cell (MLC) block, a triple-level cell (TLC) block, and / or a quad-level cell (QLC) block. In addition, each block includes a plurality of data pages, for example, the data pages P1-PA shown in the figure.

[0044] To manage the flash memory module 120, the flash memory controller 110 establishes and continuously updates the Figure 3 The erase count comparison table 300 is shown, wherein the erase count comparison table 300 is temporarily stored in the buffer memory 116 in the flash memory controller 110. Figure 3As shown, the erase count comparison table 300 records the erase count of each block B1-BN, wherein the "erase count" refers to the cumulative erase count of the block since the memory device 100 began to be used. Specifically, the flash memory controller 110 needs to select one or more blocks for erase operations due to some mechanisms to delete all data in the block and make it a blank block for subsequent use. For example, if the number of remaining blank blocks in the flash memory module 120 is lower than a critical value, the flash memory controller 110 can perform a garbage collection operation to select multiple blocks with lower valid data pages, and after all the valid data of these blocks are moved to one or more blank blocks, erase these blocks to become blank blocks, and at this time, the erase count comparison table 300 will add "1" to the erase count of these blocks. In another example, the flash memory controller 110 may record the number of reads of each block, wherein the number of reads of each block will be reset after the block is erased. Since the data quality of a block with a large number of reads will decrease, the flash memory controller 110 may select a block with a number of reads higher than a critical value, and at an appropriate time point, move all valid data of the block to a blank block, and then erase the block to make it a blank block. At this time, the erase count comparison table 300 will add "1" to the erase count of the block. In another example, if the flash memory controller 110 finds that the number of error bits of a block is higher than a critical value when reading the block, the flash memory controller 110 may move all valid data of the block to a blank block at an appropriate time point, and then erase the block to make it a blank block. At this time, the erase count comparison table 300 will add "1" to the erase count of the block.

[0045] In addition, the flash memory controller 110 establishes and continuously updates the Figure 4 The average wear times table 400 is temporarily stored in the buffer memory 116 in the flash memory controller 110. Figure 4 As shown, the wear average count comparison table 400 records the erase count of each block B1-BN, wherein the "wear average count" refers to the cumulative erase count generated by the wear leveling mechanism since the memory device 100 starts to be used. Specifically, the update of the wear average count comparison table 400 can refer to Figure 5. In step 500, the process starts, and the memory device 100 is powered on and starts to operate. In step 502, the flash memory controller 110 determines whether a maximum erase count difference between blocks is greater than a critical value according to the content of the erase count comparison table 300. If so, the process proceeds to step 504; if not, the process stays at step 502. For example, the maximum erase count difference between blocks can be the difference between a maximum erase count and a minimum erase count recorded in the erase count comparison table 300.

[0046] In step 504 , the flash memory controller 110 selects a source block and a target block, wherein the source block may be a block having the minimum erase count or a lower erase count in the erase count comparison table 300 , and the target block may be a block having the maximum erase count in the erase count comparison table 300 .

[0047] In step 506, the flash memory controller 110 erases the target block to make the target block a blank block, and at this time, the flash memory controller 110 updates the erase count comparison table 300 and the wear average count comparison table 400 to add "1" to the erase count and the wear average count of the target block. It should be noted that if the target block is already a blank block, step 506 can be ignored.

[0048] In step 508 , the flash memory controller 110 moves all contents of the source block to the target block.

[0049] In step 510, the flash memory controller 110 erases the source block to make the source block a blank block, and at this time, the flash memory controller 110 updates the erase count comparison table 300 to add "1" to the erase count of the source block. It should be noted that the flash memory controller 110 does not update the wear average count comparison table 400 due to the erasure of the source block.

[0050] exist Figure 5 In the process, since the block with the minimum erase count or a lower erase count usually represents that the stored data is cold data, that is, data that is rarely updated, therefore, by moving the data of the source block with the minimum erase count or a lower erase count to the target block with the maximum erase count, the target block can store cold data that is not frequently updated, thereby reducing the probability that the target block needs to be erased due to garbage collection operation in the future.

[0051] In addition, the flash memory controller 110 establishes and continuously updates a power-on count of the memory device 100. Figure 6In the flowchart shown, the process starts at step 600, when the memory device 100 is not powered on. At step 602, the memory device 100 is powered on, and the flash memory controller 110 and the flash memory module 120 therein complete the initialization operation. At step 604, the flash memory controller 110 reads a power-on count stored in the flash memory module 120, and updates the power-on count (i.e., adds "1" to the power-on count) and stores it in the flash memory module 120.

[0052] Figure 7 Flow chart of a control method of a memory device 100 according to an embodiment of the present invention. In step 700, the process starts. In step 702, the flash memory controller 100 obtains a plurality of parameters, wherein the plurality of parameters may include at least a part of a total number of erase times, a total number of wear leveling times, a maximum erase times difference between blocks, a wear leveling threshold, the number of power-on times of the memory device 100, and a total number of written data. For example, the total number of erase times is the total number of erase times of all blocks in the flash memory module 120, that is, the total number of erase times in the erase times comparison table 300. The wear leveling threshold may be the cumulative number of erase times generated by the wear leveling mechanism for all blocks in the flash memory module 120, that is, the total number of wear leveling times in the wear leveling times comparison table 400. The maximum erase times difference between blocks is the difference between the maximum erase times and the minimum erase times recorded in the erase times comparison table 300. The wear level threshold may be a threshold value determined according to the type of the block. For example, if the blocks B1-BN are single-layer storage blocks, the wear level threshold may be a higher value, such as 10% of the permissible erasure times (e.g., 100,000 times) of the single-layer storage blocks; if the blocks B1-BN are triple-layer storage blocks, the wear level threshold may be a lower value, such as 10% of the permissible erasure times (e.g., 3,000 times) of the triple-layer storage blocks. The total written data is the total amount of written data since the flash memory module 120 was first used (i.e., including all the data that has been written), wherein the total written data can be estimated through the erase times comparison table 300, the size of each block, and the amount of data currently stored in the flash memory module 120.

[0053] In step 704, the flash memory controller 110 determines a write frequency for copying a wear leveling related data from the buffer memory 116 to the flash memory module 120 according to the plurality of parameters. In a first embodiment, the flash memory controller 110 determines the write frequency according to a ratio of the total wear leveling times to the total erase times, wherein the higher the ratio is, the more wear leveling operations have been performed in the past, and the selected source block and / or target block may not be appropriate when performing the wear leveling operations in the past, so the write frequency needs to be increased. For example, when the ratio is in a first range with a higher value, the flash memory controller 110 determines a higher first write frequency; and when the ratio is in a second range with a lower value, the flash memory controller 110 determines a lower second write frequency.

[0054] In a second embodiment, the flash memory controller 110 determines the write frequency according to a ratio of the maximum erase count difference between blocks to the wear leveling threshold, wherein the higher the ratio is, the greater the effect of the erase count difference between blocks on the flash memory module 120 is, and therefore the write frequency needs to be increased. For example, when the ratio is in a first range with a higher value, the flash memory controller 110 determines a higher first write frequency; and when the ratio is in a second range with a lower value, the flash memory controller 110 determines a lower second write frequency.

[0055] In a third embodiment, the flash memory controller 110 determines the write frequency according to a ratio of the number of power-on times of the memory device 100 to the total written data, wherein the higher the ratio is, the higher the probability of errors caused by sudden power failures in the wear leveling related data (e.g., the erase times table 300, the wear leveling times table 400, the current wear leveling status, the garbage collection status, etc.), and therefore the write frequency needs to be increased. For example, when the ratio is in a first range with a higher value, the flash memory controller 110 determines a higher first write frequency; and when the ratio is in a second range with a lower value, the flash memory controller 110 determines a lower second write frequency.

[0056] In a fourth embodiment, the flash memory controller 110 may determine the write frequency based on at least two of the three ratios described in the first to third embodiments. For example, assuming that the ratio of the total wear leveling times to the total erase times is represented by "A", the ratio of the maximum erase times difference to the wear leveling threshold is represented by "B", and the ratio of the power-on times of the memory device 100 to the total written data is represented by "C", the flash memory controller 110 may use one of the following four formulas (1) to (4) to calculate a specific parameter D:

[0057] D=W1*A+W2*B……………………………………………………(1);

[0058] D=W1*A+W3*C……………………………………………………(2);

[0059] D=W2*B+W3*C……………………………………………………(3);

[0060] D=W1*A+W2*B+W3*C…………………………………………(4);

[0061] Wherein W1, W2, and W3 are weights corresponding to A, B, and C, respectively. In this embodiment, a higher value of the specific parameter D indicates that the write frequency needs to be increased. For example, when the specific parameter D is in a first range with a higher value, the flash memory controller 110 determines a higher first write frequency; and when the specific parameter D is in a second range with a lower value, the flash memory controller 110 determines a lower second write frequency.

[0062] It should be noted that the ranges and the number of write frequencies mentioned in the above embodiments are only used as examples. In other embodiments, the flash memory controller 110 can determine which of the multiple ranges the specific parameter D belongs to to determine the corresponding write frequency. As long as a higher specific parameter D corresponds to a higher write frequency, the number of multiple ranges can be determined by the designer.

[0063] In step 706, the flash memory controller 110 determines the frequency of subsequently copying the wear leveling related data from the buffer memory 116 to the flash memory module 120 according to the write frequency determined in step 704. Specifically, if the flash memory controller 110 determines the first write frequency to be higher in step 704, the flash memory controller 110 will copy the wear leveling related data from the buffer memory 116 to the flash memory module 120 more frequently to avoid distortion of the wear leveling related data due to sudden power failure; and if the flash memory controller 110 determines the second write frequency to be lower in step 704, the flash memory controller 110 will extend the cycle of writing the wear leveling related data to the flash memory module 120, that is, the wear leveling related data will be written to the flash memory module 120 again after a longer interval to avoid affecting the efficiency of the memory device 100.

[0064] In brief, the present invention can effectively reduce the problem of distortion of wear leveling related data due to sudden power failure by dynamically adjusting the write frequency of wear leveling related data to the flash memory module according to multiple parameters, and can also avoid excessive impact on the performance of the memory device as a whole.

[0065] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A control method for a memory device, wherein the memory device comprises a flash memory module, the flash memory module comprises a plurality of blocks, and the control method comprises: updating wear leveling related data temporarily stored in a buffer memory; Get multiple parameters; Determining a writing frequency according to the plurality of parameters; and The wear leveling related data is copied from the buffer memory to the flash memory module according to the writing frequency.

2. The control method according to claim 1, characterized in that: The wear leveling related data at least includes an erase count comparison table, wherein the erase count comparison table records the erase count of each block in the plurality of blocks.

3. The control method according to claim 1, characterized in that: The plurality of parameters include a total erase count and a total wear leveling count, wherein the total erase count is the total erase count of the plurality of blocks, and the total wear leveling count is the cumulative erase count of the plurality of blocks due to the wear leveling mechanism.

4. The control method according to claim 1, characterized in that: The step of determining the write frequency according to the plurality of parameters comprises: The writing frequency is determined according to a ratio of the total erasing times to the total wear average times.

5. The control method according to claim 1, characterized in that: The parameters include a maximum erase count difference between blocks and a wear leveling threshold.

6. The control method according to claim 5, characterized in that: The step of determining the write frequency according to the plurality of parameters comprises: The writing frequency is determined according to a ratio of the maximum erasing times difference between blocks to the wear level threshold.

7. The control method according to claim 1, characterized in that: The plurality of parameters include a power-on number of the memory device and a total amount of written data of the flash memory module.

8. The control method according to claim 7, characterized in that: The step of determining the write frequency according to the plurality of parameters comprises: The writing frequency is determined according to a ratio of the power-on times of the memory device to the total written data of the flash memory module.

9. The control method according to claim 4, 6 or 8, characterized in that: The step of determining the write frequency according to the plurality of parameters comprises: When the ratio is within a first range, a first writing frequency is determined as the writing frequency; and When the ratio is within a second range, a second writing frequency is determined as the writing frequency; The value of the first range is higher than that of the second range, and the first writing frequency is higher than the second writing frequency.

10. The control method according to claim 1, characterized in that: The plurality of parameters include a total erase count, a total wear leveling count, a maximum erase count difference between blocks, and a wear leveling threshold; and the step of determining the write frequency according to the plurality of parameters includes: The write frequency is determined according to a ratio of the total erase times to the total wear leveling times and a ratio of the maximum erase times difference between blocks to the wear leveling threshold.

11. The control method according to claim 1, characterized in that: The plurality of parameters include a total erase count, a total wear leveling count, a power-on count of the memory device, and a total write data of the flash memory module; and the step of determining the write frequency according to the plurality of parameters includes: The write frequency is determined according to a ratio of the total erase times to the total wear leveling times and a ratio of the power-on times of the memory device to the total write data of the flash memory module.

12. The control method according to claim 1, characterized in that: The plurality of parameters include a maximum erase count difference between blocks, a wear leveling threshold, a power-on count of the memory device, and a total amount of written data of the flash memory module; and the step of determining the write frequency according to the plurality of parameters includes: The write frequency is determined according to a ratio of the maximum erase times difference between blocks to the wear level threshold value and a ratio of the power-on times of the memory device to the total write data of the flash memory module.

13. The control method according to claim 1, characterized in that: The plurality of parameters include a total erase count, a total wear leveling count, a maximum erase count difference between blocks, a wear leveling threshold, a power-on count of the memory device, and a total write data of the flash memory module; and the step of determining the write frequency according to the plurality of parameters includes: The write frequency is determined according to a ratio of the total erase times to the total wear leveling times, a ratio of the maximum erase times difference between blocks to the wear leveling threshold, and a ratio of the power-on times of the memory device to the total write data of the flash memory module.

14. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module includes a plurality of blocks, and the flash memory controller includes: A read-only memory for storing a program code; a buffer memory; and a microprocessor for executing the program code to control access to the flash memory module; The microprocessor is used to perform the following operations: updating wear leveling related data temporarily stored in the buffer memory; Get multiple parameters; Determining a writing frequency according to the plurality of parameters; as well as The wear leveling related data is copied from the buffer memory to the flash memory module according to the writing frequency.

15. A memory device comprising: a flash memory module comprising a plurality of blocks; and a flash memory controller for accessing the flash memory module; The flash memory controller performs the following operations: updating wear leveling related data temporarily stored in a buffer memory in the flash memory controller; Get multiple parameters; Determining a writing frequency according to the plurality of parameters; as well as The wear leveling related data is copied from the buffer memory to the flash memory module according to the writing frequency.

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