NAND flash memory rereading method, computer equipment and storage medium

Abstract

The embodiment of the present application proposes a NAND flash memory rereading method, a computer device and a storage medium, wherein the method includes: receiving an error correction request for data to be processed; performing error correction processing on the data to be processed according to a preset rereading table and a preset priority queue to obtain target data, wherein the preset rereading table includes multiple voltage offset parameter groups, multiple associated parameter groups and a usage mark. The embodiment of the present application performs error correction processing according to the preset rereading table and the preset priority queue, which can reduce the time consumption of the error correction process and improve the data error correction efficiency of the flash memory.

Description

Technical Field

[0001] The present application relates to the field of flash memory rereading technology, and in particular to a NAND flash memory rereading method, a computer device and a storage medium. Background Art

[0002] In the related art, when the existing flash memory is used under various complex working conditions, read errors will inevitably occur due to internal and external reasons. When a page of the flash memory fails to read at the default voltage, the controller will use multiple sets of voltage offset parameters in the reread table in sequence to reread until the data is completely corrected. The existing reread table consists of multiple sets of voltage offset parameters, which are arranged in a certain order. When correcting data, they will be used in sequence starting from the first set of parameters until the data is corrected or all parameters are exhausted. Since the default voltage read failure caused by different application scenarios requires different offset voltage correction, the reread process in the prior art may use many inappropriate voltage offset parameters, resulting in a long error correction process, affecting read performance and user experience. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a nand flash memory rereading method, a computer device and a storage medium, aiming to reduce the time consumption of the error correction process and improve the data error correction efficiency of the flash memory.

[0004] In a first aspect, an embodiment of the present application provides a NAND flash memory rereading method, comprising:

[0005] receiving an error correction request for data to be processed;

[0006] The data to be processed is error corrected according to a preset rereading table and a preset priority queue to obtain target data, wherein the preset rereading table includes a plurality of voltage offset parameter groups, a plurality of associated parameter groups and a use mark.

[0007] According to some embodiments of the present application, the method further includes:

[0008] Dividing the voltage offset parameter group into a plurality of offset regions according to the first offset amount and the default voltage;

[0009] Obtaining a plurality of negative offset regions and a plurality of positive offset regions according to the plurality of offset regions, wherein the plurality of negative offset regions are located on a first side of the default voltage, and the plurality of positive offset regions are located on a second side of the default voltage;

[0010] The plurality of voltage offset parameter groups are placed in the negative offset region and the positive offset region respectively according to first negative then positive and first small offset then large offset.

[0011] According to some embodiments of the present application, performing error correction processing on the to-be-processed data according to a preset rereading table and a preset priority queue to obtain target data includes:

[0012] Performing error correction processing on the data to be processed using a first voltage offset parameter group in the voltage offset parameter group according to a first order of the rereading table to obtain first data, wherein the first data has not been corrected;

[0013] Performing error correction processing on the first data according to a second voltage offset parameter group in the voltage offset parameter group to obtain second data, wherein the second data is partially correct;

[0014] The second data is error corrected using the associated parameter group according to the second order of the priority queue to obtain the target data.

[0015] According to some embodiments of the present application, before performing error correction processing on the data to be processed using the first voltage offset parameter group in the voltage offset parameter group according to the first order of the rereading table to obtain the first data, the method further includes:

[0016] The usage flag in the reread table is set to 0 and the state of the priority queue is set to empty.

[0017] According to some embodiments of the present application, the method further includes one of the following:

[0018] When the state of the priority queue is not empty, performing error correction processing according to the priority voltage offset parameter group in the priority queue;

[0019] When the state of the priority queue is empty, error correction processing is performed according to a third voltage offset parameter group in the voltage offset parameter groups, wherein the third voltage offset parameter group is the first voltage offset parameter group in the voltage offset parameter groups whose usage mark is 0.

[0020] According to some embodiments of the present application, it further includes:

[0021] When the priority voltage offset parameter group is used, the priority voltage offset parameter group is removed from the priority queue.

[0022] According to some embodiments of the present application, it further includes:

[0023] When the priority voltage offset parameter group or the third voltage offset parameter group is used, the use flag of the priority voltage offset parameter group is set to 1 or the use flag of the third voltage offset parameter group is set to 1.

[0024] According to some embodiments of the present application, when the first data is subjected to error correction processing according to the second voltage offset parameter group in the voltage offset parameter group to obtain the second data, the method further includes:

[0025] The associated parameter group with the usage mark of 0 in the second voltage offset parameter group is added to the priority queue.

[0026] In a second aspect, an embodiment of the present application provides a computer device, including:

[0027] at least one memory;

[0028] at least one processor;

[0029] at least one computer program;

[0030] The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement the NAND flash memory rereading method described in the first aspect above.

[0031] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is used to enable a computer to execute the NAND flash memory rereading method described in the first aspect above.

[0032] According to the technical solution of the embodiment of the present application, at least the following beneficial effects are achieved: first, the embodiment of the present application receives an error correction request for data to be processed; and performs error correction processing on the data to be processed according to a preset rereading table and a preset priority queue to obtain target data, wherein the preset rereading table includes multiple voltage offset parameter groups, multiple associated parameter groups, and a usage mark. The embodiment of the present application performs error correction processing according to the preset rereading table and the preset priority queue, which can reduce the time consumption of the error correction process and improve the data error correction efficiency of the flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0034] Figure 1 It is a flowchart of a nand flash memory rereading method provided by an embodiment of the present application;

[0035] Figure 2 It is a schematic diagram of a process for partitioning a voltage offset parameter group provided by an embodiment of the present application;

[0036] Figure 3is a schematic diagram of a method for arranging voltage offset parameter groups in a rereading table provided by an embodiment of the present application;

[0037] Figure 4 This is a schematic diagram of a process for performing error correction processing on data to be processed provided by an embodiment of the present application;

[0038] Figure 5 is a schematic diagram of the parameter usage sequence provided by an embodiment of the present application;

[0039] Figure 6 It is an overall flow chart of a nand flash memory rereading method provided by an embodiment of the present application;

[0040] Figure 7 is a schematic diagram of a rereading table provided by an embodiment of the present application;

[0041] Figure 8 It is a schematic diagram of the hardware structure of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0042] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0043] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0044] In the description of this application, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0045] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0046] First, some nouns involved in this application are analyzed:

[0047] Flash memory: Flash memory is a non-volatile storage technology that is able to retain data in the event of a power outage. It is a type of electronically erasable programmable read-only memory (EEPROM) that allows data to be erased and rewritten in a single operation. The non-volatility of flash memory means that the data stored in it will not be lost even in the absence of power.

[0048] Priority Queue: A priority queue is an abstract data type that is similar to a queue, but each element has a priority. The order in which the elements are dequeued depends on their priority, not the order in which they entered the queue. In a priority queue, each element has a priority value associated with it. The priority is used to determine the order in which the elements are dequeued. Generally, elements with higher priorities are dequeued before elements with lower priorities.

[0049] When existing flash memory is used under various complex working conditions, read errors will inevitably occur due to internal and external reasons. When a page of the flash memory fails to read at the default voltage, the controller will use multiple sets of voltage offset parameters in the reread table in sequence to reread until the data is completely corrected. The existing reread table consists of multiple sets of voltage offset parameters, which are arranged in a certain order. When correcting data, they will be used in sequence starting from the first set of parameters until the data is corrected or all parameters are exhausted. Since the default voltage read failure caused by different application scenarios requires different offset voltage correction, the reread process in the prior art may use many inappropriate voltage offset parameters, resulting in a long error correction process, affecting read performance and user experience.

[0050] The nand flash memory rereading method provided in the embodiment of the present application is specifically described through the following embodiments. First, the nand flash memory rereading method in the embodiment of the present application is described.

[0051] The embodiments of the present application can acquire and process relevant data based on artificial intelligence technology. Artificial Intelligence (AI) is the theory, method, technology and application system that uses digital computers or machines controlled by digital computers to simulate, extend and expand human intelligence, perceive the environment, acquire knowledge and use knowledge to obtain the best results.

[0052] AI basic technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing technology, operation / interaction systems, mechatronics, etc. AI software technologies mainly include computer vision technology, robotics technology, biometrics technology, speech processing technology, natural language processing technology, and machine learning / deep learning.

[0053] The nand flash memory rereading method provided in the embodiment of the present application relates to the field of flash memory rereading technology. The nand flash memory rereading method provided in the embodiment of the present application can be applied to a terminal, can also be applied to a server side, and can also be software running in a terminal or a server side. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, etc.; the server side can be configured as an independent physical server, or can be configured as a server cluster or a distributed system composed of multiple physical servers, and can also be configured as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can be an application that implements the nand flash memory rereading method, etc., but is not limited to the above forms.

[0054] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0055] It should be noted that in each specific implementation of the present application, when it is necessary to perform relevant processing based on data related to user identity or characteristics such as user information, user behavior data, user historical data, and user location information, the user's permission or consent will be obtained first, and the collection, use, and processing of these data will comply with relevant laws, regulations, and standards. In addition, when the embodiment of the present application needs to obtain the user's sensitive personal information, the user's separate permission or consent will be obtained through a pop-up window or by jumping to a confirmation page. After clearly obtaining the user's separate permission or consent, the necessary user-related data for the normal operation of the embodiment of the present application will be obtained.

[0056] See also Figure 1 , Figure 1 is a flow chart of a nand flash memory rereading method provided by an embodiment of the present application; Figure 1As shown, a nand flash memory rereading method provided by an embodiment of the present application includes but is not limited to steps S110-S120, and each step is introduced in turn below.

[0057] Step S110, receiving an error correction request for data to be processed;

[0058] Step S120 , performing error correction processing on the data to be processed according to a preset rereading table and a preset priority queue to obtain target data, wherein the preset rereading table includes a plurality of voltage offset parameter groups, a plurality of associated parameter groups and a use mark.

[0059] In one embodiment, the system receives a request, which includes data that needs to be error-corrected. After receiving the error-correction request for the data to be processed, the data to be processed is error-corrected according to a preset plurality of voltage offset parameter groups, a plurality of associated parameter groups, a use tag, and a preset priority queue. The plurality of voltage offset parameter groups, the plurality of associated parameter groups, and the use tag are used to adjust the read voltage to correct the read error caused by the voltage offset. The reread table is used to reread and correct the error by adjusting the voltage offset value when an error that cannot be corrected by the error correction code (ECC) occurs during the data reading process. The priority queue is used to manage tasks or data of different priorities in the error correction process. It ensures that high-priority tasks or data can be processed first, so as to obtain the target data, thereby reducing the time consumption of the error correction process and improving the data error correction efficiency of the flash memory.

[0060] It should be noted that for the definition of associated parameter groups, the associated parameters of a group of parameters are the parameter groups with the closest "distance". Assuming that the nth group of voltage offset parameters are Xn, Yn, and Zn, taking the first group of parameters as an example, define the "distance" of other parameter groups to the first parameter group. The "distance" from the first group of parameters to the nth group of parameters is (Xn-X1)^2 + (Yn-Y1)^2 + (Zn-Z1)^2. An and Bn in the figure represent the two groups of parameters closest to the nth group of parameters. For example, if A1 and B1 are equal to 3 and 5 respectively, it means that the third group of parameters is the shortest "distance" to the first group of parameters, and then the fifth group.

[0061] See also Figure 2 , Figure 2 is a schematic diagram of a process for partitioning a voltage offset parameter group provided in an embodiment of the present application; Figure 2 As shown, a nand flash memory rereading method provided by an embodiment of the present application includes but is not limited to steps S210-S230, and each step is introduced in turn below.

[0062] Step S210, dividing the voltage offset parameter group into a plurality of offset regions according to the first offset amount and the default voltage;

[0063] Step S220, obtaining a plurality of negative offset regions and a plurality of positive offset regions according to the plurality of offset regions, wherein the plurality of negative offset regions are located on a first side of a default voltage, and the plurality of positive offset regions are located on a second side of the default voltage;

[0064] Step S230 , placing multiple voltage offset parameter groups in the negative offset area and the positive offset area respectively according to first negative then positive and first small offset then large offset.

[0065] In one embodiment, the voltage offset parameter group is divided into a plurality of offset zones, and the voltage offset parameter group is divided based on the following two key factors: a first offset and a default voltage. The first offset refers to the voltage change relative to the default voltage, and the default voltage is the reference voltage when the system is operating normally. Through this division, the voltage offset parameter group can be more effectively managed and adjusted to adapt to different operating conditions. A negative offset zone and a positive offset zone are further distinguished from the plurality of offset zones. The negative offset zone is located on the first side of the default voltage (usually refers to the area below the default voltage), while the positive offset zone is located on the second side of the default voltage (usually refers to the area above the default voltage). This distinction helps to more accurately control the direction and amplitude of the voltage offset during the voltage adjustment process. The voltage offset parameter group is placed in the negative offset zone and the positive offset zone in an orderly manner. The placement order follows the principles of "negative first, positive later" and "small offset first, large offset later". In the negative offset zone, the parameter group with a smaller negative offset will be placed first, and in the positive offset zone, the parameter group with a smaller positive offset will also be placed first. This orderly placement method helps to optimize the voltage adjustment process and ensure the reasonable application of the voltage offset parameter group.

[0066] See also Figure 3 , Figure 3 It is a schematic diagram of a method for arranging voltage offset parameter groups in a rereading table provided in an embodiment of the present application.

[0067] It should be noted that all voltage offset parameter groups are represented by dots and divided into several regions according to the size of the offset, and these voltage offset parameter groups are distributed in each region.

[0068] In one embodiment, there are 40 voltage offset parameter groups, which are divided into 8 regions according to positive and negative offsets. Each region has a certain number of voltage offset parameter groups. The voltage offset parameter group (red dot) near the middle of each region is first selected as the parameter group placed in the front column of the re-reading table. Figure 3 The priority order of each area follows two requirements: negative first, positive second, and small offset first, large offset second. Figure 3The dot in the middle of the first negative offset zone (voltage offset parameter group) is numbered 1 in the reread table, while the first positive offset zone is numbered 2, the second negative offset zone is numbered 3, etc. Subsequent parameters can be selected in each zone in turn until the parameter group arrangement is completed. Figure 3 In the table, the numbers next to each voltage offset parameter group are arranged according to this rule, which is the serial number in the re-reading table. This arrangement method enables the error correction process to use the parameters of the correct area to re-read as quickly as possible.

[0069] See also Figure 4 , Figure 4 FIG. 1 is a flow chart of error correction processing of data to be processed provided by an embodiment of the present application; Figure 4 As shown, a nand flash memory rereading method provided by an embodiment of the present application includes but is not limited to steps S410-S430, and each step is introduced in turn below.

[0070] Step S410, performing error correction processing on the data to be processed using a first voltage offset parameter group in the voltage offset parameter group according to a first order of the rereading table to obtain first data, wherein the first data is not corrected;

[0071] Step S420, performing error correction processing on the first data according to the second voltage offset parameter group in the voltage offset parameter group to obtain second data, wherein the second data is partially correct;

[0072] Step S430: Perform error correction processing on the second data using the associated parameter group according to the second order of the priority queue to obtain target data.

[0073] It should be noted that the system uses the first set of parameters in the voltage offset parameter group to perform error correction processing on the processed data according to the first order preset in the rereading table. The purpose of this process is to try to correct the errors in the data, but the first data obtained still contains errors and cannot be corrected. Then the system uses the second set of parameters in the voltage offset parameter group to perform further error correction processing on the first data. This processing process is intended to improve the accuracy of the first data. As a result, the second data obtained is partially correct, but there may still be some uncorrected errors in the data. Then the system uses the associated parameter group to perform final error correction processing on the second data according to the second order of the priority queue. This process uses the characteristics of the priority queue to optimize the order and efficiency of the error correction processing, ensuring that high-priority error correction tasks are executed first. The target data finally obtained is the result after multiple rounds of error correction processing, which is expected to be accurate and reliable.

[0074] In one embodiment, it is assumed that the data of the flash memory fails to be read at the default voltage and enters the data error correction process, and its actual voltage offset is in the third negative offset area. Then the entire re-read error correction process should be as follows: re-read using the previous 1, 2, 3, and 4 sets of voltage offset parameters in sequence, but without correcting the data. Then use the fifth set of voltage offset parameters, which may correct part of the data. Then, according to the associated groups of the fifth set of parameters, the associated groups of the associated groups, the voltage offset parameter group in the third negative offset area is preferentially selected for re-reading to complete the data error correction.

[0075] In one embodiment, when error correction processing is performed on first data according to a second voltage offset parameter group in the voltage offset parameter group to obtain second data, an associated parameter group marked as 0 in the second voltage offset parameter group is added to a priority queue.

[0076] In one embodiment, before using the first voltage offset parameter group in the voltage offset parameter group to perform error correction processing on the processed data to obtain the first data according to the first order of the reread table, the use mark in the reread table is set to 0 and the state of the priority queue is set to empty.

[0077] It should be noted that setting the usage mark in the reread table to 0 means resetting the state of the reread table, ensuring that all voltage offset parameter groups are available and not marked as used during the new error correction process, and setting the state of the priority queue to empty means clearing all elements in the queue so that in the new error correction process, the priority queue can reorganize tasks or data according to the new priority order.

[0078] Specifically, each voltage offset parameter group has a usage mark. Each time before entering the data error correction process, all usage marks need to be set to zero. Each time a certain group of parameters is used for rereading and error correction, the usage mark of the group needs to be set to 1 to indicate that it has been used. By using the usage mark, the voltage offset parameter group can be avoided from being reused.

[0079] In one embodiment, when the state of the priority queue is not empty, error correction processing is performed according to the priority voltage offset parameter group in the priority queue. It can be understood that when the state of the priority queue is not empty, it means that there are already some voltage offset parameter groups with higher priorities in the queue. In this case, the system will perform error correction processing according to the priority voltage offset parameter groups in the priority queue. This method ensures that high-priority parameter groups are used first to improve the efficiency and accuracy of error correction processing.

[0080] See also Figure 5 , Figure 5 It is a schematic diagram of the parameter usage sequence provided in the embodiment of the present application.

[0081] In one embodiment, when a priority voltage offset parameter set is used, the priority voltage offset parameter set is removed from the priority queue.

[0082] In one embodiment, when the first to fourth items in the priority queue are 3, 11, 25, and 9 respectively, the third set of voltage offset parameters will be reread next. After the rereading, the priority queue becomes 11, 25, and 9, and the 11th set of voltage offset parameters will be used next time.

[0083] In one embodiment, when the priority queue is empty, error correction is performed according to a third voltage offset parameter group in the voltage offset parameter groups, wherein the third voltage offset parameter group is the first voltage offset parameter group in the voltage offset parameter groups whose use mark is 0.

[0084] When the priority voltage offset parameter set or the third voltage offset parameter set is used, the use flag of the priority voltage offset parameter set is set to 1 or the use flag of the third voltage offset parameter set is set to 1.

[0085] In one embodiment, the current priority queue is empty, and the first group of voltage offset parameters is used for reread error correction. After partial data is corrected, groups A1 and B1 are added to the priority queue, and group A1 is used for reread error correction next time. If group A1 also corrects partial data, A1's associated groups A(A1) and B(A1) are added to the priority queue. At this time, the priority queue is B1, A(A1), B(A1), and group B1 is used for reread error correction next time.

[0086] See also Figure 6 , Figure 6 is an overall flow chart of a nand flash memory rereading method provided by an embodiment of the present application; Figure 6 As shown, a nand flash memory rereading method provided by an embodiment of the present application includes but is not limited to steps S6001-S6011, and each step is introduced in turn below.

[0087] Step S6001, start;

[0088] Step S6002, set the usage flag in the parameter to 0 and clear the priority queue;

[0089] Step S6003: determine whether the priority queue is empty, if so, execute step S6004, if not, execute step S6005;

[0090] Step S6004, find the first group of unused parameter groups in the reread table;

[0091] Step S6005, find the first parameter group in the priority queue;

[0092] Step S6006, using the group of parameters to perform reread error correction;

[0093] Step S6007, determine whether all data are correct, if so, execute step S6011, if not, execute step S6008;

[0094] Step S6008, determine whether to check part of the data, if so, execute step S6009, if not, execute step S6010;

[0095] Step S6009, add the parameters marked as 0 in the two associated groups of the group of parameters to the priority queue;

[0096] Step S6010, determine whether all parameters have been reread, if so, execute step S6011, if not, execute step S6003;

[0097] Step S6011, end, return result.

[0098] In one embodiment, the data error correction process is entered, and the use marks of the reread table are all set to zero, indicating that no set of voltage offset parameters has been used for rereading in this error correction process. The priority queue is cleared, indicating that there is no priority parameter group. It is determined whether the priority queue is empty. If it is empty, the first set of voltage offset parameters that have not been used is found in the order of the reread table for rereading (use mark == 0). If it is not empty, the first set of voltage offset parameters in the priority queue is obtained, and then the group is removed from the priority queue. Then the group of voltage offset parameters is used for rereading, and the use mark of the group of parameters is set to 1. The rereading result is determined. If all the data is read correctly, the error correction process is terminated; if part of the data is read correctly, the use mark == 0 (i.e., it has not been used) in the two associated groups of the group of voltage offset parameters is added to the priority queue. It is determined whether all voltage offset parameters have been used for rereading. If so, the error correction result is returned. If not, it returns to the step of determining whether the priority queue is empty.

[0099] See also Figure 7 , Figure 7 It is a schematic diagram of a rereading table provided in one embodiment of the present application.

[0100] In one embodiment, when a set of data fails to read at the default voltage, it enters the error correction process, and the correct voltage offset parameter group is 1, 5, and 6, then the error correction process is as follows. Entering the data error correction process, first use the first set of voltage offset parameters to reread, correct part of the data, and then add the associated groups 5 and 9 to the priority queue, and the usage mark of the first group of parameters becomes 1. Because there is a priority queue, the priority queue will be used for the next reread error correction. The priority queue records 5 and 9, so the fifth group of voltage offset parameters is then used for reread error correction, and part of the data is read correctly, and then the fifth group of associated groups 1 and 6 will be added to the priority queue. Because the usage mark of the first group is 1, only the sixth group will be added to the priority queue. The current priority queues are 9 and 6, and the usage mark of the fifth group becomes 1. Because there is a priority queue, the next reread error correction will use the priority queue. The priority queue records 9 and 6, so the 9th group of voltage offset parameters are used for reread error correction. The data cannot be read correctly, and the use mark of the 9th group becomes 1. Because there is a priority queue, the next reread error correction will use the priority queue. The priority queue records 6, so the 6th group of voltage offset parameters are used for reread error correction. All the remaining data are read correctly, and the data error correction process ends.

[0101] The embodiment of the present application also provides a computer device, the computer device comprising: at least one memory, at least one processor, at least one computer program, the at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement any one of the nand flash memory rereading methods in the above embodiments. The computer device can be any intelligent terminal including a tablet computer, a car computer, etc.

[0102] See also Figure 8 , Figure 8 The hardware structure of a computer device according to another embodiment is illustrated. The computer device includes:

[0103] The processor 810 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0104] The memory 820 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 820 can store an operating system and other applications. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 820, and the processor 810 calls and executes the nand flash memory rereading method of the embodiment of this application;

[0105] Input / output interface 830, used to implement information input and output;

[0106] The communication interface 840 is used to realize the communication interaction between the device and other devices. The communication can be realized through a wired manner (such as USB, network cable, etc.) or a wireless manner (such as mobile network, WIFI, Bluetooth, etc.);

[0107] A bus 850 that transmits information between the various components of the device (e.g., the processor 810, the memory 820, the input / output interface 830, and the communication interface 840);

[0108] The processor 810 , the memory 820 , the input / output interface 830 and the communication interface 840 are connected to each other in communication within the device via a bus 850 .

[0109] The embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the above-mentioned NAND flash memory rereading method is implemented.

[0110] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0111] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0112] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0113] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0114] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0115] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0116] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0117] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0118] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0119] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0120] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0121] The preferred embodiments of the present application are described above with reference to the accompanying drawings, but the scope of the rights of the present application is not limited thereto. Any modification, equivalent substitution and improvement made by those skilled in the art without departing from the scope and essence of the present application should be within the scope of the rights of the present application.

Claims

1. A nand flash memory rereading method, characterized in that: include: receiving an error correction request for data to be processed; Performing error correction processing on the data to be processed according to a preset rereading table and a preset priority queue to obtain target data, wherein the preset rereading table includes a plurality of voltage offset parameter groups, a plurality of associated parameter groups and a use mark; Dividing the plurality of voltage offset parameter groups into a plurality of offset regions according to the first offset amount and the default voltage; Obtaining a plurality of negative offset regions and a plurality of positive offset regions according to the plurality of offset regions, wherein the plurality of negative offset regions are located on a first side of the default voltage, and the plurality of positive offset regions are located on a second side of the default voltage; Placing the plurality of voltage offset parameter groups in the negative offset region and the positive offset region respectively according to the order of first negative then positive and first small offset then large offset; The step of performing error correction processing on the data to be processed according to a preset rereading table and a preset priority queue to obtain target data includes: Setting the usage flag in the reread table to 0 and setting the state of the priority queue to empty; Performing error correction processing on the data to be processed using a first voltage offset parameter group among the plurality of voltage offset parameter groups according to a first order of the rereading table to obtain first data, wherein the first data has not been corrected; Performing error correction processing on the first data according to a second voltage offset parameter group among the multiple voltage offset parameter groups to obtain second data, wherein the second data is partially correct; Adding the associated parameter group with the usage mark of 0 in the second voltage offset parameter group to the priority queue; The second data is error corrected using the associated parameter group according to the second order of the priority queue to obtain the target data.

2. The method according to claim 1, characterized in that The method further comprises one of the following: When the state of the priority queue is not empty, performing error correction processing according to the priority voltage offset parameter group in the priority queue; When the state of the priority queue is empty, error correction processing is performed according to a third voltage offset parameter group among the multiple voltage offset parameter groups, wherein the third voltage offset parameter group is the first voltage offset parameter group among the multiple voltage offset parameter groups whose usage mark is 0.

3. The method according to claim 2, characterized in that Also includes: When the priority voltage offset parameter group is used, the priority voltage offset parameter group is removed from the priority queue.

4. The method according to claim 2, characterized in that: Also includes: When the priority voltage offset parameter group or the third voltage offset parameter group is used, the use flag of the priority voltage offset parameter group is set to 1 or the use flag of the third voltage offset parameter group is set to 1.

5. A computer device, characterized in that: include: at least one memory; at least one processor; at least one computer program; The at least one computer program is stored in the at least one memory, and the at least one processor executes the at least one computer program to implement: the method according to any one of claims 1 to 4.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is used to make a computer execute: the method according to any one of claims 1 to 4.

Images