Instruction scheduling optimization method and device based on directed acyclic graph and compiling method

Abstract

The invention provides an instruction scheduling optimization method based on a directed acyclic graph, which comprises the following steps: initializing the directed acyclic graph, constructing a dependency relationship among instructions, and creating a node for each instruction; defining an instruction compounding strategy, using an instruction buffer to store instructions on the directed acyclic graph in sequence, extracting the type of each instruction, and selecting the instruction capable of being compounded in the instruction buffer as a candidate instruction according to the defined instruction compounding strategy; performing instruction composition on the selected candidate instruction, creating a new node for the composite instruction, deleting a precursor instruction node, updating a directed edge on which the composite instruction depends, and constructing a new directed acyclic graph; and on the basis of the updated directed acyclic graph, preferentially scheduling the instruction on the key path, and executing the instruction at the same time. The invention further provides an instruction scheduling optimization device based on the directed acyclic graph and a compiling method, and the device and the method are used in cooperation with the instruction scheduling optimization method.

Description

Technical Field

[0001] The present invention belongs to the technical field of compilers, and in particular relates to an instruction scheduling optimization method, device and compilation method based on a directed acyclic graph. Background Art

[0002] With the complexity of modern processors and the diversification of instruction set architectures (ISAs), compiler optimization plays a vital role in improving processor performance. Instruction scheduling is a key part of compiler optimization, which aims to optimize the execution order of instructions to maximize the use of processor resources and reduce the clock cycles required due to data competition hazards.

[0003] The table scheduling algorithm based on DAG (directed acyclic graph) graph is a commonly used instruction scheduling algorithm in the GCC compiler, which is designed to represent the dependencies between instructions. Although this method can significantly improve the efficiency of the pipeline and reduce pipeline pauses caused by data dependencies, it is mainly based on static analysis and only considers the direct dependencies between instructions, ignoring the indirect dependencies between instructions, and cannot adapt to dynamic changes at runtime. In addition, when processing a large number of instructions, it does not support instruction compounding functions, its optimization effect is limited, and it cannot fully schedule the instruction execution order, resulting in certain limitations in the instruction execution order.

[0004] Therefore, it is necessary to fully optimize its algorithm and improve the flexibility of instruction scheduling, so as to reduce the pause cycle during instruction execution and improve the execution efficiency of instructions. Summary of the invention

[0005] The invention provides an instruction scheduling optimization method based on a directed acyclic graph, which improves the flexibility of instruction scheduling through an instruction compounding method, and assists in an adaptive scheduling strategy. During the instruction execution process, the execution of instructions can be adjusted in real time, thereby improving the execution efficiency of instructions.

[0006] The present invention also provides an instruction scheduling optimization device and a compilation method based on a directed acyclic graph, which are used in conjunction with the instruction scheduling optimization method.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] To achieve one or part or all of the above purposes or other purposes, a technical solution of the present invention provides an instruction scheduling optimization method based on a directed acyclic graph, including: initializing a directed acyclic graph, building dependencies between instructions, creating a node for each instruction, and adding a weight value to the directed edge to represent the delay period of the instruction; defining an instruction compounding strategy, using an instruction buffer to sequentially store instructions on the directed acyclic graph, and extracting each instruction type, and selecting compoundable instructions in the instruction buffer as candidate instructions according to the defined instruction compounding strategy; compounding the selected candidate instructions, creating a new node for the compound instruction, deleting the predecessor instruction node, updating the directed edge on which the compound instruction has dependencies, and building a new directed acyclic graph; based on the updated directed acyclic graph, giving priority to scheduling instructions on the critical path and executing the instructions at the same time.

[0009] The compounding strategy is to compound the current instruction with its predecessor instruction.

[0010] The compound strategy also includes: classifying instructions into load instructions, storage instructions and fixed-point / floating-point operation instructions; when encountering load, fixed-point / floating-point operation, fixed-point / floating-point operation type instructions, adopting a load-fixed-point / floating-point operation instruction compound mode; when encountering fixed-point / floating-point operation, fixed-point / floating-point operation, storage type instructions, adopting a fixed-point / floating-point operation-fixed-point / floating-point operation instruction compound mode; when encountering floating-point multiplication and addition, floating-point division, floating-point square root instructions, giving priority to compounding such instructions.

[0011] It also includes optimizing the compound strategy based on the dependency relationship, calculating the execution time of individual instructions with dependencies and the execution time of compound instructions after the instructions with dependencies are compounded, calculating the ratio of the time cost reduced by the compound instructions to the time cost of individual execution of the instructions with dependencies as the compound benefit score; traversing the candidate instructions, and selecting instruction pairs with high compound benefit scores for compounding.

[0012] The execution time of a single instruction with a dependency relationship is the sum of the delay cycle of the single instruction and the dependency delay time between the instructions; and the execution time of a compound instruction after the instructions with a dependency relationship are combined is the sum of the longest delay cycle of the instructions in the instruction pair and the compound overhead, where the compound overhead is the delay added by the hardware when executing the compound instruction.

[0013] Determining the dependency relationship between the instructions includes performing a dependency analysis on the instructions in the directed acyclic graph, and the dependency analysis includes static dependency analysis and multi-level dependency analysis; the static dependency analysis includes defining the data structure of nodes and edges, identifying the direct data dependency relationship between instructions, and constructing a directed acyclic graph based on the direct dependency relationship; the multi-level dependency analysis includes capturing the direct dependency and indirect dependency relationship between instructions, and marking the indirect dependency relationship on the directed acyclic graph.

[0014] Instructions that do not have data competition risks in the instruction buffer and can be compounded are selected as candidate instructions, and there is no register conflict or operand address overlap between the compound instructions.

[0015] During the instruction scheduling process, instructions with higher dependency depth are scheduled first: among instructions with direct dependencies, instructions with longer dependency chains are scheduled first. During the instruction execution process, weight values ​​are dynamically assigned to instructions with higher latency, and the critical path of the directed acyclic graph is calculated in real time based on the weight values. During the instruction scheduling process, instructions on the critical path are scheduled first.

[0016] An adaptive scheduling strategy is used during instruction execution to dynamically monitor processor performance, collect processor performance data, and feed the data back to the scheduler. The scheduler adjusts the instruction execution order based on the fed-back processor performance data.

[0017] When an instruction takes too long to execute due to a cache miss, if the subsequent instruction does not depend on the cache miss instruction, the scheduler executes the subsequent instruction in advance; when there are frequent pauses in the execution stage in the pipeline, the scheduler reschedules the instruction execution order.

[0018] Another technical solution of the present invention provides an instruction scheduling optimization device based on a directed acyclic graph, which performs instruction scheduling optimization based on the instruction scheduling optimization method based on a directed acyclic graph described above, including a data structure updater, which updates the instruction structure of the directed acyclic graph and the dependency relationship between instructions; a directed acyclic graph updater, which updates the directed acyclic graph based on the update result of the data structure updater, and combines static dependency analysis, multi-level dependency analysis and instruction compound results; a function optimizer, which is used to support the generation function of the introduced compound instructions and the call of the dynamic adjustment function of the adaptive scheduling strategy; a compound instruction generator, which includes using a modified and extended compiler to generate compound instruction encoding, and modifying the extended processor architecture to support the operation of compound instructions; an optimization option generator, which updates the optimization option generator and starts the new optimization function after the function optimizer supports the optimization function.

[0019] Another technical solution of the present invention provides an instruction scheduling optimization compilation method based on a directed acyclic graph, which integrates the above-mentioned instruction scheduling optimization method based on a directed acyclic graph into the RISCV-GUN-TOOLCHAIN ​​compilation suite, including the following steps: Step 1: design a new data structure to represent the directed acyclic graph nodes and dependencies, and add the designed new data structure to the gcc / sched-int.h file; at the same time, add the updated directed acyclic graph function to the gcc / sched-deps.c file; Step 2: write a function for compound instruction operation, generate a new compound instruction, and replace the original instruction in the DAG. Add new mode detection logic and compound operations in the combine.cc file, and define a new compound instruction mode in the riscv.md file; integrate the performance monitoring mode in GCC to allow the collection of processor performance indicators when the instruction is running, and use these indicators to adjust the execution order of instructions; modify the sched-deps.c and sched-rgn.c files, add the adaptive scheduling policy module code, and dynamically adjust the instruction execution order according to the runtime performance feedback to optimize the performance of the processor; Step 3: Expand the compiler according to the encoding format of the compound instruction so that the compiler can support the compilation of the compound instruction; expand and modify the decoding unit, control unit and execution unit corresponding to the processor so that the processor can correctly execute the compound instruction and output the correct result; Step 4: Expand the GCC compiler options and add the adaptive scheduling policy dynamic adjustment function and the compilation options of the instruction compound function in the gcc / opt.cc file.

[0020] Compared with the prior art, the beneficial effects of the present invention mainly include: the instruction scheduling optimization method, device and compilation method based on directed acyclic graph proposed by the present invention integrate the method of multi-level dependency analysis and compound instruction to construct a directed acyclic graph; the compound method supports the compounding between load instructions, storage instructions, and fixed-point / floating-point operation instructions; and the compound strategy of compounding with the predecessor node is adopted in the compound instruction generation. The use of an adaptive scheduling strategy in the scheduling process can effectively improve the flexibility of instruction scheduling and the performance of the processor, reduce the pause cycle of instruction execution, and improve the execution efficiency of instructions.

[0021] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 This is a flow chart of the instruction scheduling algorithm specified in the present invention.

[0024] Figure 2 It is a schematic diagram of the optimized DAG of the present invention.

[0025] Figure 3 It is an integrated schematic diagram of the instruction scheduling method of the present invention.

[0026] Figure 4 Schematic diagram of the instruction scheduling optimization device of the present invention DETAILED DESCRIPTION

[0027] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0028] Embodiment 1 Embodiment 1 provides an instruction scheduling optimization method based on a directed acyclic graph, including: initializing a directed acyclic graph, constructing dependencies between instructions, creating a node for each instruction, and adding a weight value to the directed edge to represent the delay cycle of the instruction; defining an instruction compounding strategy, using an instruction buffer to sequentially store instructions on the directed acyclic graph, and extracting each instruction type, selecting instructions that can be compounded in the instruction buffer as candidate instructions according to the defined instruction compounding strategy; compounding the selected candidate instructions, creating a new node for the compound instruction, deleting the predecessor instruction node, and updating the directed edge with dependencies of the compound instruction, and constructing a new directed acyclic graph; on the basis of the updated directed acyclic graph, preferentially scheduling instructions on the critical path, and executing the instructions at the same time. The present invention can refine the directed acyclic graph by analyzing the dependencies between instructions, and compound the instructions at the same time, so as to improve the throughput and execution efficiency of the instructions.

[0029] The following is an explanation of the specific implementation process of the solution of the first embodiment in conjunction with the accompanying drawings. Figure 1 as well as Figure 2 The instruction scheduling optimization method based on directed acyclic graph of the present embodiment 1 comprises the following steps: Step 1: Optimize the DAG graph (directed acyclic graph) Step 1-1: Initialize the DAG graph, build the dependency relationship between instructions, create a node for each instruction, the node is used to represent the instruction, and the dependency depth of the instruction is marked on the node. At the same time, add weight values ​​to the directed edges to represent the delay cycle of the instruction, and then calculate the critical path in the DAG graph (calculating the critical path of the DAG graph is mainly to find the longest path from the starting point to the end point. The total execution time of all tasks on this path determines the shortest completion time of the entire project. The operation time on the critical path refers to the sum of the weight values ​​attached to the directed edges on this path). Initialize the dependency relationship between instructions in the basic block.

[0030] Step 1-2: Analyze the dependencies between instructions, including static dependency analysis and multi-level dependency analysis. Static dependency analysis includes static data flow analysis to identify the direct data dependencies between instructions. Static dependency analysis mainly identifies the direct predecessor and successor instructions (i.e., dependencies) of each instruction. After completing the static data analysis, a preliminary DAG graph is constructed based on the dependencies.

[0031] After constructing the preliminary DAG graph, a multi-level dependency analysis method is used to capture the deep dependencies between instructions, including direct dependencies and indirect dependencies (dependencies across one or more instructions, for example, if an addition instruction depends on the result of the previous instruction, then the previous instruction is the direct dependent instruction of the addition instruction. If there is a subsequent calculation instruction that depends on the result of the addition instruction, then the previous instruction is the indirect dependent instruction of the subsequent calculation instruction) to solve the bottleneck of static dependency analysis and establish a more sophisticated dependency graph relationship.

[0032] Step 1-3: Perform the compounding of instructions. Before compounding instructions, it is necessary to define the compounding strategy. The compounding strategy adopted is the strategy of compounding with the predecessor instruction, giving priority to compounding the current instruction with its predecessor instruction. The goal of this compounding is to improve the execution efficiency of instructions by reducing the number of instructions while ensuring that the instruction dependency relationship is not destroyed. At the same time, the execution cycle of instructions can be reduced through instruction compounding to improve the execution efficiency of instructions.

[0033] When encountering a specific instruction type, the present application also provides a special compound strategy, specifically, classifying the instructions into load instructions, storage instructions, and fixed-point / floating-point operation types. Therefore, the following three compound modes can be defined: load-fixed-point / floating-point operation, fixed-point / floating-point-fixed-point / floating-point operation, and fixed-point / floating-point operation-storage.

[0034] When encountering load, fixed-point / floating-point operation, fixed-point / floating-point operation type, the composite mode of "load-fixed-point / floating-point operation" is adopted to composite the load instruction with the fixed-point / floating-point operation; When encountering fixed-point / floating-point operations, fixed-point / floating-point operations, and storage types, the composite mode of "fixed-point / floating-point operations-fixed-point / floating-point operations" is adopted; Floating-point multiplication and addition, floating-point division, and floating-point square root instructions have longer cycles and are likely to become instructions on the critical path. When such instructions can be compounded, they are compounded first.

[0035] The specific instruction compounding process is as follows: 1-3-1: Select candidate instructions, use an instruction buffer to store some instructions in the DAG graph in sequence (for example, sequentially fetch the first dozen instructions), extract the type of each instruction, and determine whether it belongs to the category of load, fixed-point / floating-point operation, or storage instruction; According to the compounding strategy defined above and the dependencies between instructions, compoundable instructions with no data hazards in the instruction buffer are selected as candidate instructions. These instructions need to conform to the defined compounding mode while ensuring that there are no conflicts in registers and no overlap in operand addresses.

[0036] 1-3-2: Based on the analysis results of the compound strategy, the candidate instructions are compounded. After the compound operation, a new node is created for the compound instruction, and the predecessor instruction node is deleted. At the same time, the dependent directed edges related to the compound instruction are updated to reduce unnecessary dependency chains.

[0037] After the compound operation is executed, a compound instruction that performs multiple operations in the same cycle will be generated. In the DAG graph, the compound instruction is processed as a single unit, which reduces the length of the dependency chain and the complexity of the dependencies between instructions, thereby improving the instruction throughput and overall execution efficiency.

[0038] As an optional method, when selecting candidate instructions for compounding based on the compound strategy, the compound strategy can be optimized. Specifically, a machine learning algorithm (decision tree) is used to train the model to predict compound returns. The type of instruction, critical path length, directed edge weight, and node weight are used as input, and the compound return score is used as output. The calculation formula for the selected features of the compound return score is performed (taking instructions I1 and I2 as examples): 1) Cost of executing a single instruction: Cs=L(I1)+L(I2)+D(I1,I2); Where L(I): delay cycle of instruction I; D(I1, I2): dependency delay between instruction I1 and instruction I2; 2) Compound instruction execution cost Cf = Max(L(I1), L(I2)) + composite overhead; Compound overhead: refers to the delay added by the hardware to execute compound instructions (assuming it is 0.5 cycles).

[0039] 3) Calculate compound returns Compound return = (Cs-Cf) / Cs.

[0040] Traverse the candidate instructions and prioritize the instruction pairs with the highest scores for compounding.

[0041] 1-3-3: Build a new DAG graph. Based on the results of comprehensive analysis of static dependencies, multi-level dependencies and compound instructions, create a new node for the compound instruction. At the same time, update the current instruction node to a compound instruction node, delete the predecessor node, adjust the weight value, update the dependency depth between instructions, reduce unnecessary dependency chains, and build a new DAG graph.

[0042] Step 2: Instruction Scheduling During the instruction scheduling process, instructions with higher dependency depth are scheduled first to ensure that instructions on the critical path are scheduled first, making the processor execution more efficient and reducing the impact of the critical path on the overall processor performance.

[0043] The dependency depth includes static dependency depth and dynamic dependency depth. The static dependency depth refers to the length of the data chain between instructions. The longer the length, the higher the depth. The dynamic dependency depth mainly considers runtime factors and dynamically adjusts the dependency weight. For example, the weight of high-latency multiplication and division instructions is increased. At this time, the weighted path will be scheduled first.

[0044] Step 3: Instruction Execution Step 3-1: During the instruction execution process, an adaptive scheduling strategy is used to monitor the processor's performance indicators in real time, mainly the cache hit rate and the number of pipeline pauses, and the monitored data is fed back to the scheduler. The scheduler dynamically adjusts the scheduling order of instructions based on the performance feedback and optimizes the subsequent scheduling process.

[0045] Specifically: when it is found that an instruction takes too long to execute due to a cache miss, and there are some subsequent instructions that do not depend on the result of this instruction, the scheduler will execute these subsequent instructions in advance to make full use of the processor resources and avoid the processor being idle. If it is found that the pipeline frequently pauses at a certain execution stage, the scheduler will reschedule the order of instruction execution to minimize the number and time of pipeline pauses and improve the overall execution efficiency and performance of the processor.

[0046] Step 3-2: Loop scheduling execution The instructions in the scheduler are scheduled and executed step by step until all instructions are executed.

[0047] Embodiment 2 Embodiment 2 provides an instruction scheduling optimization compilation method based on a directed acyclic graph. Embodiment 2 integrates the optimized scheduling method in Embodiment 1 into the RISCV-GNU-TOOLCHAIN ​​compilation suite. Figure 3 , the specific steps are as follows: Step 1: Modify the GCC source code Step 1-1: Define a new data structure GCC uses GIMPLE and RTL as intermediate representations to optimize the code, so at these stages the data structure is extended to build a DAG graph of instructions and to store information about the new DAG graph.

[0048] The gcc / sched-int.h file mainly defines the internal data structure related to instruction scheduling, and redefines the new data structure to represent the relationship between DAG nodes and dependencies so that it corresponds to the nodes and dependencies of the updated DAG graph.

[0049] Step 1-2: Build DAG graph The gcc / sched-deps.c file is responsible for generating the DAG graph.

[0050] Add the updated DAG graph functions to the gcc / sched-deps.c file to ensure that they can be used normally during the GCC optimization phase.

[0051] Step 2: Update and optimize functions Step 2-1: Compound Instructions According to the compound strategy of compounding with the predecessor instruction, the instruction pattern detection mechanism of GCC and the implementation method of compound instructions are extended to find the instructions that can be compounded in the DAG graph. The function of compound instruction operation is written to generate new compound instructions and replace the original instructions in the DAG.

[0052] Add new mode detection logic and compound operations in the combine.cc file, and define new compound instruction modes in the riscv.md file.

[0053] Step 2-2: Adaptive adjustment strategy Integrate performance monitoring mode in GCC, allowing you to collect performance indicators about the processor when instructions are running, such as cache hit rate, pipeline stall times, etc. Use these indicators to adjust the scheduling strategy during compilation.

[0054] Modify the sched-deps.c and sched-rgn.c files, add the adaptive scheduling policy module code, and dynamically adjust the instruction scheduling order according to runtime performance feedback to optimize performance.

[0055] Step 3: Adding a Compound Instruction The compiler and processor do not support compound instructions. Compound instructions need to be formatted according to the compound instruction type, including the instruction's opcode, function code, and register information. It should be noted that when the compound instruction mode is "fixed-point / floating-point operation-fixed-point / floating-point operation" mode, three registers are required, and the original instruction format needs to be readjusted for instruction encoding.

[0056] The compiler is extended according to the encoding format of the compound instruction in the compiler, so that the compiler can support the compilation of the compound instruction and can normally enable the instruction scheduling function after adding the compound instruction.

[0057] Modifications and extensions are made to the decoding unit, control unit and execution unit corresponding to the processor so that the processor can correctly execute the compound instruction and output the correct result.

[0058] Adding instructions to the compiler and the processor is a conventional technique in the art, which is not the invention point of the present application and will not be described in detail here.

[0059] Step 4: Integrate compiler optimization options In order to enable the new optimization function, it is necessary to extend the compiler options of GCC. Add the compile options that control the adaptive scheduling function and the instruction compound function in the gcc / opt.cc file.

[0060] Embodiment 3 Embodiment 3 provides an instruction scheduling optimization device based on a directed acyclic graph, see Figure 4 , including a data structure updater, which updates the instruction structure and inter-instruction dependencies of the directed acyclic graph; The directed acyclic graph updater updates the directed acyclic graph based on the update results of the data structure updater, combined with static dependency analysis, multi-level dependency analysis and instruction compound results; Function optimizer, used to support the generation of introduced compound instructions and the calling of adaptive scheduling strategy dynamic adjustment function; A compound instruction generator, including modifying a compiler and a processor, using a modified and extended compiler to generate compound instruction encoding and modifying an extended processor architecture to support operations of compound instructions; Optimization option generator, after the function optimizer supports the optimization function, update the optimization option generator and enable the new optimization function.

[0061] The above is a detailed introduction to the instruction scheduling optimization method, device and compilation method based on a directed acyclic graph provided by the present invention. The structure and working principle of the present invention are described in detail using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for optimizing instruction scheduling based on a directed acyclic graph, characterized in that: include: Initialize a directed acyclic graph, build dependencies between instructions, create a node for each instruction, and attach weight values ​​to directed edges to represent the delay period of the instruction; An instruction compounding strategy is defined, and instructions on the directed acyclic graph are sequentially stored using an instruction buffer, and each instruction type is extracted, and instructions that can be compounded in the instruction buffer are selected as candidate instructions according to the defined instruction compounding strategy; Perform instruction compounding on the selected candidate instructions, create new nodes for the compound instructions, delete the predecessor instruction nodes, update the directed edges that the compound instructions have dependencies on, and construct a new directed acyclic graph; Based on the updated directed acyclic graph, the instructions on the critical path are scheduled preferentially and executed simultaneously.

2. The instruction scheduling optimization method based on directed acyclic graph according to claim 1, characterized in that: The compounding strategy is to compound the current instruction with its predecessor instruction.

3. The instruction scheduling optimization method based on directed acyclic graph according to claim 2, characterized in that: The composite strategy also includes: classifying instructions into load instructions, storage instructions, and fixed-point / floating-point operation instructions; When encountering instructions of the load, fixed-point / floating-point operation, or fixed-point / floating-point operation type, the load-fixed-point / floating-point operation instruction composite mode is adopted; When encountering fixed-point / floating-point operations, fixed-point / floating-point operations, and storage type instructions, the fixed-point / floating-point-fixed-point / floating-point operation instruction composite mode is adopted; When encountering floating-point multiplication and addition, floating-point division, and floating-point square root instructions, these instructions are compounded first.

4. The instruction scheduling optimization method based on directed acyclic graph according to claim 1, characterized in that: It also includes optimizing the compound strategy according to the dependency relationship, calculating the execution time of the individual instructions with the dependency relationship and the execution time of the compound instructions after the instructions with the dependency relationship are compounded, and calculating the ratio of the time cost reduced by the compound instructions to the time cost of the individual execution of the instructions with the dependency relationship as the compound benefit score; Traverse the candidate instructions and select instruction pairs with high compound benefit scores for compounding.

5. The instruction scheduling optimization method based on directed acyclic graph according to claim 4, characterized in that: The execution time of a dependent instruction is the sum of the delay cycle of the independent instruction and the dependent delay time between the instructions. The execution time of the compound instruction after the instructions with dependency relationship are compounded is the sum of the longest delay cycle of the instructions in the instruction pair and the compound overhead, where the compound overhead is the delay added by the hardware executing the compound instruction.

6. The instruction scheduling optimization method based on directed acyclic graph according to claim 1, characterized in that: Determining the dependency relationship between the instructions includes performing dependency analysis on the instructions in the directed acyclic graph, wherein the dependency analysis includes static dependency analysis and multi-level dependency analysis; The static dependency analysis includes defining the data structure of nodes and edges, identifying the direct data dependency relationship between instructions, and constructing a directed acyclic graph based on the direct dependency relationship; The multi-level dependency analysis includes capturing direct dependencies and indirect dependencies between instructions, and marking the indirect dependencies on a directed acyclic graph.

7. The instruction scheduling optimization method based on directed acyclic graph according to claim 1, characterized in that: Instructions that do not have data competition risks in the instruction buffer and can be compounded are selected as candidate instructions, and there is no register conflict or operand address overlap between the compound instructions.

8. The instruction scheduling optimization method based on directed acyclic graph according to claim 6, characterized in that: During instruction scheduling, instructions with higher dependency depth are scheduled first: among instructions with direct dependencies, instructions with longer dependency chains are scheduled first; During the execution of instructions, weight values ​​are dynamically assigned to instructions with higher delays, and the critical path of the directed acyclic graph is calculated in real time based on the weight values. During the instruction scheduling process, instructions on the critical path are scheduled first.

9. The instruction scheduling optimization method based on directed acyclic graph according to claim 1, characterized in that: An adaptive scheduling strategy is used during instruction execution to dynamically monitor processor performance, collect processor performance data, and feed the data back to the scheduler. The scheduler adjusts the instruction execution order based on the fed-back processor performance data.

10. The instruction scheduling optimization method based on directed acyclic graph according to claim 9, characterized in that: When there is an instruction that takes too long to execute due to a cache miss, if the subsequent instruction does not depend on the instruction that missed the cache, the scheduler executes the subsequent instruction in advance; When there are frequent pauses in the execution stage of the pipeline, the scheduler reschedules the instruction execution order.

11. An instruction scheduling optimization device based on a directed acyclic graph, which performs instruction scheduling optimization based on the instruction scheduling optimization method based on a directed acyclic graph according to any one of claims 1 to 10, characterized in that: It includes a data structure updater to update the instruction structure and dependencies between instructions of the directed acyclic graph; The directed acyclic graph updater updates the directed acyclic graph based on the update results of the data structure updater, combined with static dependency analysis, multi-level dependency analysis and instruction compound results; Function optimizer, used to support the generation of introduced compound instructions and the calling of adaptive scheduling strategy dynamic adjustment function; A compound instruction generator, including using a modified and extended compiler to generate compound instruction encoding, and modifying an extended processor architecture to support operations of compound instructions; Optimization option generator, after the function optimizer supports the optimization function, update the optimization option generator and enable the new optimization function.

12. A directed acyclic graph-based instruction scheduling optimization compilation method, which integrates the directed acyclic graph-based instruction scheduling optimization method described in any one of claims 1 to 10 into the RISCV-GUN-TOOLCHAIN ​​compilation suite, characterized in that: The steps include: Step 1: Design a new data structure to represent the nodes and dependencies of the directed acyclic graph, and add the designed new data structure to the gcc / sched-int.h file; at the same time, add the updated directed acyclic graph function to the gcc / sched-deps.c file; Step 2: Write a function for compound instruction operation, generate a new compound instruction, and replace the original instruction in the DAG. Add new mode detection logic and compound operation in the combine.cc file, and define the new compound instruction mode in the riscv.md file. Integrate a performance monitoring mode into GCC, which allows to collect performance metrics about the processor as instructions are executed, and use these metrics to adjust the execution order of instructions; Modify the sched-deps.c and sched-rgn.c files, add the adaptive scheduling strategy module code, and dynamically adjust the instruction scheduling order according to runtime performance feedback to optimize performance; Step 3: Expand the compiler according to the encoding format of the compound instruction so that the compiler can support the compilation of the compound instruction; Expand and modify the decoding unit, control unit and execution unit corresponding to the processor so that the processor can correctly execute the compound instruction and output the correct result; Step 4: Expand the GCC compiler options and add the compilation options of the adaptive scheduling policy dynamic adjustment function and the instruction compound function in the gcc / opt.cc file.

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