A thread data reading and writing method, device, equipment and storage medium

Abstract

The present application discloses a thread data reading and writing back method, device, equipment and storage medium, which relates to the field of data reading and writing, including: marking several operands based on the operand types of several operands in the current branch thread to obtain corresponding several marked operands; if a read request is received, determining whether the operand corresponding to the request is an operand marked as reusable; if so, reading cache data corresponding to the operand from a preset cache; if not, reading target data corresponding to the operand and saving it to the preset cache; if a write-back request is received, determining whether the operand corresponding to the request is an operand marked as reusable; if so, adding the request to a local cache queue, and merging and writing back the data based on the requests in the queue when the queue is full; if not, writing the data corresponding to the operand into a target register. Thus, the efficiency of data reading and writing can be improved.

Description

Technical Field

[0001] The present invention relates to the field of data reading and writing, and in particular to a thread data reading and writing back method, device, equipment and storage medium. Background Art

[0002] With the development of computer language and software technology, the number of branch tasks that GPGPU (General-Purpose Graphics Processing Unit, GPGPU) needs to handle has increased significantly. In terms of thread branch management, unlike the CPU (Central Processing Unit) which has few threads and uses complex branch logic, GPGPU introduces predicate registers based on the SIMT (Single Instruction Multiple Threads) structure to achieve independent execution of different thread branches. However, compared with sequentially executed programs, branch programs require each branch to collect operands independently. The increase in branches will cause the read and write requests of the register file to double, which will not only increase the execution time of the program, but also further increase the probability of register block conflicts, seriously affecting the overall parallel performance of GPGPU.

[0003] Therefore, it can be seen that how to improve the read and write efficiency of GPGPU registers under multi-branch threads is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a thread data reading and writing method, device, equipment and storage medium to uniformly read the operands independently read by each branch thread, realize data reuse between branches, and merge the operands that need to be written back by each branch separately, so as to realize unified data writing back. The specific scheme is as follows:

[0005] In a first aspect, the present application discloses a thread data reading and writing method, which is applied to a general graphics processor, comprising:

[0006] Performing a marking operation on the operands in the current branch thread based on the operand types of the operands to obtain a number of marked operands corresponding to the operands;

[0007] If a read request is received, determining whether the operand to be read corresponding to the read request is an operand marked as reusable among the marked operands; if so, reading cache data corresponding to the operand to be read from a preset cache; if not, reading target data corresponding to the operand to be read, and saving the target data to the preset cache;

[0008] If a write-back request is received, determine whether the operand to be written back corresponding to the write-back request is an operand marked as reusable among the several marked operands; if so, add the write-back request to the local cache queue, and perform corresponding merge operations and data write-back operations on the requests in the local cache queue when the local cache queue is full; if not, write the data corresponding to the operand to be written back to the target register.

[0009] Optionally, the performing a marking operation on the operands based on the operand types of the operands in the current branch thread to obtain a number of marked operands corresponding to the operands includes:

[0010] Temporary operands used only in the current branch thread and global operands used in other branch threads among the current operands are determined, and the global operands are marked as reusable operands to obtain a plurality of marked operands.

[0011] Optionally, if a read request is received, determining whether the operand to be read corresponding to the read request is an operand marked as reusable among the plurality of marked operands; if so, reading cache data corresponding to the operand to be read from a preset cache; if not, reading target data corresponding to the operand to be read, includes:

[0012] If a read request is received, decoding the read request to determine an operand to be read corresponding to the read request and operand information corresponding to the operand to be read;

[0013] If the operand to be read is an operand marked as readable and reused among the marked operands, then based on the operand information, cache data corresponding to the operand to be read is read and reused from a preset cache;

[0014] If the operand to be read is not an operand marked as reusable among the marked operands, a register number corresponding to the operand to be read is determined based on the operand information, and register data of the register corresponding to the register number is read.

[0015] Optionally, the reading and reusing cache data corresponding to the to-be-read operand from a preset cache based on the operand information includes:

[0016] Reading cache data corresponding to the to-be-read operand from a preset cache based on the operand information, and determining whether the cache data is marked as dirty data;

[0017] If the cached data is not marked as dirty data, reading and reusing the cached data;

[0018] If the cache data is marked as dirty data, the register number corresponding to the operand to be read is determined based on the operand information, and then the register data of the register corresponding to the register number is read.

[0019] Optionally, determining a register number corresponding to the operand to be read based on the operand information, and reading register data of a register corresponding to the register number, includes:

[0020] Determine a register number corresponding to the operand to be read based on the operand information, and determine a register file of a target register corresponding to the register number;

[0021] The register data in the register file is read, and the register data is returned to the register unit corresponding to the target register.

[0022] Optionally, if a write-back request is received, determining whether the operand to be written back corresponding to the write-back request is an operand marked as reusable among the plurality of marked operands; if so, adding the write-back request to a local cache queue, and performing corresponding merge operations and data write-back operations on the requests in the local cache queue when the local cache queue is full; if not, writing the data corresponding to the operand to be written back into a target register, including:

[0023] If a write-back request is received, the write-back request is decoded to determine an operand to be written back in the write-back request, and to determine whether the operand to be written back is an operand marked as write-backable among the marked operands;

[0024] If the operand to be written back is an operand marked as write-back available among the marked operands, the write-back request is added to the local cache queue, and when the local cache queue is in a queue full state, all the write-back requests in the local cache queue are called, and then all the write-back requests are merged to perform a data write-back operation according to the merged request;

[0025] If the operand to be written back is not an operand marked as writable among the several marked operands, write-back operand information corresponding to the operand to be written back is determined based on the write-back request, and the register number corresponding to the operand to be written back is determined according to the write-back operand information, and the corresponding write-back data in the write-back operand information is written back to the register corresponding to the register number.

[0026] Optionally, merging all the write-back requests to perform a data write-back operation according to the obtained merged request includes:

[0027] respectively determining write-back register numbers corresponding to all the write-back requests, and merging all the write-back requests based on the write-back register numbers to obtain a merged request corresponding to the write-back register numbers;

[0028] The write-back data corresponding to the merge request is written back to the merge register corresponding to the write-back register number.

[0029] In a second aspect, the present application discloses a thread data reading and writing device, which is applied to a general-purpose graphics processor, comprising:

[0030] A data marking module, used for performing a marking operation on the operands in the current branch thread based on the operand types of the operands, so as to obtain a plurality of marked operands corresponding to the operands;

[0031] A data reading module, configured to, if a read request is received, determine whether the operand to be read corresponding to the read request is an operand marked as reusable among the plurality of marked operands; if so, read cache data corresponding to the operand to be read from a preset cache; if not, read target data corresponding to the operand to be read, and save the target data to the preset cache;

[0032] A data write back module is used to, if a write back request is received, determine whether the to-be-written-back operand corresponding to the write back request is an operand marked as reusable among the several marked operands; if so, add the write back request to the local cache queue, and perform corresponding merge operations and data write back operations on the requests in the local cache queue when the local cache queue is full; if not, write the data corresponding to the to-be-written-back operand into the target register.

[0033] In a third aspect, the present application discloses an electronic device, comprising:

[0034] Memory, used to store computer programs;

[0035] The processor is used to execute the computer program to implement the thread data reading and writing method as described above.

[0036] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the aforementioned thread data reading and writing method.

[0037] In the present application, a marking operation can be performed on several operands in the current branch thread based on the operand types of the several operands to obtain several marked operands corresponding to the several operands; if a read request is received, it is determined whether the operand to be read corresponding to the read request is an operand marked as reusable among the several marked operands; if so, the cache data corresponding to the operand to be read is read from the preset cache; if not, the target data corresponding to the operand to be read is read and saved to the preset cache; if a write back request is received, it is determined whether the operand to be written back corresponding to the write back request is an operand marked as reusable among the several marked operands; if so, the write back request is added to the local cache queue, and when the local cache queue is full, corresponding merge operations and data write back operations are performed on the requests in the local cache queue; if not, the data corresponding to the operand to be written back is written into the target register.

[0038] It can be seen that the method of the present application can mark several operands in the current branch thread based on the operand type. If a read request is received, it is determined whether the operand corresponding to the read request is an operand marked as reusable; if so, the cache data corresponding to the operand to be read is read from the preset cache; if not, the target data corresponding to the operand to be read is read and saved to the preset cache. If a write-back request is received, it is determined whether the operand to be written back corresponding to the write-back request is an operand marked as reusable; if so, the write-back request is added to the local cache queue, and when the queue is full, the corresponding merge operation and data write-back operation are performed on the requests in the queue; if not, the data corresponding to the operand to be written back is written to the target register. In this way, the operands independently read by each branch thread can be read uniformly to realize data reuse between branches, and the operands that need to be written back by each branch can be merged to realize unified data write-back. The operand collection logic is optimized from both the reading and writing aspects, which effectively improves the reading and writing efficiency of registers. It can effectively alleviate the register block conflict problem caused by thread branches, and thus improve the parallel performance of general-purpose graphics processors to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0040] Figure 1 A schematic diagram of an operand-based data processing architecture disclosed in this application;

[0041] Figure 2 A flow chart of a thread data reading and writing method disclosed in this application;

[0042] Figure 3 A data reading and writing timing diagram based on operands disclosed in this application;

[0043] Figure 4 A schematic diagram of register multiplexing disclosed in this application;

[0044] Figure 5 A flowchart of a specific thread data reading and writing method disclosed in this application;

[0045] Figure 6 Another specific flow chart of the thread data reading and writing method disclosed in this application;

[0046] Figure 7 This is a structural schematic diagram of a thread data reading and writing back device disclosed in this application;

[0047] Figure 8 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] In the prior art, in terms of GPGPU thread branch management, most of the branch threads are executed independently. Compared with sequentially executed programs, branch programs require each branch to collect operands independently. The increase in branches will double the read and write requests of the register file, which will not only increase the execution time of the program, but also further increase the probability of register block conflicts, seriously affecting the overall parallel performance of GPGPU.

[0050] In order to overcome the above-mentioned technical problems, the present application discloses a thread data reading and writing back method, apparatus, device and storage medium to uniformly read the operands independently read by each branch thread, realize data reuse between branches, and merge the operands that need to be written back separately by each branch to realize unified data write back.

[0051] In this application, thread data reading and writing back need to be based on Figure 1The operand-based data processing architecture shown in the figure is mainly composed of three parts: compiler marking unit, read multiplexing unit and write-back merging unit. Among them, the compiler marking unit is implemented by modifying the instruction compilation rules; the read multiplexing unit is implemented by data multiplexing logic and operand collector; the write-back merging unit is implemented by type discrimination and write-back merging logic. Both read and write units are connected to the register file of the multi-plate structure to complete data exchange.

[0052] In the compiler marking unit, the compiler marks operands that meet read multiplexing and write merging, and generates read and write control signals. In the read multiplexing unit, the data multiplexing logic determines the type of operands to be read based on the control information to achieve data cache multiplexing; the operand collector merges the read requests of each branch and reads data from the register file. In the writeback merging unit, the type discrimination logic determines the writeback request type based on the control information and caches the merged requests; the writeback merging logic integrates the writeback requests of each branch and writes the data to the register file.

[0053] See also Figure 2 As shown, an embodiment of the present invention discloses a thread data reading and writing method, which is applied to a general graphics processor, comprising:

[0054] Step S11: performing a marking operation on the operands in the current branch thread based on their operand types to obtain a plurality of marked operands corresponding to the operands.

[0055] In this embodiment, it is necessary to determine temporary operands used only in the current branch thread and global operands used in other branch threads among the current operands, and mark the global operands as reusable operands to obtain several marked operands. Specifically, it is necessary to distinguish the operand types based on the context information of the current branch thread, and it is necessary to determine the operand types of several operands of the current branch thread. According to whether the operands are only used in the current branch thread, the operands are divided into temporary operands and global operands, and then the global operands are marked as reusable operands to obtain several marked operands. Further, as Figure 3 As shown, the compiler marking unit needs to generate corresponding read requests and write-back requests according to the marking information, so that the read multiplexing unit and the write-back merging unit can perform corresponding data read operations or data write-back operations after receiving the corresponding requests.

[0056] Furthermore, when the compiler marking unit generates a read request and a write back request, it is necessary to generate corresponding requests according to the actual situation of the current branch thread, such as Figure 4As shown, there are instructions ADDI, SUBI, and BGE, among which instruction ADDI reads data from register r13 and writes the data back to register r15; instruction SUBI reads data from register r11 and writes the data back to register r11; instruction BGE reads data from register r10 and writes the data back to register r13, and the instructions are used in both branch B / 1100 and branch B / 0011. Therefore, in terms of data reading, register r13 and register r10 may be read multiplexed. In terms of data writing back, since register r11 and register r13 are both read registers and write-back registers, the possibility of them being used for writing back is small, and register r15 may be used for writing back. Therefore, it is necessary to generate a read request and a write-back request.

[0057] Step S12: If a read request is received, determine whether the operand to be read corresponding to the read request is an operand marked as reusable among the several marked operands; if so, read the cache data corresponding to the operand to be read from the preset cache; if not, read the target data corresponding to the operand to be read, and save the target data to the preset cache.

[0058] In this embodiment, Figure 3 As shown, if the read multiplexing unit receives a read request, that is, a read multiplexing instruction, the read request needs to be decoded to determine the operand to be read corresponding to the read request and the operand information corresponding to the operand to be read, wherein the read multiplexing unit is composed of data multiplexing logic and an operand collector, and after receiving the read request, the read request is decoded by the data multiplexing logic, and then the operand information corresponding to the corresponding operand to be read is obtained.

[0059] After decoding is completed, it is necessary to apply for cache space, and then create a collection table through the operand collector and read the operand data. The collection table is used to save operand information. Each collection table contains 3 collection entries, where the entry corresponds to the operand. Each request contains up to 3 operands. The collection entry contains five fields: a valid bit field, indicating whether the operand corresponding to the entry needs to be read; a register number field, indicating the register number where the source operand is located; a mask field, indicating which threads need to read, and setting it indicates that the corresponding thread is valid; a data field, used to store operand data; a ready bit field, indicating whether the operand corresponding to the entry has been read.

[0060] In a specific implementation scenario, if the operand to be read corresponding to the request is an operand marked as readable and reusable among several marked operands, it indicates that the preset cache can store corresponding cache data, and data reuse can be performed based on the cache data. Therefore, the cache data corresponding to the operand to be read can be read and reused from the preset cache based on the operand information; in another specific implementation scenario, if the operand to be read is not an operand marked as reusable among several marked operands, the register number corresponding to the operand to be read is determined based on the operand information, and the register data of the register corresponding to the register number is read. In this way, data reuse between branch threads can be achieved, the process of data reading is simplified, and the data reading efficiency is effectively improved.

[0061] Step S13: If a write-back request is received, determine whether the operand to be written back corresponding to the write-back request is an operand marked as reusable among the several marked operands; if so, add the write-back request to the local cache queue, and perform corresponding merge operations and data write-back operations on the requests in the local cache queue when the local cache queue is full; if not, write the data corresponding to the operand to be written back to the target register.

[0062] In this embodiment, if the write-back merging unit receives a write-back request, that is, a write-back merging instruction, the write-back request is decoded to determine the operand to be written back corresponding to the write-back request, wherein the write-back merging unit is composed of a type discrimination logic and a write-back merging logic. The type discrimination logic decodes the write-back merging control instruction, records the mergeable operands, and also opens a cache queue for the mergeable operands. The request merging logic takes out the requests of each branch from the cache queue according to the mergeable operand information after all the write-back requests of each branch are cached, and then integrates them into a unified operand write-back request.

[0063] In a specific implementation scenario, if the operand to be written back is an operand marked as write-back available among several marked operands, the write-back request is added to the local cache queue, and then when the queue of the local cache queue is full, the write-back requests in the local cache queue are merged. It should be noted that when merging requests, it is necessary to merge requests based on the write-back register number, such as Figure 3 As shown, when merging, the requests whose write-back registers are all r1 are merged, and the same method is used when merging other requests. After the merging is completed, data needs to be written back based on the merged request.

[0064] In another specific implementation scenario, if the operand to be written back is not marked as an operand that can be written back, the write-back operand information corresponding to the operand to be written back is determined based on the write-back request, and the register number corresponding to the operand to be written back is determined based on the write-back operand information, and the corresponding write-back data in the write-back operand information is written back to the register file corresponding to the register number.

[0065] In this way, the operands that need to be written back by each branch can be merged to achieve unified data writing, thereby improving the efficiency of registers for data writing back.

[0066] It can be seen that, through this embodiment, several operands in the current branch thread can be marked based on the operand type. If a read request is received, it is determined whether the operand corresponding to the read request is an operand marked as reusable; if so, the cache data corresponding to the operand to be read is read from the preset cache; if not, the target data corresponding to the operand to be read is read and saved to the preset cache. If a write-back request is received, it is determined whether the operand to be written back corresponding to the write-back request is an operand marked as reusable; if so, the write-back request is added to the local cache queue, and when the queue is full, the corresponding merge operation and data write-back operation are performed on the requests in the queue; if not, the data corresponding to the operand to be written back is written to the target register. In this way, the operands independently read by each branch thread can be read uniformly to realize data reuse between branches, and the operands that need to be written back by each branch can be merged to realize unified data write-back. The operand collection logic is optimized from both the reading and writing aspects, which effectively improves the reading and writing efficiency of registers. It can effectively alleviate the register block conflict problem caused by thread branches, and thus improve the parallel performance of general-purpose graphics processors to a certain extent.

[0067] Based on the above embodiments, it can be seen that the method of the present application can read the operands that need to be read independently by each branch in a unified manner, thereby realizing data reuse between branches. To this end, this embodiment describes in detail how to realize data reuse between branch threads. Figure 5 As shown, an embodiment of the present invention discloses a thread data reading and writing method, comprising:

[0068] Step S21: If a read request is received, the read request is decoded to determine an operand to be read corresponding to the read request and operand information corresponding to the operand to be read.

[0069] In this embodiment, if the read multiplexing unit receives a read request, the read request is decoded to determine the operand to be read corresponding to the read request and the corresponding operand information. Specifically, after the read multiplexing unit receives the read request, the request is decoded through the read multiplexing logic to obtain the operand to be read corresponding to the read request and the operand information corresponding to the operand to be read, and then the corresponding cache space needs to be applied for each operand.

[0070] Step S22: If the operand to be read is an operand marked as readable and reused among the marked operands, cache data corresponding to the operand to be read is read and reused from a preset cache based on the operand information.

[0071] In this embodiment, if the operand to be read is an operand marked as readable and reusable, it is necessary to directly obtain the cache data corresponding to the operand to be read from the preset cache, and determine whether the obtained cache data is marked as dirty data. It should be noted that dirty data is data that is written back multiple times, resulting in the data after writing back being inconsistent with the cached data. If the cache data is not marked as dirty data, the cache data obtained by read reuse is read. It should be further explained that when other branch threads are executed, the data reuse logic queries the operand to be read in the decoded operand information. If the operand is marked as reusable and the data in the cache space is the original data, the cache data is also directly reused.

[0072] Step S23: If the operand to be read is not an operand marked as reusable among the marked operands, determine the register number corresponding to the operand to be read based on the operand information, and read the register data of the register corresponding to the register number.

[0073] In this embodiment, if the operand to be read is not marked as a reusable operand, it indicates that the operand may be received for the first time, and a corresponding collection entry needs to be created for the operand. Based on the content in step S12, it can be known that the collection entry includes five valid fields, namely, a valid bit field, a register number field, a mask field, a data field, and a ready bit field. Therefore, the collection entry corresponding to the operand can be filled based on the operand information corresponding to the operand. If the operand needs to be read, the valid field in the entry is set; then the register number of the entry is set to the register number to be read corresponding to the operand; if the operand is marked in the operand information, the thread mask is expanded to the thread bundle width (that is, the operands of all threads are read); the operand collector reads data from the register file, returns the data to the data field of the entry, and sets the ready field.

[0074] It should be noted that when reading data from a register file, it is necessary to determine the register number corresponding to the operand to be read based on the operand information, and determine the register file of the target register corresponding to the register number, and then read the register data in the register file, and return the register data to the register unit corresponding to the target register.

[0075] It can be seen that in this embodiment, in order to realize data read multiplexing, after receiving the read request, the read request can be decoded to determine the operand to be read corresponding to the read request and the operand information corresponding to the operand to be read. If the operand to be read is an operand marked as readable and reused among several marked operands, the cache data corresponding to the operand to be read is read and reused from the preset cache based on the operand information; if the operand to be read is not an operand marked as reused among several marked operands, the register number corresponding to the operand to be read is determined based on the operand information, and the register data of the register corresponding to the register number is read. In this way, data reuse between branch threads can be realized, the process of data reading is simplified, and the data reading efficiency is effectively improved.

[0076] Based on the above embodiments, it can be known that the method of the present application can merge the operands that need to be written back by each branch separately to achieve unified data write-back. To this end, this embodiment describes in detail how to achieve unified data write-back. Figure 6 As shown, an embodiment of the present invention discloses a thread data reading and writing method, comprising:

[0077] Step S31: If a write-back request is received, the write-back request is decoded to determine the operand to be written back in the write-back request, and to determine whether the operand to be written back is an operand marked as write-backable among several marked operands.

[0078] In this embodiment, if a write-back request is received, the write-back request needs to be decoded by the type discrimination logic in the write-back merging unit to obtain the operand to be written back corresponding to the learning request and the corresponding write-back operand information. It should be noted that if the current thread is in the state of just being powered on, it is necessary to create a local cache queue, and save the write-back request to the local cache queue based on the type of the operand to be written back. If the local cache queue has been created, the write-back request is directly saved to the local cache queue when it is needed. And after determining the operand to be written back, it is necessary to determine whether the operand to be written back is an operand marked as write-backable.

[0079] Step S32: If the operand to be written back is an operand marked as write-back available among the marked operands, the write-back request is added to the local cache queue, and when the local cache queue is in a queue full state, all the write-back requests in the local cache queue are called, and then all the write-back requests are merged to perform a data write-back operation according to the merged request.

[0080] In this embodiment, if the operand to be written back is an operand marked as write-backable among several marked operands, the learning request needs to be added to the local cache queue. If the write-back requests in the local cache queue are full, the write-back requests of all branches are taken out of the queue at one time and the write-back requests are merged.

[0081] Specifically, the process of request merging is as follows: determine the write-back register numbers corresponding to all write-back requests respectively, and merge all write-back requests based on the write-back register numbers to obtain a merged request corresponding to the write-back register number; write back the write-back data corresponding to the merged request to the merged register corresponding to the write-back register number. That is, determine the write-back register corresponding to each write-back request based on the write-back operand information corresponding to each write-back operand, and then merge the write-back requests with the same write-back register, and generate a unified write-back request by merging control information and operands, and write the data into the register file corresponding to the corresponding write-back register.

[0082] Step S33: If the operand to be written back is not an operand marked as writable among the marked operands, then based on the write-back request, the write-back operand information corresponding to the operand to be written back is determined, and according to the write-back operand information, the register number corresponding to the operand to be written back is determined, and the corresponding write-back data in the write-back operand information is written back to the register corresponding to the register number.

[0083] In this embodiment, if the operand to be written back is not an operand marked as writable among several marked operands, it is necessary to determine the register number corresponding to the operand to be written back based on the write-back operand information corresponding to the operand to be written back, and then write the data to the register file corresponding to the register number, and it is also necessary to mark the cached data of the corresponding operand in the read multiplexing unit as "dirty", which means that the data is written back multiple times, resulting in inconsistency between the written-back data and the cached data.

[0084] It can be seen that in this embodiment, if a write-back request is received, the write-back request is decoded to determine the operand to be written back in the write-back request, and to determine whether the operand to be written back is an operand marked as being writeable among several marked operands; if the operand to be written back is an operand marked as being writeable among several marked operands, the write-back request is added to the local cache queue, and when the local cache queue is in a queue full state, all write-back requests in the local cache queue are called, and then all write-back requests are merged to perform data write-back operations according to the merged request; if the operand to be written back is not an operand marked as being writeable among several marked operands, the write-back operand information corresponding to the operand to be written back is determined based on the write-back request, and the register number corresponding to the operand to be written back is determined based on the write-back operand information, and the corresponding write-back data in the write-back operand information is written back to the register corresponding to the register number. In this way, the operands that need to be written back by each branch can be merged to achieve unified write-back of data, thereby improving the efficiency of data write-back.

[0085] See also Figure 7 As shown, an embodiment of the present invention discloses a thread data reading and writing device, which is applied to a general-purpose graphics processor, comprising:

[0086] A data marking module 11 is used to perform a marking operation on the operands in the current branch thread based on their operand types, so as to obtain a number of marked operands corresponding to the operands;

[0087] The data reading module 12 is used for, if a read request is received, determining whether the operand to be read corresponding to the read request is an operand marked as reusable among the plurality of marked operands; if so, reading cache data corresponding to the operand to be read from a preset cache; if not, reading target data corresponding to the operand to be read, and saving the target data to the preset cache;

[0088] The data write back module 13 is used to, if a write back request is received, determine whether the operand to be written back corresponding to the write back request is an operand marked as reusable among the several marked operands; if so, add the write back request to the local cache queue, and perform corresponding merge operations and data write back operations on the requests in the local cache queue when the local cache queue is full; if not, write the data corresponding to the operand to be written back to the target register.

[0089] It can be seen that, through this embodiment, several operands in the current branch thread can be marked based on the operand type. If a read request is received, it is determined whether the operand corresponding to the read request is an operand marked as reusable; if so, the cache data corresponding to the operand to be read is read from the preset cache; if not, the target data corresponding to the operand to be read is read and saved to the preset cache. If a write-back request is received, it is determined whether the operand to be written back corresponding to the write-back request is an operand marked as reusable; if so, the write-back request is added to the local cache queue, and when the queue is full, the corresponding merge operation and data write-back operation are performed on the requests in the queue; if not, the data corresponding to the operand to be written back is written to the target register. In this way, the operands independently read by each branch thread can be read uniformly to realize data reuse between branches, and the operands that need to be written back by each branch can be merged to realize unified data write-back. The operand collection logic is optimized from both the reading and writing aspects, which effectively improves the reading and writing efficiency of registers. It can effectively alleviate the register block conflict problem caused by thread branches, and thus improve the parallel performance of general-purpose graphics processors to a certain extent.

[0090] In some embodiments, the data marking module 11 may specifically include:

[0091] The data marking unit is used to determine temporary operands used only in the current branch thread and global operands used in other branch threads among the current operands, and mark the global operands as reusable operands to obtain a plurality of marked operands.

[0092] In some embodiments, the data reading module 12 may specifically include:

[0093] a read request analysis submodule, configured to decode a read request if one is received, so as to determine an operand to be read corresponding to the read request and operand information corresponding to the operand to be read;

[0094] A first data reading submodule, configured to read cache data corresponding to the operand to be read from a preset cache based on the operand information if the operand to be read is an operand marked as readable and reused among the plurality of marked operands;

[0095] The second data reading submodule is used to determine the register number corresponding to the operand to be read based on the operand information if the operand to be read is not an operand marked as reusable among the several marked operands, and read the register data of the register corresponding to the register number.

[0096] In some embodiments, the first data reading submodule may specifically include:

[0097] A data type determination unit, configured to read cache data corresponding to the operand to be read from a preset cache based on the operand information, and determine whether the cache data is marked as dirty data;

[0098] A read multiplexing unit, configured to read and reuse the cached data if the cached data is not marked as dirty data;

[0099] A data reading unit is used to determine the register number corresponding to the operand to be read based on the operand information if the cache data is marked as dirty data, and then read the register data of the register corresponding to the register number.

[0100] In some embodiments, the second data reading submodule may specifically include:

[0101] a register file determining unit, configured to determine a register number corresponding to the operand to be read based on the operand information, and determine a register file of a target register corresponding to the register number;

[0102] The data return unit is used to read the register data in the register file and return the register data to the register unit corresponding to the target register.

[0103] In some embodiments, the data write-back module 13 may specifically include:

[0104] A write-back request analysis submodule, configured to decode the write-back request if a write-back request is received, so as to determine an operand to be written back in the write-back request, and to determine whether the operand to be written back is an operand marked as write-backable among the marked operands;

[0105] a request merging submodule, configured to add the write-back request to a local cache queue if the operand to be written back is an operand marked as write-back available among the marked operands, and to call all write-back requests in the local cache queue when the local cache queue is in a queue full state, and then merge all the write-back requests to perform a data write-back operation according to the merged request;

[0106] A data write-back submodule is used to determine the write-back operand information corresponding to the operand to be written back based on the write-back request if the operand to be written back is not an operand marked as writable among the several marked operands, and to determine the register number corresponding to the operand to be written back according to the write-back operand information, and to write the corresponding write-back data in the write-back operand information back to the register corresponding to the register number.

[0107] In some embodiments, the request merging submodule may specifically include:

[0108] a request merging unit, configured to respectively determine write-back register numbers corresponding to all the write-back requests, and perform request merging on all the write-back requests based on the write-back register numbers to obtain a merged request corresponding to the write-back register numbers;

[0109] A data write-back unit is used to write the write-back data corresponding to the merge request back to the merge register corresponding to the write-back register number.

[0110] Furthermore, the present application also discloses an electronic device. Figure 8 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0111] Figure 8 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the thread data reading and writing back method disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0112] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0113] In addition, the memory 22 as a carrier for resource storage may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage method may be temporary storage or permanent storage.

[0114] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device 20, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the thread data reading and writing back method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0115] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned disclosed thread data reading and writing back method. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, and no further description will be given here.

[0116] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0117] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0118] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0119] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0120] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A thread data reading and writing method, characterized in that: Applicable to general-purpose graphics processors, including: Performing a marking operation on the operands in the current branch thread based on the operand types of the operands to obtain a number of marked operands corresponding to the operands; If a read request is received, determining whether the operand to be read corresponding to the read request is an operand marked as reusable among the marked operands; if so, reading cache data corresponding to the operand to be read from a preset cache; if not, reading target data corresponding to the operand to be read, and saving the target data to the preset cache; If a write-back request is received, determine whether the operand to be written back corresponding to the write-back request is an operand marked as reusable among the several marked operands; if so, add the write-back request to the local cache queue, and perform corresponding merge operations and data write-back operations on the requests in the local cache queue when the local cache queue is full; if not, write the data corresponding to the operand to be written back to the target register.

2. The thread data reading and writing method according to claim 1, characterized in that: The marking operation on the operands based on the operand types of the operands in the current branch thread to obtain a number of marked operands corresponding to the operands includes: Temporary operands used only in the current branch thread and global operands used in other branch threads among the current operands are determined, and the global operands are marked as reusable operands to obtain a plurality of marked operands.

3. The thread data reading and writing method according to claim 1, characterized in that: If a read request is received, determining whether the operand to be read corresponding to the read request is an operand marked as reusable among the plurality of marked operands; if so, reading cache data corresponding to the operand to be read from a preset cache; If not, then reading the target data corresponding to the operand to be read includes: If a read request is received, decoding the read request to determine an operand to be read corresponding to the read request and operand information corresponding to the operand to be read; If the operand to be read is an operand marked as readable and reused among the marked operands, then based on the operand information, cache data corresponding to the operand to be read is read and reused from a preset cache; If the operand to be read is not an operand marked as reusable among the marked operands, a register number corresponding to the operand to be read is determined based on the operand information, and register data of the register corresponding to the register number is read.

4. The thread data reading and writing method according to claim 3, characterized in that: The step of reading and reusing cache data corresponding to the operand to be read from a preset cache based on the operand information includes: Reading cache data corresponding to the to-be-read operand from a preset cache based on the operand information, and determining whether the cache data is marked as dirty data; If the cached data is not marked as dirty data, reading and reusing the cached data; If the cache data is marked as dirty data, the register number corresponding to the operand to be read is determined based on the operand information, and then the register data of the register corresponding to the register number is read.

5. The thread data reading and writing method according to claim 3, characterized in that: The step of determining the register number corresponding to the operand to be read based on the operand information, and reading the register data of the register corresponding to the register number, comprises: Determine a register number corresponding to the operand to be read based on the operand information, and determine a register file of a target register corresponding to the register number; The register data in the register file is read, and the register data is returned to the register unit corresponding to the target register.

6. The thread data reading and writing method according to any one of claims 1 to 5, characterized in that: If a write-back request is received, determining whether the operand to be written back corresponding to the write-back request is an operand marked as reusable among the marked operands; if so, adding the write-back request to a local cache queue, and performing corresponding merge operations and data write-back operations on the requests in the local cache queue when the local cache queue is full; If not, writing the data corresponding to the operand to be written back into the target register includes: If a write-back request is received, the write-back request is decoded to determine an operand to be written back in the write-back request, and to determine whether the operand to be written back is an operand marked as write-backable among the marked operands; If the operand to be written back is an operand marked as write-back available among the marked operands, the write-back request is added to the local cache queue, and when the local cache queue is in a queue full state, all the write-back requests in the local cache queue are called, and then all the write-back requests are merged to perform a data write-back operation according to the merged request; If the operand to be written back is not an operand marked as writable among the several marked operands, write-back operand information corresponding to the operand to be written back is determined based on the write-back request, and the register number corresponding to the operand to be written back is determined according to the write-back operand information, and the corresponding write-back data in the write-back operand information is written back to the register corresponding to the register number.

7. The thread data reading and writing method according to claim 6, characterized in that: The merging of all the write-back requests to perform a data write-back operation according to the merged requests includes: respectively determining write-back register numbers corresponding to all the write-back requests, and merging all the write-back requests based on the write-back register numbers to obtain a merged request corresponding to the write-back register numbers; The write-back data corresponding to the merge request is written back to the merge register corresponding to the write-back register number.

8. A thread data reading and writing device, characterized in that: Applicable to general-purpose graphics processors, including: A data marking module, used for performing a marking operation on the operands in the current branch thread based on the operand types of the operands, so as to obtain a plurality of marked operands corresponding to the operands; A data reading module, configured to, if a read request is received, determine whether the operand to be read corresponding to the read request is an operand marked as reusable among the plurality of marked operands; if so, read cache data corresponding to the operand to be read from a preset cache; if not, read target data corresponding to the operand to be read, and save the target data to the preset cache; A data write back module is used to, if a write back request is received, determine whether the to-be-written-back operand corresponding to the write back request is an operand marked as reusable among the several marked operands; if so, add the write back request to the local cache queue, and perform corresponding merge operations and data write back operations on the requests in the local cache queue when the local cache queue is full; if not, write the data corresponding to the to-be-written-back operand into the target register.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the thread data reading and writing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store a computer program, wherein the computer program, when executed by a processor, implements the thread data reading and writing back method according to any one of claims 1 to 7.

Images