Method for automatically adjusting DDR reference voltage based on video memory test result

Abstract

The invention provides a DDR reference voltage automatic adjusting method based on a video memory test result. The DDR reference voltage automatic adjusting method comprises the steps that a DDR system is initialized; the DDR system is subjected to video memory testing, and adjustment is not needed when the video memory testing is passed; if the video memory test is not passed and the operation in the RX direction is wrong, adjusting the output driving impedance ODI at the DRAM side; if the operation in the TX direction has an error, if 0 is written into the DRAM side and is judged to be 1, increasing the reference voltage Vref; if 1 is written into the DRAM and is judged to be 0, the reference voltage Vref is turned down. According to the method, the DDRVref is automatically adjusted according to the test result of the video memory, a reliable theoretical basis is provided for adjustment of the Vref, the debugging period of the storage system and a chip can be shortened, meanwhile, the reliability of DDR data is improved, the overall stability of the system is improved, only the highest frequency of one storage system needs to be selected for debugging, and one-by-one frequency debugging is not needed.

Description

Technical Field

[0001] The present invention relates to the field of video memory testing, and more specifically, to a method for automatically adjusting a DDR reference voltage based on a video memory testing result. Background Art

[0002] Double Data Rate SDRAM (DDR) is an improvement on the original Synchronous Dynamic Random Access Memory (SDRAM). One advantage of DDR over other memory types is that it can greatly reduce the memory units on the integrated circuit (IC).

[0003] The 4th generation double data rate synchronous dynamic random access memory (DDR4) and the 4th generation low power double data rate synchronous dynamic random access memory (LPDDR4X) are widely used in the storage system design of various computers and embedded systems. Their main function is to store various data and automatically and quickly access data during program execution. The correctness of DDR data directly determines the stability of the system.

[0004] From DDR SRAM to DDR4, the core voltage is reduced from 2.5V to 1.2V, and the operating frequency of DDR is increased from 400Mbps to 3200Mbps. For LPDDR4X, the core voltage is as low as 0.6V, and the frequency is increased to 4266Mbps. The voltage is lower, the rate is higher, and the accuracy of the reference voltage is also higher. Every time the computer is turned on, the DDR controller will optimize the delay and Vref of the double data rate synchronous dynamic random access memory (DRAM) through a series of calibration and training. Vref depends not only on the DDR data line power supply voltage (Data In / Out Power Supply, VDDQ), but also on the transmission line characteristics and the receiving chip characteristics. Therefore, the value of Vref may be different every time the power is turned on. Different frequencies, DRAMs from different manufacturers, and different printed circuit boards (Print Circuit Board, PCB) will result in different Vref values.

[0005] At present, the configuration of Vref generally involves first obtaining the theoretical value of Vref through theoretical calculation, and then making multiple attempts around the theoretical value. This method takes a lot of time and is very blind. Multiple attempts are required for multiple ODT configurations, which consumes a lot of manpower. Summary of the invention

[0006] The present invention aims at the technical problems in the prior art that, at various frequencies, the reference voltage Vref of the DDR4 / LPDDR4X system is improperly configured, resulting in memory data errors, unstable storage system, and manual blind adjustment of Vref requires a lot of effort. The present invention provides a DDR reference voltage automatic adjustment method based on memory test results, including:

[0007] Step 1, when the DDR system is powered on, the clock and reset of the DDR system are configured based on the highest clock frequency available to a storage system;

[0008] Step 2, performing a video memory test on the DDR system based on a video memory test tool. If the video memory test passes, there is no need to adjust the reference voltage Vref of the DDR system; if the video memory test fails, executing step 3;

[0009] Step 3, determine whether an operation error occurs in the RX direction. If so, adjust the output drive impedance ODI on the DRAM side to be consistent with the output drive impedance ODI on the PHY side. After adjustment, repeat steps 1 to 3 until the read test passes. If not, an operation error occurs in the TX direction, and execute step 4.

[0010] Step 4, if 0 is written to the DRAM side and it is judged as 1, the reference voltage Vref is increased; if 1 is written to the DRAM and it is judged as 0, the reference voltage Vref is lowered; after adjusting the reference voltage Vref, repeat steps 1 to 4 until the video memory test passes.

[0011] Based on the above technical solution, the present invention can also make the following improvements.

[0012] Optionally, in step 1, when the DDR system is powered on, configuring the clock and reset of the DDR system based on the highest clock frequency available to a storage system includes:

[0013] According to the type of DDR system, select the highest clock frequency available for the DDR system to configure the clock and reset of the DDR system, where:

[0014] For DDR4 systems, the commonly used frequencies are 1600 / 1866 / 2133 / 2400 / 2666 / 2933 / 3200Mbps. Choose to debug 3200Mbps directly.

[0015] For LPDDR4X systems, common frequencies are 1600 / 2133 / 2666 / 3200 / 3733

[0016] / 4266Mbps, choose to debug 4266Mbps directly.

[0017] Optionally, the DDR system includes a PHY side and a DRAM side, the PHY side includes a switch SW0 connected between VDDQ and ground, an on-chip termination impedance Ron1, a switch SW1 and an on-chip termination impedance Ron2, wherein the impedances of the on-chip termination impedance Ron1 and the on-chip termination impedance Ron2 are equal, both are Ron, the DRAM side includes a switch SW2 connected between VDDQ and ground, an output driver termination impedance Rtt1, a switch SW3, and an output driver termination impedance Rtt2, wherein the impedances of the output driver termination impedance Rtt1 and the output driver termination impedance Rtt2 are equal, both are Rtt, and a data line is connected between a common end of the on-chip termination impedance Ron1 and the switch SW1 and a common end of the output driver termination impedance Rtt1 and the switch SW3;

[0018] The step 1, when the DDR system is powered on, configures the clock and reset of the DDR system based on the highest clock frequency available to a storage system, and further includes:

[0019] An initial theoretical value of a reference voltage Vref in the TX direction of the DDR system is calculated according to an on-chip termination impedance Ron on the PHY side and an output driver termination impedance Rtt on the DRAM side.

[0020] Optionally, the calculating an initial theoretical value of a reference voltage Vref in a TX direction of a DDR system according to an on-chip termination impedance Ron on a PHY side and an output driver termination impedance Rtt on a DRAM side includes:

[0021] If it is a DDR4 system, for the TX direction, the PHY side performs a write operation, the data is driven from the PHY side, and absorbed at the DRAM side particle end. When 1 is written to the DARM side, switches SW0 and SW2 are closed, switches SW1 and SW3 are disconnected, and the level of the data line is DQ1 = VDDQ; when 0 is written to the DARM side, switches SW1 and SW2 are closed, switches SW0 and SW3 are disconnected, and the level of the data line is The reference voltage Vref is the average value of DQ1 and DQ2.

[0022] If it is an LPDDR4X system, for the TX direction, the PHY side performs a write operation, the data is driven from the PHY side, and absorbed at the DRAM particle end. When 1 is written to the DRAM side, switches SW0 and SW3 are closed, switches SW1 and SW2 are opened, and the level of the data line is When 0 is written to the DARM side, switches SW1 and SW3 are closed, switches SW0 and SW2 are open, the level of the data line is DQ4=0, and the reference voltage Vref value is the average of the levels of DQ3 and DQ4.

[0023] Optionally, the step 2, performing a video memory test on the DDR system based on a video memory test tool, and if the video memory test passes, there is no need to adjust the reference voltage Vref of the DDR system, includes:

[0024] Based on the video memory test tool, the DDR system is subjected to a 0-traversal test and a 1-traversal test. The 0-traversal test is to write all 0s into the DRAM, and then read them out one by one to compare with the expected value 0. If the test result fails, it indicates that 0 is misread or mistakenly written as 1. The 1-traversal test is to write all 1s into the DRAM, and then read them out one by one to compare with the expected value 1. If the test result fails, it indicates that 1 is misread or mistakenly written as 0.

[0025] If both the 0-pass test and the 1-pass test of the DRAM are passed, there is no need to adjust the reference voltage Vref of the DDR system.

[0026] Optionally, the step 3, determining whether an operation error occurs in the RX direction, and if so, adjusting the output drive impedance ODI on the DRAM side to be consistent with the output drive impedance ODI on the PHY side, includes:

[0027] If the video memory test fails, first determine whether there is a problem with the operation in the RX direction. According to the printed information of the video memory test tool, randomly select an error address, write a value to the error address once, and read it out continuously for multiple times. If the results of multiple reads are consistent, it indicates that there is no error in the read operation. If the values ​​read out multiple times are inconsistent, it indicates that the operation in the RX direction is wrong, then adjust the output drive impedance ODI on the DRAM side to be consistent with the output drive impedance ODI on the PHY side.

[0028] Optionally, the step 4, if 0 is written into the DRAM side and it is judged as 1, then the reference voltage Vref is increased; if 1 is written into the DRAM and it is judged as 0, then the reference voltage Vref is decreased; includes:

[0029] When an operation error occurs in the TX direction of the DDR system, if 0 is written to the DRAM side and is judged as 1, the reference voltage Vref is adjusted up by one level based on the initial theoretical value of the reference voltage Vref;

[0030] If 1 is written into the DRAM and is judged as 0, the reference voltage Vref is adjusted down by one level based on the initial theoretical value of the reference voltage Vref.

[0031] The present invention provides a method for automatically adjusting a DDR reference voltage based on a video memory test result. The method includes the following steps: first, the DDR system is initialized; then, a video memory test is performed on the DDR system. If the video memory test is passed, there is no need to adjust the reference voltage Vref; if the video memory test is not passed, if an operation error occurs in the RX direction, the output drive impedance ODI on the DRAM side is adjusted; if an operation error occurs in the TX direction, if 0 is written into the DRAM side and is judged as 1, the reference voltage Vref is increased; if 1 is written into the DRAM and is judged as 0, the reference voltage Vref is decreased. The present invention automatically adjusts the reference voltage Vref of the DDR system according to the result of the video memory test, provides a reliable theoretical basis for adjusting the reference voltage Vref, can shorten the debugging cycle of the storage system and the chip, and at the same time improves the reliability of DDR data, improves the overall stability of the system, and only needs to select the highest frequency of a storage system for debugging, without the need to debug each frequency one by one. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A flow chart of a method for automatically adjusting DDR reference voltage based on video memory test results provided by the present invention;

[0033] Figure 2 This is a diagram showing the training operation principle of the DDR system;

[0034] Figure 3 This is the circuit schematic diagram of the DDR system;

[0035] Figure 4 The figure is an overall flow chart of a method for automatically adjusting DDR reference voltage based on video memory test results. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention can be arbitrarily combined with each other to form a feasible technical solution. This combination is not subject to the constraints of the sequence of steps and / or the structural composition mode, but must be based on the ability of ordinary technicians in this field to achieve. When the combination of technical solutions is contradictory or cannot be achieved, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0037] At present, the method of adjusting the reference voltage Vref for DDR data errors is blind manual adjustment. Trials are performed around the theoretical value of the reference voltage Vref. There is no theoretical basis and multiple adjustments are required. In high-frequency application scenarios, the accuracy of the reference voltage Vref and the on-die termination (ODT) is higher, the reference voltage Vref adjustment accuracy is smaller, and more tests are required. For particles from different manufacturers and DDR Controllers and physical layers (PHY) from different manufacturers, the ODT design is not exactly the same. Different boards and different packages may also have inconsistent ODT. DDR can configure more than 100 Vrefs, and the workload of blind debugging without a theoretical basis is huge.

[0038] In view of this problem, the present invention provides a method for automatically adjusting the DDR reference voltage Vref according to the video memory test result, which provides a reliable theoretical basis for adjusting the reference voltage Vref, can greatly shorten the debugging cycle of the storage system and the chip, and at the same time improve the reliability of DDR data and the overall stability of the system. This method only needs to select the highest frequency of a storage system for debugging, without debugging each frequency one by one.

[0039] Figure 1 A flow chart of a method for automatically adjusting DDR reference voltage based on video memory test results provided by the present invention is shown in FIG. Figure 1 As shown, the method includes:

[0040] Step 1, when the DDR system is powered on, the clock and reset of the DDR system are configured based on the highest clock frequency available to a storage system.

[0041] Among them, see Figure 2, which is the overall flow chart of the DDR reference voltage automatic adjustment method. Before the DDR system is tested for video memory, the DDR system is initialized. When the DDR system is initialized, it is powered on according to the system requirements, the highest clock frequency point available for a storage system is selected, and the clock and reset of the DDR system are configured. According to the backward compatibility characteristics of high-frequency parameters, when the DDR system is initialized, a highest frequency point at which a storage system or DRAM can work is selected for debugging, and its electrical parameters can be directly used for other lower frequencies without further debugging. For DDR4 systems, the commonly used frequencies are 1600 / 1866 / 2133 / 2400 / 2666 / 2933 / 3200Mbps, and 3200Mbps can be directly debugged. For LPDDR4 systems, the commonly used frequencies are 1600 / 2133 / 2666 / 3200 / 3733 / 4266Mbps, and 4266Mbps can be directly debugged. The stabilized ODT and Vref parameters are applicable to other lower frequencies.

[0042] Then configure the DDR Controller and PHY to enable the DDR to complete a series of operations such as activation, charging, refreshing, and training and enter the mission mode.

[0043] The training operation of the DDR system includes Delay Training and Vref Training. Delay Training must be performed before Vref Training, and Delay Training must be passed. The main purpose of Delay Training is to adjust the phase relationship between the data strobe signal (Data strobe, DQS) and the clock (Clock, CK), the input mask signal (InputData Mask, DMI) of DQS and DQ / data, and DQ and DQ in the same data group (Data Byte, DByte), to ensure that the phase relationship between all DQS, DQ, DMI and CK meets the timing requirements of DRAM. The reference voltage Vref Training is based on Delay Training, and a set of delay and Vref configurations are selected for training to find the best Vref and Delay combination to make the data eye diagram optimal. The schematic diagram of the training operation can be seen in Figure 2 .

[0044] Among them, see Figure 3The DDR system includes a PHY side and a DRAM side. The PHY side includes a switch SW0 connected between VDDQ and ground, an on-chip termination impedance Ron1, a switch SW1, and an on-chip termination impedance Ron2, wherein the impedance of the on-chip termination impedance Ron1 and the on-chip termination impedance Ron2 are equal, both are Ron. The DRAM side includes a switch SW2 connected between VDDQ and ground, an output driver termination impedance Rtt1, a switch SW3, and an output driver termination impedance Rtt2, wherein the impedance of the output driver termination impedance Rtt1 and the output driver termination impedance Rtt2 are equal, both are Rtt. A data line is connected between a common end of the on-chip termination impedance Ron1 and the switch SW1 and a common end of the output driver termination impedance Rtt1 and the switch SW3.

[0045] When the DDR system is initialized, the initial theoretical value of the reference voltage Vref in the TX direction of the DDR system is calculated based on the on-chip termination impedance Ron on the PHY side and the output driver termination impedance Rtt on the DRAM side. Figure 3 This is a structural diagram of a DDR system. The initial theoretical value for calculating the reference voltage Vref may differ depending on the type of DDR system.

[0046] Specifically, if it is a DDR4 system, for the TX direction, the PHY side performs a write operation, the data is driven from the PHY side, and absorbed at the DRAM side particle end. When 1 is written to the DARM side, switches SW0 and SW2 are closed, switches SW1 and SW3 are disconnected, and the level of the data line is DQ1 = VDDQ; when 0 is written to the DARM side, switches SW1 and SW2 are closed, switches SW0 and SW3 are disconnected, and the level of the data line is The reference voltage Vref is the average value of DQ1 and DQ2. Among them, DDR4 is of pull-up type, so no matter whether 1 or 0 is written into DDR4, the switch SW3 is always in the off state.

[0047] If it is an LPDDR4X system, for the TX direction, the PHY side performs a write operation, the data is driven from the PHY side, and absorbed at the DRAM particle end. When 1 is written to the DRAM side, switches SW0 and SW3 are closed, switches SW1 and SW2 are opened, and the level of the data line is When 0 is written to the DARM side, switches SW1 and SW3 are closed, switches SW0 and SW2 are open, the level of the data line is DQ4=0, and the reference voltage Vref value is the average of the levels of DQ3 and DQ4. Among them, LPDDR4X is a pull-down type, so no matter whether 1 or 0 is written to LPDDR4X, the switch SW2 is always in the off state.

[0048] After calculating the initial theoretical value of the reference voltage Vref of the RRD system, the Vref value is assigned to the mode register (Mode Register, MR) MR6 according to the DDR4 protocol.

[0049] Step 2: Perform a video memory test on the DDR system based on a video memory test tool. If the video memory test passes, there is no need to adjust the reference voltage Vref of the DDR system; if the video memory test fails, execute step 3.

[0050] After the DDR system is initialized, a video memory test is performed on the DRR system, and the reference voltage Vref is adjusted according to the video memory test result. The process of automatically adjusting the reference voltage Vref according to the video memory test result is as follows: Figure 4 shown.

[0051] The DDR system is tested for memory using the Memtester tool. The main test items include random values, XOR comparison, subtraction, multiplication, division, AND / OR operations, 0 traversal and 1 traversal, etc. Users can test the memory system by giving the size, number of times and test items of the test memory according to their own needs. The present invention mainly focuses on the test results of 0 traversal (walkzero) and 1 traversal (WalkOne). 0 traversal (walkzero) is to write all 0s to the memory space specified by the user for testing, and then read them out one by one for comparison with the expected value 0. If the test result fails, it indicates that 0 is misread or mistakenly written as 1. 1 traversal (walkzero) is to write all 1s to the memory space specified by the user for testing, and then read them out one by one for comparison with the expected value 1. If the test result fails, it indicates that 1 is misread or mistakenly written as 0. If all memory tests pass, there is no need to adjust the reference voltage Vref, and the process ends.

[0052] If the video memory test fails, the video memory test tool Memtester will automatically judge and adjust steps 2 and 3 based on the video memory test results, and automatically restart the system to complete step 1 until the video memory test passes.

[0053] Step 3, determine whether an operation error occurs in the RX direction. If so, adjust the output drive impedance ODI on the DRAM side to be consistent with the output drive impedance ODI on the PHY side. After adjustment, repeat steps 1 to 3 until the read test passes; if not, an operation error occurs in the TX direction, and execute step 4.

[0054] It is understandable that when the video memory test fails, there may be an error in the operation in the RX direction or an error in the operation in the TX direction. In the present invention, the judgment of errors in the TX direction and the RX direction is as follows: by repeatedly reading the data of the same address for comparison, it can be judged whether the data in the RX direction is wrong. If the repeatedly read data is inconsistent, it indicates that the data in the RX direction is wrong, and if the repeatedly read data is consistent, it indicates that the data in the TX direction is wrong.

[0055] Specifically, when the video memory test fails, first determine whether there is a problem with the operation in the RX direction. According to the print information of the video memory test tool Memtester, select an erroneous address, such as address 0xa, write 0x5a5a5a5a once, and read it out continuously for multiple times. If the results of multiple reads are consistent, it indicates that the read operation is not wrong; if the values ​​read out multiple times are inconsistent, it indicates that the read operation is wrong. When the read operation is wrong, it is necessary to adjust the output drive impedance ODI on the DRAM side, specifically to adjust the output drive impedance ODI on the DRAM side to be consistent with the output drive impedance ODI on the PHY side. After adjusting the output drive impedance ODI on the DRAM side, repeat steps 1 and 2 until the read test passes. Among them, the output drive impedance ODI in the RX direction has only two configurations of 34Ω and 48Ω. If there is a problem with the read data, the ODI on the DRAM side and the ODI on the PHY can be configured to be consistent, both 34Ω or 48Ω. For the reference voltage Vref in the RX direction, the DRR system can realize automatic configuration.

[0056] Step 4, if 0 is written to the DRAM side and it is judged as 1, the reference voltage Vref is increased; if 1 is written to the DRAM and it is judged as 0, the reference voltage Vref is lowered; after adjusting the reference voltage Vref, repeat steps 1 to 4 until the video memory test passes.

[0057] It is understandable that the video memory test fails, but the RX direction test passes, indicating that the TX direction fails. The TX direction is mainly judged based on the test results of WalkZero (0 traversal) and WalkOne (1 traversal). If WalkZero fails, it means that the voltage value of the input 0 is greater than the Vref value, 0 is judged as 1, and Vref is too low. The Vref value needs to be increased to repeat steps 1 to 3. If WalkOne fails, it means that the voltage value of the input 1 is lower than the Vref value, 1 is judged as 0, and Vref is too high. The Vref value needs to be lowered to repeat steps 1 to 4 until the video memory test passes.

[0058] When an operation error occurs in the TX direction of the DDR system, if 0 is written into the DRAM side and it is judged as 1, the reference voltage Vref is adjusted up by one level based on the initial theoretical value of the reference voltage Vref. If 1 is written into the DRAM and it is judged as 0, the reference voltage Vref is adjusted down by one level based on the initial theoretical value of the reference voltage Vref.

[0059] Specifically, after calculating the initial theoretical values ​​of the reference voltages Vref of DDR4 and LPDDR4X respectively in step 1, the Vref values ​​are assigned to the mode register (Mode Register, MR) MR6 according to the DDR4 protocol.

[0060] When the reference voltage Vref needs to be adjusted higher or lower, it is adjusted by looking up a table, as shown in Table 1 below, which is the adjustment range of the reference voltage Vref of DDR4.

[0061] Table 1 DDR4 reference voltage Vref adjustment range Table 34-VrefDQTraining: Values

[0062]

[0063] The initial theoretical value of the reference voltage Vref is stored in the register. For example, the calculated initial theoretical value of the reference voltage Vref is 3, and the corresponding register configuration is 000011. Range1 indicates that the initial theoretical value of the reference voltage Vref is 61.95% of VDDQ. If Vref needs to be adjusted up by one level, the Vref value is increased to 62.60% of VDDQ; if Vref needs to be adjusted down by one level, the Vref value is reduced to 61.30% of VDDQ.

[0064] Table 2 shows the adjustment range of the reference voltage Vref of LPDDR4X

[0065]

[0066] For LPDDR4X, if the initial theoretical value of the reference voltage Vref is 3, the corresponding register configuration is 000011, indicating that the initial theoretical value of the reference voltage Vref is 16.8% of VDDQ. Then, if Vref needs to be adjusted up one gear, the Vref value is increased to 17.4% of VDDQ; if Vref needs to be adjusted down one gear, the Vref value is reduced to 16.2% of VDDQ.

[0067] The embodiment of the present invention provides a method for automatically adjusting the DDR reference voltage based on the video memory test result, which has the following beneficial effects:

[0068] Currently, the debugging scheme of the DDR system has no reliable theoretical basis, and confuses the TX direction with the RX direction. Each frequency point needs to be debugged, and the manual debugging workload is huge. The reference voltage Vref can be configured with more than 100 values, which is very easy to make mistakes.

[0069] In view of these defects, the present invention proposes a method for automatically adjusting the reference voltage Vref according to the video memory test results. By utilizing the downward compatibility characteristics of high-frequency electrical parameters, only one highest frequency point needs to be debugged; and a method for distinguishing read and write errors is also proposed, which can effectively separate read and write and avoid read and write confusion. At the same time, a method for inferring the deviation direction of Vref according to the results of video memory test items WalkZero and WalkOne is proposed, and the Vref configuration is automatically adjusted with a theoretical basis. The present invention can provide a reliable theoretical basis for adjusting Vref and greatly reduce the workload of system debugging.

[0070] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0071] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0072] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0073] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0074] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0075] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0076] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for automatically adjusting DDR reference voltage based on video memory test results, characterized in that: include: Step 1, when the DDR system is powered on, the clock and reset of the DDR system are configured based on the highest clock frequency available to a storage system; Step 2, performing a video memory test on the DDR system based on a video memory test tool. If the video memory test passes, there is no need to adjust the reference voltage Vref of the DDR system; if the video memory test fails, executing step 3; Step 3, determine whether the operation error is in the RX direction. If so, adjust the output drive impedance ODI on the DRAM side to be consistent with the output drive impedance ODI on the PHY side. After adjustment, repeat steps 1 to 3 until the read test passes. If not, the operation in the TX direction is wrong, go to step 4; Step 4, if 0 is written to the DRAM side and it is judged as 1, the reference voltage Vref is increased; if 1 is written to the DRAM and it is judged as 0, the reference voltage Vref is lowered; after adjusting the reference voltage Vref, repeat steps 1 to 4 until the video memory test passes.

2. The DDR reference voltage automatic adjustment method according to claim 1, characterized in that: The step 1, when the DDR system is powered on, configures the clock and reset of the DDR system based on the highest clock frequency available to a storage system, including: According to the type of DDR system, select the highest clock frequency available for the DDR system to configure the clock and reset of the DDR system, where: For DDR4 systems, the commonly used frequencies are 1600 / 1866 / 2133 / 2400 / 2666 / 2933 / 3200Mbps. Choose to debug 3200Mbps directly. For LPDDR4X systems, common frequencies are 1600 / 2133 / 2666 / 3200 / 3733 / 4266Mbps. Choose to debug 4266Mbps directly.

3. The DDR reference voltage automatic adjustment method according to claim 1, characterized in that: The DDR system includes a PHY side and a DRAM side, the PHY side includes a switch SW0 connected between VDDQ and ground, an on-chip termination impedance Ron1, a switch SW1 and an on-chip termination impedance Ron2, wherein the impedances of the on-chip termination impedance Ron1 and the on-chip termination impedance Ron2 are equal, both are Ron, the DRAM side includes a switch SW2 connected between VDDQ and ground, an output driver termination impedance Rtt1, a switch SW3, and an output driver termination impedance Rtt2, wherein the impedances of the output driver termination impedance Rtt1 and the output driver termination impedance Rtt2 are equal, both are Rtt, and a data line is connected between a common end of the on-chip termination impedance Ron1 and the switch SW1 and a common end of the output driver termination impedance Rtt1 and the switch SW3; The step 1, when the DDR system is powered on, configures the clock and reset of the DDR system based on the highest clock frequency available to a storage system, and further includes: An initial theoretical value of a reference voltage Vref in the TX direction of the DDR system is calculated according to an on-chip termination impedance Ron on the PHY side and an output driver termination impedance Rtt on the DRAM side.

4. The DDR reference voltage automatic adjustment method according to claim 3, characterized in that: The calculating the initial theoretical value of the reference voltage Vref in the TX direction of the DDR system according to the on-chip termination impedance Ron of the PHY side and the output driver termination impedance Rtt of the DRAM side includes: If it is a DDR4 system, for the TX direction, the PHY side performs a write operation, the data is driven from the PHY side, and absorbed at the DRAM side particle end. When 1 is written to the DARM side, switches SW0 and SW2 are closed, switches SW1 and SW3 are disconnected, and the level of the data line is DQ1 = VDDQ; when 0 is written to the DARM side, switches SW1 and SW2 are closed, switches SW0 and SW3 are disconnected, and the level of the data line is The reference voltage Vref is the average value of DQ1 and DQ2. If it is an LPDDR4X system, for the TX direction, the PHY side performs a write operation, the data is driven from the PHY side, and absorbed at the DRAM particle end. When 1 is written to the DRAM side, switches SW0 and SW3 are closed, switches SW1 and SW2 are opened, and the level of the data line is When 0 is written to the DARM side, switches SW1 and SW3 are closed, switches SW0 and SW2 are opened, the level of the data line is DQ4=0, and the reference voltage Vref value is the average value of the DQ3 and DQ4 levels.

5. The DDR reference voltage automatic adjustment method according to claim 1, characterized in that: The step 2, performing a video memory test on the DDR system based on a video memory test tool, and if the video memory test passes, there is no need to adjust the reference voltage Vref of the DDR system, includes: Based on the video memory test tool, the DDR system is subjected to a 0-traversal test and a 1-traversal test. The 0-traversal test is to write all 0s into the DRAM, and then read them out one by one to compare with the expected value 0. If the test result fails, it indicates that 0 is misread or mistakenly written as 1. The 1-traversal test is to write all 1s into the DRAM, and then read them out one by one to compare with the expected value 1. If the test result fails, it indicates that 1 is misread or mistakenly written as 0. If both the 0-pass test and the 1-pass test of the DRAM are passed, there is no need to adjust the reference voltage Vref of the DDR system.

6. The DDR reference voltage automatic adjustment method according to claim 5, characterized in that: The step 3, determining whether an operation error occurs in the RX direction, and if so, adjusting the output drive impedance ODI on the DRAM side to be consistent with the output drive impedance ODI on the PHY side, includes: If the video memory test fails, first determine whether there is a problem with the operation in the RX direction. According to the printed information of the video memory test tool, randomly select an error address, write a value to the error address once, and read it out continuously for multiple times. If the results of multiple reads are consistent, it indicates that there is no error in the read operation. If the values ​​read out multiple times are inconsistent, it indicates that the operation in the RX direction is wrong, then adjust the output drive impedance ODI on the DRAM side to be consistent with the output drive impedance ODI on the PHY side.

7. The DDR reference voltage automatic adjustment method according to claim 3, characterized in that: The step 4, if 0 is written into the DRAM side and it is judged as 1, then the reference voltage Vref is increased; if 1 is written into the DRAM and it is judged as 0, then the reference voltage Vref is decreased; includes: When an operation error occurs in the TX direction of the DDR system, if 0 is written to the DRAM side and is judged as 1, the reference voltage Vref is adjusted up by one level based on the initial theoretical value of the reference voltage Vref; If 1 is written into the DRAM and is judged as 0, the reference voltage Vref is adjusted down by one level based on the initial theoretical value of the reference voltage Vref.

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