Reliable data transmission method based on SPI (Serial Peripheral Interface)

Abstract

The invention discloses a reliable data transmission method based on an SPI interface, and belongs to the technical field of data communication. The method comprises the steps that the SPI comprises a master control end and a slave control end, the slave control end is provided with a slave control sending queue, and when slave control data needing to be sent to the master control end exists, the slave control end writes the slave control data into the slave control sending queue; the method further comprises the following steps: the master control end periodically sends master control data to the slave control end according to a data frame sending format; the slave control end carries out data feedback to the master control end aiming at the master control data sent by the master control end every time, and whether effective data is fed back or not when data feedback is carried out to the master control end is determined by combining the master control data sent by the master control end and whether slave control data exists in the slave control sending queue or not; wherein the slave control end feeds back data to the master control end according to a received data frame format. According to the invention, the reliability of master-slave end data transmission of the SPI interface can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data communication, and in particular to a reliable data transmission method based on an SPI interface. Background Art

[0002] SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus used for MCU to communicate with various peripheral devices in serial mode. The SPI interface adopts master-slave mode and uses a standard four-wire system to connect the master and slave ends.

[0003] In the related art, the master terminal actively initiates data transmission and data reception, and only receives data sent by the slave terminal after the master terminal sends data to the slave terminal. If the slave terminal has no data to send to the master terminal, the master terminal cannot determine whether the data is valid when receiving the data, resulting in unreliable data transmission. Summary of the invention

[0004] The present invention provides a reliable data transmission method based on an SPI interface, which can solve the problem of unreliable data transmission in related technologies. The technical solution is as follows:

[0005] On the one hand, a reliable data transmission method based on an SPI interface is provided, wherein the SPI interface includes a master end and a slave end, wherein the slave end is provided with a slave transmission queue, and when there is slave data to be sent to the master end, the slave end writes the slave data into the slave transmission queue; the method further includes:

[0006] The master control end periodically sends master control data to the slave control end in accordance with the data frame format;

[0007] The slave end provides data feedback to the master end for each master data sent by the master end, and determines whether valid data is fed back to the master end by combining the master data sent by the master end and whether there is slave data in the slave sending queue; wherein the slave end provides data feedback to the master end in accordance with the received data frame format.

[0008] On the other hand, a reliable data transmission device based on an SPI interface is provided, wherein the SPI interface includes a master end and a slave end, wherein the slave end is provided with a slave transmission queue, and when there is slave data to be sent to the master end, the slave end writes the slave data into the slave transmission queue; the device includes:

[0009] A first processing unit located at the master control end is used for the master control end to periodically send master control data to the slave control end in accordance with a data frame format;

[0010] The second processing unit located at the slave end is used for the slave end to provide data feedback to the master end for each master data sent by the master end, and determines whether valid data is fed back to the master end by combining the master data sent by the master end and whether the slave data exists in the slave sending queue; wherein the slave end feeds back data to the master end in accordance with the received data frame format.

[0011] On the other hand, a computer device is provided, which includes a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory to implement the steps of the above-mentioned reliable data transmission method based on the SPI interface.

[0012] On the other hand, a computer-readable storage medium is provided, wherein a computer program is stored in the storage medium, and when the computer program is executed by a processor, the steps of the above-mentioned reliable data transmission method based on the SPI interface are implemented.

[0013] On the other hand, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the steps of the above-mentioned reliable data transmission method based on the SPI interface are implemented.

[0014] The technical solution provided by the present invention can at least bring the following beneficial effects:

[0015] Regardless of whether the master end has valid data to send, it will periodically send master data to the slave end, and the data is sent in accordance with the data frame format, which ensures that the slave end can send and receive data immediately. The data frame format enables the slave end to confirm whether the master end has sent valid data. In addition, the slave end is provided with a slave sending queue. As long as the slave end has slave data that needs to be sent to the master end, the slave data will be written into the slave sending queue first, and when the master end is waiting to send the master data to the slave end in the next cycle, it determines whether to feed back valid data to the master end based on whether there is slave data in the master data and the slave sending queue. It can be seen that this scheme, by designing the data frame format and the data frame format, enables the slave end to determine whether the master data is valid and whether to feed back data, and the master end can also determine whether there is valid data in the feedback data, thereby ensuring the reliability of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 This is a flow chart of a reliable data transmission method based on an SPI interface provided by an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of a master-slave connection in an SPI interface provided by an embodiment of the present invention;

[0019] Figure 3 It is a schematic diagram comparing the sending data frame format and the receiving data frame format provided by an embodiment of the present invention;

[0020] Figure 4 It is a hardware architecture diagram of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0022] Please refer to Figure 1 The embodiment of the present invention provides a reliable data transmission method based on an SPI interface, wherein the SPI interface includes a master end and a slave end, wherein the slave end is provided with a slave control sending queue, and when there is slave control data to be sent to the master end, the slave control data is written into the slave control sending queue; the method further includes:

[0023] Step 100, the master control end periodically sends master control data to the slave control end according to the data frame format;

[0024] Step 102, the slave end provides data feedback to the master end for each master data sent by the master end, and determines whether valid data is fed back to the master end by combining the master data sent by the master end and whether there is slave data in the slave sending queue; wherein the slave end provides data feedback to the master end in accordance with the received data frame format.

[0025] In the embodiment of the present invention, the master end periodically sends master control data to the slave end regardless of whether there is valid data to send, and the data is sent in accordance with the data frame format, which ensures that the slave end can send and receive data immediately. The data frame format enables the slave end to confirm whether the master end has sent valid data. In addition, the slave end is provided with a slave control sending queue. As long as the slave end has slave control data that needs to be sent to the master end, the slave control data is first written into the slave control sending queue, and when the master end waits for the next cycle to send the master control data to the slave end, it determines whether to feed back valid data to the master end according to whether there is slave control data in the master control data and the slave control sending queue. It can be seen that this scheme, by designing the data frame format and the data frame format, enables the slave end to determine whether the master control data is valid and whether to feed back data, and the master end can also determine whether there is valid data in the feedback data, thereby ensuring the reliability of data transmission.

[0026] Please refer to Figure 2 , the master end of the SPI interface is located in the processor system, and the slave end is located in the external device. The processor system and the external device are connected through the SPI interface. The master end and the slave end are connected by 4 standard lines, namely mosi, miso, clk and gate lines. The master end performs periodic queries according to the period T. Assuming that the period T is n nanoseconds, n is a positive integer, a data query is performed every n nanoseconds. Each time a query is performed, the master data is sent to the slave end. If valid data is received, it is used for data processing in the processor system. In addition to the slave sending queue, the slave end can also include a slave receiving queue. Every time the master data sent by the master end is received, if the master data is valid, the master data is written into the slave receiving queue. If there is slave data sent to the master end, the slave data is written into the slave sending queue. The master data in the slave receiving queue can be used for data processing of external devices.

[0027] In order to improve data transmission reliability, the embodiment of the present invention designs a sending data frame format and a receiving data frame format, which are described below.

[0028] Since the data reception and transmission of the standard SPI interface are synchronously performed under clock control, the master end can grasp the information of the received and sent data from the first clock, and the slave end can grasp the X-bit information after receiving X-bit data, and then determine whether the slave end sends data and what data to send based on the X-bit information. Based on this, in the embodiment of the present invention, according to the above characteristics of the SPI interface, the sending data frame format and the receiving data frame format are asymmetric; the data frame length required by the receiving data frame format is shorter than the data frame length required by the sending data frame format by a set number of bits, and the set number of bits is vacated from the start bit of the receiving data frame format, and is used by the slave end to use the vacated set number of bits to realize information discrimination and data processing of the master data.

[0029] For example, the first X bits in the received data frame format are undefined bits, and the X bits are the sum of the lengths of the command bits and the padding bits. The X bits left blank in the received data frame format are used to perform information discrimination and data processing on the sent master control data. Among them, X is a positive integer. Taking the command bit occupying 2 bits and the padding bit occupying 2 bits as an example, then X bits are 4 bits. For the master control end, the received data frame is 4 bits shorter than the sent data frame. Among them, the first 2 bits left blank in the received data frame are the information bits for discrimination by the slave control end, and the last 2 bits left blank are used for the clock cycle for discrimination and processing by the slave control end. This ensures that the slave control end has effective command reception and processing time and space at the protocol level, and through the support of the slave control receiving queue and the slave control sending queue, the slave control end can not only actively send master control data to the master control end, but also respond to the master control end's commands in real time.

[0030] Please refer to Figure 3 , is a schematic diagram comparing the format of the sent data frame and the format of the received data frame. The sent data frame format includes at least the following data frames in sequence starting from the start bit: a command bit, a padding bit, and a sent data bit; the number of bits occupied by the command bit and the padding bit is the set number of bits; Figure 3 In the example, the setting bit number is 4 bits, and the command bit and padding bit occupy 2 bits respectively.

[0031] The received data frame format includes at least the following data frames in sequence after the set number of bits is left out from the start bit: a received identification bit and a received data bit.

[0032] Among them, the command bit in the sending data frame format is used to indicate whether the master control data sent this time is valid and whether the feedback data from the slave control end is received this time; the fill bit is used to provide the parsing waiting time for the slave control end; the sending data bit is used to fill the master control data to be sent; the receiving identification bit is used to indicate whether the feedback data this time is valid data; the receiving data bit is used to fill the slave control data required for feedback.

[0033] Then, the master control end periodically sends the master control data to the slave control end according to the data frame format, which may specifically include:

[0034] The master end periodically queries the SPI interface to determine the content of each data frame in the master data sent to the slave end this time;

[0035] When it is determined that data needs to be sent to the slave end but data does not need to be received, the command bit in the master data sent to the slave end this time is used to indicate that only sending is not to be received and the sent data is valid, and the data to be sent is filled into the send data bit;

[0036] When it is determined that data does not need to be sent to the slave end but needs to be received, the command bit in the master control data sent to the slave end this time is used to indicate that only receiving is required and sending data is invalid;

[0037] When it is determined that data needs to be sent to the slave end and data needs to be received, the command bit in the master control data sent to the slave end this time is used to indicate that the data is sent and received at the same time and that the sent data is valid, and the data to be sent is filled into the send data bit;

[0038] Accordingly, the determining whether to feed back valid data to the master end by combining the master control data sent by the master end and whether there is slave control data in the slave control sending queue may specifically include:

[0039] When the slave receives the command bit in the master control data sent by the master control end, which indicates that only sending but not receiving is allowed and the sent data is valid, the slave parses the data from the sent data bit of the master control data, and the receiving identification bit in the feedback data is used to indicate that the data fed back this time is invalid data;

[0040] When the slave end receives the command bit in the master control data sent by the master control end and indicates that only receiving and sending data is invalid, it determines whether there is slave control data in the slave control sending queue. If so, the slave control data is taken out from the slave control sending queue and filled into the receiving data bit of the feedback data, and the receiving identification bit in the feedback data is used to indicate that the data fed back this time is valid data; if not, the receiving identification bit in the feedback data is used to indicate that the data fed back this time is invalid data;

[0041] When the slave end receives the command bit in the master control data sent by the master control end, which is used to indicate simultaneous transmission and reception and the transmitted data is valid, the slave end parses the data from the transmitted data bit in the master control data, and determines whether there is slave control data in the slave control transmission queue. If so, the slave control data is taken out from the slave control transmission queue and filled into the received data bit of the feedback data, and the received identification bit in the feedback data is used to indicate that the data fed back this time is valid data; if not, the received identification bit in the feedback data is used to indicate that the data fed back this time is invalid data.

[0042] Furthermore, in addition to the above data frame, in one embodiment of the present invention, the data frame format may also include: a master address bit and a master check bit. In one implementation, the master address bit may be located between the padding bit and the data bit to be sent, and the master check bit may be located after the data bit to be sent.

[0043] The master address bit is used to indicate the destination address of the master data. When the SPI interface has multiple slave terminals, by writing the address of the target slave terminal into the master address bit, when multiple slave terminals receive the master data sent by the master terminal, the master address bit in the master data is used to determine whether the master data is sent to itself. The master check bit is used by the slave terminal to check the master data.

[0044] Similarly, in addition to the above data frame, in one embodiment of the present invention, the received data frame format may also include: a slave control address bit and a slave control check bit. In one implementation, the slave control address bit may be located before the receiving identifier, and the slave control check bit may be located after the received data bit.

[0045] The slave address bit is used to indicate the destination address of the feedback data. When the SPI interface has multiple master terminals, by writing the address of the target master terminal into the slave address bit, when multiple master terminals receive feedback data from the slave terminal, the slave address bit in the feedback data is used to determine whether the feedback data is sent to itself. The slave check bit is used by the master terminal to check the feedback data.

[0046] In the embodiment of the present invention, since 8 bits are one byte, in order to facilitate data processing, the total length of the master control data and the feedback data may be an integer multiple of 8.

[0047] In one embodiment, in the data frame format, the command bit occupies 2 bits of the data frame length, the padding bit occupies 2 bits of the data frame length, the master address bit occupies 3 bits of the data frame length, the transmitted data bit occupies M bits, where M is a positive integer, and the master check bit can be 8 kbits, where k is a positive integer.

[0048] Correspondingly, in the receive data frame format, after leaving 4 bits from the start bit, the slave control address bit occupies 3 bits of the data frame length, the receive identification bit occupies 1 bit of the data frame length, the receive data bit occupies Mbits, M is a positive integer, and the slave control check bit can be 8kbits, k is a positive integer.

[0049] In order to make the total length of the master control data and the feedback data an integer multiple of 8, the sending data frame format may also include an undefined bit, which is used to supplement the data length and occupies 1 bit of the data frame length; the receiving data frame format may also include an undefined bit, and the undefined bit in the receiving data frame format is used to leave the start bit empty for a set number of bits, that is, the undefined bit occupies 4 bits of the data frame length.

[0050] Taking the bit occupied by each bit in the above embodiment as an example, the setting of the command bit in the data transmission frame format is explained.

[0051] When the command bit is 01, it is used to indicate that only sending is not received and the sent data is valid;

[0052] When the command bit is 10, it is used to indicate that only receiving and sending data is invalid;

[0053] When the command bit is 11, it is used to indicate simultaneous transmission and reception and the transmitted data is valid;

[0054] When the command bit is 00, it means that the field is not defined and the sent data is invalid.

[0055] It can be seen that the master end will periodically query the SPI interface to determine whether there is data to be sent and whether there is data to be received, regardless of whether there is a demand. When there is no data to be sent or received, the command bit can be set to 00 to send the master data.

[0056] It should be noted that, no matter whether there is data to be sent or not, the total length of the master control data sent by the master control end to the slave control end is L.

[0057] Taking the occupied bits in the above embodiment as an example, the setting of the receiving identification bit in the receiving data frame format is explained.

[0058] When the receiving flag is 1, it indicates that the feedback data is valid.

[0059] When the receiving flag is 0, it is used to indicate that the feedback data is invalid data.

[0060] It can be seen that as long as the slave control end has slave control data to be sent to the master control end, the slave control data will be written into the slave control sending queue. When the master control data sent by the master control end is received, when the command bit of the master control data indicates that feedback data can be received, the slave control data in the slave control sending queue is filled into the feedback data as valid data, and the receiving identification bit is indicated as valid data. Otherwise, the slave control data in the slave control sending queue will not be filled into the feedback data. In this way, the slave control end can perform data feedback according to the actual situation, ensuring the effectiveness of data transmission between the master and the slave.

[0061] It should be noted that, no matter whether the feedback data is filled with valid data to be sent or not, the total length of the data fed back from the control end to the master control end is L.

[0062] In one embodiment of the present invention, in order to ensure that data can be processed in time after transmission and without confusion, a slave control receiving queue is also provided at the slave control end. After parsing the data from the transmission data bit in the master control data sent from the master control end, the method may further include: writing the parsed data into the slave control receiving queue. Thus, when there is data in the slave control receiving queue, the data can be processed in sequence according to the order in which the data is put into the slave control receiving queue.

[0063] In one embodiment of the present invention, in order to avoid queue data overflow, the lengths of the slave control sending queue and the slave control receiving queue are both N, and N satisfies the following relationship:

[0064]

[0065] Among them, L is the total length of the master data and feedback data, T is the period of the master end querying the SPI interface, and S is the sending rate of the master end.

[0066] In the embodiment of the present invention, the delay time n nanoseconds of the periodic query can be set in time granularity according to the real-time requirement, so that the real-time performance of sending and receiving data from the control end can be guaranteed.

[0067] The embodiment of the present invention provides a reliable data transmission device based on an SPI interface, wherein the SPI interface includes a master end and a slave end, wherein the slave end is provided with a slave transmission queue, and when there is slave data to be sent to the master end, the slave end writes the slave data into the slave transmission queue; the device includes:

[0068] A first processing unit located at the master control end is used for the master control end to periodically send master control data to the slave control end in accordance with a data frame format;

[0069] The second processing unit located at the slave end is used for the slave end to provide data feedback to the master end for each master data sent by the master end, and determines whether valid data is fed back to the master end by combining the master data sent by the master end and whether the slave data exists in the slave sending queue; wherein the slave end feeds back data to the master end in accordance with the received data frame format.

[0070] In one embodiment of the present invention, the sending data frame format and the receiving data frame format are asymmetric;

[0071] The data frame length required by the receiving data frame format is shorter by a set number of bits than the data frame length required by the sending data frame format. The set number of bits is left empty starting from the start bit of the receiving data frame format and is used by the control end to implement information identification and data processing of the master control data using the left empty set number of bits.

[0072] In one embodiment of the present invention, the transmission data frame format includes at least the following data frames in sequence starting from the start bit: a command bit, a padding bit and a transmission data bit; the number of bits occupied by the command bit and the padding bit is the set number of bits;

[0073] The received data frame format includes at least the following data frames in sequence after the set number of bits is left out from the start bit: a received identification bit and a received data bit;

[0074] When the master control end periodically sends the master control data to the slave control end according to the data frame format, it specifically includes:

[0075] The master end periodically queries the SPI interface to determine the content of each data frame in the master data sent to the slave end this time;

[0076] When it is determined that data needs to be sent to the slave end but data does not need to be received, the command bit in the master data sent to the slave end this time is used to indicate that only sending is not to be received and the sent data is valid, and the data to be sent is filled into the send data bit;

[0077] When it is determined that data does not need to be sent to the slave end but needs to be received, the command bit in the master control data sent to the slave end this time is used to indicate that only receiving is required and sending data is invalid;

[0078] When it is determined that data needs to be sent to the slave end and data needs to be received, the command bit in the master control data sent to the slave end this time is used to indicate that the data is sent and received at the same time and that the sent data is valid, and the data to be sent is filled into the send data bit;

[0079] The determining whether to feed back valid data to the master control end by combining the master control data sent by the master control end and whether there is slave control data in the slave control sending queue specifically includes:

[0080] When the slave receives the command bit in the master control data sent by the master control end, which indicates that only sending but not receiving is allowed and the sent data is valid, the slave parses the data from the sent data bit of the master control data, and the receiving identification bit in the feedback data is used to indicate that the data fed back this time is invalid data;

[0081] When the slave end receives the command bit in the master control data sent by the master control end and indicates that only receiving and sending data is invalid, it determines whether there is slave control data in the slave control sending queue. If so, the slave control data is taken out from the slave control sending queue and filled into the receiving data bit of the feedback data, and the receiving identification bit in the feedback data is used to indicate that the data fed back this time is valid data; if not, the receiving identification bit in the feedback data is used to indicate that the data fed back this time is invalid data;

[0082] When the slave end receives the command bit in the master control data sent by the master control end, which is used to indicate simultaneous transmission and reception and the transmitted data is valid, the slave end parses the data from the transmitted data bit in the master control data, and determines whether there is slave control data in the slave control transmission queue. If so, the slave control data is taken out from the slave control transmission queue and filled into the received data bit of the feedback data, and the received identification bit in the feedback data is used to indicate that the data fed back this time is valid data; if not, the received identification bit in the feedback data is used to indicate that the data fed back this time is invalid data.

[0083] In one embodiment of the present invention, a slave receiving queue is also provided at the slave end, and the second processing unit at the slave end is further used to parse data from the data bits in the slave master data and write the parsed data into the slave receiving queue.

[0084] In one embodiment of the present invention, the lengths of the slave control sending queue and the slave control receiving queue are both N, and N satisfies the following relationship:

[0085]

[0086] Among them, L is the total length of the master data and feedback data, T is the period of the master end querying the SPI interface, and S is the communication rate between the master end and the slave end.

[0087] In one embodiment of the present invention, the total length of the main control data and the feedback data is an integer multiple of 8.

[0088] It should be noted that the reliability data transmission device based on the SPI interface provided in the above embodiment is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the reliability data transmission device based on the SPI interface provided in the above embodiment and the reliability data transmission method embodiment based on the SPI interface belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0089] The embodiment of the present application also provides a computer device, please refer to Figure 4The computer device includes a processor and a memory, in which at least one instruction, at least one program, code set or instruction set is stored, and the at least one instruction, at least one program, code set or instruction set is loaded and executed by the processor to implement the reliable data transmission method based on the SPI interface provided by the above-mentioned method embodiments.

[0090] An embodiment of the present application also provides a computer-readable storage medium, on which is stored at least one instruction, at least one program, code set or instruction set, and the at least one instruction, at least one program, code set or instruction set is loaded and executed by a processor to implement the reliability data transmission method based on the SPI interface provided by the above-mentioned method embodiments.

[0091] An embodiment of the present application also provides a computer program product, which includes a computer program. A processor of a computer device reads the computer program from a computer-readable storage medium, and the processor executes the computer program, so that the computer device executes any of the reliable data transmission methods based on the SPI interface described in the above embodiments.

[0092] For the convenience of description, the above system or device is described by dividing it into various modules or units according to its functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0093] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly contributed to the prior art in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.

[0094] Finally, it should be noted that, in this article, relational terms such as first, second, third and fourth are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0095] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A reliable data transmission method based on SPI interface, characterized in that: The SPI interface includes a master end and a slave end, the slave end is provided with a slave control sending queue, and when there is slave control data to be sent to the master end, the slave control data is written into the slave control sending queue; the method further includes: The master control end periodically sends master control data to the slave control end in accordance with the data frame format; The slave end provides data feedback to the master end for each master data sent by the master end, and determines whether valid data is fed back to the master end by combining the master data sent by the master end and whether there is slave data in the slave sending queue; wherein the slave end provides data feedback to the master end in accordance with the received data frame format.

2. The method according to claim 1, characterized in that The sending data frame format and the receiving data frame format are asymmetric; The data frame length required by the receiving data frame format is shorter by a set number of bits than the data frame length required by the sending data frame format. The set number of bits is left empty starting from the start bit of the receiving data frame format and is used by the control end to implement information identification and data processing of the master control data using the left empty set number of bits.

3. The method according to claim 2, characterized in that The transmission data frame format includes at least the following data frames in sequence starting from the start bit: a command bit, a padding bit and a transmission data bit; the command bit and the padding bit occupy a total of the set number of bits; The received data frame format includes at least the following data frames in sequence after the set number of bits is left out from the start bit: a received identification bit and a received data bit; The master control end periodically sends master control data to the slave control end according to the data frame format, including: The master end periodically queries the SPI interface to determine the content of each data frame in the master data sent to the slave end this time; When it is determined that data needs to be sent to the slave end but data does not need to be received, the command bit in the master data sent to the slave end this time is used to indicate that only sending is not to be received and the sent data is valid, and the data to be sent is filled into the send data bit; When it is determined that data does not need to be sent to the slave end but needs to be received, the command bit in the master control data sent to the slave end this time is used to indicate that only receiving is required and sending data is invalid; When it is determined that data needs to be sent to the slave end and data needs to be received, the command bit in the master control data sent to the slave end this time is used to indicate that the data is sent and received at the same time and the sent data is valid, and the data to be sent is filled into the send data bit; The determining whether to feed back valid data to the master control end by combining the master control data sent by the master control end and whether there is slave control data in the slave control sending queue comprises: When the slave receives the command bit in the master control data sent by the master control end, which indicates that only sending but not receiving is allowed and the sent data is valid, the slave parses the data from the sent data bit of the master control data, and the receiving identification bit in the feedback data is used to indicate that the data fed back this time is invalid data; When the slave end receives the command bit in the master control data sent by the master control end and indicates that only receiving and sending data is invalid, it determines whether there is slave control data in the slave control sending queue. If so, the slave control data is taken out from the slave control sending queue and filled into the receiving data bit of the feedback data, and the receiving identification bit in the feedback data is used to indicate that the data fed back this time is valid data; if not, the receiving identification bit in the feedback data is used to indicate that the data fed back this time is invalid data; When the slave end receives the command bit in the master control data sent by the master control end, which is used to indicate simultaneous transmission and reception and the transmitted data is valid, the slave end parses the data from the transmitted data bit in the master control data, and determines whether there is slave control data in the slave control transmission queue. If so, the slave control data is taken out from the slave control transmission queue and filled into the received data bit of the feedback data, and the received identification bit in the feedback data is used to indicate that the data fed back this time is valid data; if not, the received identification bit in the feedback data is used to indicate that the data fed back this time is invalid data.

4. The method according to claim 3, characterized in that A slave control receiving queue is also provided at the slave control end. After parsing the data from the data bits in the slave control data, the method further includes: writing the parsed data into the slave control receiving queue.

5. The method according to claim 4, characterized in that The lengths of the slave control sending queue and the slave control receiving queue are both N, and N satisfies the following relationship: Among them, L is the total length of the master data and feedback data, T is the cycle of the master end querying the SPI interface, and S is the communication rate between the master end and the slave end.

6. The method according to claim 5, characterized in that The total length of the master control data and feedback data is an integer multiple of 8.

7. A reliable data transmission device based on SPI interface, characterized in that: The SPI interface includes a master end and a slave end, wherein the slave end is provided with a slave transmission queue, and when there is slave data to be transmitted to the master end, the slave end writes the slave data into the slave transmission queue; the device includes: A first processing unit located at the master control end is used for the master control end to periodically send master control data to the slave control end in accordance with a data frame format; The second processing unit located at the slave end is used for the slave end to provide data feedback to the master end for each master data sent by the master end, and determines whether valid data is fed back to the master end by combining the master data sent by the master end and whether the slave data exists in the slave sending queue; wherein the slave end feeds back data to the master end in accordance with the received data frame format.

8. A computer device, characterized in that: The computer device includes a memory and a processor, the memory is used to store a computer program, and the processor is used to execute the computer program stored in the memory to implement the steps of any one of the methods described in claims 1-6.

9. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 6 are implemented.

10. A computer program product, characterized in that The method comprises a computer program, wherein when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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