Method and system for controlling matrix type elastic bus

Abstract

The invention discloses a matrix type elastic bus control method and system, the system comprises a plurality of bus matrix nodes, each bus matrix node comprises a northbound interface, an east interface, a southbound interface, a west interface and a self-interface, the bus matrix nodes are distributed according to a dot matrix, the northbound interface and the southbound interface of the adjacent bus matrix nodes are connected, and the self-interface is connected with the northbound interface and the southbound interface of the adjacent bus matrix nodes. The east interface and the west interface of the adjacent bus matrix nodes are connected. The method and the system can solve various problems caused by too many peripherals during bus addressing.

Description

Technical Field

[0001] The invention belongs to the field of digital simulation and testing of secondary equipment of intelligent substations, and relates to a control method and system of a matrix elastic bus. Background Art

[0002] The power system requires a large number of test and simulation equipment, which generally have the characteristics of a large number of interfaces, a wide variety, high bandwidth, and strong real-time performance. Conventional communication buses are generally ARM's AXI (Advanced Extensible Interface) bus and Intel's Avalon bus. These buses are addressed in registers. When there are too many peripherals, the bus addressing efficiency is low and the bandwidth is difficult to increase, which seriously limits the number of peripherals. At the same time, these buses generally adopt the CPU-peripheral model, which cannot meet the communication between peripherals. Summary of the invention

[0003] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art and provide a control method and system for a matrix elastic bus, which can solve various problems caused by too many peripherals in bus addressing.

[0004] In order to achieve the above object, the present invention adopts the following technical scheme:

[0005] On the one hand, the present invention provides a control system of a matrix-type elastic bus, including a plurality of bus matrix nodes, each bus matrix node including a northbound interface, an eastbound interface, a southbound interface, a westbound interface, and a self-interface, each bus matrix node is distributed in a dot matrix, the northbound interface and the southbound interface of adjacent bus matrix nodes are connected, and the eastbound interface and the westbound interface of adjacent bus matrix nodes are connected.

[0006] The sending end and receiving end of the northbound interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y are respectively connected to the receiving end and sending end of the southbound interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y+1;

[0007] The sending end and receiving end of the east interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y are respectively connected to the receiving end and sending end of the west interface of the bus matrix node with the horizontal coordinate X+1 and the vertical coordinate Y;

[0008] The sending end and receiving end of the southbound interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y are respectively connected to the receiving end and sending end of the northbound interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y-1;

[0009] The sending end and receiving end of the west interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y are connected to the receiving end and sending end of the east interface of the bus matrix node with the horizontal coordinate X-1 and the vertical coordinate Y respectively.

[0010] The bus matrix node also includes a port input module, a data storage unit, and a port output module;

[0011] The port input module is used to receive data packets received by the northbound interface, the eastbound interface, the southbound interface, the westbound interface, and the self-interface, or receive data packets generated by the upper layer application;

[0012] A data storage unit, used for caching data packets;

[0013] The port output module is used to read the data packet in the data storage unit and forward it to its corresponding interface according to its own bus matrix node and destination node coordinates.

[0014] The port output module determines the size of the X coordinate of the target node coordinate in the data packet and the X coordinate of the bus matrix node itself:

[0015] When the X coordinate of the target node in the data packet is greater than the X coordinate of the own bus matrix node, the data packet is output from the east interface;

[0016] When the X coordinate of the target node in the data packet is less than the X coordinate of the own bus matrix node, the data packet is output from the west interface;

[0017] When the X coordinate of the target node coordinate in the data packet is equal to the X coordinate of the own bus matrix node, the following judgment is made: the size of the Y coordinate of the target node coordinate in the data packet and the Y coordinate of the own bus matrix node is judged:

[0018] When the Y coordinate of the target node in the data packet is greater than the Y coordinate of the own bus matrix node, the data packet is output from the southbound interface;

[0019] When the Y coordinate of the target node in the data packet is less than the Y coordinate of the own bus matrix node, the data packet is output from the northbound interface;

[0020] When the Y coordinate of the target node coordinate in the data packet is equal to the Y coordinate of the own bus matrix node, the data packet is returned to the upper layer application or output from the self interface to the peripheral module.

[0021] In a second aspect of the present invention, the present invention provides a control method for a matrix elastic bus, comprising the following steps:

[0022] 1) Divide the bus matrix nodes into source nodes, intermediate nodes, and target nodes;

[0023] 2) Define the frame format of the data packet for data communication;

[0024] 3) The bus matrix node as a source node generates a data packet according to the upper layer application requirements, and the bus matrix node as a source node stores the generated data packet into an internal data storage unit;

[0025] 4) The port output module of the bus matrix node as the source node reads the data packet in the data storage unit, parses the destination node coordinates, and forwards it to its own corresponding interface according to its own bus matrix node and the destination node coordinates;

[0026] 5) The bus matrix node as an intermediate node receives the data packet;

[0027] 6) The port input module in the bus matrix node as the intermediate node receives the data packets input by each interface;

[0028] 7) The port input module in the bus matrix node as the intermediate node stores the generated data packet into the internal data storage unit;

[0029] 8) The port output module in the bus matrix node as the intermediate node reads the data packet in the data storage unit, parses the destination node coordinates, and forwards it to its own corresponding interface according to its own bus matrix node and the destination node coordinates;

[0030] 9) The port input module in the bus matrix node as the target node receives the data packets inputted by each interface, and the bus matrix node as the target node stores the received data packets into the internal data storage unit;

[0031] 10) The port output module in the bus matrix node as the target node parses the data packet content and sends the data packet to the upper layer application or to the peripheral module from its own self interface.

[0032] The process of storing the data packet into the internal data storage unit is as follows:

[0033] Determine whether the full flag of the internal data storage unit is full. When the full flag is not full and the free storage space is greater than or equal to the size of the data packet, write the current data packet to the data storage unit; if the full flag is full, or the free storage space is less than the size of the data packet, discard the current data packet.

[0034] The process of forwarding to its corresponding interface according to its own coordinates and the destination node coordinates is as follows:

[0035] Determine the size of the X coordinate of the target node in the data packet and the X coordinate of the bus matrix node itself:

[0036] When the X coordinate of the target node in the data packet is greater than the X coordinate of the own bus matrix node, the data packet is output from the east interface;

[0037] When the X coordinate of the target node in the data packet is less than the X coordinate of the own bus matrix node, the data packet is output from the west interface;

[0038] When the X coordinate of the target node coordinate in the data packet is equal to the X coordinate of the own bus matrix node, the following judgment is made: the size of the Y coordinate of the target node coordinate in the data packet and the Y coordinate of the own bus matrix node is judged:

[0039] When the Y coordinate of the target node in the data packet is greater than the Y coordinate of the own bus matrix node, the data packet is output from the southbound interface;

[0040] When the Y coordinate of the target node in the data packet is less than the Y coordinate of the own bus matrix node, the data packet is output from the northbound interface;

[0041] When the Y coordinate of the target node coordinate in the data packet is equal to the Y coordinate of the own bus matrix node, the data packet is returned to the upper layer application or output from the self interface to the peripheral module.

[0042] The bus matrix node also includes a port input module, a data storage unit, and a port output module;

[0043] The port input module is used to receive data packets received by the northbound interface, the eastbound interface, the southbound interface, the westbound interface, and the self-interface, or receive data packets generated by the upper layer application;

[0044] A data storage unit, used for caching data packets;

[0045] The port output module is used to read the data packet in the data storage unit and forward it to its corresponding interface according to its own bus matrix node and destination node coordinates.

[0046] The present invention has the following beneficial effects:

[0047] The control method and system of the matrix elastic bus described in the present invention include a plurality of bus matrix nodes during specific operation, each bus matrix node includes a northbound interface, an eastbound interface, a southbound interface, a westbound interface, and a self-interface, each bus matrix node is distributed in a dot matrix, and the bus matrix nodes that need to communicate can be flexibly expanded. The bus matrix nodes are more than the traditional method, which solves various problems caused by too many peripherals in bus addressing. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0049] Figure 1 It is a schematic diagram of bus matrix node distribution of the present invention;

[0050] Figure 2 It is a schematic diagram of the internal structure of the bus matrix node of the present invention;

[0051] Figure 3 This is the communication data frame format of the present invention. DETAILED DESCRIPTION

[0052] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0053] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0054] The present invention is further described in detail below in conjunction with the accompanying drawings:

[0055] Embodiment 1

[0056] refer to Figure 1The control system of the matrix elastic bus described in the present invention includes multiple bus matrix nodes, each bus matrix node includes a northbound interface NorthPort, an eastbound interface EsatPort, a southbound interface SouthPort, a westbound interface WestPort, and a self-interface OwnPort, and the northbound interface NorthPort, the eastbound interface EsatPort, the southbound interface SouthPort, the westbound interface WestPort, and the self-interface OwnPort are all bidirectional bus interfaces, which can input or output data to realize data sending, receiving, and forwarding functions.

[0057] Each bus matrix node is distributed in a dot matrix, the northbound interfaces of adjacent bus matrix nodes are connected to the southbound interfaces, and the eastbound interfaces of adjacent bus matrix nodes are connected to the westbound interfaces, specifically:

[0058] The sending end and receiving end of the northbound interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y are respectively connected to the receiving end and sending end of the southbound interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y+1;

[0059] The sending end and receiving end of the east interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y are respectively connected to the receiving end and sending end of the west interface of the bus matrix node with the horizontal coordinate X+1 and the vertical coordinate Y;

[0060] The sending end and receiving end of the southbound interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y are respectively connected to the receiving end and sending end of the northbound interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y-1;

[0061] The sending end and receiving end of the west interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y are connected to the receiving end and sending end of the east interface of the bus matrix node with the horizontal coordinate X-1 and the vertical coordinate Y respectively.

[0062] The sending end and receiving end of the self interface of the bus matrix node are respectively connected to the receiving end and sending end of the peripheral module, and the peripheral module includes a CPU data interface, a Flash controller and a DA controller.

[0063] Figure 1 The bus matrix node network is shown in Figure 1, which is composed of 12 bus matrix nodes. The bus matrix nodes can be expanded according to the actual application.

[0064] like Figure 2 As shown, the bus matrix node also includes a port input module, a data storage unit, and a port output module.

[0065] The port input module is used to receive data packets received from the northbound interface NorthPort, the eastbound interface EsatPort, the southbound interface SouthPort, the westbound interface WestPort, and the own interface OwnPort, or receive data packets generated by an upper layer application.

[0066] Data storage unit, used to cache data packets.

[0067] The port output module is used to read the data packet in the data storage unit and forward it to its corresponding interface according to its own bus matrix node and destination node coordinates.

[0068] Embodiment 2:

[0069] Accordingly, the present invention discloses a control method for a matrix elastic bus. The control system based on the matrix elastic bus comprises the following steps:

[0070] 1) The bus matrix nodes are divided into data producers, data forwarders and data consumers according to data generation, data forwarding and data consumption. Data producers generate and send data, data forwarders forward data, and data consumers are the final nodes of certain data. All bus matrix nodes may be data producers, data forwarders or data consumers. When a data packet is sent from a data producer to a data consumer, the data producer is the source node and the data consumer is the target node; when a data packet is sent from a data consumer to a data producer, the data consumer is the source node and the data producer is the target node;

[0071] 2) Define the frame format of the data packet for data communication as Figure 3 As shown, the data packet includes the destination node coordinates (2 bytes), the source node coordinates (2 bytes), the frame number (2 bytes), the data length (2 bytes), and the data content (64 to 2048 bytes). The first byte of the destination node coordinates and the source node coordinates is set as the X coordinate of the destination node and the source node, respectively, and the second byte of the destination node coordinates and the source node coordinates is set as the Y coordinate of the destination node and the source node, respectively;

[0072] 3) The bus matrix node as a source node generates a data packet according to the upper-layer application requirements. The data packet can be provided by the upper-layer application or obtained from the peripheral module connected to its own self-interface OwnPort. The data packet is encapsulated according to the frame format of step 2). The bus matrix node as a source node stores the generated data packet into an internal data storage unit (the data storage unit can be a RAM or a FIFO, with a read / write port, an empty and full flag, a data width of 32 / 64 / 128 bits, a depth of 1K / 1M / 1G, etc., which can be flexibly adjusted according to the actual device). Specifically, it is determined whether the full flag (Data_full) of the internal data storage unit is full. If it is not full and the free storage space is greater than or equal to the size of the data packet, the current data packet is written to the data storage unit; if the full flag (Data_full) is full, or the free storage space is less than the size of the data packet, the current data packet is discarded;

[0073] 4) The port output module of the bus matrix node as the source node reads the data packet in the data storage unit, parses the destination node coordinates, and forwards it to its own corresponding interface according to its own bus matrix node and the destination node coordinates;

[0074] 5) The bus matrix node as an intermediate node receives a data packet, and the received data packet may also receive data from a northbound interface, an eastbound interface, a southbound interface, and a westbound interface;

[0075] 6) The port input module in the bus matrix node as the intermediate node receives the data packets input from each interface, and the input data packets are received according to the frame structure;

[0076] 7) The port input module in the bus matrix node as the intermediate node stores the generated data packet into the internal data storage unit, specifically: judging whether the full mark (Data_full) of the internal data storage unit is full, if it is not full and the free storage space is greater than or equal to the size of the data packet, then the current data packet is written into the data storage unit; if the full mark (Data_full) is full, or the free storage space is less than the size of the data packet, then the current data packet is discarded;

[0077] 8) The port output module in the bus matrix node as the intermediate node reads the data packet in the data storage unit, parses the destination node coordinates, and forwards it to its own corresponding interface according to its own bus matrix node and the destination node coordinates;

[0078] 9) The port input module in the bus matrix node as the target node receives the data packets inputted by each interface, and the bus matrix node as the target node stores the received data packets into the internal data storage unit, specifically: judging whether the full mark (Data_full) of the internal data storage unit is full, and when it is not full and the free storage space is greater than or equal to the size of the data packet, writing the current data packet into the data storage unit; if the full mark (Data_full) is full, or the free storage space is less than the size of the data packet, discarding the current data packet;

[0079] 10) The port output module in the bus matrix node as the target node parses the data packet content and sends the data packet to the upper layer application or sends it to the peripheral module from its own self-interface OwnPort.

[0080] Forwarding to its corresponding interface according to its own coordinates and the destination node coordinates specifically includes the following steps:

[0081] Determine the size of the X coordinate of the target node in the data packet and the X coordinate of the bus matrix node itself:

[0082] When the X coordinate of the target node in the data packet is greater than the X coordinate of the own bus matrix node, the data packet is output from the east interface;

[0083] When the X coordinate of the target node in the data packet is less than the X coordinate of the own bus matrix node, the data packet is output from the west interface;

[0084] When the X coordinate of the target node coordinate in the data packet is equal to the X coordinate of the own bus matrix node, the following judgment is made: the size of the Y coordinate of the target node coordinate in the data packet and the Y coordinate of the own bus matrix node is judged:

[0085] When the Y coordinate of the target node in the data packet is greater than the Y coordinate of the own bus matrix node, the data packet is output from the southbound interface;

[0086] When the Y coordinate of the target node in the data packet is less than the Y coordinate of the own bus matrix node, the data packet is output from the northbound interface;

[0087] When the Y coordinate of the target node coordinate in the data packet is equal to the Y coordinate of the own bus matrix node, the data packet is returned to the upper layer application or output from the self interface to the peripheral module.

[0088] The bus matrix node in the present invention can be any communication subject, including a digital signal processor, a general processor, a 100M or 1000M optical module, or a DDR2\Flash memory, etc.

[0089] In the present invention, when any two bus matrix nodes communicate as target nodes and source nodes, other bus matrix nodes can also communicate freely. This also avoids the problem of too large a combinational logic chain and limited system bandwidth due to the use of address addressing. It also allows upper-layer application users to focus on the content of the communication data packet itself instead of specific physical layer information, which facilitates programming and use of the application layer.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A matrix elastic bus control system, characterized in that: It includes several bus matrix nodes, each of which includes a northbound interface, an eastbound interface, a southbound interface, a westbound interface, and a self-interface. Each bus matrix node is distributed in a dot matrix, the northbound interface and the southbound interface of adjacent bus matrix nodes are connected, and the eastbound interface and the westbound interface of adjacent bus matrix nodes are connected.

2. The control system of the matrix elastic bus according to claim 1, characterized in that: The sending end and receiving end of the northbound interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y are respectively connected to the receiving end and sending end of the southbound interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y+1; The sending end and receiving end of the east interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y are respectively connected to the receiving end and sending end of the west interface of the bus matrix node with the horizontal coordinate X+1 and the vertical coordinate Y; The sending end and receiving end of the southbound interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y are respectively connected to the receiving end and sending end of the northbound interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y-1; The sending end and receiving end of the west interface of the bus matrix node with the horizontal coordinate X and the vertical coordinate Y are connected to the receiving end and sending end of the east interface of the bus matrix node with the horizontal coordinate X-1 and the vertical coordinate Y respectively.

3. The control system of the matrix elastic bus according to claim 2, characterized in that: The bus matrix node also includes a port input module, a data storage unit, and a port output module; The port input module is used to receive data packets received by the northbound interface, the eastbound interface, the southbound interface, the westbound interface, and the self-interface, or receive data packets generated by the upper layer application; A data storage unit, used for caching data packets; The port output module is used to read the data packet in the data storage unit and forward it to its corresponding interface according to its own bus matrix node and destination node coordinates.

4. The control system of the matrix elastic bus according to claim 3, characterized in that: The port output module determines the size of the X coordinate of the target node coordinate in the data packet and the X coordinate of the bus matrix node itself: When the X coordinate of the target node in the data packet is greater than the X coordinate of the own bus matrix node, the data packet is output from the east interface; When the X coordinate of the target node in the data packet is less than the X coordinate of the own bus matrix node, the data packet is output from the west interface; When the X coordinate of the target node coordinate in the data packet is equal to the X coordinate of the own bus matrix node, the following judgment is made: the size of the Y coordinate of the target node coordinate in the data packet and the Y coordinate of the own bus matrix node is judged: When the Y coordinate of the target node in the data packet is greater than the Y coordinate of the own bus matrix node, the data packet is output from the southbound interface; When the Y coordinate of the target node in the data packet is less than the Y coordinate of the own bus matrix node, the data packet is output from the northbound interface; When the Y coordinate of the target node coordinate in the data packet is equal to the Y coordinate of the own bus matrix node, the data packet is returned to the upper layer application or output from the self interface to the peripheral module.

5. A control method for a matrix elastic bus, based on the control device for a matrix elastic bus according to claim 2, characterized in that: The following steps are involved: 1) Divide the bus matrix nodes into source nodes, intermediate nodes, and target nodes; 2) Define the frame format of the data packet for data communication; 3) The bus matrix node as a source node generates a data packet according to the upper layer application requirements, and the bus matrix node as a source node stores the generated data packet into an internal data storage unit; 4) The port output module of the bus matrix node as the source node reads the data packet in the data storage unit, parses the destination node coordinates, and forwards it to its own corresponding interface according to its own bus matrix node and the destination node coordinates; 5) The bus matrix node as an intermediate node receives the data packet; 6) The port input module in the bus matrix node as the intermediate node receives the data packets input by each interface; 7) The port input module in the bus matrix node as the intermediate node stores the generated data packet into the internal data storage unit; 8) The port output module in the bus matrix node as the intermediate node reads the data packet in the data storage unit, parses the destination node coordinates, and forwards it to its own corresponding interface according to its own bus matrix node and the destination node coordinates; 9) The port input module in the bus matrix node as the target node receives the data packets inputted by each interface, and the bus matrix node as the target node stores the received data packets into the internal data storage unit; 10) The port output module in the bus matrix node as the target node parses the data packet content and sends the data packet to the upper layer application or to the peripheral module from its own self interface.

6. The control method of the matrix elastic bus according to claim 5, characterized in that: The process of storing the data packet into the internal data storage unit is as follows: Determine whether the full flag of the internal data storage unit is full. When the full flag is not full and the free storage space is greater than or equal to the size of the data packet, write the current data packet to the data storage unit; if the full flag is full, or the free storage space is less than the size of the data packet, discard the current data packet.

7. The control method of the matrix elastic bus according to claim 6, characterized in that: The process of forwarding to its corresponding interface according to its own coordinates and the destination node coordinates is as follows: Determine the size of the X coordinate of the target node in the data packet and the X coordinate of the bus matrix node itself: When the X coordinate of the target node in the data packet is greater than the X coordinate of the own bus matrix node, the data packet is output from the east interface; When the X coordinate of the target node in the data packet is less than the X coordinate of the own bus matrix node, the data packet is output from the west interface; When the X coordinate of the target node coordinate in the data packet is equal to the X coordinate of the own bus matrix node, the following judgment is made: the size of the Y coordinate of the target node coordinate in the data packet and the Y coordinate of the own bus matrix node is judged: When the Y coordinate of the target node in the data packet is greater than the Y coordinate of the own bus matrix node, the data packet is output from the southbound interface; When the Y coordinate of the target node in the data packet is less than the Y coordinate of the own bus matrix node, the data packet is output from the northbound interface; When the Y coordinate of the target node coordinate in the data packet is equal to the Y coordinate of the own bus matrix node, the data packet is returned to the upper layer application or output from the self interface to the peripheral module.

8. The control method of the matrix elastic bus according to claim 5, characterized in that: The bus matrix node also includes a port input module, a data storage unit, and a port output module; The port input module is used to receive data packets received by the northbound interface, the eastbound interface, the southbound interface, the westbound interface, and the self-interface, or receive data packets generated by the upper layer application; A data storage unit, used for caching data packets; The port output module is used to read the data packet in the data storage unit and forward it to its corresponding interface according to its own bus matrix node and destination node coordinates.

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