Efficient multi-bit register merging method with physical and time sequence perception

Abstract

The invention provides an efficient multi-bit register merging method with physical and time sequence perception, which performs physical and time sequence perception prediction through a machine learning method, and realizes that a plurality of single-bit registers are merged into a multi-bit register in an early stage of a design process. Therefore, the problems that the multi-bit registers are not combined thoroughly and the influence on the overall time sequence of the chip is large are solved, and the effects that the multi-bit registers are combined more thoroughly and the power consumption is more saved under the condition that the designed overall time sequence level is close to or even better are achieved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to an efficient multi-bit register merging method with physical and timing awareness. Background Art

[0002] The current multi-bit register merging methods are mainly based on accurate information in the later stage of design, while the main early multi-bit register merging methods do not consider timing information and cannot efficiently obtain high-quality multi-bit register merging results that meet timing.

[0003] Patent document CN202011403040.2 discloses an efficient multi-bit register clustering and merging method, which identifies the mergible areas of single-bit registers and merges multi-bit registers through a coordinate mapping algorithm to reduce the power consumption of digital chips. However, this solution is based on accurate physical and timing information in the middle and late stages of the design, which is related to the quality of the early design and cannot fully tap the power saving potential of merging multi-bit registers.

[0004] The Chinese patent document CN202310141759.0 discloses a register merging method for balancing timing violations, which realizes the merging of multi-bit registers for timing-sensitive designs, so that the merged registers do not cause setup timing check violations. However, this solution is also based on accurate physical and timing information in the middle and late stages of the design, which is related to the quality of the early stage design and cannot fully tap the power saving potential of multi-bit register merging.

[0005] The following paper published in the International Conference on Computer-Aided Design in 2016 proposed an early multi-bit register merging algorithm based on logical locality. However, this method does not consider timing information in the algorithm, so it requires multiple process iterations and consumes a lot of time. Compared with this method, the technology proposed in this patent can more efficiently obtain better multi-bit register merging results.

[0006] This application is proposed based on the above problems. Summary of the invention

[0007] The purpose of the present invention is to provide an efficient multi-bit register merging method with physical and timing awareness to solve the problems existing in the above-mentioned prior art.

[0008] To achieve the above object, the present invention provides the following solutions:

[0009] The present invention provides an efficient multi-bit register merging method with physical and timing awareness, comprising the following steps:

[0010] S1. After the chip logic synthesis is completed, a netlist will be generated;

[0011] S2. Use electronic automation design tools for rough placement;

[0012] S3. Filter single-bit register combinations based on distance thresholds;

[0013] S4. Extract all signal path features based on the netlist;

[0014] S5. Input the signal path characteristics into the machine learning timing prediction model to obtain the delay prediction of the corresponding signal path;

[0015] S6. Merge the single-bit register combination based on the conflict graph and greedy algorithm;

[0016] S7. Based on the merging of single-bit register combinations, appropriately loosen the distance threshold and repeat the iteration until all possible multi-bit registers are merged.

[0017] Preferably, step S3 specifically includes: calculating the Manhattan distances between all single-bit register combinations based on the rough placement result, and selecting a distance threshold to filter the single-bit register combinations.

[0018] Preferably, in step S4, the signal path characteristics include logic gate delay, load, slew rate, and fan-out.

[0019] Preferably, step S6 specifically comprises: constructing a conflict graph, constructing nodes for the screened single-bit register combinations, calculating the node weight for each node based on the signal path delay prediction result and the multi-bit register power consumption reduction, and then using a greedy algorithm to select single-bit register combinations for merging until there are no remaining single-bit register combinations.

[0020] Compared with the prior art, the present invention has achieved the following beneficial technical effects:

[0021] The present invention provides an efficient multi-bit register merging method with physical and timing awareness. Physical and timing awareness prediction is performed through machine learning methods, and multiple single-bit registers are merged into multi-bit registers in the early stage of the design process, thereby solving the problem of incomplete merging of multi-bit registers and a great impact on the overall timing of the chip. The multi-bit registers are merged more thoroughly and power consumption is saved more while ensuring that the overall timing level of the design is close to or even better. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0023] Figure 1 A flow chart of an efficient multi-bit register merging method with physical and timing awareness provided by the present invention. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] The purpose of the present invention is to provide an efficient multi-bit register merging method with physical and timing awareness to solve the problems existing in the prior art.

[0026] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] Embodiment 1:

[0028] This embodiment provides an efficient multi-bit register merging method with physical and timing awareness, such as Figure 1 As shown, the following steps are included:

[0029] S1. After the chip logic synthesis is completed, a netlist will be generated;

[0030] S2. Use electronic automation design tools for rough placement;

[0031] S3. Calculate the Manhattan distance between all single-bit register combinations based on the rough placement results, and select the distance threshold to filter the single-bit register combinations

[0032] S4. Extract all signal path features based on the netlist; signal path features include logic gate delay, load, slew rate, and fan-out;

[0033] S5. Input the signal path characteristics into the machine learning timing prediction model to obtain the delay prediction of the corresponding signal path;

[0034] S6. Construct a conflict graph, construct nodes for the filtered single-bit register combinations, calculate the node weight for each node based on the signal path delay prediction result and the power consumption reduction of the multi-bit registers, and then use the greedy algorithm to select single-bit register combinations for merging until there are no remaining single-bit register combinations

[0035] S7. Based on the merging of single-bit register combinations, appropriately loosen the distance threshold and repeat the iteration until all possible multi-bit registers are merged.

[0036] The present invention provides an efficient multi-bit register merging method with physical and timing awareness. Physical and timing awareness prediction is performed through machine learning methods, and multiple single-bit registers are merged into multi-bit registers in the early stage of the design process, thereby solving the problem of incomplete merging of multi-bit registers and a great impact on the overall timing of the chip. The multi-bit registers are merged more thoroughly and power consumption is saved more while ensuring that the overall timing level of the design is close to or even better.

[0037] The present invention uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only used to help understand the method and core ideas of the present invention. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. An efficient multi-bit register merging method with physical and timing awareness, characterized by: The following steps are involved: S1. After the chip logic synthesis is completed, a netlist will be generated; S2. Use electronic automation design tools for rough placement; S3. Filter single-bit register combinations based on distance thresholds; S4. Extract all signal path features based on the netlist; S5. Input the signal path characteristics into the machine learning timing prediction model to obtain the delay prediction of the corresponding signal path; S6. Merge the single-bit register combination based on the conflict graph and greedy algorithm; S7. Based on the merging of single-bit register combinations, appropriately loosen the distance threshold and repeat the iteration until all possible multi-bit registers are merged.

2. The method for efficiently merging multi-bit registers with physical and timing awareness according to claim 1, characterized in that: Step S3 specifically includes: calculating the Manhattan distances between all single-bit register combinations based on the rough placement result, and selecting a distance threshold to filter the single-bit register combinations.

3. The method for efficiently merging multi-bit registers with physical and timing awareness according to claim 1, characterized in that: In step S4, the signal path characteristics include logic gate delay, load, slew rate, and fan-out.

4. The method for efficiently merging multi-bit registers with physical and timing awareness according to claim 1, characterized in that: Step S6 is specifically as follows: constructing a conflict graph, constructing nodes for the screened single-bit register combinations, calculating the node weight for each node based on the signal path delay prediction result and the multi-bit register power consumption reduction, and then using a greedy algorithm to select single-bit register combinations for merging until there are no remaining single-bit register combinations.

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