Circuit parasitic parameter verification method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a circuit parasitic parameter verification method and device, electronic equipment and a storage medium, relates to the technical field of integrated circuits, and is designed for improving the reliability of circuit parasitic parameter verification. The circuit parasitic parameter verification method comprises the following steps: acquiring an inference value of a target parasitic parameter under a first process based on a process design kit (PDK) process library; based on a detailed standard parasitic parameter format DSPF file corresponding to the circuit, obtaining an actual value of the target parasitic parameter of the circuit under the first process; and verifying the target parasitic parameter according to the reasoning value of the target parasitic parameter and the actual value of the target parasitic parameter. The embodiment of the invention can be used for pre-judgment check of parasitic parameters in integrated circuit design.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more specifically, to a circuit parasitic parameter verification method, device, electronic equipment and storage medium. Background Art

[0002] Parasitic parameters refer to the additional resistance, capacitance, and inductance generated by the physical connection between components in an electronic circuit. These parameters are not intentionally added during design, but are caused by the actual physical connection and layout. Parasitic parameters have a significant impact on the performance of the circuit. For example, parasitic capacitance can cause signal delays and oscillations, affecting the stability and speed of the circuit; parasitic resistance can increase power consumption; and parasitic inductance can cause electromagnetic interference and radiation problems. Therefore, the impact of parasitic parameters needs to be fully considered in circuit design, and the impact of parasitic parameters can be reduced by optimizing the layout and using appropriate components.

[0003] At present, in integrated circuit design, for the designed circuit module, the parasitic parameter information of the circuit module is usually extracted using the DSPF (Detailed Standard Parasitic Format) file, and the parasitic parameters of the designed circuit module are verified using the pre-set tolerance value to control the parasitic parameters of the circuit module within a better range and effectively reduce the adverse effects of the parasitic parameters on the performance. However, the reliability of the verification results of the parasitic parameters is currently low. Summary of the invention

[0004] In view of this, embodiments of the present invention provide a circuit parasitic parameter verification method, device, electronic device and storage medium, which can effectively improve the reliability of verification results, thereby effectively reducing the adverse effects of parasitic parameters on circuit performance.

[0005] In a first aspect, an embodiment of the present invention provides a method for verifying circuit parasitic parameters, the method comprising: Based on a process design toolkit PDK process library, obtaining an inference value of a target parasitic parameter under a first process; Based on a detailed standard parasitic parameter format DSPF file corresponding to the circuit, obtaining an actual value of the target parasitic parameter of the circuit under the first process; The target parasitic parameter is verified according to the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter.

[0006] Optionally, in an embodiment of the present invention, the verifying the target parasitic parameter according to the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter includes: Obtaining a deviation value according to the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, the deviation value comprising a difference between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, a ratio between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, or a ratio between the difference between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter and one of the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter; Determining whether the deviation value is within a preset first allowable deviation range; If the deviation value is not within the preset first allowable deviation range, an adjustment process is performed on the actual value of the target parasitic parameter to adjust the deviation value until the deviation value is within the preset first allowable deviation range.

[0007] Further, in one embodiment of the present invention, after determining whether the deviation value is within a preset first allowable deviation range, the method further includes: If the deviation value is within a preset first allowable deviation range, obtaining a second actual value of a target parasitic parameter of the circuit under the first process based on a liberty file of a timing library corresponding to the circuit; Acquire a second deviation value according to the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, wherein the second deviation value includes a difference between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, a ratio between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, or a ratio between the difference between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter and one of the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter; determining whether the second deviation value is within a preset second allowable deviation range; If the second deviation value is not within the preset second allowable deviation range, the actual value and / or the second actual value of the target parasitic parameter are adjusted to adjust the deviation value and / or the second deviation value until the deviation value is within the preset first allowable deviation range and the second deviation value is within the preset second allowable deviation range.

[0008] Optionally, in one embodiment of the present invention, after determining whether the deviation value is within a preset first allowable deviation range, the method further includes: If the deviation value is within a preset first allowable deviation range, a post-simulation process of the circuit is performed based on the actual value of the target parasitic parameter.

[0009] Optionally, in one embodiment of the present invention, obtaining the inference value of the target parasitic parameter under the first process based on the process design toolkit PDK process library includes: Based on a process design toolkit PDK process library, obtaining first target metal layer parameter information corresponding to the target parasitic parameter under the first process; Based on the first target metal layer parameter information, generating a test case layout and a pre-simulation netlist corresponding to the first target metal layer; The basic values ​​of the target parasitic parameters under the first process are extracted from the test case layout and the pre-simulation netlist as the inference values.

[0010] Optionally, in one embodiment of the present invention, obtaining the inference value of the target parasitic parameter under the first process based on the process design toolkit PDK process library includes: Based on a process design toolkit PDK process library, obtaining a ratio between a basic value of the target parasitic parameter under the first process and a basic value of the target parasitic parameter under the second process; Based on the historical DSPF file corresponding to the second process, obtaining a reference value of the target parasitic parameter under the second process; An inferred value of the target parasitic parameter under the first process is obtained based on a ratio between a base value of the target parasitic parameter under the first process and a base value of the target parasitic parameter under the second process and a reference value of the target parasitic parameter under the second process.

[0011] Further, in one embodiment of the present invention, obtaining the ratio between the target parasitic parameter under the first process and the target parasitic parameter under the second process based on the process design toolkit PDK process library includes: Based on the process library of the process design toolkit PDK, obtaining the first target metal layer parameter information corresponding to the target parasitic parameters under the first process, generating the test case layout and pre-simulation netlist corresponding to the first target metal layer based on the first target metal layer parameter information, and extracting the basic values ​​of the target parasitic parameters under the first process from the test case layout and pre-simulation netlist; and, based on the process library of the process design toolkit PDK, obtaining the target metal layer parameter information corresponding to the target parasitic parameters under the second process, generating the test case layout and pre-simulation netlist corresponding to the target metal layer based on the target metal layer parameter information, and extracting the basic values ​​of the target parasitic parameters under the second process from the test case layout and pre-simulation netlist corresponding to the target metal layer; Based on the basic value of the target parasitic parameter under the first process and the basic value of the target parasitic parameter under the second process, a ratio between the basic value of the target parasitic parameter under the first process and the basic value of the target parasitic parameter under the second process is obtained.

[0012] Optionally, in one embodiment of the present invention, the adjustment process of the actual value of the target parasitic parameter includes: Prompt information that the actual value of the target parasitic parameter deviates greatly from the inferred value is provided and / or adjustment suggestions for the actual value of the target parasitic parameter are provided.

[0013] Optionally, in one embodiment of the present invention, the parasitic parameters include capacitance, resistance or inductance.

[0014] In a second aspect, an embodiment of the present invention provides a circuit parasitic parameter verification device, the device comprising: A first acquisition unit, configured to acquire an inference value of a target parasitic parameter under a first process based on a process design toolkit PDK process library; A second acquisition unit, configured to acquire an actual value of the target parasitic parameter of the circuit under the first process based on a detailed standard parasitic parameter format DSPF file corresponding to the circuit; A verification unit is used to verify the target parasitic parameter according to the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter.

[0015] Optionally, in one embodiment of the present invention, the verification unit includes: an acquisition module, configured to acquire a deviation value according to the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, wherein the deviation value includes a difference between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, a ratio between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, or a ratio between the difference between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter and the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter; A determination module, used to determine whether the deviation value is within a preset first allowable deviation range; The adjustment module is used for adjusting the actual value of the target parasitic parameter to adjust the deviation value if the deviation value is not within the preset first allowable deviation range, until the deviation value is within the preset first allowable deviation range.

[0016] Furthermore, in one embodiment of the present invention, the device further comprises: A third acquisition unit is used to acquire, if the deviation value is within a preset first allowable deviation range, a second actual value of a target parasitic parameter of the circuit under the first process based on a timing library liberty file corresponding to the circuit; a fourth acquiring unit, configured to acquire a second deviation value according to the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, wherein the second deviation value includes a difference between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, a ratio between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, or a ratio between the difference between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter and one of the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter; A second verification unit is used to determine whether the second deviation value is within a preset second allowable deviation range. If the second deviation value is not within the preset second allowable deviation range, an adjustment process is performed on the actual value and / or the second actual value of the target parasitic parameter, thereby adjusting the deviation value and / or the second deviation value until the deviation value is within the preset first allowable deviation range and the second deviation value is within the preset second allowable deviation range.

[0017] Optionally, in one embodiment of the present invention, the device further includes: The simulation unit performs post-simulation processing of the circuit based on the actual value of the target parasitic parameter if the deviation value is within a preset first allowable deviation range.

[0018] Optionally, in one embodiment of the present invention, the first acquiring unit includes: A first acquisition module is used to acquire first target metal layer parameter information corresponding to the target parasitic parameter under the first process based on a process design toolkit PDK process library; A generation module, used for generating a test case layout and a pre-simulation netlist corresponding to the first target metal layer based on the parameter information of the first target metal layer; The second acquisition module is used to extract the basic value of the target parasitic parameter under the first process from the test case layout and the pre-simulation netlist as the inference value.

[0019] Optionally, in one embodiment of the present invention, the first acquiring unit includes: A third acquisition module is used to acquire a ratio between a basic value of the target parasitic parameter under the first process and a basic value of the target parasitic parameter under the second process based on a process design toolkit PDK process library; A fourth acquisition module, configured to acquire a reference value of the target parasitic parameter under the second process based on a historical DSPF file corresponding to the second process; A fifth acquisition module is used to acquire an inferred value of the target parasitic parameter under the first process based on a ratio between a base value of the target parasitic parameter under the first process and a base value of the target parasitic parameter under the second process and a reference value of the target parasitic parameter under the second process.

[0020] Furthermore, in one embodiment of the present invention, the third acquisition module is specifically used for: Based on the process library of the process design toolkit PDK, obtaining the first target metal layer parameter information corresponding to the target parasitic parameters under the first process, generating the test case layout and pre-simulation netlist corresponding to the first target metal layer based on the first target metal layer parameter information, and extracting the basic values ​​of the target parasitic parameters under the first process from the test case layout and pre-simulation netlist; and, based on the process library of the process design toolkit PDK, obtaining the target metal layer parameter information corresponding to the target parasitic parameters under the second process, generating the test case layout and pre-simulation netlist corresponding to the target metal layer based on the target metal layer parameter information, and extracting the basic values ​​of the target parasitic parameters under the second process from the test case layout and pre-simulation netlist corresponding to the target metal layer; Based on the basic value of the target parasitic parameter under the first process and the basic value of the target parasitic parameter under the second process, a ratio between the basic value of the target parasitic parameter under the first process and the basic value of the target parasitic parameter under the second process is obtained.

[0021] Optionally, in one embodiment of the present invention, the adjustment module is specifically used to: Prompt information that the actual value of the target parasitic parameter deviates greatly from the inferred value is provided and / or adjustment suggestions for the actual value of the target parasitic parameter are provided.

[0022] Optionally, in one embodiment of the present invention, the parasitic parameters include capacitance, resistance or inductance.

[0023] In a third aspect, an embodiment of the present invention provides an electronic device, comprising: a processor and a memory, wherein the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the verification method described in the method of the first aspect above.

[0024] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the verification method described in the first aspect above.

[0025] The circuit parasitic parameter verification method, device, electronic device and storage medium provided in the embodiments of the present invention use the PDK process library to obtain the inference value corresponding to the target parasitic parameter under the first process, use the DSPF file to obtain the actual value of the target parasitic parameter of the circuit, and verify the target parasitic parameter based on the inference value and the actual value. Since the basic process corresponding information in the PDK is used when obtaining the inference value, the inference value has significant process correspondence, thereby effectively improving the reliability of the verification result and significantly reducing the adverse effects of the parasitic parameters on the circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A flow chart of a circuit parasitic parameter verification method provided by an embodiment of the present invention; Figure 2 A schematic diagram of the structure of a verification device provided by an embodiment of the present invention; Figure 3 for Figure 2 A schematic diagram of the structure of a verification unit in the verification device shown; Figure 4 A schematic diagram of the structure of a verification device provided by an embodiment of the present invention; Figure 5 for Figure 2 A schematic diagram of the structure of a first acquisition unit in the verification device shown; Figure 6 for Figure 2 A schematic diagram of the structure of a first acquisition unit in the verification device shown; Figure 7 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The implementation methods described in the following examples do not represent all implementation methods consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the attached claims.

[0031] It should be noted that the phrase "at least one of the items" in the present invention includes three types of parallel situations: "any one of the items", "a combination of any number of the items", and "all of the items". For example, "including at least one of A and B" includes the following three parallel situations: (1) including A; (2) including B; (3) including A and B. Another example is "executing at least one of step 1 and step 2" which means the following three parallel situations: (1) executing step 1; (2) executing step 2; (3) executing step 1 and step 2.

[0032] As described in the background technology above, parasitic parameters have a significant impact on the performance of the circuit. Therefore, in integrated circuit design, it is usually necessary to verify the parasitic parameters of the designed circuit module through QA (quality assurance). After the parasitic parameter QA process, the layout of the circuit module is adjusted to control the parasitic parameters of the circuit module within an optimal range, thereby effectively reducing the adverse effects of the parasitic parameters on the performance.

[0033] DSPF is a detailed standard format for describing parasitic parameters in a circuit. It is often used in the post-simulation stage of integrated circuit design to ensure that the circuit design meets performance requirements. The DSPF file contains detailed parasitic capacitance and resistance information for each network (net) in the circuit, which is essential for accurately simulating the behavior of the circuit under actual working conditions. DSPF files usually contain the following: Parasitic capacitance of the network: describes the capacitive coupling between each network and the ground or other networks. Parasitic resistance of the network: describes the resistance value of the network, which is usually related to the width, length and material of the wiring.

[0034] Interconnection delay: The RC network model is used to simulate the propagation delay of the signal in the wiring.

[0035] Unit Instance: In the file, each circuit element (such as transistor, capacitor, inductor, etc.) is instantiated and associated with the corresponding network.

[0036] In the prior art, the parasitic parameter information of the circuit is usually extracted from the DSPF file corresponding to the circuit, and then the parasitic parameter information is verified, but the parasitic parameters are greatly affected by the actual process, and the reliability of the verification results of the parasitic parameters is currently low. In view of this, an embodiment of the present invention provides a circuit parasitic parameter verification method, which can effectively improve the reliability of the verification results. Among them, the parasitic parameter can be any parasitic parameter such as capacitance, resistance, inductance, etc., and the embodiment of the present invention does not limit this.

[0037] The following is combined with Figure 1 , describes in detail the technical solution provided by the embodiments of the present invention. Figure 1 The flowchart of the circuit parasitic parameter verification method provided by the embodiment of the present invention, the implementation subject of the method may include an electronic device, specifically a platform or application set on the electronic device. The electronic device may be a terminal device, such as a personal computer, a desktop computer, etc. The electronic device may also be a server.

[0038] like Figure 1 As shown, the verification method of this embodiment specifically includes the following steps: Step 110: Based on the PDK process library, obtain the inference value of the target parasitic parameter under the first process.

[0039] Among them, PDK, or Process Design Kit, is an abbreviation for process design toolkit or process design kit, which is a bridge for communication between chip design companies, chip manufacturers and EDA (Electronic Design Automation) tool manufacturers. A typical PDK contains the original device library, physical rule verification check files, technology files, rule files, device models, etc.

[0040] In this step, the first process is the process used by the circuit or circuit module that needs to be verified for parasitic parameters, which is also referred to as the process used by the new project in the embodiment of the present invention. After determining the process used by the new project, the PDK process library can be used to obtain various basic information associated with the process used by the new project, that is, the PDK process library can be used to obtain process-related information corresponding to the target parasitic parameters under the first process.

[0041] In the embodiment of the present invention, the verification process of the "target parasitic parameter" will be described. It should be emphasized that the target parasitic parameter refers to a specific parasitic parameter with clear attributes, such as the network (net) where the parasitic parameter is located, the metal layer (i.e., the target metal layer) corresponding to the net corresponding to the parasitic parameter, the process corner corresponding to the parasitic parameter, the parasitic parameter model caused by the layout and wiring in the layout (layout design) to which the parasitic parameter belongs, etc.

[0042] In this step, considering that the process has a great influence on the parasitic parameters, in order to improve the process relevance of the verification process, the inferred value of the target parasitic parameter under the first process is obtained based on the PDK process library. The inferred value can be considered as a reasonable value of the target parasitic parameter under the first process obtained based on the basic process information provided by the PDK process library.

[0043] Optionally, in one embodiment of the present invention, in this step, the first target metal layer parameter information corresponding to the target parasitic parameters under the first process can be obtained based on the PDK process library, for example, the metal layer identification information ID, the minimum width (width) of the metal line corresponding to the metal layer, and the minimum gap (space) between the metal lines, etc. Then, based on these first target metal layer parameter information, the test case layout (GDS, Graphic Data System) and pre-simulation netlist (CDL, Compact Design Language) corresponding to the first target metal layer are generated; then, the basic values ​​of the target parasitic parameters under the first process are extracted from the test case layout and pre-simulation netlist as inference values.

[0044] Optionally, in another embodiment of the present invention, in this step, the ratio of the base value of the target parasitic parameter under the first process to the base value of the target parasitic parameter under the second process can be first obtained based on the PDK process library. Wherein, the second process can be a process used in a previous historical process project, and a corresponding historical DSPF file has been accumulated. The target parasitic parameter value under the second process can be obtained based on the historical DSPF file corresponding to the second process as a reference value. This step does not limit what kind of process the second process is, and preferably a process similar to the first process can be selected. The inference value of the target parasitic parameter under the first process can be obtained based on the ratio of the base value of the target parasitic parameter under the first process to the base value of the target parasitic parameter under the second process and the reference value of the target parasitic parameter under the second process. Wherein, inference value / reference value=ratio, then, inference value=ratio×reference value, or, reference value / inference value=ratio, then, inference value=reference value / ratio.

[0045] Among them, the basic values ​​of the target parasitic parameters under the first process and the basic values ​​of the target parasitic parameters under the second process can be obtained based on the PDK process library, respectively, and then the ratio of the two can be obtained. Specifically, the first target metal layer parameter information corresponding to the target parasitic parameters under the first process can be obtained based on the PDK process library, and the test case layout and pre-simulation netlist corresponding to the first target metal layer can be generated based on the first target metal layer parameter information, and the basic values ​​of the target parasitic parameters under the first process can be extracted from the test case layout and pre-simulation netlist; in parallel or serially, the target metal layer parameter information corresponding to the target parasitic parameters under the second process can be obtained based on the process design toolkit PDK process library, and the test case layout and pre-simulation netlist corresponding to the target metal layer can be generated based on the parameter information of the target metal layer, and the basic values ​​of the target parasitic parameters under the second process can be extracted from the test case layout and pre-simulation netlist corresponding to the target metal layer; based on the basic values ​​of the target parasitic parameters under the first process and the basic values ​​of the target parasitic parameters under the second process, the ratio of the basic values ​​of the target parasitic parameters under the first process and the basic values ​​of the target parasitic parameters under the second process can be obtained.

[0046] In this embodiment, the basic value of the first process is obtained from the PDK process library, the basic value of the second process is obtained by using the DSPF file corresponding to the second process of the historical project, and the ratio is used to obtain the inferred value of the target parasitic parameter under the first process. This method not only takes into account the influence of the process (PDK), but also draws on the results of the actual process (historical DSPF file of the second process). Therefore, the obtained inferred value is more process reasonable and can effectively improve the reliability of the verification result.

[0047] Step 120 : acquiring actual values ​​of target parasitic parameters of the circuit under the first process based on a detailed standard parasitic parameter format DSPF file corresponding to the circuit.

[0048] In this step, the DSPF file of the circuit in the new project is used to obtain the value of the target parasitic parameter in the actual circuit under the first process, that is, the actual value.

[0049] Step 130 : verifying the target parasitic parameter according to the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter.

[0050] In this step, the target parasitic parameters are verified based on the inference values ​​and actual values. Since the basic process correspondence information in the PDK is used when obtaining the inference values, the inference values ​​have significant process correspondence, which effectively improves the reliability of the verification results and significantly reduces the adverse effects of parasitic parameters on circuit performance.

[0051] In this step, the inferred value and the actual value of the target parasitic parameter are compared to achieve the purpose of verification. Specifically, the deviation value can be first obtained according to the inferred value of the target parasitic parameter (assuming A) and the actual value of the target parasitic parameter (assuming B), and it is determined whether the deviation value is within a reasonable deviation range, that is, whether the deviation value is within a preset first allowable deviation range.

[0052] The deviation value is used to indicate the difference between the inferred value and the actual value, and may be the difference (AB) or (BA) between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter. The deviation value may also be the ratio A / B or B / A between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter. The deviation value may also be the ratio (AB) / A, (AB) / B, (BA) / A or (BA) / B between the difference between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter and one of the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter. It should be noted that the above-mentioned difference or ratio may take an absolute value.

[0053] If the deviation value is not within the preset first allowable deviation range, execute step 140, perform adjustment processing on the actual value of the target parasitic parameter to adjust the deviation value, and return to the layout design of the first process. The specific adjustment processing may include adjusting the design of the relevant metal wires, or modifying the configuration to regenerate CDL and GDS, or correcting the parameters to re-extract DSPF, re-acquire the actual value, and continue to compare it with the inference value of the target parasitic parameter to obtain the deviation value, determine whether the deviation value is within the preset first allowable deviation range, and repeat and iterate the above process until the deviation value obtained from the reference value and inference value of the target parasitic parameter in the DSPF corresponding to the actual circuit is within the preset first allowable deviation range. In this way, the adjustment direction can be indicated for the layout design, so that the layout is continuously iterated and adjusted to the optimal situation.

[0054] In one embodiment of the present invention, optionally, if the deviation value is not within a pre-set first allowable deviation range, a prompt message can be provided that the actual value of the target parasitic parameter is unreasonable, for example, a prompt message that the actual value of the target parasitic parameter deviates greatly from the inferred value. Adjustment suggestions for the actual value of the target parasitic parameter can also be provided, for example, prompt information and adjustment suggestions can be provided in the form of a pop-up window, etc., to facilitate the staff to perform subsequent adjustment processing.

[0055] In one embodiment of the present invention, optionally, if the deviation value is within a preset first allowable deviation range, it can be considered that the target parasitic parameter has passed the verification, and post-simulation processing of the circuit can be performed based on the actual value of the target parasitic parameter.

[0056] In one embodiment of the present invention, in order to further improve the reliability of verification, optionally, if the deviation value is within a pre-set first allowable deviation range, the target parasitic parameter value of the circuit's timing library liberty file can be combined for further inspection. Among them, in the field of integrated circuit (IC) design, ".lib" file, sometimes also called "Libertyfile", is a standard file format containing timing and power consumption information of a standard cell library (Standard Cell Library) or IP core, which is widely used for timing analysis and power consumption optimization. In Chinese integrated circuit design literature and technical communities, people often directly use the original English noun "Liberty" to retain its original meaning and to facilitate consistency with international technical standards and practices. In an embodiment of the present invention, the liberty file is called a "timing library file."

[0057] Specifically, based on the liberty file of the timing library, the second actual value of the target parasitic parameter of the circuit under the first process can be obtained; according to the actual value of the target parasitic parameter (assuming it is B) and the second actual value of the target parasitic parameter (assuming it is C), the second deviation value is obtained. Similar to the deviation value in the aforementioned step 130, the second deviation value can be the difference (BC) or (CB) between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, or the ratio B / C or C / B between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter. The second deviation value can also be the ratio (BC) / B, (BC) / C, (CB) / B, (CB) / C between the difference between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter and one of the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter. It should be noted that the above difference or ratio can be taken as an absolute value.

[0058] If the second deviation value is within the preset second allowable deviation range, it means that the target parasitic parameter under the first process has passed the verification, and then the post-simulation processing of the circuit and other operations can be performed based on the actual value of the target parasitic parameter. If the second deviation value is not within the preset second allowable deviation range, it is necessary to adjust the actual value of the target parasitic parameter and / or the second actual value. For example, the configuration can be modified to regenerate the liberty file (i.e., adjust the second actual value), the configuration can be modified to regenerate the DSPF file (i.e., adjust the actual value), and even the layout design can be re-performed (adjust the second actual value and the actual value). That is, the actual value and the second actual value are adjusted, and the deviation value and the second deviation value also change accordingly. Therefore, it is necessary to determine again whether the deviation value is within the preset first allowable deviation range. If it is not within the first allowable deviation range, The actual value is adjusted again, and when it is in the first allowable deviation range, it is further verified whether the second deviation value is in the second allowable range. When it is in the second allowable deviation range, it means that the target parasitic parameter has passed the verification. When it is not in the second allowable deviation range, the actual value of the target parasitic parameter and / or the second actual value are adjusted again. This iteration is repeated until the deviation value is in the preset first allowable deviation range, and the second deviation value is in the preset second allowable deviation range, which means that the verification is passed, and the post-simulation processing of the circuit and other operations can be performed based on the actual value of the target parasitic parameter and the second actual value. Of course, when the second deviation value is not in the preset second allowable deviation range, a prompt message that the actual value of the target parasitic parameter has a large deviation from the second actual value can be provided, and adjustment suggestions for the actual value and / or the second actual value can also be provided.

[0059] The circuit parasitic parameter verification method provided in an embodiment of the present invention obtains the inference value corresponding to the target parasitic parameter under the first process by using the PDK process library, obtains the actual value of the target parasitic parameter of the circuit by using the DSPF file, obtains the deviation value based on the inference value and the actual value, and if the deviation value is not within the preset first allowable deviation range, adjusts the actual value of the target parasitic parameter until the deviation value is within the preset first allowable deviation range. Since the basic process corresponding information in the PDK is used when obtaining the inference value for comparison, the inference value has significant process correspondence, thereby effectively improving the reliability of the verification result and significantly reducing the adverse effects of the parasitic parameters on the circuit performance.

[0060] The following is a detailed description of the circuit parasitic parameter verification method of the present invention through a specific embodiment. In this specific embodiment, the previous (i.e. historical) project uses process 1, and the new project uses process 2. The parasitic parameter to be verified is capacitance. What needs to be verified is whether the multiple target parasitic capacitances under process 1 are reasonable, and the impact on performance is small. The verification method of this embodiment includes: Step A, using the PDK process library, collect and organize the basic values ​​of each parasitic parameter under Process1 and Process2, and then calculate the ratio between the basic values ​​of a certain target parasitic parameter under Process1 and Process2, and store the properties, basic values ​​and ratios of each parasitic parameter in the database. Specifically: A configuration file may be prepared in advance, wherein the configuration file indicates relevant information of the target metal layer to be measured for two processes Process1 and Process2; Based on the configuration file, the target metal layers and related parameters such as width and space that need to be measured under Process1 and Process2 are obtained from the PDK process library; according to the read metal layer related parameters, the test case layout (GDS) and the corresponding pre-simulation netlist (CDL) are generated for the target metal layers under Process1 and Process2 respectively; Extract parasitic parameter information from the layout and pre-simulation netlist of Process1 and Process2 respectively, and output the file in dspf format; Collect the capacitance value of the target wire under each test case of each target metal layer in the layout of each Process1 and Process2 and the pre-simulation netlist from the dspf format file. At the same time, compare the relevant capacitance values ​​of Process1 and Process2, and record the ratio in the database. The ratio of each capacitance under the two processes is shown in Table 1 below:

[0061] Step B, collect and organize the capacitance data of each important signal line in the DSPF netlist file of the circuit design project in the previous process Process1, and store it in the database. The database content can be specifically shown in Table 2 below, recording the relevant capacitance information of different nets in the DSPF file under different corners of Process1, and recording the metal layer corresponding to each net and the parasitic parameter model caused by the layout and wiring in the layout (layout design) to which each net belongs (not shown in the table):

[0062] in, PAD is the M1CB metal layer and uses the Neighbor_pwr 1w1p model; XCommon_18 is the M2CA metal layer and uses the Neighbor_no_pwr 1w1p model.

[0063] It is understandable that the execution order of steps A and B is not limited, and they can be executed in parallel or in series.

[0064] Step C: Based on the capacitance ratio information under Process1 and Process2 obtained in step A and the capacitance data of each important signal line in the DSPF netlist file of the circuit design project in the previous process Process1 in step B, the inference value of each target capacitance data of Process2 is obtained. The inference value = ratio × each capacitance value under Process1, as shown in the following table. The relevant capacitance information of different nets under different corners (which may also involve the metal layer corresponding to each net and the metal layer parasitic model to which each net belongs) in the DSPF netlist of process Process2 is calculated based on the ratio of step A and the capacitance value of step B, that is, the inference value:

[0065] For example, for NET is PAD (M1CB metal layer, using Neighbor_pwr 1w1p model), the target parasitic capacitance of Corner1 can be found in the database table 1 of step A, the capacitance ratio of Process 1 and Process 2 is 74.60%, and the capacitance of the previous process Process 1 can be found in the database table 2 of step B, which is 1.623. Then, the capacitance of Process 2 can be deduced to be 1.623 / 74.6%=2.176 (see Table 3). Other calculations can be carried out in the same way.

[0066] Step D, based on the capacitance inference value of each target parasitic parameter under Process2 in step 3 and the actual capacitance value in the DSPF netlist of the circuit under the actual Process2 (see Table 4), obtain the tolerance between the inference value and the actual value, that is, the deviation value (see Table 5), and determine whether the deviation value is within a reasonable tolerance range. If the deviation value is within the preset tolerance range, the DSPF capacitance value of Process2 passes, and step E can be executed to perform a joint check with the capacitance value (second actual value) in the liberty file. If the deviation value is not within the preset tolerance range, it is necessary to return to the layout design of Process2, adjust the design of the relevant metal lines, or modify the configuration to regenerate cdl and gds, or correct the parameters to re-extract DSPF, so as to obtain the actual capacitance value in DSPF again, and continue to compare with the capacitance inference value. Repeat and iterate the above process until the deviation between the actual capacitance value and the inference value in DSPF is within the preset tolerance range.

[0067]

[0068]

[0069] Among them, Proc1 is the inferred value and Proc2 is the actual value.

[0070] Assuming that the reasonable tolerance range is preset to no more than 2%, it can be seen that the value of 2.39% in XCommon_18:corner2 has exceeded the limit and the layout needs to be redesigned.

[0071] Step E, based on the actual values ​​of each capacitor in DSPF in Process2, QA the capacitor value in liberty of Process2 release to determine whether the difference between the two (i.e., the second deviation value) is within a reasonable tolerance range. If it is within a certain reasonable range, the capacitor verification in liberty of Process2 also passes, and the process ends; if it is not within a certain range, it is necessary to regenerate the liberty file or regenerate the DSPF, or even redesign the layout, and iterate repeatedly to find the optimal capacitor value (actual value and / or second actual value).

[0072] Figure 2 A schematic diagram of a device structure provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, the device of this embodiment may include: A first acquisition unit 20 is used to acquire an inference value of a target parasitic parameter under a first process based on a process design toolkit PDK process library; A second acquisition unit 21 is used to acquire an actual value of the target parasitic parameter of the circuit under the first process based on a detailed standard parasitic parameter format DSPF file corresponding to the circuit; The verification unit 22 is used to verify the target parasitic parameter according to the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter.

[0073] Optional, such as Figure 3 As shown, in one embodiment of the present invention, the verification unit 22 includes: an acquisition module 220, configured to acquire a deviation value according to the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, wherein the deviation value includes a difference between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, a ratio between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, or a ratio between the difference between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter and the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter; A determination module 221 is used to determine whether the deviation value is within a preset first allowable deviation range; The adjustment module 222 is used for adjusting the actual value of the target parasitic parameter to adjust the deviation value if the deviation value is not within the preset first allowable deviation range, until the deviation value is within the preset first allowable deviation range.

[0074] Optionally, in one embodiment of the present invention, Figure 4 As shown, the device also includes: A third acquisition unit 23 is used to acquire a second actual value of a target parasitic parameter of the circuit under the first process based on a timing library liberty file corresponding to the circuit if the deviation value is within a preset first allowable deviation range; a fourth acquiring unit 24, configured to acquire a second deviation value according to the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, wherein the second deviation value includes a difference between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, a ratio between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, or a ratio between the difference between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter and one of the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter; The second verification unit 25 is used to determine whether the second deviation value is within a preset second allowable deviation range. If the second deviation value is not within the preset second allowable deviation range, an adjustment process is performed on the actual value and / or the second actual value of the target parasitic parameter, thereby adjusting the deviation value and / or the second deviation value until the deviation value is within the preset first allowable deviation range and the second deviation value is within the preset second allowable deviation range.

[0075] Optionally, in one embodiment of the present invention, the device further includes: The simulation unit performs post-simulation processing of the circuit based on the actual value of the target parasitic parameter if the deviation value is within a preset first allowable deviation range.

[0076] Optional, such as Figure 5 As shown, in one embodiment of the present invention, the first acquisition unit 20 includes: A first acquisition module 201 is used to acquire first target metal layer parameter information corresponding to the target parasitic parameter under a first process based on a process design toolkit PDK process library; A generating module 202, configured to generate a test case layout and a pre-simulation netlist corresponding to the first target metal layer based on the parameter information of the first target metal layer; The second acquisition module 203 is used to extract the basic value of the target parasitic parameter under the first process from the test case layout and the pre-simulation netlist as the inference value.

[0077] Optional, such as Figure 6 As shown, in another embodiment of the present invention, the first acquisition unit 20 includes: A third acquisition module 204 is used to acquire a ratio between a basic value of the target parasitic parameter under the first process and a basic value of the target parasitic parameter under the second process based on a process design toolkit PDK process library; A fourth acquisition module 205 is used to acquire a reference value of the target parasitic parameter under the second process based on a historical DSPF file corresponding to the second process; The fifth acquisition module 206 is used to acquire an inferred value of the target parasitic parameter under the first process based on a ratio between a base value of the target parasitic parameter under the first process and a base value of the target parasitic parameter under the second process and a reference value of the target parasitic parameter under the second process.

[0078] Optionally, in one embodiment of the present invention, the third acquisition module 204 is specifically used for: Based on the process library of the process design toolkit PDK, the first target metal layer parameter information corresponding to the target parasitic parameters under the first process is obtained, based on the first target metal layer parameter information, a test case layout and a pre-simulation netlist corresponding to the first target metal layer are generated, and the basic values ​​of the target parasitic parameters under the first process are extracted from the test case layout and the pre-simulation netlist; and, based on the process library of the process design toolkit PDK, the target metal layer parameter information corresponding to the target parasitic parameters under the second process is obtained, based on the target metal layer parameter information, a test case layout and a pre-simulation netlist corresponding to the target metal layer are generated, and the basic values ​​of the target parasitic parameters under the second process are extracted from the test case layout and the pre-simulation netlist corresponding to the target metal layer; based on the basic values ​​of the target parasitic parameters under the first process and the basic values ​​of the target parasitic parameters under the second process, the ratio between the basic values ​​of the target parasitic parameters under the first process and the basic values ​​of the target parasitic parameters under the second process is obtained.

[0079] Optionally, in one embodiment of the present invention, the adjustment module 222 is specifically used to: provide prompt information that the actual value of the target parasitic parameter deviates greatly from the inferred value and / or provide adjustment suggestions for the actual value of the target parasitic parameter.

[0080] Optionally, in one embodiment of the present invention, the parasitic parameters include capacitance, resistance or inductance.

[0081] The device of the embodiment of the present invention can be used to perform Figure 1 The technical solution of the method embodiment shown has similar implementation principles and technical effects, which will not be repeated here.

[0082] Accordingly, a device provided by an embodiment of the present invention may also be implemented by another structure. Figure 6 A schematic diagram of the structure of an electronic device embodiment provided by the present invention can implement the present invention Figure 1 The process of the embodiment shown is as follows: Figure 6 As shown, the electronic device may include: a housing 61, a processor 62, a memory 63, a circuit board 64 and a power supply circuit 65, wherein the circuit board 64 is arranged inside the space enclosed by the housing 61, and the processor 62 and the memory 63 are arranged on the circuit board 64; the power supply circuit 65 is used to supply power to various circuits or devices of the electronic device; the memory 63 is used to store executable program codes; the processor 62 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 63, so as to execute the method of the aforementioned embodiment.

[0083] For details on the specific execution process of the above steps by the processor 62 and the steps further executed by the processor 62 by running the executable program code, please refer to the present invention. Figure 1The description of the illustrated embodiment will not be repeated here.

[0084] The electronic device is a device that provides computing services. The electronic device consists of a processor, hard disk, memory, system bus, etc. The electronic device is similar to the general computer architecture, but because it needs to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, manageability, etc.

[0085] It should be noted that, in this article, terms such as "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0086] Each embodiment in this specification is described in a corresponding manner, and the same or similar parts between the embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments.

[0087] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the corresponding parts can be referred to the partial description of the method embodiment.

[0088] The logic and / or steps represented in the flowchart or otherwise described herein, for example, may be considered as an ordered list of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by an instruction execution system, apparatus or device (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, apparatus or device and execute instructions), or in conjunction with such instruction execution system, apparatus or device. For purposes of this specification, "computer-readable medium" may be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, apparatus or device, or in conjunction with such instruction execution system, apparatus or device.

[0089] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0090] It should be understood that various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof.

[0091] In the above embodiments, multiple steps or methods may be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it may be implemented by any one of the following technologies known in the art or a combination thereof: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0092] A person skilled in the art may understand that all or part of the steps in the above-mentioned embodiment method may be completed by instructing the corresponding hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0093] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0094] It can be known from the above description of the implementation mode that those skilled in the art can clearly understand that the present invention can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present invention can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of various embodiments of the present invention or certain parts of the embodiments.

Claims

1. A method for verifying circuit parasitic parameters, characterized in that: The method comprises: Based on a process design toolkit PDK process library, obtaining an inference value of a target parasitic parameter under a first process; Based on a detailed standard parasitic parameter format DSPF file corresponding to the circuit, obtaining an actual value of the target parasitic parameter of the circuit under the first process; The target parasitic parameter is verified according to the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter.

2. The method according to claim 1, characterized in that The verifying the target parasitic parameter according to the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter includes: Obtaining a deviation value according to the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, the deviation value comprising a difference between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, a ratio between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, or a ratio between the difference between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter and one of the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter; Determining whether the deviation value is within a preset first allowable deviation range; If the deviation value is not within the preset first allowable deviation range, an adjustment process is performed on the actual value of the target parasitic parameter to adjust the deviation value until the deviation value is within the preset first allowable deviation range.

3. The method according to claim 2, characterized in that After determining whether the deviation value is within a preset first allowable deviation range, the method further includes: If the deviation value is within a preset first allowable deviation range, obtaining a second actual value of a target parasitic parameter of the circuit under the first process based on a liberty file of a timing library corresponding to the circuit; Acquire a second deviation value according to the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, wherein the second deviation value includes a difference between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, a ratio between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, or a ratio between the difference between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter and one of the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter; determining whether the second deviation value is within a preset second allowable deviation range; If the second deviation value is not within the preset second allowable deviation range, the actual value and / or the second actual value of the target parasitic parameter are adjusted to adjust the deviation value and / or the second deviation value until the deviation value is within the preset first allowable deviation range and the second deviation value is within the preset second allowable deviation range.

4. The method according to claim 2, characterized in that: After determining whether the deviation value is within a preset first allowable deviation range, the method further includes: If the deviation value is within a preset first allowable deviation range, a post-simulation process of the circuit is performed based on the actual value of the target parasitic parameter.

5. The method according to any one of claims 1 to 4, characterized in that: The step of obtaining the inference value of the target parasitic parameter under the first process based on the process design toolkit PDK process library includes: Based on a process design toolkit PDK process library, obtaining first target metal layer parameter information corresponding to the target parasitic parameter under the first process; Based on the first target metal layer parameter information, generating a test case layout and a pre-simulation netlist corresponding to the first target metal layer; The basic values ​​of the target parasitic parameters under the first process are extracted from the test case layout and the pre-simulation netlist as the inference values.

6. The method according to any one of claims 1 to 4, characterized in that: The step of obtaining the inference value of the target parasitic parameter under the first process based on the process design toolkit PDK process library includes: Based on a process design toolkit PDK process library, obtaining a ratio between a basic value of the target parasitic parameter under the first process and a basic value of the target parasitic parameter under the second process; Based on the historical DSPF file corresponding to the second process, obtaining a reference value of the target parasitic parameter under the second process; An inferred value of the target parasitic parameter under the first process is obtained based on a ratio between a base value of the target parasitic parameter under the first process and a base value of the target parasitic parameter under the second process and a reference value of the target parasitic parameter under the second process.

7. The method according to claim 6, characterized in that The obtaining, based on the process design toolkit PDK process library, a ratio between the target parasitic parameter under the first process and the target parasitic parameter under the second process comprises: Based on the process library of the process design toolkit PDK, obtaining the first target metal layer parameter information corresponding to the target parasitic parameters under the first process, generating the test case layout and pre-simulation netlist corresponding to the first target metal layer based on the first target metal layer parameter information, and extracting the basic values ​​of the target parasitic parameters under the first process from the test case layout and pre-simulation netlist; and, based on the process library of the process design toolkit PDK, obtaining the target metal layer parameter information corresponding to the target parasitic parameters under the second process, generating the test case layout and pre-simulation netlist corresponding to the target metal layer based on the target metal layer parameter information, and extracting the basic values ​​of the target parasitic parameters under the second process from the test case layout and pre-simulation netlist corresponding to the target metal layer; Based on the basic value of the target parasitic parameter under the first process and the basic value of the target parasitic parameter under the second process, a ratio between the basic value of the target parasitic parameter under the first process and the basic value of the target parasitic parameter under the second process is obtained.

8. The method according to claim 2, characterized in that: The step of adjusting the actual value of the target parasitic parameter comprises: Prompt information that the actual value of the target parasitic parameter deviates greatly from the inferred value is provided and / or adjustment suggestions for the actual value of the target parasitic parameter are provided.

9. The method according to claim 1, characterized in that: The parasitic parameters include capacitance, resistance or inductance.

10. A circuit parasitic parameter verification device, characterized in that: The device comprises: A first acquisition unit is used to acquire an inference value of a target parasitic parameter under a first process based on a process design toolkit PDK process library; A second acquisition unit, configured to acquire an actual value of the target parasitic parameter of the circuit under the first process based on a detailed standard parasitic parameter format DSPF file corresponding to the circuit; A verification unit is used to verify the target parasitic parameter according to the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter.

11. The device according to claim 10, characterized in that The verification unit comprises: an acquisition module, configured to acquire a deviation value according to the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, wherein the deviation value includes a difference between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, a ratio between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter, or a ratio between the difference between the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter and the inferred value of the target parasitic parameter and the actual value of the target parasitic parameter; A determination module, used to determine whether the deviation value is within a preset first allowable deviation range; The adjustment module is used for adjusting the actual value of the target parasitic parameter to adjust the deviation value if the deviation value is not within the preset first allowable deviation range, until the deviation value is within the preset first allowable deviation range.

12. The device according to claim 11, characterized in that The device also includes: A third acquisition unit is used to acquire, if the deviation value is within a preset first allowable deviation range, a second actual value of a target parasitic parameter of the circuit under the first process based on a timing library liberty file corresponding to the circuit; a fourth acquiring unit, configured to acquire a second deviation value according to the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, wherein the second deviation value includes a difference between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, a ratio between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter, or a ratio between the difference between the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter and one of the actual value of the target parasitic parameter and the second actual value of the target parasitic parameter; A second verification unit is used to determine whether the second deviation value is within a preset second allowable deviation range. If the second deviation value is not within the preset second allowable deviation range, an adjustment process is performed on the actual value and / or the second actual value of the target parasitic parameter, thereby adjusting the deviation value and / or the second deviation value until the deviation value is within the preset first allowable deviation range and the second deviation value is within the preset second allowable deviation range.

13. The device according to claim 11, characterized in that The device also includes: The simulation unit performs post-simulation processing of the circuit based on the actual value of the target parasitic parameter if the deviation value is within a preset first allowable deviation range.

14. The device according to any one of claims 10 to 13, characterized in that The first acquiring unit includes: A first acquisition module is used to acquire first target metal layer parameter information corresponding to the target parasitic parameter under the first process based on a process design toolkit PDK process library; A generation module, used for generating a test case layout and a pre-simulation netlist corresponding to the first target metal layer based on the parameter information of the first target metal layer; The second acquisition module is used to extract the basic value of the target parasitic parameter under the first process from the test case layout and the pre-simulation netlist as the inference value.

15. The device according to any one of claims 10 to 13, characterized in that The first acquiring unit includes: A third acquisition module is used to acquire a ratio between a basic value of the target parasitic parameter under the first process and a basic value of the target parasitic parameter under the second process based on a process design toolkit PDK process library; A fourth acquisition module, configured to acquire a reference value of the target parasitic parameter under the second process based on a historical DSPF file corresponding to the second process; A fifth acquisition module is used to acquire an inferred value of the target parasitic parameter under the first process based on a ratio between a base value of the target parasitic parameter under the first process and a base value of the target parasitic parameter under the second process and a reference value of the target parasitic parameter under the second process.

16. The device according to claim 15, characterized in that The third acquisition module is specifically used for: Based on the process library of the process design toolkit PDK, obtaining the first target metal layer parameter information corresponding to the target parasitic parameters under the first process, generating the test case layout and pre-simulation netlist corresponding to the first target metal layer based on the first target metal layer parameter information, and extracting the basic values ​​of the target parasitic parameters under the first process from the test case layout and pre-simulation netlist; and, based on the process library of the process design toolkit PDK, obtaining the target metal layer parameter information corresponding to the target parasitic parameters under the second process, generating the test case layout and pre-simulation netlist corresponding to the target metal layer based on the target metal layer parameter information, and extracting the basic values ​​of the target parasitic parameters under the second process from the test case layout and pre-simulation netlist corresponding to the target metal layer; Based on the basic value of the target parasitic parameter under the first process and the basic value of the target parasitic parameter under the second process, a ratio between the basic value of the target parasitic parameter under the first process and the basic value of the target parasitic parameter under the second process is obtained.

17. The device according to claim 11, characterized in that The adjustment module is specifically used for: Prompt information that the actual value of the target parasitic parameter deviates greatly from the inferred value is provided and / or adjustment suggestions for the actual value of the target parasitic parameter are provided.

18. The device according to claim 10, characterized in that The parasitic parameters include capacitance, resistance or inductance.

19. An electronic device, characterized in that: The electronic device comprises: a processor and a memory, wherein the memory is used to store executable program codes; the processor runs a program corresponding to the executable program codes by reading the executable program codes stored in the memory, so as to execute the method described in any one of the preceding claims 1-9.

20. A computer-readable storage medium storing one or more programs, wherein the one or more programs can be executed by one or more processors to implement the method of any one of claims 1 to 9.

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