Communication system of chip module to be verified on FPGA

Abstract

A communication system for a chip module to be verified on an FPGA includes a sampler, a clock signal generator, a level transmitter, a level receiver, a first restorer, a phase and voltage detector, a phase level transmitter, a phase level receiver, a loop filter, an oscillator, and a second restorer. Driven by a second clock signal, the level transmitter, the level receiver, the phase level transmitter, and the phase level receiver can send or receive more data information per unit time. Thus, only a small number of communication pins are required between FPGAs to transmit signals. Simultaneously, for a first signal, the first clock signal and level information are transmitted between FPGAs. Signal transmission adopts a method of first sampling and sending followed by receiving and restoring, thereby ensuring high-precision transmission of the first signal. For a second signal, a method of first acquiring and transmitting level and phase information, and then restoring the signal based on the level and phase information, thereby ensuring high-precision transmission of the second signal.

Description

Technical Field

[0001] The present invention belongs to the field of FPGA verification technology, and in particular relates to a communication system of a chip module to be verified on an FPGA. Background Art

[0002] Before a chip is taped out, FPGA verification is performed to ensure that its internal modules are functioning properly. FPGA verification involves programming all or part of a chip's modules into the FPGA, where the chip's logical functions are verified. A single FPGA has limited logic resources. If the chip to be verified is large, a single FPGA cannot verify the entire chip. In this case, the chip to be verified must be placed across multiple FPGAs, with each FPGA verifying different chip modules. Data is transmitted between FPGAs via communication pins. For example, if the chip to be verified has four modules, a single FPGA can accommodate up to three modules. In this case, two FPGAs are required to accommodate all four modules.

[0003] Currently, chip modules have a large number of input and output signals, and the number of communication pins of a single FPGA is limited. In many cases, the number of input and output signals of the chip module is greater than the number of communication pins of the FPGA, making it impossible to complete signal transmission between FPGAs. Summary of the Invention

[0004] Based on this, in order to solve the above technical problems, a communication system for a chip module to be verified on an FPGA is provided.

[0005] The technical solution adopted in the present invention is as follows:

[0006] A communication system for a chip module to be verified on an FPGA, characterized by comprising:

[0007] The sampler is configured to, when the chip module to be verified on the FPGA outputs a plurality of first signals driven by the first clock signal of the module, sample and send level information of each first signal to the level transmitter under the drive of the first clock signal;

[0008] a clock signal generator, configured to output a second clock signal, wherein the frequency of the second clock signal is at least five times the frequency of the first clock signal;

[0009] A level transmitter, configured to sequentially transmit the plurality of level information to a level receiver on the FPGA where the chip module to be verified is located, driven by the second clock signal;

[0010] A level receiver, configured to receive, in sequence, multiple level information sent from a level transmitter on the FPGA where the chip module to be verified is located, driven by the second clock signal, and send the multiple level information to the first restorer;

[0011] A first restorer, configured to restore the plurality of level information to the plurality of first signals under the drive of the first clock signal, and send the first signals to the receiving chip module to be verified;

[0012] a phase and voltage detector, configured to, when the transmitter chip module to be verified on the FPGA outputs a plurality of second signals that are not driven by the first clock signal of the module, obtain and send level information and phase information of each second signal to the phase level transmitter under the drive of the second clock signal;

[0013] A phase level transmitter, configured to sequentially transmit the plurality of level information and the plurality of phase information to a phase level receiver on the FPGA where the chip module to be verified is located, under the drive of the second clock signal;

[0014] a phase level receiver, configured to, under the drive of the second clock signal, sequentially receive a plurality of level information and a plurality of phase information sent from a phase level receiver on the FPGA where the chip module to be verified on the transmitter is located, and send the plurality of level information and a plurality of phase information to the loop filter;

[0015] A loop filter, configured to filter out clutter in the plurality of level information and the plurality of phase information and then send the filtered information to an oscillator;

[0016] The oscillator is used to obtain multiple second signals under the drive of the second clock signal according to multiple level information and multiple phase information after filtering out noise, and send them to the receiving chip module to be verified.

[0017] The present invention provides a communication system for a chip module to be verified on an FPGA. Since the frequency of a second clock signal is at least five times that of a first clock signal, a level transmitter, a level receiver, a phase level transmitter, and a phase level receiver can transmit or receive more data information per unit time under the drive of the second clock signal. As a result, only a small number of communication pins are required to transmit signals between FPGAs. Simultaneously, for the first signal, the first clock signal and level information are transmitted between FPGAs. Signal transmission adopts a method of first sampling and sending, then receiving and restoring, ensuring high-precision transmission of the first signal. For the second signal, since it is not driven by a clock, a method of first acquiring and transmitting level and phase information, and then restoring the signal based on the level and phase information is adopted, ensuring high-precision transmission of the second signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments:

[0019] Figure 1 A schematic diagram of a communication system for a chip module to be verified on an FPGA provided by an embodiment of the present invention;

[0020] Figure 2 A schematic diagram illustrating the sequential transmission and reception of information between a level transmitter and a level receiver according to an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of a phase level transmitter and a phase level receiver sequentially transmitting and receiving information according to an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of a first restorer recovering a signal according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will illustrate the implementation of the present invention in conjunction with the drawings in the specification. It should be noted that the implementation methods involved in this specification are not exhaustive and do not represent the only implementation methods of the present invention. The following corresponding embodiments are only for the purpose of clearly illustrating the invention content of the patent of this invention and are not intended to limit its implementation methods. For ordinary technicians in this field, different forms of changes and modifications can be made based on the description of this embodiment. Any obvious changes or modifications that belong to the technical concept and invention content of the present invention are also within the scope of protection of the present invention.

[0024] like Figure 1 As shown, an embodiment of the present application provides a communication system for a chip module to be verified on an FPGA. The communication system is set on the FPGA, and includes a sampler 110, a clock signal generator 120, a level transmitter 130, a level receiver 140, a first restorer 150, a phase detector and voltage detector 160, a phase level transmitter 170, a phase level receiver 180, a loop filter 190, an oscillator 197, a second restorer 198 and a delay control module 199.

[0025] The working principle of the communication system of the embodiment of the present application is explained below using the first FPGA21 and the second FPGA22 as examples, wherein the first FPGA21 has a chip module to be verified (hereinafter referred to as the sender module 3) as a signal sender, and the second FPGA22 has a chip module to be verified (hereinafter referred to as the receiver module 4) as a signal receiver, and both the first FPGA21 and the second FPGA22 have the above-mentioned communication system.

[0026] When the transmitter module 3 simultaneously transmits five first signals and three second signals to the receiver module 4, the sampler 110, clock signal generator 120, and level transmitter 130 on the first FPGA 21, as well as the phase and voltage detector 160 and phase level transmitter 170, operate. The level receiver 140 and first restorer 150, as well as the phase level receiver 180, loop filter 190, oscillator 197, second restorer 198, and delay control module 199 on the second FPGA 22 operate. The first signal refers to a signal driven by the first clock signal of the transmitter module 3. The change in its signal value is related to the edge of the first clock signal. The signal value changes at the rising or falling edge of the clock. This embodiment uses the signal that changes at the rising edge of the clock as an example. The second signal refers to a signal not driven by the first clock signal of the transmitter module 3. The change in its signal value is not related to the edge of the first clock signal. The signal value may change at any time when the clock is rising, falling, high, or low. The specific process of signal transmission and reception is as follows:

[0027] 1. Driven by the first clock signal, the sampler 110 samples five levels (0 or 1) of the first signal and sends the five levels to the level transmitter 130. Simultaneously, the clock signal generator 120 outputs a second clock signal having a frequency at least five times that of the first clock signal. In this embodiment, the frequency of the second clock signal is 15 times that of the first clock signal. For example, if the frequency of the first clock signal is 100 MHz, the frequency of the second clock signal is 1.5 GHz.

[0028] 2. Driven by the second clock signal, the level transmitter 130 sends five level information to the level receiver 140 in sequence.

[0029] 3. Driven by the second clock signal, the level receiver 140 receives five level information in sequence and sends them to the first restorer 150 .

[0030] It can be seen that only one communication pin is needed between the first FPGA 21 and the second FPGA 22 to transmit and receive the first signal.

[0031] In this embodiment, the level transmitter 130 sends a level information to the level receiver 140 in each clock cycle after the first clock cycle of the second clock signal. The level receiver 140 receives a level information in each clock cycle of the second clock signal. The clock cycle for receiving the level information is the next clock cycle for sending the level information. The specific process is as follows:

[0032] like Figure 2As shown, in the first FPGA 21, the sampler 110 completes the sampling of the five first signals in the first clock cycle of the second clock signal, the level transmitter 130 sends five level information in the 2nd to 6th clock cycles of the second clock signal respectively, and in the second FPGA 22, the level receiver 140 receives five level information in the 3rd to 7th clock cycles of the second clock signal respectively.

[0033] from Figure 2 As can be seen, after the level receiver 140 of the second FPGA 22 receives all the signals, there are still 15-2-5 = 8 clock cycles. Therefore, it is possible to send and receive more signals in groups, for example, sending and receiving seven signals in groups, which leaves 15-2-7 = 6 clock cycles. The frequency of the second clock signal can also be changed. For example, if the second clock signal is 1 GHz, which is 10 times the frequency of the first clock signal, there are still 10-2-5 = 3 clock cycles after receiving five signals.

[0034] 4. When receiving the five level information, the first restorer 150 outputs the first delay time Tm to the delay control module 199 and restores the five level information into five first signals under the drive of the first clock signal.

[0035] The first delay time Tm is related to two aspects: one is the delay TI of the entire link, which is a fixed value of the device; the other is the clock period T2 of the first clock signal, so the first delay time Tm=T1+T2.

[0036] like Figure 4 As shown, the first restorer 150 has multiple registers inside, the input value of the register is the received level information, and when the rising edge of the first clock signal arrives, the register outputs the first signal.

[0037] 5. Driven by the second clock signal, the phase and voltage detector 160 obtains level information and phase information of the three second signals, and sends the three level information and three phase information to the phase level transmitter 170 .

[0038] Since the change in the signal value of the second signal is independent of the clock, such a signal cannot be simply transmitted by a clock sampling and recovery method, but needs to be transmitted by a phase level transmission method.

[0039] During each clock cycle of the second clock signal, phase detector 160 determines the levels of the three second signals and generates three levels of information. If the levels of the three second signals change between two consecutive clock cycles, it indicates that a level jump has occurred in the three second signals. In this case, phase detector 160 records the phase difference between the level jump location and the rising or falling edge of the second clock signal, generating three phase information. If there is no level jump, indicating that the signal has not changed, no phase information is transmitted. In this case, no phase information is transmitted; level and phase information are only transmitted when a level jump occurs.

[0040] 6. Driven by the second clock signal, the phase level transmitter 170 sends three level information and three phase information to the phase level receiver 180 in sequence.

[0041] 7. Driven by the second clock signal, the phase level receiver 180 sequentially receives three level information and three phase information, and sends them to the loop filter 190 .

[0042] It can be seen that only one communication pin is needed between the first FPGA 21 and the second FPGA 22 to transmit and receive the second signal.

[0043] In this embodiment, the phase level transmitter 170 sends a piece of information to the level receiver 180 in each clock cycle after the first clock cycle of the second clock signal in the order of first sending multiple level information and then sending multiple phase information. The level receiver 180 receives a piece of information in each clock cycle of the second clock signal. The clock cycle for receiving the information is the next clock cycle for sending the information. The specific process is as follows:

[0044] like Figure 3 As shown, in the first FPGA 21, the phase detector and voltage detector 160 obtains 3 level information and 3 phase information in the 1st clock cycle of the second clock signal, the phase level transmitter 170 sends 3 level information and 3 phase information in the 2nd to 7th clock cycles of the second clock signal respectively, and in the second FPGA 22, the phase level receiver 180 receives 3 level information and 3 phase information in the 3rd to 8th clock cycles of the second clock signal respectively.

[0045] It should be noted that the three level information and three phase information at this time contain noise. The noise comes from two sources: one is the noise generated by the phase and voltage detector 160, and the other is the noise introduced during the transmission process.

[0046] 8. The loop filter 190 filters out the noise in the three level information and the three phase information and sends them to the oscillator 197.

[0047] 9. Driven by the second clock signal, the oscillator 197 obtains three second signals (an oscillator is a physical device that can generate output signals based on input information) based on the three level information and three phase information after filtering out the noise, and sends them to the second restorer 198. At the same time, the second delay time Tc is output to the delay control module 199.

[0048] Oscillator 197 determines the high and low levels of the three second signals based on the three level information and the phases of the three second signals based on the three phase information. Based on the magnitude of the three level information, oscillator 197 determines whether the signal to be transmitted has experienced a level jump. If the magnitudes of the three level information are the same within two adjacent clock cycles of the second clock signal, it indicates that the signal to be transmitted has not experienced a level jump, and the three second signals remain unchanged. If the magnitudes of the three level information are different within two adjacent clock cycles of the second clock signal, it indicates that a level jump has occurred. In this case, oscillator 197 generates the three second signals with corresponding changes based on the three phase information.

[0049] The second delay time Tc is related to two aspects: one is the delay T3 of the entire link, which is a fixed value of the device; the other is the clock period T4 of the second clock signal. Therefore, the second delay time Tc = T3 + T4 * (2 + the number of second signals * 2). In this embodiment, the number of second signals is 3, Tc = T3 + T4 * 8.

[0050] 10. Under the delay control of the delay control module 199 , the second restorer 198 sends the three second signals to the receiver module 4 , so that the three second signals and the five first signals sent by the first restorer 150 arrive at the receiver module 4 at the same time.

[0051] The delay time Tde l ay used by the delay control module 199 to control the delay of the second restorer 198 is the difference between the first delay time and the second delay time: Tm−Tc.

[0052] In the above process, driven by the second clock signal, the level transmitter 130, the level receiver 140, the phase level transmitter 170 and the phase level receiver 180 can send or receive more data information per unit time. Therefore, only two communication pins are needed between the first FPGA 21 and the second FPGA 22 to transmit the first signal and the second signal.

[0053] It is understandable that, in a scenario where the first signal or the second signal is sent separately, the delay control module 199 and the second restorer 198 can be omitted, and the oscillator 197 directly sends the three second signals to the receiving module 4 .

[0054] As can be seen from the above, an embodiment of the present application provides a communication system for a chip module to be verified on an FPGA. Under the drive of a second clock signal, the level transmitter, level receiver, phase level transmitter and phase level receiver can send or receive more data information per unit time. Therefore, only a small number of communication pins are needed between FPGAs to transmit signals. At the same time, for the first signal, the first clock signal and level information are transmitted between FPGAs. The signal transmission adopts a method of first sampling and sending and then receiving and restoring, so that the phase and numerical relationship between the first signal and the first clock signal in the two FPGAs are consistent, ensuring high-precision transmission of the first signal. For the second signal, since it is not driven by a clock, the level and phase information are first acquired and transmitted, and then the signal is restored based on the level and phase information, thereby ensuring high-precision transmission of the second signal.

[0055] In addition, in a scenario where the first signal and the second signal are transmitted simultaneously, the delay control module enables the first signal and the second signal to arrive at the receiving module at the same time, thereby ensuring the relative temporal relationship between the two.

[0056] Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include these modifications and variations.

Claims

1. A communication system for a chip module to be verified on an FPGA, characterized in that: include: The sampler is configured to, when the chip module to be verified on the FPGA outputs a plurality of first signals driven by the first clock signal of the module, sample and send level information of each first signal to the level transmitter under the drive of the first clock signal; a clock signal generator, configured to output a second clock signal, wherein the frequency of the second clock signal is at least five times the frequency of the first clock signal; A level transmitter, configured to sequentially transmit a plurality of level information to a level receiver on the FPGA where the chip module to be verified is located, driven by the second clock signal; A level receiver, configured to receive, in sequence, multiple level information sent from a level transmitter on the FPGA where the chip module to be verified is located, driven by the second clock signal, and send the multiple level information to the first restorer; A first restorer, configured to restore the plurality of level information to the plurality of first signals under the drive of the first clock signal, and send the first signals to the receiving chip module to be verified; a phase and voltage detector, configured to, when the transmitter chip module to be verified on the FPGA outputs a plurality of second signals that are not driven by the first clock signal of the module, obtain and send level information and phase information of each second signal to the phase level transmitter under the drive of the second clock signal; A phase level transmitter, configured to sequentially transmit the plurality of level information and the plurality of phase information to a phase level receiver on the FPGA where the chip module to be verified is located, under the drive of the second clock signal; a phase level receiver, configured to, under the drive of the second clock signal, sequentially receive a plurality of level information and a plurality of phase information sent from a phase level receiver on the FPGA where the chip module to be verified on the transmitter is located, and send the plurality of level information and a plurality of phase information to the loop filter; A loop filter, configured to filter out clutter in the plurality of level information and the plurality of phase information and then send the filtered information to an oscillator; The oscillator is used to obtain multiple second signals under the drive of the second clock signal according to multiple level information and multiple phase information after filtering out noise, and send them to the receiving chip module to be verified.

2. The method for transmitting and receiving signals between FPGA chip modules to be verified according to claim 1, wherein: The frequency of the second clock signal is 15 times the frequency of the first clock signal.

3. The signal receiving and sending method of a chip module to be verified between FPGAs according to claim 1, characterized in that: The step of sequentially sending the plurality of level information to a level receiver on the FPGA where the chip module to be verified is located on the receiving side under the driving of the second clock signal further includes: In each clock cycle after the first clock cycle of the second clock signal, a level information is sent to a level receiver on the FPGA where the chip module to be verified is located on the receiving side.

4. The method for transmitting and receiving signals between FPGA chip modules to be verified according to claim 3, wherein: The method of sequentially receiving, under the drive of the second clock signal, a plurality of level information sent from a level transmitter on the FPGA where the chip module to be verified is located on the transmitter side further includes: A level information is received in each clock cycle of the second clock signal, wherein the clock cycle for receiving the level information is the next clock cycle for sending the level information.

5. The method for transmitting and receiving signals between chip modules to be verified between FPGAs according to claim 4, characterized in that: The method further includes: sending the plurality of level information and the plurality of phase information in sequence to a phase level receiver on the FPGA where the chip module to be verified is located on the receiving side under the driving of the second clock signal; In the order of sending multiple level information first and then sending multiple phase information, one information is sent to the level receiver on the FPGA where the receiving chip module to be verified is located in each clock cycle after the first clock cycle of the second clock signal.

6. The method for transmitting and receiving signals between chip modules to be verified between FPGAs according to claim 5, characterized in that: The sequentially receiving a plurality of level information and a plurality of phase information sent from a phase level receiver on the FPGA where the chip module to be verified is located on the transmitter further includes: A piece of information is received in each clock cycle of the second clock signal, wherein the clock cycle for receiving the information is the next clock cycle for sending the information.

7. The method for transmitting and receiving signals between chip modules to be verified between FPGAs according to claim 6, characterized in that: The system further includes a delay control module and a second restorer. When the multiple first signals and the multiple second signals are simultaneously output by the chip module to be verified on the sending side, the first restorer outputs a first delay time to the delay control module upon receiving multiple level information. The oscillator sends the multiple second signals to the second restorer and simultaneously outputs a second delay time to the delay control module. Under the delay control of the delay control module, the second restorer sends the multiple second signals to the chip module to be verified on the receiving side, so that the multiple second signals and the multiple first signals sent by the first restorer arrive at the chip module to be verified on the receiving side at the same time. Among them, the first delay time Tm = link delay TI + clock period T2 of the first clock signal, the second delay time Tc = link delay T3 + clock period T4 of the second clock signal * (2 + number of second signals * 2), and the delay time of the delay control module to delay the second restorer = Tm-Tc.

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