Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. A first pixel circuit and a first shift register circuit in the display panel are at least partially overlapped in a first direction. The first type of signal lines are electrically connected with the pixel circuit, and the second type of signal lines are electrically connected with the shift register circuit. The first type of signal lines and the second type of signal lines are located on the two opposite sides of the first pixel circuit in the second direction, and the first type of signal lines and the second type of signal lines are located on the two opposite sides of the first shift register circuit. According to the embodiment of the invention, the first pixel circuit and / or the first shift register circuit are / is arranged between the first type signal line electrically connected with the first pixel circuit and the second type signal line electrically connected with the first shift register circuit in the second direction; the coupling degree between the first type of signal lines and the second type of signal lines and the risk of wiring interference are reduced, and the stability of the signal lines during signal transmission is improved, so that the uniformity and stability of the display panel during display are improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The display panel includes multiple signal lines that provide pulse signals for the pixel circuit. There is a risk of mutual interference between two signal lines that transmit different types of pulse signals, such as overlapping and close to each other. The above situation easily leads to a decrease in the accuracy of signal line transmission provided to the pixel circuit, which is not conducive to improving the display effect of the display panel. Summary of the invention

[0003] In view of this, the present application provides a display panel and a display device to solve the above problems.

[0004] In a first aspect, an embodiment of the present application provides a display panel, including a pixel circuit and a shift register group, the shift register group includes a plurality of shift register circuits, and the pixel circuit and the shift register circuit are arranged along a first direction;

[0005] The pixel circuit includes a first pixel circuit, the shift register group includes a first shift register circuit, and the first pixel circuit and the first shift register circuit at least partially overlap in a first direction;

[0006] A first type of signal line, the first type of signal line is electrically connected to the pixel circuit, and the first type of signal line provides the pixel circuit with a first type of signal;

[0007] A second type of signal line, the second type of signal line is electrically connected to the shift register circuit, and the second type of signal line transmits a pulse signal in at least a part of the time period;

[0008] Along the second direction, the first type of signal line and the second type of signal line are located on two opposite sides of the first pixel circuit;

[0009] Along the second direction, the first type of signal line and the second type of signal line are located at two opposite sides of the first shift register circuit;

[0010] The first direction intersects the second direction.

[0011] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0012] In an embodiment of the present application, it is proposed that along the second direction, the first type of signal line and the second type of signal line are arranged on opposite sides of the first pixel circuit. And along the second direction, the first type of signal line and the second type of signal line are arranged on opposite sides of the first shift register circuit, and the first direction intersects with the second direction. So that in the second direction, the first type of signal line electrically connected to the first pixel circuit and the second type of signal line electrically connected to the first shift register circuit include the first pixel circuit and / or the first shift register circuit, which increases the spacing between the first type of signal line and the second type of signal line, reduces the coupling degree between the first type of signal line and the second type of signal line and the risk of routing interference, is conducive to improving the stability of the first type of signal line and the second type of signal line when transmitting signals, improves the accuracy of the signals received by the pixel circuit and the shift register circuit, is conducive to ensuring that the pixel circuit generates an accurate light-emitting drive current, is conducive to ensuring the working stability of the shift register circuit, and thus improves the uniformity and stability of the display panel when displaying. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0014] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application;

[0015] Figure 2 A schematic plan view of another display panel proposed in an embodiment of the present application;

[0016] Figure 3 A method provided in the embodiment of the present application Figure 1 A partial schematic diagram of the middle area E1;

[0017] Figure 4 A schematic plan view of another display panel provided in an embodiment of the present application;

[0018] Figure 5 A method provided in the embodiment of the present application Figure 4 Schematic diagram of the cross section along the A-A' direction;

[0019] Figure 6 A schematic plan view of another display panel provided in an embodiment of the present application;

[0020] Figure 7 A schematic plan view of another display panel provided in an embodiment of the present application;

[0021] Figure 8A method provided in the embodiment of the present application Figure 7 A partial schematic diagram of the middle area E2;

[0022] Fig. 9 A schematic plan view of another display panel provided in an embodiment of the present application;

[0023] Fig.10 A schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0024] Fig.11 A method provided in the embodiment of the present application Fig. 9 A partial schematic diagram of the middle region E3;

[0025] Fig.12 A schematic plan view of another display panel provided in an embodiment of the present application;

[0026] Fig.13 A schematic plan view of another display panel provided in an embodiment of the present application;

[0027] Fig.14 A method provided in the embodiment of the present application Fig.13 Schematic diagram of the cross section along the B-B' direction;

[0028] Fig.15 A schematic plan view of another display panel provided in an embodiment of the present application;

[0029] Fig.16 A schematic diagram of a layout of a multi-way selection circuit provided in an embodiment of the present application;

[0030] Fig.17 A method provided in the embodiment of the present application Fig.15 Partial schematic diagram of the middle area E4

[0031] Fig.18 A schematic plan view of another display panel provided in an embodiment of the present application;

[0032] Fig.19 A schematic plan view of another display panel provided in an embodiment of the present application;

[0033] Fig. 20 A schematic plan view of another display panel provided in an embodiment of the present application;

[0034] Fig.21 A method provided in the embodiment of the present application Fig. 20 A partial schematic diagram of the middle area E5;

[0035] Fig. 22 A schematic plan view of another display panel provided in an embodiment of the present application;

[0036] Fig.23 A schematic diagram of another display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0038] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0039] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0040] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0041] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0042] It should be understood that although the terms first, second, etc. may be used to describe directions, shift register circuits, pixel circuits, etc. in the embodiments of the present application, these should not be limited to these terms. These terms are only used to distinguish directions, shift register circuits, pixel circuits, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first direction may also be referred to as the second direction, and similarly, the second direction may also be referred to as the first direction. The applicant of this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0043] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application.

[0044] The present application embodiment provides a display panel 100, such as Figure 1As shown, the display panel 100 includes a pixel circuit 10 and a shift register group 20A, the shift register group 20A includes a plurality of shift register circuits 20, and the pixel circuit 10 and the shift register circuit 20 are arranged along a first direction X1. Optionally, a plurality of shift register circuits 20 in the same shift register group 20A are cascaded in the first direction X1, and at least part of the shift register circuits 20 are electrically connected to the pixel circuit 10 and control the pixel circuit 10 electrically connected thereto to enter various working stages. It should be noted that the pixel circuit 10 is usually located in the display area of ​​the display panel 100, and in the embodiment of the present application, at least part of the shift register circuit is also located in the display area of ​​the display panel 100, which is conducive to realizing a narrow frame or a frameless design of the display panel 100.

[0045] The pixel circuit 10 includes a first pixel circuit 101, and the shift register group 20A includes a first shift register circuit 201. The first pixel circuit 101 and the first shift register circuit 201 overlap at least partially in the first direction X1. In the display panel 100, the pixel circuit 10 and the shift register circuit 201 that overlap in the first direction X1 are the first pixel circuit 101 and the first shift register circuit 201, respectively. The shift register group 20A is located in the interval between adjacent pixel circuits 10. In the embodiment of the present application, at least part of the first pixel circuit 101 and the first shift register circuit 201 are alternately arranged in the first direction X1 as an example for explanation, which is beneficial to make the distribution of the first pixel circuit 101 and the first shift register circuit 201 more uniform, avoid the situation of inconsistent routing impedance, improve the stability of each signal transmission in the display panel 100, and improve the display effect.

[0046] The display panel 100 also includes a first type of signal line SL1, which is electrically connected to the pixel circuit 10, and provides the pixel circuit 10 with a first type of signal. Optionally, the first type of signal line SL1 is used to transmit a data signal to the pixel circuit 10. In a working cycle of the pixel circuit 100, different working stages are included, and the pixel circuit 10 can enter different working stages after receiving different valid scanning signals. For example, when the pixel circuit 10 receives a valid scanning signal and enters the data writing stage, the pixel circuit 10 can receive the data signal transmitted by the first signal line SL1. Different data signals cause the pixel circuit to generate different light-emitting drive currents or different data signals can cause the corresponding light-emitting elements to have different light-emitting durations. It can be seen from the above that the first type of signal line SL1 is not electrically connected to a fixed potential and always transmits the same signal, but can transmit signals of different amplitudes at different time periods.

[0047] The display panel 100 further includes a second type of signal line SL2, which is electrically connected to the shift register circuit 20, and the second type of signal line SL2 transmits a pulse signal in at least a portion of the time period. Optionally, the second type of signal line SL2 is used to transmit one of a pulse clock signal, an output signal of the shift register circuit 20, and an input signal of the shift register circuit 20.

[0048] Optionally, in the embodiment of the present application, the second-type signal line SL2 is used as an example of a cascade line for cascading adjacent-stage shift register circuits 20, and the second-type signal line SL2 can be used to transmit the output end and input end of the shift register circuit 20 of two adjacent stages. At this time, the second-type signal line SL2 can be used to transmit the output signal of the previous-stage shift register circuit 20, such as a scanning signal, a light-emitting control signal and other drive signals, to the input end of the next-stage shift register circuit, and multiplex these signals as a trigger signal for the next-stage shift register circuit. Therefore, when receiving the drive signal output from the output end of the shift register circuit 20, the pixel circuit 10 can also be directly electrically connected to the second-type signal line SL2, such as Figure 1 As shown, the driving signal receiving terminals 10D in the plurality of pixel circuits 20 arranged along the second direction X2 are electrically connected to the second type signal lines SL2 through the driving signal lines DL1 .

[0049] It should be noted that if Figure 1 The omitted mark portion shown indicates that the display panel 100 also includes a plurality of circuits and electrical connection structures with similar structures, which are indicated by omitted marks.

[0050] In summary, the first type of signal line SL1 can transmit signals of different amplitudes at different time periods, while the second type of signal line SL2 can transmit pulse signals of non-fixed potential at different time periods. Both the first type of signal line SL1 and the second type of signal line SL2 can transmit signals of different amplitudes at different time periods, which can easily lead to greater coupling between the first type of signal line SL1 and the second type of signal line SL2 when transmitting signals, making the first type of signal line SL1 and the second type of signal line SL2 have poor anti-interference capabilities. Moreover, when the second type of signal line SL2 and the first type of signal line SL1 transmit different signals at the same time, if there is a routing conflict between the first type of signal line SL1 and the second type of signal line SL2, the coupling between the two is also more serious, which is not conducive to improving the stability of the first type of signal line SL1 and the second type of signal line SL2 when transmitting signals.

[0051] In the embodiment of the present application, it is proposed that along the second direction X2, the first type signal line SL1 and the second type signal line SL2 are arranged at opposite sides of the first pixel circuit 101. And along the second direction X2, the first type signal line SL1 and the second type signal line SL2 are arranged at opposite sides of the first shift register circuit 201, and the first direction X1 intersects with the second direction X2. In the second direction X2, the first type of signal line SL1 electrically connected to the first pixel circuit 101 and the second type of signal line SL2 electrically connected to the first shift register circuit 201 include the first pixel circuit 101 and / or the first shift register circuit 201, thereby increasing the spacing between the first type of signal line SL1 and the second type of signal line SL2, reducing the degree of coupling between the first type of signal line SL1 and the second type of signal line SL2 and the risk of routing interference, which is beneficial to improving the stability of the first type of signal line SL1 and the second type of signal line SL2 when transmitting signals, improving the accuracy of the signals received by the pixel circuit 10 and the shift register circuit 20, ensuring that the pixel circuit 10 generates an accurate light-emitting drive current, and ensuring the working stability of the shift register circuit 20, thereby improving the uniformity and stability of the display panel 100 during display.

[0052] Figure 2 This is a schematic plan view of another display panel proposed in an embodiment of the present application.

[0053] In one embodiment of the present application, Figure 2 As shown, the pixel circuit 10 includes a pulse width modulation module 10A, and the pulse width modulation module 10A is used to control the light-emitting duration of the light-emitting element 200 corresponding to the pixel circuit 10. In the pixel circuit 10, the pulse width modulation module 10A is provided to facilitate better brightness control of the light-emitting element 200, and the light-emitting duration of the light-emitting element 200 is adjusted by changing the width of the pulse. Generally, a longer pulse width corresponds to a longer light-emitting duration, so that the light-emitting element 200 produces a higher light-emitting brightness. The pulse width modulation module 10A can achieve more precise brightness control and can be applied to display applications requiring high resolution and high frequency. In addition, the inclusion of the pulse width modulation module 10A in the pixel circuit 10 is also conducive to optimizing energy use by accurately controlling the pulse width, reducing unnecessary power consumption, and improving the energy efficiency of the display panel 100.

[0054] Among them, the first type of signal line SL1 includes a first data signal line SL1A, and the first data signal line SL1A is electrically connected to the pulse width modulation module 10A to provide a data signal PWM-data for the pulse width modulation module 10A. In different time periods, there are situations where the pulse width of the data signal PWM-data provided by the first data signal line SL1A is different, and because the pulse width modulation signal transmitted by the first data signal line SL1A is usually a high-frequency signal and is used to adjust the duration of the light-emitting driving current generated by the pixel circuit 10, the accuracy of its transmission signal is required to be high.

[0055] In an embodiment of the present application, in the second direction X2, the first data signal line SL1A and the second signal line SL2 in the first type of signal line SL1 are respectively located on opposite sides of the first pixel circuit 101, and in the second direction X2, the first data signal line SL1A and the second type of signal line SL2 are respectively located on opposite sides of the first shift register circuit 201, which is beneficial to reducing the degree of coupling between the first data signal line SL1A and the second type of signal line SL2, and reducing the risk of routing interference between the first data signal line SL1A and the second type of signal line SL2, which is beneficial to improving the anti-interference ability of the first data signal line SL1A, and thereby improving the stability of the data signal PWM-data transmitted by the first data signal line SL1A, thereby ensuring the accuracy of the duration of the light-emitting drive current generated by the pixel circuit 10.

[0056] Figure 3 A method provided in the embodiment of the present application Figure 1 Schematic diagram of a part of the middle area E1.

[0057] In one embodiment of the present application, Figure 1 , Figure 3 As shown, the first type signal line SL1 is provided to include at least a first portion SL11 extending along the first direction X1 and a second portion SL12 extending along the second direction X2. Since the first portion SL11 of the first type signal line SL1 extends along the first direction X1, and the pixel circuit 10 and the shift register circuit 20 are arranged along the first direction X1, the first portion SL11 of the first type signal line SL1 is adjacent to the pixel circuit 10 and the shift register circuit 20 in the second direction X2. At this time, the electrical connection between the first type signal line SL1 and the first pixel circuit 101 can be completed through the second portion SL12 extending along the second direction X2. Optionally, the first portion SL11 and the second portion SL12 are provided to be located in different film layers, and the first portion SL11 and the second portion SL12 are electrically connected by punching, which is conducive to avoiding the second portion SL12 extending along the second direction X2 from crossing the routing extending along the first direction X1 that is not electrically connected to it, thereby ensuring the accuracy of the signal transmitted by the first type signal line SL2.

[0058] In the embodiment of the present application, the second type of signal line SL2 is arranged to extend along the first direction X1 and the second type of signal line SL2 is arranged in the same layer as the first part SL11, which is conducive to making the second type of signal line SL2 at least partially parallel to the first type of signal line SL1 in the second direction X2, and is conducive to reducing the risk of crossing between the first type of signal line SL1 and the second type of signal line SL2. In addition, the second type of signal line SL2 is arranged in the same layer as the first part SL11, which is conducive to improving the layout regularity of the second type of signal line SL2 and the first type of signal line SL1 in the display panel 100, and avoiding the second type of signal line SL2 from crossing with the second part SL12 extending along the second direction X2, and reserving wiring space for the film layer where the second part SL12 is located.

[0059] Figure 4 A schematic plan view of another display panel provided in an embodiment of the present application is shown in FIG. Figure 5 A method provided in the embodiment of the present application Figure 4 Schematic diagram of the cross section along the A-A' direction.

[0060] In one embodiment of the present application, Figure 4 As shown, the display panel 100 further includes a third type of signal line SL3, the third type of signal line SL3 is electrically connected to the pixel circuit 10, and the third type of signal line SL3 includes a third portion SL31 extending along the first direction X1, Figure 5As shown, the third part SL31 is arranged in the same layer as the second type signal line SL2. Optionally, the third type signal line SL3 also includes a fourth part SL32 extending along the second direction X2, and the fourth part SL32 electrically connects the pixel circuit 10 and the third part SL31. The third part SL31 and the fourth part SL32 can be arranged in different film layers, and the third part SL31 and the fourth part SL32 are electrically connected by punching. Optionally, the fourth part SL32 is in the same layer as the second part SL12 of the first type signal line SL1, and the third part SL31 is in the same layer as the first part SL11 of the first type signal line SL1 and the second type signal line SL2. The structural film layer of the display panel 100 includes a substrate GLASS, and also includes a first metal layer M1 located on one side of the substrate GLASS. Optionally, the first metal layer M1 includes the gate of the transistor in the pixel circuit 10, the second part SL12 of the first type signal line SL1, and the fourth part SL32 of the third type signal line SL3. The structural film layer of the display panel 100 also includes a second metal layer M2, a first flat layer PLN1, and a second flat layer PLN2 located on the side of the first metal layer M1 away from the substrate G l ass. Optionally, the second metal layer M2 includes a first portion SL11 of the first type signal line SL1 and a third portion SL31 of the second type signal line SL2 and the third type signal line SL3. The display panel 100 also includes a third metal layer M3, and optionally, the third metal layer M3 includes a switching electrode. The display panel 100 also includes a fourth metal layer M4 located on the side of the second flat layer PLN2 away from the substrate G l ass, and optionally, the fourth metal layer M4 includes two electrodes of the light emitting element 200. Optionally, the light emitting element 200 includes a first pole 2001 and a second pole 2002, and the first pole 2001 of the light emitting element 200 is electrically connected to the pixel circuit 10 for receiving the light emitting driving current transmitted by the pixel circuit 10.

[0061] The second type signal line SL2 and the third part SL31 are arranged on the same side of the pixel circuit 10, and along the second direction X2, the distance from the second type signal line SL2 to the first pixel circuit 101 is smaller than the distance from the third part SL31 to the first pixel circuit 101. Optionally, the third type signal line SL3 is used to transmit one of the pulse amplitude modulation data signal PAM-data and the reset signal received by the pulse amplitude modulation module 10B in the pixel circuit 10. The signal transmitted by the third type signal line SL3 is relatively stable and has strong anti-interference ability. Figure 4 As shown, in the embodiment of the present application, the third type signal line SL3 is electrically connected to the pulse amplitude modulation module 10B in the pixel circuit 10 to provide the pulse amplitude modulation data signal PAM-data to the pulse amplitude modulation module 10B in the pixel circuit 10 as an example for explanation.

[0062] In the embodiment of the present application, the third part SL31 of the third type signal line SL3 is arranged on the same side of the pixel circuit 10 as the second type signal line SL2, which is conducive to adapting to the scheme in which the second type signal line SL2 and the first type signal line SL1 are located on opposite sides of the first pixel circuit 101 in the second direction X2, and is conducive to avoiding the situation in which the first type signal line SL1 and the second type signal line SL2 electrically connected to the same first pixel circuit 101 are located on the same side of the first pixel circuit 101, thereby facilitating the first type signal line SL1, the second type signal line SL2 and the first pixel circuit 101 to be close in distance in the second direction X2, thereby ensuring the synchronization of the data signal PWM-data and the pulse amplitude modulation data signal PAM-data when acting on the first pixel circuit 101.

[0063] Furthermore, the distance between the second type signal line SL2 and the first pixel circuit 101 is set to be smaller than the distance between the third part SL31 of the third type signal line SL3. Since the first pixel circuit 101 and the first shift register circuit 201 at least partially overlap in the first direction X1, it is beneficial to make the distance between the second type signal line SL2 and the first shift register 201 smaller, thereby improving the compactness of the signal line design. It is also beneficial to reduce the extension length of the second type signal line SL2 between two adjacent shift register circuits 10 in the first direction X2, thereby reducing the path length of the second type signal line SL2 transmitting the signal and reducing the delay of the second type signal line SL2 when transmitting the signal.

[0064] In one embodiment of the present application, continue to refer to Figure 1 As shown, the second type of signal line SL2 is electrically connected to two shift register circuits 20 arranged along the first direction X1, and the two shift register circuits 20 are located on opposite sides of the same pixel circuit 10 in the first direction X1, then in the first direction X1, the pixel circuit 10 and the shift register circuit 20 are arranged alternately. In addition, since the second type of signal line SL2 is electrically connected to the two shift register circuits 20 arranged along the first direction X1, among the second type of signal lines SL2 electrically connected to the shift register circuits 20, the signal line SL2 for transmitting the cascade signal can be electrically connected to the output end OUT of one of the shift register circuits 20 and the input end IN of another shift register circuit 20, so as to control the multiple shift register circuits 20 in the shift register group 20A to be turned on step by step. Then, in the embodiment of the present application, the second type of signal line SL2 is taken as an example for describing the routing line for transmitting the cascade signal.

[0065] Since the plurality of shift register circuits 20 are arranged along the first direction X1 , the second-type signal lines SL2 also extend along the first direction X1 , and the first-type signal lines SL1 may also be data signal lines SL1A extending along the first direction X1 .

[0066] In the embodiment of the present application, two shift register circuits 20 are arranged on opposite sides of the same pixel circuit 10 in the first direction X1, which is conducive to realizing the alternating arrangement of the pixel circuit 10 and the shift register circuit 20 in the first direction X1, improving the distribution uniformity of the shift register circuit 20 when it is prepared in the display area of ​​the display panel 100, so that the shift register circuit 20 is closer to a row of pixel circuits 10 electrically connected to it, and reducing the winding distance when the shift register circuit 20 is electrically connected to a row of pixel circuits 10. In addition, the second type of signal line SL2 and the first type of signal line SL1 that can transmit cascade signals are arranged on opposite sides of the pixel circuit 10 and the shift register circuit 20 in the second direction X2, respectively, which is conducive to avoiding mutual interference between the transmitted data signal PWM-data and the cascade signal, and improving the working stability of the display panel 100.

[0067] Figure 6 A schematic plan view of another display panel provided in an embodiment of the present application is shown in FIG. Figure 7 A schematic plan view of another display panel provided in an embodiment of the present application is shown in FIG. Figure 8 A method provided in the embodiment of the present application Figure 7 Partial schematic diagram of the middle area E2.

[0068] In one embodiment of the present application, Figure 6As shown, the shift register group 20A includes a first shift register group 20A1 and a second shift register group 20A2, and the first shift register group 20A1 and the second shift register group 20A2 provide the same signal to the pixel circuit 10. In the display panel 100, the second direction X2 is used as the row direction, and the plurality of pixel circuits 10 are arranged along the second direction X2, and the shift register circuit 20 can output a driving signal to the plurality of pixel circuits 10 located in the same row. However, in the related art, when a shift register circuit 20 transmits a driving signal to the pixel circuits 10 in the same row, there is a risk that the signal transmission distance is long, and thus the driving signal received by the pixel circuit 10 is distorted. Then, the first shift register group 20A1 and the second shift register group 20A2 are set to generate driving signals provided to the pixel circuits 10, and the first shift register group 20A1 and the second shift register group 20A2 provide the same signal to the pixel circuits 10 in the same row, which is conducive to making some pixel circuits 10 in the same row receive the driving signal provided by the shift register circuits 20 in the first shift register group 20A1, and the other part of the pixel circuits 10 can receive the same driving signal provided by the second shift register group 20A2; thereby, it is conducive to reducing the delay and distortion of the driving signal when transmitting to the pixel circuits 10 in the same row, improving the accuracy of the driving signal received by the pixel circuit 10, and further improving the accuracy of the light-emitting driving current generated by the pixel circuit 10. Optionally, the arrangement of multiple shift register circuits 20 in the first shift register group 20A1 and the second shift register group 20A2 is the same.

[0069] Combination Figure 7 , Figure 8 As shown, the shift register circuit 20 included in the first shift register group 20A1 and the shift register circuit 20 included in the second shift register group 20A2 are symmetrical in circuit structure. The shift register 20 includes a control module 20C1 and a signal output module 20C22. The control module 20C1 is used to control the output terminal OUT of the signal output module 20C2 to output a valid signal or a non-valid signal. The signal output module 20C2 includes an input terminal IN and an output terminal OUT. Figure 8 As shown, when the circuit structures of the shift register circuit 20 in the first shift register group 20A1 and the shift register circuit 20 in the second shift register group 20A2 are symmetrical, Figure 8It can be seen that the control module 20C1 and the signal output module 20C2 in the circuit structure of the shift register circuit 20 of the first shift register group 20A1 and the shift register circuit 20 of the second shift register group 20A2 are symmetrical to each other. Optionally, the first shift register group 20A1 and the second shift register group 20A2 are respectively arranged close to two edges of the display panel 100 in the second direction X2, which is conducive to making the first shift register group 20A1 and the second shift register group 20A2 distributed more evenly in the display panel 100. Optionally, the first shift register group 20A1 and the second shift register group 20A2 can also be distributed at 1 / 4 to 3 / 4 of the display panel 100, overlapping with the pixel circuit 10 therein in the first direction X1. Reference Figure 6 As shown, if the structures of the shift register circuits 20 in the first shift register group 20A1 and the second shift register group 20A2 are set to be the same, the distance between the shift register circuit 20 in the first shift register group 20A1 and the pixel circuit 10 electrically connected to it may be different from the distance between the shift register circuit 20 in the second shift register group 20A2 and the pixel circuit 10 electrically connected to it.

[0070] Therefore, setting the circuit structures of the shift register circuit 20 included in the first shift register group 20A1 and the shift register circuit 20 included in the second shift register group 20A2 to be symmetrical is beneficial to improving the consistency of the electrical connection distance between the shift register circuit 20 in the second shift register group 20A2 and the pixel circuit 10, and the electrical connection distance between the shift register circuit 20 in the first shift register group 20A1 and the pixel circuit 10, thereby improving the synchronization of the pixel circuit 10 electrically connected to the first shift register group 20A1 and the pixel circuit 10 electrically connected to the second shift register group 20A2 receiving the driving signal.

[0071] In combination with the above content, it can be known that the second signal line SL2 electrically connected to the shift register circuit 20 and the first signal line SL1 electrically connected to the pixel circuit 10 are respectively located on opposite sides of the first pixel circuit 101 in the second direction X2. Taking the second signal line SL2 as a cascade signal line as an example, the second signal line SL2 needs to be electrically connected between two adjacent shift register circuits 20 distributed along the first direction X1. When preparing the shift register circuit 20, the partial circuit including the output terminal OUT and the input terminal IN in the shift register circuit 20 can be prepared on the side close to the second signal line SL2. In the symmetrical preparation in the embodiment of the present application, optionally, as Figure 7As shown in the figure, the output terminal OUT and the input terminal IN of the shift register circuit 20 in the first shift register group 20A1 are both arranged toward the side where the second shift register group 20A2 is located in the second direction X2, and the output terminal OUT and the input terminal IN of the shift register circuit 20 in the second shift register group 20A2 are both arranged toward the side where the first shift register group 20A1 is located in the second direction X2. This makes the structure of the shift register circuit 20 in the first shift register group 20A1 and the structure of the shift register circuit 20 in the second shift register group 20A2 symmetrical in the second direction X2. Ideally, a symmetry axis of the shift register circuit 20 located in the first shift register group 20A1 and the shift register circuit 20 located in the second shift register group 20A2 can be found in the display panel 100, and the symmetry axis extends along the first direction X1. The shift register circuit 20 in the first shift register group 20A1 and the shift register circuit 20 symmetrical thereto in the second shift register group 20A2 are respectively located on both sides of the symmetry axis in the second direction X2.

[0072] It should be noted that when the circuit structures of the shift register circuit 20 included in the first shift register group 20A1 and the shift register circuit 20 included in the second shift register group 20A2 are symmetrical, the first signal line SL1 electrically connected to the pixel circuit 10 electrically connected to the shift register circuit 20 in the first shift register group 20A1 and the first signal line SL1 electrically connected to the pixel circuit 10 electrically connected to the shift register circuit 20 in the second shift register group 20A2 are also correspondingly adjusted to different sides of the pixel circuit 10 in the second direction X2.

[0073] In the embodiment of the present application, the circuit structures of the shift register circuit 20 included in the first shift register group 20A1 and the shift register circuit 20 included in the second shift register group 20A2 are set to be symmetrical, which is beneficial to improving the consistency when the shift register circuit 20 in the first shift register group 20A1 and the shift register circuit 20 in the second shift register group 20A2 are electrically connected to the pixel circuit 10, and reducing the difference in routing impedance between the first shift register group 20A1 and the second shift register group 20A2.

[0074] Fig. 9 A schematic plan view of another display panel provided in an embodiment of the present application is shown in FIG. Fig.10 A schematic diagram of a pixel circuit provided in an embodiment of the present application is shown in FIG. Fig.11 A method provided in the embodiment of the present application Fig. 9 Partial schematic diagram of the middle area E3.

[0075] In one embodiment of the present application, Fig. 9As shown, the shift register group 20A includes a first shift register group 20A1 and a second shift register group 20A2, and the first shift register group 20A1 and the second shift register group 20A2 provide the same signal to the pixel circuit 10. In the display panel 100, the second direction X2 is used as the row direction, and the plurality of pixel circuits 10 are arranged along the second direction X2, and the shift register circuit 20 can output a driving signal to the plurality of pixel circuits 10 located in the same row. However, in the related art, when a shift register circuit 20 transmits a driving signal to the pixel circuits 10 in the same row, there is a risk that the signal transmission distance is long, and thus the driving signal received by the pixel circuit 10 is distorted. The first shift register group 20A1 and the second shift register group 20A2 are both set to generate drive signals provided to the pixel circuit 10, and the first shift register group 20A1 and the second shift register group 20A2 provide the same signal for the pixel circuits 10 in the same row, which is beneficial for making it possible for some pixel circuits 10 in the same row to receive the drive signal provided by the shift register circuit 20 in the first shift register group 20A1, and another part of the pixel circuits 10 to receive the same drive signal provided by the second shift register group 20A2; thereby helping to reduce the delay and distortion of the drive signal when it is transmitted to the pixel circuits 10 in the same row, improve the accuracy of the drive signal received by the pixel circuit 10, and further improve the accuracy of the light-emitting drive current generated by the pixel circuit 10.

[0076] The shift register circuit 20 included in the first shift register group 20A1 overlaps with the first pixel circuit 101 in the first direction X1, and the shift register circuit 20 included in the second shift register group 20A2 overlaps with the second pixel circuit 102 in the first direction X1. In the display panel 100, the shift register circuit 20 in the first shift register group 20A1 can be set to be electrically connected to the first pixel circuit 101, and the shift register circuit 20 in the second shift register group 20A2 can be set to be electrically connected to the second pixel circuit 102. Since the first shift register group 20A1 and the second shift register group 20A2 provide the same signal to the pixel circuit 10, the first pixel circuit 101 and the second pixel circuit 102 receiving the same signal are located in the same row of pixel circuits.

[0077] Combination Fig.10As shown, the pixel circuit 10 includes a first drive signal receiving terminal 10D. Optionally, the first drive signal receiving terminal 10D can be used to receive one of the scan signal or the light emitting control signal transmitted by the shift register circuit 20. In the embodiment of the present application, the first drive signal receiving terminal is used to receive the first scan control signal PWM-S1 transmitted by the output terminal of the shift register circuit 20. Optionally, the control terminal of the pulse width modulation module 10A in the pixel circuit 10 that requires the first scan signal PWM-S1 is electrically connected to the control signal line DL1. After the pulse width modulation module 10A receives the valid first scan signal PWM-S1, the transistor T2 can be turned on, so that the pulse width modulation module 10A of the pixel circuit 10 receives the data signal PWM-data.

[0078] Continue to refer Fig.10As shown, illustratively, the embodiment of the present application provides a 17T3C type pixel circuit 10, which can be used to generate a light-emitting driving current to drive a light-emitting element 200 to emit light. Optionally, the light-emitting element 200 is any one of a micro light-emitting diode (Micro-LED), a sub-millimeter light-emitting diode (Min i-LED), and an organic light-emitting diode (200). The pixel circuit 10 includes a pulse width modulation module 10A and a pulse amplitude modulation module 10B. The pulse width modulation module 10A includes transistors T1 to T7, wherein transistor T1 is used to receive a first power drive signal Pwm-VDD of the pulse width modulation module 10A; transistor T2 is used to receive a data signal PWM-data and transmit it to transistor T3; transistor T4 is used to compensate for a threshold voltage of transistor T3; transistor T5 is used to receive a pulse width reset signal Pwm-ref; transistor T6 is connected in series between a swept frequency constant voltage signal line SWEEP_GND and a first capacitor C1 (for example, a plate in the first capacitor C1 connected to the swept frequency signal line SWEEP), and transistor T6 is turned on to transmit a swept frequency constant voltage provided by the swept frequency constant voltage signal line SWEEP_GND to the first capacitor C3, and the swept frequency constant voltage can be the same as a high level of the swept frequency signal, or the same as a low level of the swept frequency signal. At this time, the sweep frequency constant voltage signal line SWEEP_GND and the sweep frequency signal line SWEEP both provide signals to one plate of the first capacitor C1 (for example, the plate in the first capacitor C3 connected to the sweep frequency signal line SWEEP), which can further ensure the stability of the plate potential of the first capacitor C1 and reduce the signal disturbance caused by peripheral signals; the transistor T7 is used to electrically connect the pulse width modulation module 10A and the pulse amplitude modulation module 10B.The pulse amplitude modulation module 10B includes transistors T8 to T14, wherein transistor T8 is used to receive the second power supply driving signal Pam-VDD of the pulse amplitude modulation module 10B; transistor T9 is used to control the light-emitting driving current to flow to the light-emitting element 200; transistor T10 is used to receive the pulse amplitude modulation data signal PAM-data and transmit it to transistor T11; transistor T12 is used to compensate the threshold voltage of transistor T11 to the gate of transistor T11; transistor T13 is used to receive the pulse amplitude reset signal Pam-REF and transmit it to the gate of transistor T11; transistor T14 is used to receive the reset signal line Pam-IN IT transmits the reset signal, and transmits it to the first pole of the light-emitting element 200; the transistor T15 is turned on to transmit the voltage provided by the second power drive signal Pam-VDD to the second capacitor C2, so that the voltage on the second power drive signal Pam-VDD is applied to the amplitude adjustment module 302 in the light-emitting stage, so as to provide the light-emitting drive current to the light-emitting element 200; the transistor T16 is connected in series between the first power drive signal Pwm-VDD and the second capacitor C2, and when the transistor T16 is turned on, the voltage provided by the first power drive signal Pwm-VDD is transmitted to the second capacitor C2; the transistor T17 is also connected in series between the first power drive signal Pwm-VDD and the second capacitor C2, and the transistor T15 is turned on to transmit the voltage provided by the first power drive signal Pwm-VDD to the second capacitor C2. Further, the pulse amplitude modulation module 302 also includes a third capacitor C3, which is connected in series between the reset signal line Pam-I NI T and the second capacitor C2, and can be used to stabilize the plate potential of the second capacitor C2.

[0079] In the embodiments of the present application, Fig.11 As shown, the circuit structures of the first pixel circuit 101 and the second pixel circuit 102 are symmetrically arranged, which is beneficial to further improve the pixel circuits 10 in the left and right areas of the display panel 100 to work under the same working conditions, thereby ensuring the uniformity of the display effect and reducing the color deviation of the left and right areas of the display panel 100. It is also beneficial to make the circuit layouts of the display panels 100 on both sides the same, reduce the difficulty in preparing the display panel 100, improve the preparation efficiency of the display panel 100, and improve the product yield. Optionally, after the structure is symmetrically arranged, the first drive signal receiving terminal 10D of the first pixel circuit 101 faces the side where the second pixel circuit 102 is located in the second direction X2, and the first drive signal receiving terminal 10D of the second pixel circuit 102 faces the side where the first pixel circuit 101 is located in the second direction X2. It should be noted that the pixel circuit 10 includes a plurality of signal ports. Fig. 9 , Fig.11The position of the first driving signal receiving terminal 10D is used as an identifier to indicate that the first pixel circuit 101 and the second pixel circuit 101 are symmetrical circuit structures. In addition, in an ideal case, a symmetry axis of the first pixel circuit 101 and the second pixel circuit 102 can be found in the display panel 100, the symmetry axis extends along the first direction X1, and the first pixel circuit 101 and the second pixel circuit 102 are respectively located on opposite sides of the symmetry axis in the second direction X2.

[0080] Fig.12 A schematic plan view of another display panel provided in an embodiment of the present application.

[0081] Furthermore, if Fig.12 As shown, when the circuit structures of the first pixel circuit 101 and the second pixel circuit 102 are set symmetrically, the circuit structures between the shift register circuit 20 overlapping with the first pixel circuit 101 and the shift register circuit 20 overlapping with the second pixel circuit 102 are also set symmetrically. At this time, the output end and the input end of the shift register 20 in the first shift register group 20A1 are also oriented toward the side where the second pixel circuit 102 is located in the second direction X2, and the output end and the input end of the shift register 20 in the second shift register group 20A2 are also oriented toward the side where the first pixel circuit 101 is located in the second direction X2, which is beneficial to further reduce the routing impedance difference between the routings electrically connecting the first pixel circuit 101 and the second pixel circuit 102, and is beneficial to avoid the winding of the second signal line SL2, so that the second signal line SL2 and the first signal line SL1 can be prepared on the opposite sides of the first pixel circuit 101 along the second direction X2, and the second signal line SL2 and the first signal line SL1 are prepared on the opposite sides of the second pixel circuit 102, thereby avoiding routing interference between the second signal line SL2 and the first signal line SL1.

[0082] Fig.13 A schematic plan view of another display panel provided in an embodiment of the present application.

[0083] In one embodiment of the present application, Fig.13 As shown, a pixel circuit 10 includes a plurality of sub-pixel circuits 10E, and the sub-pixel circuits 10E in the same pixel circuit 10 are arranged along the second direction X2. The plurality of sub-pixel circuits 10E are electrically connected to light-emitting elements 200 of different luminous colors. Optionally, a pixel circuit 10 includes three sub-pixel circuits 10E, and the three sub-pixel circuits 10E are respectively electrically connected to a first sub-pixel circuit 10E1 of a red light-emitting element 200, a second sub-pixel circuit 10E2 of a green light-emitting element, and a third sub-pixel circuit 10E3 of a blue light-emitting element. Figure 8As shown, the first signal line SL1 and the third signal line SL3 are respectively located on opposite sides of the pixel circuit 10 in the second direction X2, and different sub-pixel circuits 10E are electrically connected to different first signal lines SL1 and third signal lines SL3. Optionally, three first signal lines SL1 electrically connected to different sub-pixel circuits 10E are arranged along the second direction X2 and prepared on one side of the pixel circuit 10 in the second direction X2, and three second signal lines SL2 electrically connected to different sub-pixel circuits 10E are arranged along the second direction X2 and prepared on the other side of the pixel circuit 10 in the second direction X2, which is conducive to improving the compactness of the circuit structure in the display panel 100.

[0084] In the embodiment of the present application, the arrangement order of the light emitting elements 200 corresponding to the first pixel circuit 101 in the second direction X2 is set to be the same as the arrangement order of the light emitting elements 200 corresponding to the second pixel circuit 102 in the second direction X2, which is conducive to ensuring that the arrangement order of the light emitting elements 200 in different areas of the display panel 100 is consistent, thereby avoiding the aggregation of light emitting elements 200 of the same color, and ensuring the display uniformity of the display panel 100. The light emitting driving current output terminal 10C of the pixel circuit 10 is electrically connected to the light emitting element 200, and when the circuit structures of the first pixel circuit 101 and the second pixel circuit 102 are symmetrical, the structures of the multiple sub-pixel circuits 10E in the first pixel circuit 101 and the multiple sub-pixel circuits 10E in the second pixel circuit 102 are also symmetrical. It should be noted that the symmetry here refers to the symmetry of the circuit structures of the sub-pixel circuit 10E electrically connected to the red light-emitting element in the first pixel circuit 101 and the sub-pixel circuit 10E electrically connected to the red light-emitting element in the second pixel circuit 102, the symmetry of the circuit structures of the sub-pixel circuit 10E electrically connected to the green light-emitting element in the first pixel circuit 101 and the sub-pixel circuit 10E electrically connected to the green light-emitting element in the second pixel circuit 102, and the symmetry of the circuit structures of the sub-pixel circuit 10E electrically connected to the blue light-emitting element in the first pixel circuit 101 and the sub-pixel circuit 10E electrically connected to the blue light-emitting element in the second pixel circuit 102, which is conducive to adapting to the scheme in which the multiple light-emitting elements 200 in each pixel circuit 10 in the display panel 100 are arranged in the same order, and avoiding complicated electrical connections between the pixel circuits 10 and the light-emitting elements 200.

[0085] It should be noted that the arrangement of the light emitting elements 200 of different colors in the display panel 100 and the arrangement of the pixel circuit 10 proposed in the embodiment of the present application are only examples and are not specifically limited.

[0086] Fig.14 A method provided in the embodiment of the present application Fig.13 Schematic diagram of the cross section along the B-B' direction.

[0087] In one embodiment of the present application, Fig.14 As shown, the electrical connection distance between the sub-pixel circuit in the first pixel circuit and the corresponding light-emitting element is different from the electrical connection distance between the light-emitting elements corresponding to the sub-pixel circuit in the second pixel circuit.

[0088] Since the structures of each sub-pixel circuit 10E in the first pixel circuit 101 and each sub-pixel circuit 10E in the second pixel circuit 102 are symmetrical, the electrical connection structure between the light-emitting driving current output terminal 10C of each sub-pixel circuit 10E in the first pixel circuit 101 and the corresponding light-emitting element 200 can be adaptively set to be different from the electrical connection structure between the light-emitting driving current output terminal 10C of each sub-pixel circuit 10E in the second pixel circuit 101 and the corresponding light-emitting element 200. For example, the wiring distance between the light-emitting driving current output terminal 10C of each sub-pixel circuit 10E in the first pixel circuit 101 and the corresponding light-emitting element 200 is set to be different from the wiring distance between the light-emitting driving current output terminal 10C of each sub-pixel circuit 10E in the second pixel circuit 101 and the corresponding light-emitting element 200. It should be noted that the pixel circuit 10 includes multiple transistors. Fig. 9 A transistor is used as an example, and Fig.14 The electrical connection structure between the pixel circuit 10 and the light emitting element 200 is mainly illustrated.

[0089] Fig.15 A schematic plan view of another display panel provided in an embodiment of the application, Fig.16 A schematic diagram of a multi-way selection circuit provided in an embodiment of the present application is provided. Fig.17 A method provided in the embodiment of the present application Fig.15 A partial schematic diagram of the middle area E4.

[0090] In one embodiment of the present application, Fig.15As shown, the display panel 100 also includes a multi-way selection circuit 30, and the multi-way selection circuit 30 is electrically connected to the first type signal line SL1. The first type signal line SL1 here can be a data signal line SL1A, and the first type signal line SL1 is used to output the data signal PWM-data provided to the pulse width modulation module 10A of the pixel circuit 10. With the first direction X1 as the column direction, multiple pixel circuits 10 arranged along the first direction X1 can be electrically connected to the same first type signal line SL1. Optionally, the multi-way selection circuit 30 in the embodiment of the present application includes a source data signal input terminal for providing different data signals PWM-data. The multi-way selection circuit 30 also includes a plurality of output switches 30A, and the plurality of output switches 30A are electrically connected to different first type signal lines SL1 respectively. When the display panel 100 is working, the first type signal line SL1 can open the plurality of switches 30A in time-sharing, and output the data signals PWM-data required by the pixel circuits 10 in different columns from different switches 30A respectively. Taking the pixel circuit 10 including three sub-pixel circuits 10E as an example, the same multiplexer circuit 30 can be electrically connected to the first type signal line SL1 electrically connected to the three sub-pixel circuits 10E respectively, and the multiplexer circuit 30 sequentially outputs the data signal PWM-data required by the sub-pixel circuit 10E electrically connected to the red light-emitting element 2001, the data signal PWM-data required by the sub-pixel circuit 10E electrically connected to the green light-emitting element 2002, and the data signal PWM-data required by the sub-pixel circuit 10E electrically connected to the blue light-emitting element 2003.

[0091] As can be seen from the above, the number of columns of pixel circuits 10 in the display panel 100 is relatively large, and the use of the multiplexer circuit 30 is beneficial to saving the number of pins prepared by the power chip in the display panel 100 .

[0092] In the first direction X1 , the multiplexer circuit 20 at least partially overlaps with the pixel circuits 10 in the same column, and the output end of the multiplexer circuit 20 needs to be routed to the side where the first signal line SL1 is located to achieve electrical connection with the first signal line SL1 .

[0093] In the embodiments of the present application, Fig.16 , Fig.17As shown, the multiplexer circuit 30 includes a first multiplexer circuit 301 and a second multiplexer circuit 302 arranged along the second direction X2, and the circuit structures of the first multiplexer circuit 301 and the second multiplexer circuit 302 are symmetrical. Similar to the bilateral driving method in which the first shift register group 20A1 and the second shift register group 20A2 are used in the display panel 100 to generate the same driving signal to drive the pixel circuit 10, the first multiplexer circuit 301 and the second multiplexer circuit 302 in the display panel 100 provided in the embodiment of the present application can also be described by using the bilateral driving method as an example. Since the first multi-way selection circuit 301 and the second multi-way selection circuit 302 are arranged along the second direction X2, and the switches 30A in the multi-way selection circuit 30 are all turned on and off by the signal transmitted by the first control signal line SL4, when the control signal end electrically connected to the first control signal line SL4 is located near the first multi-way selection circuit 301, the second multi-way selection circuit 302 is far away from the control signal end electrically connected to the first control signal line SL4. As the extension distance of the first control signal line SL4 increases, there may be a large delay in opening or disconnecting the corresponding switches 30A in the first multi-way selection circuit 301 and the second multi-way selection circuit 302, resulting in poor synchronization, which is not conducive to the display uniformity of the display panel 100. Optionally, in combination with Fig.16 , Fig.17 As shown, the display panel 100 includes a first area 1001 and a second area 1002 distributed along the second direction X2. The first area 1001 may include a first multiplexer circuit 301, and the second area 1002 may include a second multiplexer circuit 302. The structures of the first multiplexer circuit 301 and the second multiplexer circuit 302 are symmetrical, and the switches 30A in the first multiplexer circuit 302 and the second multiplexer circuit 302 are respectively electrically connected to the first control signal line SL4 that is set on both sides, which is conducive to reducing the switch delay difference between the first multiplexer circuit 301 and the second multiplexer circuit 302. In an ideal case, the symmetry axis of the first multiplexer circuit 301 and the second multiplexer circuit 302 can be found in the display panel 100, and the symmetry axis extends along the first direction X1. The first multiplexer circuit 301 and the second multiplexer circuit 302 are respectively located on opposite sides of the symmetry axis in the second direction X2.

[0094] In the embodiment of the present application, the symmetrical circuit structure design of the first multiplexer circuit 301 and the second multiplexer circuit 302 is beneficial to ensure that the multiplexer circuits 30 in different areas of the display panel 100 operate under the same driving conditions, and is suitable for the display panel 100 adopting a bilateral driving working mode, which reduces the opening and closing delays of multiple switches in different multiplexer circuits 30, thereby ensuring the time accuracy of the pixel circuits 10 in different areas but the same row of the display panel 100 receiving the data signal PWM-data.

[0095] It should be noted that after the circuit structures of the first multi-way selection circuit 301 and the second multi-way selection circuit 302 are symmetrical, since the first signal line SL1 and the second signal line SL2 are located on opposite sides of the first pixel circuit 101 in the second direction X2, when the first multi-way selection circuit 301 is prepared, the connecting line between the output end of the switch and the first signal line SL1 is wound toward the side where the corresponding first signal line SL1 is located, and when the second multi-way selection circuit 302 is prepared, the connecting line between the output end of the switch and the first signal line SL1 is also wound toward the side where the corresponding first signal line SL1 is located, thereby avoiding interference between the first multi-way selection circuit 301 and the second signal line SL2.

[0096] Fig.18 A schematic plan view of another display panel provided in an embodiment of the present application.

[0097] Alternatively, if Fig.18 As shown, the first multiplexer circuit 301 in the display panel 100 at least partially overlaps with the first shift register group 20A1 in the first direction X1, and the second multiplexer circuit 302 at least partially overlaps with the second shift register group 20A2 in the first direction X1. At this time, the circuit structures of the first multiplexer circuit 301 and the second multiplexer circuit 302 are symmetrical, and the circuit structures of the shift register circuit 20 in the first shift register group 20A1 and the shift register circuit 20 in the second shift register group 20A2 are symmetrical. For example, the first region 1001 in the display panel 100 includes the first multiplexer circuit 301 and the first shift register group 20A1, and the second region 1002 includes the second multiplexer circuit 302 and the second shift register group 20A2. The second signal line SL2 in the first area 1001 is located on the side of the first pixel circuit 101 facing the second area 1002 in the second direction X2, while the second signal line SL2 in the second area 1002 is located on the side of the first pixel circuit 101 facing the first area 1001 in the second direction X2. Fig.15By comparison, it can be seen that it is beneficial to make the electrical connection distance between the multiple switches in the first multiple selection circuit 301 and the different first-type signal lines SL1 close to the electrical connection distance between the multiple switches in the second multiple selection circuit 302 and the different first-type signal lines SL1, which is beneficial to further reduce the time delay of the pixel circuits 10 located in the same row receiving the data signal PWM-data. In addition, it is beneficial to ensure that the first signal line SL1 and the second signal line SL2 in the display panel 100 are located on opposite sides of the first pixel circuit 101 in the second direction X2, reducing the degree of negotiation between the multiple selection circuit 30 and the second signal line SL2.

[0098] Fig.19 A schematic plan view of another display panel provided in an embodiment of the present application.

[0099] Alternatively, if Fig.19 As shown, the display panel 100 includes a first pixel circuit 101 overlapping with the shift register circuit 20 in the first shift register group 20A1, and also includes a second pixel circuit 102 overlapping with the shift register circuit 20 in the second shift register group 20A2. In combination with the above content, the first pixel circuit 101 and the second pixel circuit 102 can be located in the same row of pixel circuits 10, which will not be repeated here. When the circuit structure of the first multiplexer selection circuit 301 and the second multiplexer selection circuit 302 is set to be symmetrical, the circuit structure of the first pixel circuit 101 and the second pixel circuit 102 is also set to be symmetrical, which is conducive to improving the pixel circuits 10 in the first area 1001 and the second area 1002 of the display panel 100 to work under the same working conditions, thereby ensuring the uniformity of the display effect and reducing the contrast difference between the left and right areas of the display panel 100. In addition, the pixel circuits 10 and the multi-way selection circuits 30 in the first area 1001 and the second area 1002 of the display panel 100 are symmetrically prepared, which is conducive to making the circuit layout of the display panels 100 on both sides the same, reducing the difficulty in preparing the display panels 100 and improving the product yield.

[0100] Fig. 20 A schematic plan view of another display panel provided in an embodiment of the present application is shown in FIG. Fig.21 A method provided in the embodiment of the present application Fig. 20 Schematic diagram of a part of the middle area E5.

[0101] Optionally, combined Fig. 20 , Fig.21As shown, the display panel 100 includes a first pixel circuit 101 overlapping with the shift register circuit 20 in the first shift register group 20A1, and also includes a second pixel circuit 102 overlapping with the shift register circuit 20 in the second shift register group 20A2. In the first direction X1, the first multiplexer circuit 301 overlaps with the first pixel circuit 101 and the multiple shift register circuits 20 in the first shift register group 20A1, and the second multiplexer circuit 302 overlaps with the second pixel circuit 102 and the multiple shift register circuits 20 in the second shift register group 20A2. The circuit structures of the first multiplexer circuit 301 and the second multiplexer circuit 302 are symmetrical, the circuit structures of the first pixel circuit 101 and the second pixel circuit 102 are also symmetrical, and the circuit structures of the multiple shift register circuits 20 in the first shift register group 20A1 and the multiple shift register circuits 20 in the second shift register group 20A2 are also symmetrical. This is beneficial to ensuring the preparation standardization of multiple wirings in the display panel 100 when the first signal line SL1 and the second signal line SL2 are respectively located on opposite sides of the pixel circuit 10, and is beneficial to reducing the degree of winding when the multiplexer circuit 30 is electrically connected to the first signal line SL1, reducing the degree of winding when the shift register circuit 20 is electrically connected to the second signal line SL2, and reducing the length difference of the second part SL12 electrically connected to different pixel circuits 10, thereby ensuring the uniform design of the display panel 100 and improving the display effect.

[0102] In one embodiment of the present application, continue to refer to Fig.15 As shown, the multiplexer circuit 30 is located on the side of the first shift register circuit 201 close to the pixel circuit 10. The multiplexer circuit 30 is usually prepared in the part of the display panel 100 close to the frame, which is conducive to electrically connecting the multiplexer circuit 30 to the power supply terminal. Here, the multiplexer circuit 30 is adjacent to the first shift register circuit 201 in the first direction X1. The first shift register circuit 20 can be a virtual shift register circuit set to maintain the uniformity of the panel structure of the display panel 100. The output end of the first shift register circuit 201 is not electrically connected to the pixel circuit 10, but is electrically connected to the cascade test end V1 in the display panel 100. The cascade test end V1 in the display panel 100 is used to receive the cascade signal output by the first shift register circuit 201 to determine whether the multiple shift register circuits 20 in the shift register group 20A have successfully completed the cascade.

[0103] In the embodiment of the present application, the multi-way selection circuit 30 is arranged to be located on the side of the first shift register circuit 201 close to the pixel short circuit 10, which is beneficial for making the multi-way selection circuit 30 closer to the pixel circuit 10 in the first direction X1. Correspondingly, the electrical connection distance between the switch in the multi-way selection circuit 30 and the first signal line SL1 is also closer, which is beneficial for reducing the wiring impedance and improving the accuracy of the data signal PWM-data received by the pixel circuit 10.

[0104] Fig. 22 A schematic plan view of another display panel provided in an embodiment of the present application.

[0105] In one embodiment of the present application, Fig. 22 As shown, the multiplexer circuit 30 is located on a side of the first shift register circuit 201 away from the pixel circuit 10. The first shift register circuit 201 described in the above embodiment is a virtual shift register circuit electrically connected to the cascade test terminal, and the relevant contents are not repeated here.

[0106] Combination Fig.15 , Fig. 22 As shown, it can be seen that the control ends of some switches 30A in the switches 30A of the multiple multiplexer selection circuits 30 distributed in the second direction X2 are electrically connected to the same first control signal line SL4, and these first control signal lines SL4 extend along the second direction X2.

[0107] In the embodiments of the present application, Fig.14 As shown, the multiplexer selection circuit 30 is located at a side of the first shift register circuit 201 away from the pixel circuit 10. Fig.10 It can be seen that this is beneficial to avoid interference between the multiple first control signal lines SL4 electrically connected to the multi-way selection circuit 30 and the second signal line SL2 electrically connected to the first shift register circuit 201, reducing the degree of coupling between the first control signal line SL4 and the second signal line SL2, thereby helping to improve the accuracy of the first control signal line SL4 controlling the switch to open and close.

[0108] Fig.23 A schematic diagram of another display device provided in an embodiment of the present application.

[0109] The present application embodiment provides a display device 300, such as Fig.23 As shown, the display device 300 includes the display panel 100 described in any one of the above embodiments. Optionally, the display device 300 can be a device for display such as a mobile phone, a computer, or a television.

[0110] In the display device 300, it is proposed that along the second direction X2, the first type signal line SL1 and the second type signal line SL2 are arranged at opposite sides of the first pixel circuit 101. And along the second direction X2, the first type signal line SL1 and the second type signal line SL2 are arranged at opposite sides of the first shift register circuit 201, and the first direction X1 intersects with the second direction X2. In the second direction X2, the first type of signal line SL1 electrically connected to the first pixel circuit 101 and the second type of signal line SL2 electrically connected to the first shift register circuit 201 include the first pixel circuit 101 and / or the first shift register circuit 201, thereby increasing the spacing between the first type of signal line SL1 and the second type of signal line SL2, reducing the degree of coupling between the first type of signal line SL1 and the second type of signal line SL2 and the risk of routing interference, which is beneficial to improving the stability of the first type of signal line SL1 and the second type of signal line SL2 when transmitting signals, improving the accuracy of the signals received by the pixel circuit 10 and the shift register circuit 20, ensuring that the pixel circuit 10 generates an accurate light-emitting drive current, and ensuring the working stability of the shift register circuit 20, thereby improving the uniformity and stability of the display panel 100 during display.

[0111] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: It comprises a pixel circuit and a shift register group, wherein the shift register group comprises a plurality of shift register circuits, and the pixel circuit and the shift register circuit are arranged along a first direction; The pixel circuit includes a first pixel circuit, the shift register group includes a first shift register circuit, and the first pixel circuit and the first shift register circuit at least partially overlap in the first direction; A first type of signal line, the first type of signal line is electrically connected to the pixel circuit, and the first type of signal line provides a first type of signal to the pixel circuit; A second type of signal line, the second type of signal line is electrically connected to the shift register circuit, and the second type of signal line transmits a pulse signal in at least a part of the time period; Along the second direction, the first-type signal lines and the second-type signal lines are located on two opposite sides of the first pixel circuit; Along the second direction, the first type of signal lines and the second type of signal lines are located on opposite sides of the first shift register circuit; The first direction intersects with the second direction.

2. The display panel according to claim 1, characterized in that: The pixel circuit includes a pulse width modulation module, and the pulse width modulation module is used to control the light emitting duration of the light emitting element corresponding to the pixel circuit; The first type of signal line includes a first data signal line, and the first data signal line is electrically connected to the pulse width modulation module to provide a data signal for the pulse width modulation module.

3. The display panel according to claim 1, characterized in that: The first type of signal line at least includes a first portion extending along a first direction and a second portion extending along a second direction, and the second type of signal line extends along the first direction and is disposed in the same layer as the first portion.

4. The display panel according to claim 3, characterized in that: The third type of signal line includes a third type of signal line, which is electrically connected to the pixel circuit. The third type of signal line includes a third portion extending along the first direction. The third portion is arranged on the same layer as the second type of signal line. The second type of signal line and the third portion are located on the same side of the pixel circuit. Along the second direction, the distance from the second type of signal line to the first pixel circuit is smaller than the distance from the third portion to the first pixel circuit.

5. The display panel according to claim 1, characterized in that: The second type of signal line is electrically connected to two shift register circuits arranged along the first direction, and the two shift register circuits are located on opposite sides of the same pixel circuit in the first direction.

6. The display panel according to claim 1, characterized in that: The shift register group includes a first shift register group and a second shift register group, and the first shift register group and the second shift register group provide the same signal for the pixel circuit; The shift register circuit included in the first shift register group and the shift register circuit included in the second shift register group have symmetrical circuit structures.

7. The display panel according to claim 1, characterized in that: The shift register group includes a first shift register group and a second shift register group, and the first shift register group and the second shift register group provide the same signal for the pixel circuit; The shift register circuit included in the first shift register group overlaps with the first pixel circuit in the first direction, and the shift register circuit included in the second shift register group overlaps with the second pixel circuit in the first direction, wherein: The circuit structures of the first pixel circuit and the second pixel circuit are symmetrical.

8. The display panel according to claim 7, characterized in that: One of the pixel circuits includes a plurality of sub-pixel circuits, and the sub-pixel circuits in the same pixel circuit are arranged along the second direction; The plurality of sub-pixel circuits are electrically connected to light-emitting elements of different luminous colors respectively; the arrangement order of the light-emitting elements corresponding to the first pixel circuit in the second direction is the same as the arrangement order of the light-emitting elements corresponding to the second pixel circuit in the second direction.

9. The display panel according to claim 8, characterized in that: An electrical connection distance between the sub-pixel circuit in the first pixel circuit and the corresponding light-emitting element is different from an electrical connection distance between the light-emitting elements corresponding to the sub-pixel circuit in the second pixel circuit.

10. The display panel according to claim 1, characterized in that: It includes a multi-way selection circuit, which is electrically connected to the first type of signal line. The multi-way selection circuit includes a first multi-way selection circuit and a second multi-way selection circuit arranged along the second direction. The circuit structures of the first multi-way selection circuit and the second multi-way selection circuit are symmetrical.

11. The display panel according to claim 10, characterized in that: The multiplexer circuit is located on a side of the first shift register circuit close to the pixel circuit.

12. The display panel according to claim 10, characterized in that: The multiplexer circuit is located at a side of the first shift register circuit away from the pixel circuit.

13. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-12.

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