Display panel and display device

Abstract

The invention provides a display panel and a display device.The display panel comprises a substrate, a first metal layer, a photosensitive unit and a second metal layer, the first metal layer is arranged on the substrate and comprises a first shading part, and the photosensitive unit is arranged on the side, away from the substrate, of the first shading part; the photosensitive unit comprises a photosensitive doping part, a photosensitive part and a photosensitive electrode which are stacked, one end of the photosensitive part is connected with the photosensitive doping part, and the other end of the photosensitive part is connected with the photosensitive electrode; the orthographic projection of the photosensitive part on the substrate is located in the orthographic projection of the first shading part on the substrate; the first shading part is connected with the constant voltage source, so that the potential of the first shading part is always in a stable state, the potential of the first shading part is prevented from floating, the problem of electric noise caused by the floating potential of the first shading part is avoided, and the measurement precision of the photosensitive unit is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the rapid development of the panel display industry, the market demand for highly functional and highly integrated display panels continues to increase; currently, ambient light and color temperature sensing functions are usually achieved through external sensors, which require additional installation space, resulting in a wider border of the display panel.

[0003] Photoelectric sensors can integrate the functions of ambient light sensors and color temperature sensors, and have the advantages of fast response speed, simple structure and high precision. Photocurrent sensors can be directly integrated into the display panel or device, thereby effectively saving space. Summary of the invention

[0004] Embodiments of the present application provide a display panel and a display device to alleviate the deficiencies in the related art.

[0005] To achieve the above functions, the technical solutions provided by the embodiments of the present application are as follows:

[0006] An embodiment of the present application provides a display panel, including:

[0007] substrate;

[0008] A first metal layer, disposed on the substrate, the first metal layer comprising a first light shielding portion;

[0009] A photosensitive unit is provided on a side of the first light shielding portion away from the substrate, the photosensitive unit comprising a stacked photosensitive doped portion, a photosensitive portion and a photosensitive electrode, one end of the photosensitive portion is connected to the photosensitive doped portion, and the other end of the photosensitive portion is connected to the photosensitive electrode;

[0010] The orthographic projection of the first light shielding portion on the substrate covers the orthographic projection of the photosensitive portion on the substrate, and the first light shielding portion is connected to a constant voltage source.

[0011] Optionally, in one embodiment, the display panel further comprises a control unit, and the control unit is spaced apart from the photosensitive unit;

[0012] The display panel also includes a second metal layer, which is arranged on a side of the first light-shielding portion away from the substrate, and the second metal layer includes a first electrode and a second electrode arranged at intervals, the first electrode is connected to the first light-shielding portion, one end of the second electrode is connected to the photosensitive doping portion, and the other end of the second electrode is connected to the control unit.

[0013] Optionally, in one embodiment, the display panel further includes a thin film transistor layer, the thin film transistor layer includes the control unit and the photosensitive unit, and the thin film transistor layer includes:

[0014] A semiconductor layer, disposed on the substrate, the semiconductor layer comprising the photosensitive doped portion and the semiconductor portion arranged at intervals, the semiconductor portion comprising a first doped portion and a second doped portion, and a channel portion located between the first doped portion and the second doped portion;

[0015] A third metal layer is disposed on a side of the semiconductor layer away from the substrate, the third metal layer includes a gate, and the gate is disposed corresponding to the channel portion;

[0016] The first metal layer includes a second shading portion, the second shading portion is arranged corresponding to the semiconductor portion, the second metal layer includes a third electrode and a fourth electrode, the third electrode is connected to the first doped portion, and the fourth electrode is connected to the second doped portion.

[0017] Optionally, in one embodiment, the display panel further includes:

[0018] a buffer layer, disposed between the first metal layer and the semiconductor layer;

[0019] A gate insulating layer, disposed between the semiconductor layer and the third metal layer;

[0020] an interlayer insulating layer, disposed on a side of the third metal layer away from the gate insulating layer;

[0021] The display panel is provided with a first through hole and a second through hole, the first electrode is connected to the first light shielding portion through the first through hole, and the first through hole penetrates the interlayer insulating layer, the gate insulating layer and at least a portion of the buffer layer, one end of the second electrode is connected to the photosensitive doped portion through the second through hole, and the second through hole penetrates the interlayer insulating layer, the gate insulating layer, the photosensitive doped portion and the buffer layer, and the other end of the second electrode is connected to the third electrode.

[0022] Optionally, in one embodiment, the display panel is further provided with a third through hole, at least part of the photosensitive portion is filled in the third through hole, and the third through hole penetrates the interlayer insulating layer and at least part of the gate insulating layer;

[0023] Wherein, a dimension of a side of the photosensitive portion away from the substrate is greater than a dimension of a side of the third through hole away from the substrate.

[0024] Optionally, in one embodiment, the display panel further includes:

[0025] A protective layer is provided on a side of the photosensitive portion away from the photosensitive doped portion, the protective layer is provided with a fourth through hole, and the fourth through hole penetrates the protective layer;

[0026] a planar layer, disposed on a side of the second metal layer away from the interlayer insulating layer, the planar layer being provided with a fifth through hole, the fifth through hole penetrating at least a portion of the planar layer, and the fifth through hole being connected to the fourth through hole;

[0027] The first transparent electrode layer is disposed on a side of the planar layer away from the second metal layer. The first transparent electrode layer includes the photosensitive electrode. The photosensitive electrode passes through the fourth through hole and the fifth through hole to connect with the photosensitive portion.

[0028] Optionally, in one embodiment, the semiconductor portion further includes:

[0029] a third doping portion, disposed between the channel portion and the first doping portion;

[0030] a fourth doping portion, disposed between the channel portion and the second doping portion;

[0031] Wherein, the doping concentrations of the first doping portion and the second doping portion are the same, the doping concentrations of the third doping portion and the fourth doping portion are the same, and the doping concentration of the third doping portion is less than the doping concentration of the first doping portion;

[0032] The orthographic projection of the second light shielding portion on the substrate covers the orthographic projection of the channel portion on the substrate, the orthographic projection of the third doping portion on the substrate, and the orthographic projection of the fourth doping portion on the substrate.

[0033] Optionally, in one embodiment, the display panel includes a display area and a non-display area arranged on at least one side of the display area;

[0034] The display panel further includes a fan-out portion, the fan-out portion is disposed on one side of the substrate, the fan-out portion is located in the non-display area, and the fan-out portion includes a first fan-out line, a second fan-out line, and a third fan-out line that are stacked and insulated;

[0035] The first metal layer includes a first fan-out line, the second metal layer includes the second fan-out line, the third metal layer includes a third fan-out line, and at least two of the first fan-out line, the second fan-out line and the third fan-out line are overlapped.

[0036] Optionally, in one embodiment, the first fan-out line and the third fan-out line are at least partially overlapped; and / or, the second fan-out line and the third fan-out line are at least partially overlapped; and / or, the first fan-out line and the second fan-out line are at least partially overlapped.

[0037] An embodiment of the present application provides a display device, which includes any of the above-mentioned display panels.

[0038] Beneficial effects of the embodiments of the present application: The embodiments of the present application provide a display panel and a display device, wherein the display panel includes a substrate, a first metal layer, a photosensitive unit and a second metal layer, wherein the first metal layer includes a first light-shielding portion, the photosensitive unit is arranged on a side of the first light-shielding portion away from the substrate, and the photosensitive unit includes a stacked photosensitive doping portion, a photosensitive portion and a photosensitive electrode; by integrating the photosensitive unit in the display panel, an external sensor is avoided, cost and space are saved, and the orthographic projection of the photosensitive portion on the substrate is located within the orthographic projection of the first light-shielding portion on the substrate, thereby effectively reducing light interference and improving signal accuracy; at the same time, by setting the first light-shielding portion to be connected to a constant voltage source, the potential of the first light-shielding portion is ensured to be always in a stable state, the potential of the first light-shielding portion is prevented from floating, the electrical noise problem caused by the floating potential of the first light-shielding portion is avoided, and the measurement accuracy of the photosensitive unit is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0041] Figure 2 The embodiments of the present application provide Figure 1 Schematic diagram of the cross section corresponding to A-Aˋ;

[0042] Figure 3 For the embodiment of this application Figure 1 The enlarged schematic diagram of the corresponding B area;

[0043] Figure 4 The embodiments of the present application provide Figure 3 An enlarged schematic diagram of the corresponding fan-out area;

[0044] Figure 5 The embodiments of the present application provide Figure 4 Schematic diagram of the cross section corresponding to C-Cˋ;

[0045] FIG. 6A to FIG. 6I Schematic diagram corresponding to each step of the method for manufacturing a display panel provided in an embodiment of the present application;

[0046] Figure 7 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the actual use or working mode of the device, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0048] In addition, the terms "first" and "second" are used for descriptive purposes only, and the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0049] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0050] The disclosure below provides many different embodiments to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0051] See also Figure 1 and Figure 2 ;in, Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application; Figure 2 The embodiments of the present application provide Figure 1 Schematic diagram of the cross section corresponding to A-Aˋ in the figure.

[0052] In one embodiment, the display panel 1 includes but is not limited to a liquid crystal display panel, and the display panel 1 includes a substrate 11, a first metal layer 12, a buffer layer 13, a thin film transistor layer 14, a planarization layer 15, a second transparent electrode layer 16, a passivation layer 17 and a first transparent electrode layer 18.

[0053] The substrate 11 may include a rigid substrate or a flexible substrate. When the substrate 11 is a rigid substrate, the material may be metal or glass. When the substrate 11 is a flexible substrate, the material may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, and polyamide resin. This embodiment does not impose any specific restrictions on this.

[0054] The first metal layer 12 is disposed on one side of the substrate 11 , and the material of the first metal layer 12 includes but is not limited to molybdenum (Mo), molybdenum-aluminum (MoAl) stacking or molybdenum-aluminum-molybdenum (MoAlMo) stacking, thereby reducing the sheet resistance (Sheet Resistance, Rs) of the first metal layer 12 , which helps to improve the performance of the display panel 1 and the signal transmission efficiency.

[0055] The buffer layer 13 is disposed on a side of the first metal layer 12 away from the substrate 11. The buffer layer 13 can play a buffering role. The material of the buffer layer 13 includes but is not limited to silicon nitride (SiNx), silicon oxide (SiOx), a single-layer silicon oxynitride (SiONx) or a combination structure of the above film layers.

[0056] The thin film transistor layer 14 includes a semiconductor layer 141, a gate insulating layer 142, a third metal layer 143, an interlayer insulating layer 144 and a second metal layer 145 stacked on the substrate 11, and the thin film transistor layer 14 includes a photosensitive unit 1401 and a control unit 1402. The control unit 1402 is connected to the photosensitive unit 1401, and the control unit 1402 can control the switch state of the photosensitive unit 1401.

[0057] Among them, the semiconductor layer 141 is arranged on the side of the buffer layer 13 away from the first metal layer 12, and the semiconductor layer 141 includes a photosensitive doped part 1411 and a semiconductor part 1412 arranged at intervals, and the semiconductor part 1412 includes a first doped part 14121 and a second doped part 14122, and a channel part 14123 located between the first doped part 14121 and the second doped part 14122; the material of the channel part 14123 can be polycrystalline silicon (poly-Si) formed by converting amorphous silicon (a-Si) using an excimer laser annealing (ELA) process, the doping concentrations of the first doped part 14121 and the second doped part 14122 are the same, and the first doped part 14121 and the second doped part 14122 can both be formed by heavily doping polycrystalline silicon with phosphorus ions.

[0058] The gate insulating layer 142 is disposed on a side of the semiconductor layer 141 away from the buffer layer 13. The gate insulating layer 142 can be used to prevent a short circuit between the semiconductor layer 141 and the third metal layer 143. The material of the gate insulating layer 142 includes but is not limited to silicon oxide, silicon nitride, aluminum oxide or a combination structure of the above film layers.

[0059] The third metal layer 143 is arranged on a side of the gate insulating layer 142 away from the semiconductor layer 141, and the third metal layer 143 includes a gate 1431, and the gate 1431 is arranged corresponding to the channel portion 14123, and the orthographic projection of the gate 1431 on the substrate 11 covers the orthographic projection of the channel portion 14123 on the substrate 11, and the material of the third metal layer 143 includes but is not limited to at least one metal of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta) and tungsten (W).

[0060] The interlayer insulating layer 144 is disposed on a side of the third metal layer 143 away from the gate insulating layer 142 , and the material of the interlayer insulating layer 144 includes but is not limited to silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiONx) or a combination structure of the above film layers.

[0061] The second metal layer 145 is arranged on the interlayer insulating layer 144 away from the third metal layer 143. The material of the second metal layer 145 includes but is not limited to at least one of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta) and tungsten (W). The second metal layer 145 includes a first electrode 1451, a second electrode 1452, a third electrode 1453 and a fourth electrode 1454, wherein the third electrode 1453 is connected to the first doping portion 14121, and the fourth electrode 1454 is connected to the second doping portion 14122.

[0062] The planar layer 15, the second transparent electrode layer 16, the passivation layer 17 and the first transparent electrode layer 18 are sequentially stacked on the side of the second metal layer 145 away from the interlayer insulating layer 144, wherein the material of the passivation layer 17 includes but is not limited to silicon nitride (SiNx), silicon dioxide (SiOx), silicon oxynitride (SiONx) or a combination structure of the above film layers, the first transparent electrode layer 18 includes a photosensitive electrode 181 and a pixel electrode 182, the second transparent electrode layer 16 includes a common electrode 161, and the materials of the first transparent electrode layer 18 and the second transparent electrode layer 16 include but are not limited to metal oxide materials, and the metal oxide material is preferably an indium tin oxide (ITO) material with high visible light transmittance and good conductivity.

[0063] The photosensitive unit 1401 can be a photosensor, which can be used for ambient photocurrent detection. The photosensitive unit 1401 includes the stacked photosensitive doped part 1411, the photosensitive part 14011 and the photosensitive electrode 181. One end of the photosensitive part 14011 is connected to the photosensitive doped part 1411, and the other end of the photosensitive part 14011 is connected to the photosensitive electrode 181. The material of the photosensitive part 14011 includes but is not limited to amorphous silicon (a-Si). When external light is irradiated on the photosensitive part 14011, a photocurrent can be generated between the photosensitive doped part 1411 and the photosensitive electrode 181.

[0064] Specifically, the photosensitive unit 1401 may be a PIN structure; specifically, the photosensitive unit 1401 includes an N-type layer, an I-type layer located on the N-type layer, and a P-type layer located on the I-type layer.

[0065] Among them, the photosensitive doped part can be used as an N-type layer, and the material of the photosensitive doped part is N-type doped polysilicon, which provides carrier electrons and helps to form an electric field; the photosensitive part 14011 can be used as an I-type layer, and the material of the photosensitive part 14011 can be amorphous silicon, which is an intrinsic semiconductor and has good light absorption ability. Under light, the photosensitive part 14011 can absorb photons and generate electron-hole pairs; the photosensitive electrode 181 can be used as a P-type layer, and the material of the photosensitive electrode 181 can be indium tin oxide (ITO). The photosensitive electrode 181 can provide holes to help establish a built-in electric field, and light can pass through the photosensitive electrode 181 into the photosensitive part 14011, thereby realizing the photoelectric effect.

[0066] It can be understood that this embodiment integrates the photosensitive element into the display panel 1, thereby realizing the under-screen color temperature sensing and self-adjustment functions. Compared with the solution of external photosensitive elements in the related art, it has the effects of high integration and low cost, and saves structural space.

[0067] Please continue to combine Figure 1 and Figure 2 In one embodiment, the first metal layer 12 includes a first light-shielding portion 121, and the first light-shielding portion 121 is arranged corresponding to the photosensitive unit 1401, and the orthographic projection of the photosensitive unit 14011 on the substrate 11 is located within the orthographic projection of the first light-shielding portion 121 on the substrate 11, thereby avoiding unnecessary light from irradiating the photosensitive unit 1401, reducing the influence of light interference on the photosensitive unit 14011, and thereby improving the accuracy and stability of the photoelectric signal.

[0068] Specifically, the first shading portion 121 is connected to a constant voltage source; it should be noted that the photosensitive unit 1401 can integrate the functions of an ambient light sensor and a color temperature sensor, and has the advantages of fast response speed, simple structure and high precision. However, in actual working process, the floating metal inside the display panel 1 may interfere with the reading of the photosensitive unit 1401, resulting in a decrease in the accuracy of the sensor measurement.

[0069] It can be understood that this embodiment ensures that the potential of the first light shielding portion 121 is always in a stable state by directly connecting the first light shielding portion 121 to a constant voltage source. The constant voltage source provides a fixed voltage to ensure that the first light shielding portion 121 is not disturbed by external signals during operation and does not float, thereby effectively preventing the potential of the first light shielding portion 121 from drifting or changing (i.e. floating). Since light interference is effectively controlled, the photosensitive unit 1401 can sense the light signal more accurately and convert it into an electrical signal, thereby improving the efficiency and stability of the photosensitive unit 1401.

[0070] Please continue to combine Figure 1 and Figure 2 In one embodiment, the first electrode 1451 is connected to the first light shielding portion 121 , one end of the second electrode 1452 is connected to the photosensitive doping portion 1411 , and the other end of the second electrode 1452 is connected to the control unit 1402 .

[0071] Specifically, the first electrode 1451 is connected to the first light shielding portion 121 and a constant voltage (such as a COM signal) is applied to the first light shielding portion 121, so that the first light shielding portion 121 can maintain a constant voltage state, which can effectively avoid the electrical noise problem caused by the floating potential (floating) of the first light shielding portion 121, thereby reducing the interference to the photosensitive unit 1401, and helping to improve the accuracy and stability of the photoelectric signal.

[0072] At the same time, by connecting the photosensitive doped part 1411 to the second electrode 1452 and connecting the second electrode 1452 to the control unit 1402, a more precise current flow path can be achieved, thereby improving the accuracy of the photoelectric signal. The connection between the photosensitive doped part 1411 and the control unit 1402 helps to maintain a stable photocurrent output, thereby ensuring that the photosensitive unit 1401 can correctly detect and respond to changes in external light without affecting the measurement accuracy due to unnecessary potential interference.

[0073] It should be noted that the technical solution proposed in this embodiment is applicable to the application scenario where the display panel 1 integrates photoelectric sensors. In order to better illustrate the innovation of this embodiment, this embodiment uses the constant voltage as the COM signal as an example to illustrate the technical solution of this embodiment.

[0074] Please continue to combine Figure 1 and Figure 2 In one embodiment, the control unit 1402 is connected to the photosensitive unit 1401, and the control unit 1402 can control the switch state and other states of the photosensitive unit 1401; wherein, the control unit 1402 can be a thin film transistor structure, and the control unit 1402 includes a semiconductor part 1412, a gate insulating layer 142, a gate 1431, an interlayer insulating layer 144, the third electrode 1453 and the fourth electrode 1454, one end of the third electrode 1453 is connected to the first doped part 14121, the other end of the third electrode 1453 is connected to the second electrode 1452, and the fourth electrode 1454 is connected to the second doped part 14122.

[0075] It should be noted that one of the third electrode 1453 and the fourth electrode 1454 can be a source, and the other of the third electrode 1453 and the fourth electrode 1454 can be a drain, and the specific positions of the source and the drain can be selected according to design requirements, so that this embodiment has a high degree of flexibility.

[0076] Furthermore, the third electrode 1453 may be connected to the pixel electrode 182 , and the control unit 1402 may control the current and voltage changes of the pixel electrode 182 through current regulation of the source and the drain, thereby affecting the display effect.

[0077] The first metal layer 12 also includes a second shading portion 122, and the second shading portion 122 is spaced apart from the first shading portion 121. The second shading portion 122 is arranged corresponding to the control unit 1402. The orthographic projection of the semiconductor portion 1412 on the substrate 11 is located at the orthographic projection of the second shading portion 122 on the substrate 11. The second shading portion 122 is used to prevent light from irradiating the semiconductor portion 1412 to prevent affecting the device performance of the semiconductor portion 1412.

[0078] It can be understood that in this embodiment, by setting the first metal layer 12 to include a first light-shielding portion 121 and a second light-shielding portion 122, the semiconductor layer 141 includes a photosensitive doping portion 1411 and a semiconductor portion 1412 that are spaced apart, and the second metal layer 145 includes a first electrode 1451, a second electrode 1452, a third electrode 1453 and a fourth electrode 1454, thereby reducing the process difficulty of the display panel 1, saving manufacturing costs, and improving production efficiency and yield rate.

[0079] At the same time, the structural design of the display panel 1 provided in this embodiment simplifies the hierarchical relationship, and integrates the photosensitive unit 1401 and the control unit 1402 in the same thin film transistor layer 14. By directly setting the photosensitive unit 1401 in the structure of the display panel 1, the photosensitive unit 1401 can directly respond to external light without the need for additional photosensitive elements, thereby reducing the need for external photosensitive elements, which is beneficial to the integration of the equipment and saves space.

[0080] Please continue to combine Figure 1 and Figure 2; In one embodiment, the semiconductor portion 1412 also includes a third doping portion 14124 and a fourth doping portion 14125, the third doping portion 14124 is arranged between the channel portion 14123 and the first doping portion 14121; the fourth doping portion 14125 is arranged between the channel portion 14123 and the second doping portion 14122; wherein the first doping portion 14121 and the second doping portion 14122 have the same doping concentration, the third doping portion 14124 and the fourth doping portion 14125 have the same doping concentration, and the doping concentration of the third doping portion 14124 is less than the doping concentration of the first doping portion 14121.

[0081] It can be understood that, in this embodiment, by providing the third doping portion 14124 and the fourth doping portion 14125 and making their doping concentrations lower than those of the first doping portion 14121 and the second doping portion 14122, the doping concentration gradient near the channel portion 14123 is reduced, the mobility reduction problem caused by excessively high doping concentration is alleviated, and the current transmission efficiency and response speed are improved.

[0082] Specifically, since the third doping portion 14124 is arranged between the channel portion 14123 and the first doping portion 14121, and the fourth doping portion 14125 is arranged between the channel portion 14123 and the second doping portion 14122, the third doping portion 14124 and the fourth doping portion 14125 can both serve as transition portions, which help to form a smooth current path, reduce current spikes in the switching state, improve the conduction characteristics of the control unit 1402, and avoid current mutations.

[0083] At the same time, the doping concentrations of the first doping portion 14121 and the second doping portion 14122 are the same, and the doping concentrations of the third doping portion 14124 and the fourth doping portion 14125 are the same, thereby ensuring uniform distribution of current in the channel portion 14123, avoiding the problem of unbalanced current distribution caused by uneven doping, and improving the performance consistency and stability of the semiconductor portion 1412.

[0084] Please continue to combine Figure 1 and Figure 2 In one embodiment, the buffer layer 13 is disposed between the first metal layer 12 and the semiconductor layer 141; the gate insulating layer 142 is disposed between the semiconductor layer 141 and the third metal layer 143; the interlayer insulating layer 144 is disposed on a side of the third metal layer 143 away from the gate insulating layer 142, thereby ensuring that no short circuit occurs between different conductive parts, making signal transmission more stable, and thereby improving the overall reliability and performance of the display panel 1.

[0085] The display panel 1 is provided with a first through hole 10 and a second through hole 20, the first electrode 1451 passes through the first through hole 10 to be connected to the first light shielding portion 121, and the first through hole 10 passes through the interlayer insulating layer 144, the gate insulating layer 142 and at least a portion of the buffer layer 13, one end of the second electrode 1452 passes through the second through hole 20 to be connected to the photosensitive doping portion 1411, and the second through hole 20 passes through the interlayer insulating layer 144, the gate insulating layer 142, the photosensitive doping portion 1411 and the buffer layer 13, and the other end of the second electrode 1452 is connected to the third electrode 1453.

[0086] Furthermore, the display panel 1 is also provided with a sixth through hole 60 and a seventh through hole 70, the third electrode 1453 is connected to the first doped portion 14121 through the sixth through hole 60, and the sixth through hole 60 penetrates the interlayer insulating layer 144, the gate insulating layer 142, the first doped portion 14121 and the buffer layer 13, the fourth electrode 1454 is connected to the second doped portion 14122 through the seventh through hole 70, and the seventh through hole 70 penetrates the interlayer insulating layer 144, the gate insulating layer 142, the second doped portion 14122 and the buffer layer 13.

[0087] It can be understood that, by setting the second through hole 20 to pass through the photosensitive doped part 1411, the second electrode 1452 passes through the photosensitive doped part 1411, and the photosensitive doped part 1411 is arranged around the second electrode 1452, the sixth through hole 60 passes through the first doped part 14121, the third electrode 1453 passes through the first doped part 14121, and the first doped part 14121 is arranged around the third electrode 1453, the seventh through hole 70 passes through the first doped part 14121, the fourth electrode 1454 passes through the second doped part 14122, and the second doped part 14122 is arranged around the fourth electrode 1454, thereby optimizing the isolation between the electrodes, preventing unnecessary electrical interference or short circuit between the electrodes, and improving their stability.

[0088] At the same time, it can also enhance the electrical connection stability between the electrode and the doped part, increase the contact area between the electrode and the doped part, and avoid the contact instability problem caused by local poor contact or mismatch of electrode morphology.

[0089] Please continue to combine Figure 1 and Figure 2In one embodiment, the orthographic projection of the second shading portion 122 on the substrate 11 covers the orthographic projection of the semiconductor portion 1412 on the substrate 11, and the orthographic projection of the second shading portion 122 on the substrate 11 covers the orthographic projection of the third doping portion 14124 on the substrate 11 and the orthographic projection of the fourth doping portion 14125 on the substrate 11.

[0090] Specifically, the second light-shielding portion 122 is arranged corresponding to the channel region and the lightly-doped region, and the second light-shielding portion 122 is a semi-enclosed structure, which only covers the channel portion 14123, the third doped portion 14124 and the fourth lightly-doped portion, thereby avoiding the influence of light on these regions; it can be understood that the doping concentrations of the third doped portion 14124 and the fourth lightly-doped portion are relatively low, and usually have a greater influence on current control and mobility during operation, so the design of the second light-shielding portion 122 can ensure that these regions are in a stable electrical state, thereby improving the stability and performance of the display panel 1.

[0091] At the same time, compared with the full shading design in the related art (the shading layer completely covers the semiconductor part 1412), the semi-enclosed design can simplify the manufacturing process of the second shading part 122, improve manufacturing efficiency and reduce costs, and ensure that the shading effect is not affected.

[0092] Please continue to combine Figure 1 and Figure 2 In one embodiment, the display panel 1 is further provided with a third through hole 30, in which at least part of the photosensitive portion 14011 is filled, and the third through hole 30 penetrates the interlayer insulating layer 144 and at least part of the gate insulating layer 142. Thus, the photosensitive portion 14011 is prevented from contacting with other film layers, effectively improving electrical isolation, preventing possible electrical short circuit or leakage, and improving the electrical safety and reliability of the display panel 1.

[0093] The size of the side of the photosensitive portion 14011 away from the substrate 11 is greater than the size of the side of the third through hole 30 away from the substrate 11; specifically, the side of the photosensitive portion 14011 away from the substrate 11 protrudes from the surface of the side of the interlayer insulating layer 144 away from the substrate 11, that is, the distance between the surface of the side of the photosensitive portion 14011 away from the substrate 11 and the substrate 11 is greater than the distance between the surface of the side of the interlayer insulating layer 144 away from the substrate 11 and the substrate 11, so that the photosensitive portion 14011 and the third through hole 30 are more stable when in contact,

[0094] It should be noted that the dimensions mentioned in this embodiment are the width of the photosensitive portion 14011 in the first direction X, the width of the fifth through hole 50 in the first direction X, and the first direction is Figure 2 The X direction in .

[0095] Furthermore, the first through hole 10, the second through hole 20, the third through hole 30, the sixth through hole 60 and the seventh through hole 70 can be processed at one time through a mask, making the manufacturing process simpler and being able to efficiently realize the correct connection of multiple electrodes, reducing the complexity of multiple processes; at the same time, it helps to maintain the production consistency of the display panel 1, reduce the process steps, reduce the production complexity and cost, ensure the performance and structural stability, and improve the product qualification rate.

[0096] Please continue to combine Figure 1 and Figure 2 In one embodiment, the display panel 1 further comprises a protective layer 19, the protective layer 19 being arranged on a side of the photosensitive portion 14011 away from the photosensitive doping portion 1411, the protective layer 19 being provided with a fourth through hole 40, the fourth through hole 40 penetrating the protective layer 19; the flat layer 15 being arranged on a side of the second metal layer 145 away from the interlayer insulating layer 144, the flat layer 15 being provided with a fifth through hole 50, the fifth through hole 50 penetrating at least a portion of the flat layer 15, and the fifth through hole 50 being connected to the fourth through hole 40; the first transparent electrode layer 18 being arranged on a side of the flat layer 15 away from the second metal layer 145, the first transparent electrode layer 18 comprising the photosensitive electrode 181, the photosensitive electrode 181 passing through the fourth through hole 40 and the fifth through hole 50 to connect to the photosensitive portion 14011.

[0097] The material of the protective layer 19 includes but is not limited to silicon nitride (SiNx), silicon dioxide (SiOx), silicon oxynitride (SiONx) or a combination structure of the above film layers, and the material of the flat layer 15 includes but is not limited to organic photoresist materials; it can be understood that by setting the protective layer 19, the photosensitive part 14011 can be effectively prevented from being damaged by the external environment, and at the same time, panel failure caused by pollution or electrical short circuit can be avoided. Setting the flat layer 15 not only helps to improve the overall flatness of the panel, but also can further optimize the uniformity of subsequent layers, thereby improving the quality and consistency of the display panel 1.

[0098] At the same time, by providing the fourth through hole 40 and the fifth through hole 50 and ensuring that the fifth through hole 50 is connected to the fourth through hole 40, the photosensitive portion 14011 and the photosensitive electrode 181 can be accurately docked to avoid docking errors and ensure stable electrical performance.

[0099] Please combine Figure 1 , Figure 2 , Figure 3 and Figure 4 ;in, Figure 3 For the embodiment of this application Figure 1 The enlarged schematic diagram of the corresponding B area; Figure 4 The embodiments of the present application provide Figure 3 An enlarged schematic diagram of the corresponding fan-out area.

[0100] It should be noted that in the manufacturing process of the display panel, in order to pursue a narrower bezel design, the size of the lower bezel needs to be compressed. The display panel usually includes a display area and a non-display area. The non-display area can also be called a bezel area. The non-display area corresponding to the lower bezel can be divided into a binding area and a fan-out area arranged between the binding area and the display area. The fan-out area is used to arrange fan-out routing to lead the routing in the display area to the non-display area and connect with the chip in the non-display area so that the chip can transmit signals to the display area.

[0101] In the related art, the connection wiring between the signal lines and the electrode layers in the fan-out area of ​​the display panel is usually complicated, resulting in a panel frame that is too wide, affecting the display effect and aesthetics, especially when the frame design is not compact enough, affecting the overall size and appearance of the display panel.

[0102] In one embodiment, the display panel 1 includes a display area 1000 and a non-display area 2000 arranged on at least one side of the display area 1000; specifically, the display panel 1 includes the display area 1000 and a binding terminal 300 located on one side of the display area 1000, the binding terminal 300 is located in the non-display area 2000, and the binding terminal 300 can be connected to an external circuit to transmit a signal input by the external circuit to the display panel 1, thereby driving the display panel to display a picture; wherein the non-display area 2000 includes a fan-out area 2100, and the fan-out area 2100 is arranged at one end of the non-display area 2000 close to the display area 1000.

[0103] The display panel 1 also includes a fan-out portion 211, which is arranged on one side of the substrate 11, and the fan-out portion 211 is located in the fan-out area 2100, and the fan-out portion 211 includes a first fan-out line 123, a second fan-out line 1432 and a third fan-out line 1455 that are stacked and insulated; wherein the first metal layer 12 includes a first fan-out line 123, the third metal layer 143 includes a second fan-out line 1432, and the second metal layer 145 includes the third fan-out line 1455, and at least two of the first fan-out line 123, the second fan-out line 1432 and the third fan-out line 1455 are overlapped.

[0104] It can be understood that this embodiment arranges the fan-out lines (the first fan-out line 123, the second fan-out line 1432 and the third fan-out line 1455) on different metal layers in an overlapping manner and optimizes the distribution of the fan-out lines in the fan-out area 2100, so that more fan-out lines can be arranged in the same space, thereby reducing the area of ​​the non-display area 2000, which is beneficial to improving the high resolution of the display panel 1, while meeting the design requirements of a narrow frame, and providing the display panel 1 with a larger effective display area.

[0105] At the same time, by setting the first light shading portion 121, the second light shading portion 122 and the first fan-out line 123 on the same layer, setting the gate 1431 and the second fan-out line 1432 on the same layer, and setting the first electrode 1451, the second electrode 1452, the third electrode 1453, the fourth electrode 1454 and the third fan-out line 1455 on the same layer, the number of film layers of the display panel 1 can be reduced, the stacking structure can be optimized, and the manufacturing process of the display panel 1 can be simplified, which can effectively reduce production costs and reduce material consumption.

[0106] Further, the first fan-out line 123 and the second fan-out line 1432 are at least partially overlapped; and / or, the third fan-out line 1455 and the second fan-out line 1432 are at least partially overlapped; and / or, the first fan-out line 123 and the third fan-out line 1455 are at least partially overlapped.

[0107] It should be noted that the technical solution proposed in this embodiment is suitable for application scenarios with a narrow frame of the display panel 1. In order to better illustrate the innovation of this embodiment, this embodiment takes the first fan-out line 123 and the second fan-out line 1432 as at least partially overlapping, the third fan-out line 1455 and the second fan-out line 1432 as at least partially overlapping, and the first fan-out line 123 and the third fan-out line 1455 as at least partially overlapping as an example to illustrate the technical solution of this embodiment.

[0108] It can be understood that by making the first fan-out line 123 and the second fan-out line 1432 at least partially overlap, the third fan-out line 1455 and the second fan-out line 1432 at least partially overlap, and the first fan-out line 123 and the third fan-out line 1455 at least partially overlap, the space occupied by the fan-out lines can be effectively reduced, thereby making the fan-out line layout more compact, thereby improving the overall space utilization efficiency of the display panel 1.

[0109] Please combine Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 ;in, Figure 5The embodiments of the present application provide Figure 4 Schematic diagram of the cross section corresponding to C-Cˋ in the figure.

[0110] In one embodiment, the second electrode 1452 layer also includes a connecting portion 1456, and the connecting portion 1456 is located in the fan-out area 2100. One end of the connecting portion 1456 is connected to the first fan-out line 123, and the other end of the connecting portion 1456 is connected to the second fan-out line 1432, so that the connecting portion 1456 can serve as a transition bridge for electrical connection to ensure a stable connection between the first fan-out line 123 and the second fan-out line 1432; at the same time, the complex crossing of the fan-out lines in the fan-out area 2100 is avoided, the space occupied by the fan-out lines is reduced, and the wiring of the display panel 1 is more simple and compact.

[0111] Specifically, the display panel 1 is further provided with a tenth through hole 100 and an eleventh through hole 110, one end of the connecting portion 1456 passes through the tenth through hole 100 and is connected to the first fan-out line 123, the tenth through hole 100 passes through the interlayer insulating layer 144, the gate insulating layer 142 and at least a portion of the buffer layer 13, the other end of the connecting portion 1456 passes through the eleventh through hole 110 and is connected to the second fan-out line 1432, and the eleventh through hole 110 passes through at least a portion of the interlayer insulating layer 144.

[0112] The first through hole 10, the second through hole 20, the third through hole 30, the sixth through hole 60, the seventh through hole 70, the tenth through hole 100 and the eleventh through hole 110 can be processed at one time through a photomask, which makes the manufacturing process simpler and can efficiently realize the correct connection of multiple electrodes, reducing the complexity of multiple processes.

[0113] Please combine Figure 2 , FIG. 6A to FIG. 6I ;in; FIG. 6A to FIG. 6I Schematic diagram corresponding to each step of the method for manufacturing a display panel provided in an embodiment of the present application.

[0114] In one embodiment, the method for manufacturing the display panel 1 comprises the following steps:

[0115] like Fig. 6A As shown, step S10: forming a first metal layer 12 on a substrate 11, and patterning the first metal layer 12 by an exposure and etching method to form a first light shielding portion 121 and a second light shielding portion 122 that are spaced apart.

[0116] like Figure 6BAs shown, step S20: a buffer layer 13 and a first amorphous silicon (a-Si) are sequentially formed on the first light-shielding portion 121 and the second light-shielding portion 122, and after excimer laser annealing, the first amorphous silicon (a-Si) is converted into polycrystalline silicon (poly-Si), and then the entire surface is doped with boron ions, and the polycrystalline silicon (poly-Si) is patterned by an exposure and etching method to form a photosensitive doping portion 1411 and a semiconductor portion semi-finished product 14120.

[0117] like Figure 6C As shown, step S30: a gate insulating layer 142 and a third metal layer 143 are sequentially formed on the photosensitive doped part 1411, the semiconductor part semi-finished product 14120 and the buffer layer 13, the third metal layer 143 is patterned to form a gate 1431, and a portion of the semiconductor part semi-finished product 14120 is covered by the gate 1431 and the photoresist, and the semiconductor part semi-finished product 14120 not covered by the gate 1431 and the photoresist is heavily doped with phosphorus ions to form a first doped part 14121 and a second doped part 14122, and then the photoresist is torn off, and the portion of the semiconductor part semi-finished product 14120 not covered by the gate 1431 is lightly doped with phosphorus ions to form a third doped part 14124 and a fourth doped part 14125 respectively, and the semiconductor part semi-finished product 14120 covered by the gate 1431 forms a channel part 14123.

[0118] Among them, the first doping part 14121, the third doping part 14124, the channel part 14123, the fourth doping part 14125 and the second doping part 14122 form a semiconductor part 1412; it should be noted that when the part of the semiconductor part semi-finished product 14120 not blocked by the gate 1431 is lightly doped with phosphorus ions to form the third doping part 14124 and the fourth doping part 14125 respectively, the first doping part 14121 and the second doping part 14122 can be blocked by photoresist to ensure the accurate distribution of different doping parts and avoid excessively high or low doping concentration, which will cause the device performance to not meet the requirements.

[0119] like Fig.6D As shown, step S40: an interlayer insulating layer 144 is formed on the gate 1431 and the gate insulating layer 142, and the interlayer insulating layer 144 is patterned by an exposure and etching method to form a first sub-through hole 101, a second sub-through hole 201, a third sub-through hole 601, a fourth sub-through hole 701 and a third through hole 30 that are spaced apart.

[0120] Among them, the first sub-through hole 101 is arranged corresponding to the first light shielding portion 121, and the first sub-through hole 101 penetrates the interlayer insulating layer 144, the gate insulating layer 142 and at least a part of the buffer layer 13; the second sub-through hole 201 exposes part of the photosensitive doped portion 1411, and the second sub-through hole 201 penetrates the interlayer insulating layer 144 and at least a part of the gate insulating layer 142; the third sub-through hole 601 exposes part of the first doped portion 14121, and the third sub-through hole 601 penetrates the interlayer insulating layer 144 and at least a part of the gate insulating layer 142; the fourth sub-through hole 701 exposes part of the second doped portion 14122, and the fourth sub-through hole 701 penetrates the interlayer insulating layer 144 and at least a part of the gate insulating layer 142; the third through hole 30 exposes part of the photosensitive doped portion 1411, and the third through hole 30 penetrates the interlayer insulating layer 144 and at least a part of the gate insulating layer 142.

[0121] like Fig. 6E As shown, step S50: a second amorphous silicon (a-Si) is formed in the third through hole 30, a protective layer 19 is formed on the second amorphous silicon (a-Si), and then the second amorphous silicon (a-Si) is patterned by an exposure and etching method to form a photosensitive portion 14011; at the same time, the interlayer insulating layer 144 is patterned to form a fifth sub-through hole 102, a sixth sub-through hole 202, a seventh sub-through hole 602 and an eighth sub-through hole 702 that are spaced apart.

[0122] At least a portion of the photosensitive portion 14011 is filled in the third through hole 30 , and a side of the photosensitive portion 14011 away from the substrate 11 protrudes from a side surface of the interlayer insulating layer 144 away from the substrate 11 .

[0123] The fifth sub-through hole 102 is arranged corresponding to the first sub-through hole 101, the fifth sub-through hole 102 is connected with the first sub-through hole 101, the fifth sub-through hole 102 exposes a portion of the first light shielding portion 121, and the fifth sub-through hole 102 penetrates a portion of the buffer layer 13, and the first sub-through hole 101 and the fifth sub-through hole 102 form a first through hole 10; the sixth sub-through hole 202 is arranged corresponding to the second sub-through hole 201, the sixth sub-through hole 202 is connected with the second sub-through hole 201, the sixth sub-through hole 202 exposes a portion of the substrate 11, and the sixth sub-through hole 202 penetrates the photosensitive doped portion 1411 and the buffer layer 13, and the second sub-through hole 201 and the sixth sub-through hole 202 form a second through hole 20.

[0124] The seventh sub-through hole 602 is arranged corresponding to the third sub-through hole 601, the seventh sub-through hole 602 is connected to the third sub-through hole 601, the seventh sub-through hole 602 exposes a portion of the substrate 11, and the seventh sub-through hole 602 passes through the first doped portion 14121 and the buffer layer 13, and the third sub-through hole 601 and the seventh sub-through hole 602 form a sixth through hole 60; the eighth sub-through hole 702 is arranged corresponding to the fourth sub-through hole 701, the eighth sub-through hole 702 is connected to the fourth sub-through hole 701, the eighth sub-through hole 702 exposes a portion of the substrate 11, and the eighth sub-through hole 702 passes through the second doped portion 14122 and the buffer layer 13, and the fourth sub-through hole 701 and the eighth sub-through hole 702 form a seventh through hole 70.

[0125] like Fig. 6F As shown, step S60: forming a second metal layer 145 on the interlayer insulating layer 144, patterning the second metal layer 145 by an exposure and etching method to form a first electrode 1451, a second electrode 1452, a third electrode 1453 and a fourth electrode 1454 arranged at intervals, the first electrode 1451 passes through the first through hole 10 to be connected to the first light shielding portion 121, one end of the second electrode 1452 passes through the second through hole 20 to be connected to the photosensitive doped portion 1411, the third electrode 1453 passes through the sixth through hole 60 to be connected to the first doped portion 14121, and the fourth electrode 1454 passes through the seventh through hole 70 to be connected to the second doped portion 14122; wherein the semiconductor portion 1412, the gate insulating layer 142, the gate 1431, the interlayer insulating layer 144, the third electrode 1453 and the fourth electrode 1454 form a control unit 1402.

[0126] The first electrode 1451 is connected to the first light shielding portion 121 and applies a constant voltage (such as a COM signal) to enable the first light shielding portion 121 to maintain a constant voltage state.

[0127] like Figure 6G As shown, step S70: a flat layer 15 is formed on the first electrode 1451, the second electrode 1452, the third electrode 1453, the fourth electrode 1454 and the interlayer insulating layer 144, and the flat layer 15 is patterned by an exposure and development method to form a fifth through hole 50 and an eighth through hole 80, wherein the fifth through hole 50 exposes a portion of the protective layer 19, and the fifth through hole 50 penetrates a portion of the flat layer 15, and the eighth through hole 80 exposes a portion of the third electrode 1453, and the eighth through hole 80 penetrates a portion of the flat layer 15.

[0128] like Figure 6HAs shown, step S80: forming a second transparent electrode layer 16 on the planar layer 15, and patterning the second transparent electrode layer 16 to form a common electrode 161.

[0129] like Fig.6I As shown, step S90: a passivation layer 17 is formed on the planar layer 15, the protective layer 19 and the pixel electrode 182, and the planar layer 15 is patterned by an exposure and development method to form a fourth through hole 40 and a ninth through hole 90, wherein the fourth through hole 40 exposes a portion of the photosensitive portion 14011, the fourth through hole 40 is connected to the fifth through hole 50, and the fourth through hole 40 passes through the passivation layer 17 and the protective layer 19, the ninth through hole 90 exposes a portion of the third electrode 1453, the ninth through hole 90 is connected to the eighth through hole 80, and the ninth through hole 90 passes through the passivation layer 17.

[0130] like Figure 2 As shown, step S100: forming a first transparent electrode layer 18 on the passivation layer 17 and the photosensitive portion 14011, patterning the first transparent electrode layer 18 to form a pixel electrode 182 and a photosensitive electrode 181, the photosensitive electrode 181 passes through the fourth through hole 40 and the fifth through hole 50 to connect to the photosensitive portion 14011, and the pixel electrode 182 passes through the eighth through hole 80 and the ninth through hole 90 to connect to the third electrode 1453; wherein the photosensitive electrode 181, the photosensitive portion 14011 and the photosensitive doping portion 1411 form a photosensitive element.

[0131] It can be understood that this embodiment ensures that the potential of the first light shielding portion 121 is always in a stable state by directly connecting the first light shielding portion 121 to a constant voltage source. The constant voltage source provides a fixed voltage to ensure that the first light shielding portion 121 is not disturbed by external signals during operation and does not float, thereby effectively preventing the potential of the first light shielding portion 121 from drifting or changing (i.e. floating). Since light interference is effectively controlled, the photosensitive unit 1401 can sense the light signal more accurately and convert it into an electrical signal, thereby improving the efficiency and stability of the photosensitive unit 1401.

[0132] See also Figure 7 , is a schematic diagram of the structure of the display device provided in an embodiment of the present application.

[0133] This embodiment further provides a display device 2 , which includes the display panel 1 described in any one of the above embodiments.

[0134] It can be understood that the display panel 1 has been described in detail in the above embodiments, and will not be repeated here.

[0135] The display device 2 may further include a housing 2A, and the housing 2A is integrated with the display panel 1 to provide support, fixation and protection for the display panel 1 .

[0136] In specific applications, the display device 2 can be at least one of a smart phone, a tablet computer, a mobile phone, a video phone, an e-book reader, a desktop computer, a laptop, a netbook, a workstation, a server, a personal digital assistant, a portable media player, an MP3 player, a mobile medical machine, a camera, a game console, a digital camera, a car navigation system, an electronic billboard, an ATM or a wearable device, etc., which have a display function.

[0137] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0138] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: substrate; A first metal layer, disposed on the substrate, the first metal layer comprising a first light shielding portion; A photosensitive unit is provided on a side of the first light shielding portion away from the substrate, the photosensitive unit comprising a stacked photosensitive doped portion, a photosensitive portion and a photosensitive electrode, one end of the photosensitive portion is connected to the photosensitive doped portion, and the other end of the photosensitive portion is connected to the photosensitive electrode; The orthographic projection of the first light shielding portion on the substrate covers the orthographic projection of the photosensitive portion on the substrate, and the first light shielding portion is connected to a constant voltage source.

2. The display panel according to claim 1, characterized in that: The display panel further includes a control unit, and the control unit is spaced apart from the photosensitive unit; The display panel also includes a second metal layer, which is arranged on a side of the first light-shielding portion away from the substrate, and the second metal layer includes a first electrode and a second electrode arranged at intervals, the first electrode is connected to the first light-shielding portion, one end of the second electrode is connected to the photosensitive doping portion, and the other end of the second electrode is connected to the control unit.

3. The display panel according to claim 2, characterized in that: The display panel further includes a thin film transistor layer, the thin film transistor layer includes the control unit and the photosensitive unit, and the thin film transistor layer includes: A semiconductor layer, disposed on the substrate, the semiconductor layer comprising the photosensitive doped portion and the semiconductor portion arranged at intervals, the semiconductor portion comprising a first doped portion and a second doped portion, and a channel portion located between the first doped portion and the second doped portion; A third metal layer is disposed on a side of the semiconductor layer away from the substrate, the third metal layer includes a gate, and the gate is disposed corresponding to the channel portion; The first metal layer includes a second shading portion, the second shading portion is arranged corresponding to the semiconductor portion, the second metal layer includes a third electrode and a fourth electrode, the third electrode is connected to the first doped portion, and the fourth electrode is connected to the second doped portion.

4. The display panel according to claim 3, characterized in that: The display panel further includes: a buffer layer, disposed between the first metal layer and the semiconductor layer; A gate insulating layer, disposed between the semiconductor layer and the third metal layer; an interlayer insulating layer, disposed on a side of the third metal layer away from the gate insulating layer; The display panel is provided with a first through hole and a second through hole, the first electrode is connected to the first light shielding portion through the first through hole, and the first through hole penetrates the interlayer insulating layer, the gate insulating layer and at least a portion of the buffer layer, one end of the second electrode is connected to the photosensitive doped portion through the second through hole, and the second through hole penetrates the interlayer insulating layer, the gate insulating layer, the photosensitive doped portion and the buffer layer, and the other end of the second electrode is connected to the third electrode.

5. The display panel according to claim 4, characterized in that: The display panel is further provided with a third through hole, at least part of the photosensitive portion is filled in the third through hole, and the third through hole penetrates the interlayer insulating layer and at least part of the gate insulating layer; Wherein, a dimension of a side of the photosensitive portion away from the substrate is greater than a dimension of a side of the third through hole away from the substrate.

6. The display panel according to claim 5, characterized in that: The display panel further includes: A protective layer is provided on a side of the photosensitive portion away from the photosensitive doped portion, the protective layer is provided with a fourth through hole, and the fourth through hole penetrates the protective layer; a planar layer, disposed on a side of the second metal layer away from the interlayer insulating layer, the planar layer being provided with a fifth through hole, the fifth through hole penetrating at least a portion of the planar layer, and the fifth through hole being connected to the fourth through hole; The first transparent electrode layer is disposed on a side of the planar layer away from the second metal layer. The first transparent electrode layer includes the photosensitive electrode. The photosensitive electrode passes through the fourth through hole and the fifth through hole to connect with the photosensitive portion.

7. The display panel according to claim 3, characterized in that: The semiconductor unit further includes: a third doping portion, disposed between the channel portion and the first doping portion; a fourth doping portion, disposed between the channel portion and the second doping portion; Wherein, the doping concentrations of the first doping portion and the second doping portion are the same, the doping concentrations of the third doping portion and the fourth doping portion are the same, and the doping concentration of the third doping portion is less than the doping concentration of the first doping portion; The orthographic projection of the second light shielding portion on the substrate covers the orthographic projection of the channel portion on the substrate, the orthographic projection of the third doping portion on the substrate, and the orthographic projection of the fourth doping portion on the substrate.

8. The display panel according to claim 3, characterized in that: The display panel includes a display area and a non-display area arranged on at least one side of the display area; The display panel further includes a fan-out portion, the fan-out portion is disposed on one side of the substrate, the fan-out portion is located in the non-display area, and the fan-out portion includes a first fan-out line, a second fan-out line, and a third fan-out line that are stacked and insulated; The first metal layer includes a first fan-out line, the second metal layer includes the second fan-out line, the third metal layer includes a third fan-out line, and at least two of the first fan-out line, the second fan-out line and the third fan-out line are overlapped.

9. The display panel according to claim 8, characterized in that: The first fan-out line and the third fan-out line are at least partially overlapped; and / or, the second fan-out line and the third fan-out line are at least partially overlapped; and / or, the first fan-out line and the second fan-out line are at least partially overlapped.

10. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 9.

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