One-time programmable memory device

Abstract

A one-time programmable (OTP) memory device includes an active region and a gate electrode layer. The active region includes a channel region having a channel layer and source / drain regions disposed on opposite sides of the channel region in a Y direction. The gate electrode layer extends in the X direction and surrounds the channel layer. A first thickness of the gate electrode layer from a first edge of the first end portion of the gate electrode layer to the channel layer in the X direction is equal to a second thickness of the gate electrode layer from a second edge of the second end portion of the gate electrode layer to the channel layer in the X direction. The first thickness is different from the second thickness after the first end is connected to a first voltage and the second end is connected to a second voltage different from the first voltage.

Description

Technical Field

[0001] The present invention relates to a one-time-programmable (OTP) memory device, and more particularly to an OTP memory device having a new OTP programming mechanism. Background Art

[0002] One-time programmable memory has been developed. An OTP memory device is a one-time programmable non-volatile memory that can be programmed once. When an OTP memory cell in the OTP memory device is programmed, the storage state of the OTP memory cell is determined, and the storage state of the OTP memory cell cannot be modified. Therefore, OTP memory devices are often used in security applications such as secure key storage, device ID, and code storage.

[0003] However, while existing technologies for anti-fuse OTP memory devices have generally been adequate for their intended purposes, they are not satisfactory in every aspect. Summary of the invention

[0004] The present invention provides a one-time programmable (OTP) memory device. The OTP memory device includes a first active region, a first gate dielectric layer, and a first gate electrode layer. The first active region includes a first channel region having a first channel layer and a first source / drain region disposed on opposite sides of the first channel region in the Y direction. The first source / drain region has a first source / drain feature electrically connected to the first channel layer. The first gate dielectric layer surrounds the first channel layer. The first gate electrode layer extends in the X direction and surrounds the first channel layer and the first gate dielectric layer. The first thickness of the first gate electrode layer is equal to the second thickness of the first gate electrode layer. The first thickness is from the first edge of the first end of the first gate electrode layer to the first channel layer in the X direction, the second thickness is from the second edge of the second end of the first gate electrode layer to the first channel layer in the X direction, and the logic state of the OTP memory device is in a first logic state. In a first programming operation of the OTP memory device, after the first end is connected to a first voltage and the second end is connected to a second voltage different from the first voltage, the first thickness is different from the second thickness, and the logic state of the OTP memory device is in a second logic state different from the first logic state.

[0005] The present invention provides a one-time programmable (OTP) memory device. The OTP memory device includes a first memory cell. The first memory cell includes a first active region and a first gate structure. The first active region includes a first channel region having a first channel layer and a first source / drain region disposed on opposite sides of the first channel region in the Y direction. The first source / drain region has a first source / drain feature electrically connected to the first channel layer. The first gate structure extends in the X direction and joins the first active region to construct a first transistor. Before a first programming operation of the OTP memory device, the first transistor has a first threshold voltage, and the logic state of the OTP memory device is in a first logic state. In the first programming operation of the OTP memory device, a first end of the first gate structure is connected to a first voltage, and a second end of the first gate structure is connected to a second voltage different from the first voltage, so that a programming current is generated along the first gate structure. The voltage difference between the first voltage and the second voltage is greater than an electromigration threshold. After the first programming operation of the OTP memory device, the first transistor has a second threshold voltage different from the first threshold voltage, and the logic state of the OTP memory device is in a second logic state different from the first logic state. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to make the description of the present invention include the above examples, other advantages and features, the principles briefly described above will be described in more detail through specific examples in the accompanying drawings. It should be understood that the drawings shown here are only examples of the present invention and cannot limit the scope of the present invention. The principles of the present invention are described and explained with additional features and details through the accompanying drawings.

[0007] Figure 1 A top view (or layout) of an OTP memory device having an OTP memory cell is shown for some embodiments of the present invention;

[0008] Figure 2A Some embodiments of the present invention show that before the OTP memory device is programmed, Figure 1 An XZ cross-sectional view of an OTP memory device having an OTP memory cell along a line segment AA′, wherein the OTP memory cell has a FinFET structure;

[0009] Figure 2B Some embodiments of the present invention show that after the OTP memory device is programmed, the Figure 1 An XZ cross-sectional view of an OTP memory device having an OTP memory cell along a line segment AA′, wherein the OTP memory cell has a FinFET structure;

[0010] Figure 2CSome embodiments of the present invention show that after the OTP memory device is programmed, the Figure 1 An XZ cross-sectional view of an OTP memory device having an OTP memory cell along a line segment AA′, wherein the OTP memory cell has a FinFET structure;

[0011] Figure 3A Some embodiments of the present invention show that before the OTP memory device is programmed, Figure 1 An XZ cross-sectional view of an OTP memory device having an OTP memory cell along a line segment AA′, wherein the OTP memory cell has a GAA structure;

[0012] Figure 3B Some embodiments of the present invention show that after the OTP memory device is programmed, the Figure 1 An XZ cross-sectional view of an OTP memory device having an OTP memory cell along a line segment AA′, wherein the OTP memory cell has a GAA structure;

[0013] Figure 3C Some embodiments of the present invention show that after the OTP memory device is programmed, the Figure 1 An XZ cross-sectional view of an OTP memory device having an OTP memory cell along a line segment AA′, wherein the OTP memory cell has a GAA structure;

[0014] Figure 4 A top view (or layout) of an OTP memory device having an OTP memory cell is shown for some alternative embodiments of the present invention;

[0015] Figure 5 A top view (or layout) of an OTP memory device having an OTP memory cell is shown for some alternative embodiments of the present invention;

[0016] Fig. 6A Some embodiments of the present invention show that before the OTP memory device is programmed, Figure 5 An XZ cross-sectional view of an OTP memory device having an OTP memory cell along a line segment BB', wherein the OTP memory cell has a FinFET structure;

[0017] Figure 6B Some embodiments of the present invention show that after the OTP memory device is programmed, the Figure 5 An XZ cross-sectional view of an OTP memory device having an OTP memory cell along a line segment BB', wherein the OTP memory cell has a FinFET structure;

[0018] Fig. 7ASome embodiments of the present invention show that before the OTP memory device is programmed, Figure 5 An XZ cross-sectional view of an OTP memory device having an OTP memory cell along a line segment BB', wherein the OTP memory cell has a GAA structure;

[0019] Figure 7B Some embodiments of the present invention show that after the OTP memory device is programmed, the Figure 5 An XZ cross-sectional view of an OTP memory device having an OTP memory cell along a line segment BB', wherein the OTP memory cell has a GAA structure;

[0020] Figure 8 and Fig. 9 A top view (or layout) of an OTP memory device is shown for some alternative embodiments of the present invention.

[0021] Description of symbols 100: one-time programmable memory device

[0022] 102: One-time programmable memory cell

[0023] 103: Transistor

[0024] 104: Active area

[0025] 104ch: Channel area

[0026] 104sd: Source / drain region

[0027] 106: Gate structure

[0028] 106-1:End

[0029] 106-2:End

[0030] 108: Source / drain contact window

[0031] 110: Gate contact window

[0032] A-A': Line segment

[0033] 112:Substrate

[0034] 114: Isolation Features

[0035] 116: Channel layer

[0036] 118: Gate dielectric layer

[0037] 120: Gate electrode layer

[0038] T1: Thickness

[0039] T2: Thickness

[0040] T1':Thickness

[0041] T2':Thickness

[0042] 116-1': Channel layer

[0043] 116-2': Channel Layer

[0044] 116-3': Channel layer

[0045] T3:Thickness

[0046] T4:Thickness

[0047] T3':Thickness

[0048] T4':Thickness

[0049] 200: One-time programmable memory device

[0050] 202-1: One-time programmable memory cell

[0051] 202-2: One-time programmable memory cell

[0052] 202-3: One-time programmable memory cell

[0053] 203-1: Transistor

[0054] 203-2: Transistor

[0055] 203-3: Transistor

[0056] 204: Active Zone

[0057] 206: Gate structure

[0058] 206-1: End

[0059] 206-2:End

[0060] 206-3:End

[0061] 206-4:End

[0062] 208: Source / drain contact window

[0063] 210: Gate contact window

[0064] 300: One-time programmable memory device

[0065] 302: One-time programmable memory cell

[0066] 303-1: Transistor

[0067] 303-2: Transistor

[0068] 304-1: Active Zone

[0069] 304-2: Active Zone

[0070] 304ch: Channel area

[0071] 304sd: Source / drain region

[0072] 306-1: Gate structure

[0073] 306-2: Gate structure

[0074] 306e-1: End

[0075] 306e-2: End

[0076] 306e-3: End

[0077] 306e-4: End

[0078] 307: Gate structure

[0079] 308: Source / drain contact window

[0080] 310: Gate contact window

[0081] B-B': Line segment

[0082] 312:Substrate

[0083] 314: Isolation Features

[0084] 316: Channel layer

[0085] 318: Gate dielectric layer

[0086] 320: Gate electrode layer

[0087] T5:Thickness

[0088] T6:Thickness

[0089] Th1: Thickness

[0090] Th2: Thickness

[0091] T5':Thickness

[0092] T6':Thickness

[0093] Th1': thickness

[0094] Th2': thickness

[0095] 316-1': Channel Layer

[0096] 316-2': Channel Layer

[0097] 316-3': Channel Layer

[0098] T7:Thickness

[0099] T8:Thickness

[0100] Th3: Thickness

[0101] Th4: Thickness

[0102] T7':Thickness

[0103] T8':Thickness

[0104] Th3': thickness

[0105] Th4': thickness

[0106] 400: One-time programmable memory device

[0107] 500: One-time programmable memory device DETAILED DESCRIPTION

[0108] The following disclosure provides many different embodiments or examples to implement the different features of the present invention. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the present invention describes a first feature formed on or above a second feature, it means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the same reference symbols and / or marks may be reused in different examples of the following disclosure. These repetitions are for the purpose of simplification and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

[0109] For the purpose of the detailed description of the present invention, unless specifically denied, singular words include plural words and vice versa. And the word "include" means "include without limitation". In addition, approximation terms such as "about", "almost", "quite", "roughly", etc. can be used in the embodiments of the present invention, and their meanings are such as "at, close to or close to" or "within 3 to 5%" or "within an acceptable manufacturing tolerance" or any logical combination.

[0110] In addition, it is related to spatial terms. For example, "below", "lower", "above", "higher", and similar terms are used to facilitate the description of the relationship between one element or feature and another element or feature in the diagram. In addition to the orientation shown in the accompanying drawings, these spatially related terms are intended to include different orientations of the device in use or operation. For example, if the device in the schematic diagram is reversed, the elements described as "below" or "below..." other elements or features will also become "above" other elements or features. In this way, the exemplary term "below" will cover both upward and downward interpretations. In addition, the device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used here may also be interpreted in the same way.

[0111] The terms used herein are for the purpose of describing specific embodiments only and do not limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, to the extent that the terms "encompass", "comprise", "include", "have", "have", "include" or variations thereof are used in the detailed description and / or claims, these terms are intended to be inclusive in a manner similar to "comprises".

[0112] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. In addition, terms such as those defined in common dictionaries should be interpreted as having the same meaning as in the context of the relevant art and will not be understood as idealized or overly formal unless explicitly so defined herein.

[0113] Now will refer to the accompanying drawings to describe the various aspects of the present invention in more detail. In order to avoid doubt, the X direction, Y direction and Z direction in the accompanying drawings are perpendicular to each other and used consistently. Throughout the present invention, unless otherwise specified, similar reference numerals represent similar features.

[0114] Figure 1 A top view (or layout) of an OTP memory device 100 having an OTP memory cell 102 is shown according to some embodiments of the present invention. Figure 1 The illustrated OTP memory device 100 includes one OTP memory cell 102 , but it should be noted that the OTP memory device 100 may include more OTP memory cells similar to the OTP memory cell 102 arranged in multiple columns and rows into an OTP memory array.

[0115] The OTP memory cell 102 includes an active region 104 extending longitudinally in the Y direction. The active region 104 includes a channel region 104ch and a source / drain region 104sd. Figure 1 As shown, according to some embodiments, the source / drain regions 104sd are disposed on opposite sides of the channel region 104ch in the Y direction. In some embodiments, the active region 104 is disposed over an N-type well (or N-well) or a P-well (or P-well).

[0116] The OTP memory cell 102 further includes a gate structure 106. The gate structure 106 extends longitudinally in the X direction perpendicular to the Y direction to cross the active region 104. Figure 1 The gate structure 106 is disposed in the channel region 104ch (ie, Figures 2A to 3C The active region 104 and the gate structure 106 are configured to provide a transistor for the OTP memory cell 102. For example, the gate structure 106 is coupled to the active region 104 to form the transistor 103.

[0117] The OTP memory cell 102 further includes source / drain contacts 108 and a gate contact 110. Figure 1 As shown, the source / drain contact window 108 is disposed on the source / drain region 104sd of the active region 104, over the source / drain features (not shown) in the source / drain region 104sd, and electrically connected to the source / drain features. The gate contact window 110 is disposed on the gate structure 106 and electrically connected to the gate structure 106. More specifically, the gate contact window 110 is disposed on the ends 106-1 and 106-2 of the gate structure 106, as shown in FIG. Figure 1 shown.

[0118] The source / drain contacts 108 may each include a conductive material, such as Al, Cu, W, Co, Ti, Ta, Ru, Rh, Ir, Pt, Mo, TiN, TiAl, TiAlN, TaN, TaC, combinations thereof, etc., although any suitable material may be deposited using a deposition process, such as sputtering, CVD, electroplating, electroless plating, etc. In some embodiments, the source / drain contacts 108 may each include a single conductive material layer or multiple conductive layers. The material of the gate contact 110 is selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), platinum (Pt), aluminum (Al), copper (Cu), other conductive materials, or combinations thereof.

[0119] In some embodiments, the transistor 103 in the OTP memory cell 102 may also be a fin field-effect transistor (FinFET). Figure 2A Some embodiments according to the present invention show that before an OTP memory device is programmed, Figure 1 FIG. 1 is an XZ cross-sectional view of an OTP memory device 100 having an OTP memory cell 102 along a line segment AA′, wherein the OTP memory cell 102 has a FinFET structure. Figure 2A As shown, in the case where the transistor 103 in the OTP memory cell 102 is a FinFET, the OTP memory cell 102 further includes a substrate 112 over which various features are formed, such as the gate structure 106. The substrate 112 may include a semiconductor material, such as bulk silicon (Si).

[0120] The OTP memory cell 102 further includes an isolation feature 114 over the substrate 112 and isolating the active region 104 from other active regions (not shown).

[0121] like Figure 1 and Figure 2A As shown, in the case where the transistor 103 in the OTP memory cell 102 is a FinFET, the OTP memory cell 102 further includes a channel layer 116 in the channel region 104ch of the active region 104. According to some embodiments, the channel layer 116 is above the substrate 112 and protrudes from the substrate 112. In addition, the channel layer 116 extends from the substrate 112 in the Z direction. In some embodiments, the channel layer 116 is between the isolation features 114 in the X direction, such as Figure 2AAs shown. In some aspects, the isolation feature 114 is around the channel layer 116. In some embodiments, the channel layer 116 is formed by the substrate 112. Although one channel layer 116 is shown in the OTP memory cell 102, there can be another suitable number of nanostructures in the transistor 103 in the OTP memory cell 102. For example, there can be 2 to 3 channel layers 116 in one transistor.

[0122] In some embodiments, channel layer 116 includes silicon for N-type transistors. In other embodiments, channel layer 116 includes silicon germanium for P-type transistors. In some embodiments, channel layer 116 is made entirely of silicon, and the type of transistor depends on the work function metal layer surrounding channel layer 116.

[0123] As described above, the gate structure 106 is bonded to the active region 104 to construct the transistor 103 in the OTP memory cell 102. More specifically, the gate structure 106 surrounds the channel layer 116 in the channel region 104 of the active region 104ch. The gate structure 106 has a gate dielectric layer 118 and a gate electrode layer 120. The gate dielectric layer 118 surrounds the channel layer 116, and the gate electrode layer 120 surrounds the gate dielectric layer 118 and the channel layer 116. More specifically, the gate dielectric layer 118 is on the top surface and sidewalls of the channel layer 116, as shown in FIG. Figure 2A shown.

[0124] In some embodiments, the gate structure 106 further includes an interfacial layer (e.g., having silicon dioxide, silicon oxynitride, or other suitable materials) between the gate dielectric layer 118 and the channel layer 116. The gate dielectric layer 118 may include an oxide having a nitrogen-doped dielectric material (initial layer) combined with a metal-containing high-K dielectric material (K value (dielectric constant)>13). For example, the gate dielectric layer 118 may include hafnium oxide (HfO2), which has a dielectric constant in the range of about 18 to about 40. Alternatively, the gate dielectric layer 118 may include other high-K dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiON), combinations thereof, or other suitable materials. The gate dielectric layer 118 may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods.

[0125] The gate electrode layer 120 is formed to surround the gate dielectric layer 118 and the channel layer 116. Figure 2AAs shown. In some embodiments, the gate electrode layer 120 may include one or more N-type work function metal layers for N-type transistors or one or more P-type work function metal layers for P-type transistors surrounding the channel layer 116. The materials of the N-type work function metal layer and the P-type work function metal layer may be the same. In some embodiments, the materials of the N-type work function metal layer and the P-type work function metal layer are different. As described above, the OTP memory cell 102 includes the gate contact window 110. As shown Figure 2A As shown, according to some embodiments, the gate contact window 110 is above the gate electrode layer 120 of the gate structure 106 and is electrically connected to the gate electrode layer 120 of the gate structure 106. In addition, as described above, the gate contact window 110 is disposed on the end portions 106-1 and 106-2 of the gate structure 106. Figure 1 In some embodiments, the ends 106-1 and 106-2 of the gate structure 106 may also represent the ends of the gate electrode layer 120. In other words, the gate contact window 110 is disposed on the ends 106-1 and 106-2 of the gate electrode layer 120, as shown in FIG. Figure 1 and Figure 2A shown.

[0126] As described above, the source / drain region 104sd of the OTP memory cell 102 includes source / drain features. The source / drain features in the source / drain region 104sd are arranged on opposite sides of the corresponding gate structure 106 in the Y direction to form the transistor 103 in the OTP memory cell 102. The channel layer 116 connects one source / drain feature in one source / drain region 104sd to another source / drain feature in another source / drain region 104sd. More specifically, the source / drain features are also arranged on opposite sides of the corresponding channel layer 116 in the Y direction. Therefore, the source / drain features in the source / drain region 104sd are attached and electrically connected to the channel layer 116 in the Y direction. The source / drain features may also be referred to as source / drain. In some embodiments, the source / drain features may refer to the source or drain individually or collectively, depending on the context.

[0127] The source / drain features may be formed using epitaxial growth. In some embodiments, the source / drain features may include an epitaxially grown material selected from the group consisting of SiP, SiC, SiPC, SiAs, Si, or a combination thereof. In some embodiments, the epitaxially grown material of the source / drain features may be doped with N-type dopants, such as phosphorus, arsenic, other N-type dopants, or a combination thereof. In some embodiments, source / drain features doped with N-type dopants for N-type transistors may be referred to as N-type features and N-type source / drain features, respectively.

[0128] In some embodiments, source / drain features doped with P-type dopants for a P-type transistor may be referred to as P-type source / drain features accordingly.

[0129] As described above, according to some embodiments of the present invention, Figure 2A The OTP memory device 100 of the FinFET structured OTP memory cell 102 is shown unprogrammed. Figure 2B Some embodiments according to the present invention show that after the OTP memory device 100 is programmed, Figure 1 FIG. 1 is an XZ cross-sectional view of the OTP memory device 100 having the OTP memory cell 102 along the line segment AA′, wherein the OTP memory cell 102 has a FinFET structure. Figure 2C Some embodiments according to the present invention show that after the OTP memory device 100 is programmed, Figure 1 FIG. 1 is an XZ cross-sectional view of the OTP memory device 100 having the OTP memory cell 102 along the line segment AA′, wherein the OTP memory cell 102 has a FinFET structure.

[0130] In order to program the OTP memory cell 102, the end 106-1 and the end 106-2 of the gate structure 106 (specifically, the gate electrode layer 120) are connected to different voltages, respectively. More specifically, in the programming operation of the OTP memory device 100, the end 106-1 of the gate electrode layer 120 is connected to a first voltage (hereinafter referred to as voltage VG1), and the end 106-2 of the gate electrode layer 120 is connected to a second voltage (hereinafter referred to as voltage VG2) different from the first voltage, so that a programming current is generated along the gate structure 106 (specifically, the gate electrode layer 120). In some embodiments, the end 106-1 and the end 106-2 of the gate electrode layer 120 are connected to the voltages VG1 and VG2, respectively, through the gate contact window 110 (that is, the gate contact window 110 above the end 106-1 and the end 106-2 of the gate electrode layer 120 is connected to the voltages VG1 and VG2). In other words, voltages VG1 and VG2 are applied to end 106-1 and end 106-2 of gate electrode layer 120 through gate contact 110, respectively (i.e., voltages VG1 and VG2 are applied to gate contact 110 above end 106-1 and end 106-2 of gate electrode layer 120). In addition, source / drain contact 108 is floating during programming of OTP memory cell 102.

[0131] After the terminals 106-1 and 106-2 are connected to the voltages VG1 and VG2, respectively, and the source / drain contact window 108 is floating, the gate electrode layer 120 changes, such as Figure 2BAs shown. Compared with the original gate electrode layer 120 (as shown by the dotted line), the shape and position of the gate electrode layer 120 have changed. This change in position and shape of the gate electrode layer 120 is caused by electromigration (i.e., the voltage difference between the voltages VG1 and VG2 is greater than the electromigration threshold (e.g., about 2V). As described above, the voltages VG1 and VG2 are different, and this voltage difference between the voltages VG1 and VG2 causes electromigration, causing the shape and position of the gate electrode layer 120 to change. In some embodiments, the voltages VG1 and VG2 may be in the range of about -2V to 2V. In some embodiments, the voltage difference between the voltages VG1 and VG2 may be about 2V.

[0132] If the voltage VG1 is less than the voltage VG2, that is, the end 106-1 of the gate electrode layer 120 is connected to a lower voltage and the end 106-2 of the gate electrode layer 120 is connected to a higher voltage, the gate electrode layer 120 is shifted to the right, as shown in FIG. Figure 2B This is because such voltages VG1 and VG2 cause electrons to flow from left to right. Similarly, according to some embodiments, if voltage VG1 is greater than voltage VG2, i.e., end 106-1 of gate electrode layer 120 is connected to a higher voltage and end 106-2 of gate electrode layer 120 is connected to a lower voltage, gate electrode layer 120 is offset to the left.

[0133] like Figure 2A As shown, before programming of the OTP memory cell 102, the gate electrode layer 120 has a thickness T1 from the edge of the end 106-1 of the gate electrode layer 120 to the channel layer 116 in the X direction, and a thickness T2 from the edge of the end 106-2 of the gate electrode layer 120 to the channel layer 116 in the X direction. In some embodiments, the thickness T1 is equal to the thickness T2, as shown in FIG. Figure 2A After programming of the OTP memory cell 102, the thickness T1 of the gate electrode layer 120 changes to a thickness T1', and the thickness T2 of the gate electrode layer 120 changes to a thickness T2'. The thickness T1' is different from the thickness T2'.

[0134] In the case where the voltage VG1 (connected to the end 106 - 1 ) is less than the voltage VG2 (connected to the end 106 - 2 ) during programming, the thickness T1 ′ is less than the thickness T2 ′ after programming, such as Figure 2B. In other words, thickness T1 decreases to thickness T1', and thickness T2 increases to thickness T2'. Similarly, in the case where voltage VG1 (connected to end 106-1) is greater than voltage VG2 (connected to end 106-2) during programming, thickness T1' is greater than thickness T2' after programming. In addition, after programming of OTP memory cell 102, the top surface of gate electrode layer 120 is non-planar. In some embodiments, after programming of OTP memory cell 102, gate electrode layer 120 has an inclined top surface, such as Figure 2B shown.

[0135] In some embodiments, the thickness T1 or T2 of the gate electrode layer 120 before programming is reduced to zero (0) after programming. For example, after programming in which the voltage VG1 (connected to the end 106-1) is less than the voltage VG2 (connected to the end 106-2), the thickness T1' of the gate electrode layer 120 is zero, as shown in FIG. Figure 2C In such an embodiment, the edge of the end portion 106-1 of the gate electrode layer 120 is aligned with the sidewall of the channel layer 116 after programming, as shown in FIG. Figure 2C shown.

[0136] Due to such a change in position and shape of the gate electrode layer 120, the gate control of the gate structure 106 changes. Therefore, the threshold voltage of the transistor 103 in the OTP memory cell 102 of the OTP memory device 100 also changes. More specifically, the OTP memory device 100 (specifically, the transistor 103 in the OTP memory cell 102) has a first threshold voltage (which may be referred to as a threshold voltage Vth1) before programming, and has a second threshold voltage (which may be referred to as a threshold voltage Vth1') after programming, which is different from the first threshold voltage. In this way, according to the read current (from one source / drain region 104sd through the channel layer 116 to another source / drain region 104sd) of the transistor 103 in the OTP memory cell 102 during the period when the OTP memory cell 102 is read, it can be determined whether the OTP memory cell 102 has been programmed.

[0137] In a read operation of the OTP memory device 100, in order to read the OTP memory cell 102, the end 106-1 and the end 106-2 of the gate structure 106 (specifically, the gate electrode layer 120) are connected to a voltage of about 0V or slightly greater than 0V (through the gate contact window 110), one of the source / drain regions 104sd is connected to 0V (through the source / drain contact window 108), and the other of the source / drain regions 104sd is connected to a power supply voltage V through the source / drain contact window 108. DD(greater than 0V), so that the transistor 103 in the OTP memory cell 102 generates a read current. If the OTP memory cell 102 is not programmed (i.e., the position and shape of the gate electrode layer 120 remain Figure 2A If the OTP memory cell 102 has been programmed (i.e., the position and shape of the gate electrode layer 120 is changed to Figure 2B or Figure 2C The position and shape shown in FIG. 1 and the transistor 103 having the threshold voltage Vth1′ discussed above), a second read current (which may be referred to as current Iread1′) of the transistor 103 in the OTP memory cell 102 is read.

[0138] As described above, since the threshold voltage Vth1 of the transistor 103 in the OTP memory cell 102 before programming is different from the threshold voltage Vth1′ of the transistor 103 in the OTP memory cell 102 after programming, the current Iread1 of the transistor 103 in the OTP memory cell 102 before programming is different from the current Iread1′ after programming. Therefore, according to the current value of the read current of the transistor 103 in the OTP memory cell 102, the logic state of the OTP memory cell 102 can be known. For example, if the read current of the transistor 103 in the OTP memory cell 102 is greater than 5 μA, the logic state of the OTP memory cell 102 is in the logic state “0”, and if the read current of the transistor 103 in the OTP memory cell 102 is less than 10 nA, the logic state of the OTP memory cell 102 is in the logic state “1”.

[0139] The OTP memory cell 102 discussed above shows a FinFET structure. In some embodiments, the transistor 103 in the OTP memory cell 102 may be a gate-all-around (GAA) transistor. Figure 3A Some embodiments according to the present invention show that the OTP memory device 100 is programmed before being programmed. Figure 1 FIG. 1 is an XZ cross-sectional view of the OTP memory device 100 having the OTP memory cell 102 along the line segment AA′, wherein the OTP memory cell 102 has a GAA structure. Figure 3A The OTP memory cell 102 is shown with Figure 2A The OTP memory cell 102 is similar to the OTP memory cell 102 shown, except that the OTP memory cell 102 includes more channel layers to construct a GAA structure. Figure 3AAs shown, the OTP memory cell 102 includes channel layers 116-1', 116-2', and 116-3' (which may be collectively referred to as channel layers 116'). The channel layer 116' is suspended above the substrate 112 and stacked in the Z direction. More specifically, the channel layer 116-1' is above the substrate 112 and separated from the substrate 112 in the Z direction, the channel layer 116-2' is above the channel layer 116-1' and separated from the channel layer 116-1' in the Z direction, and the channel layer 116-3' is above the channel layer 116-2' and separated from the channel layer 116-2' in the Z direction, as shown in FIG. Figure 3A As shown. In some embodiments, for the transistor 103 in the OTP memory cell 102, three channel layers 116-1', 116-2' and 116-3' are stacked vertically (or arranged vertically) with respect to each other in the Z direction. However, another appropriate number of nanostructures may exist in one transistor. For example, there may be 2 to 10 channel layers 116' in the transistor 103 in the OTP memory cell 102.

[0140] Similar to the above discussion, the gate structure 106 wraps around and / or surrounds the suspended, vertically stacked channel layers 116' in the channel region 104ch of the active region 104. More specifically, the gate dielectric layer 118 of the gate structure 106 surrounds each of the channel layers 116', and the gate electrode layer 120 of the gate structure 106 surrounds each of the gate dielectric layer 118 and the channel layer 116', such as Figure 3A shown.

[0141] Similarly, according to some embodiments of the present invention, having Figure 3A The OTP memory device 100 of the GAA structured OTP memory cell 102 is shown unprogrammed. Figure 3B Some embodiments according to the present invention show that after the OTP memory device 100 is programmed, Figure 1 FIG. 1 is an XZ cross-sectional view of the OTP memory device 100 having the OTP memory cell 102 along the line segment AA′, wherein the OTP memory cell 102 has a GAA structure. Figure 3C Some embodiments according to the present invention show that after the OTP memory device 100 is programmed, Figure 1 FIG. 1 is an XZ cross-sectional view of the OTP memory device 100 having the OTP memory cell 102 along the line segment AA′, wherein the OTP memory cell 102 has a GAA structure.

[0142] Similarly, to program the OTP memory cell 102, the end 106-1 and the end 106-2 of the gate structure 106 (specifically, the gate electrode layer 120) are connected to different voltages, respectively. In other words, in the programming operation of the OTP memory device 100, the end 106-1 of the gate electrode layer 120 is connected to the voltage VG1 discussed above, and the end 106-2 of the gate electrode layer 120 is connected to the voltage VG2 discussed above, so that a programming current is generated along the gate structure 106 (specifically, the gate electrode layer 120). In addition, the source / drain contact window 108 is floating during the programming of the OTP memory cell 102.

[0143] After the terminals 106-1 and 106-2 are connected to the voltages VG1 and VG2 respectively and the source / drain contact window 108 is floating, the gate electrode layer 120 also changes, such as Figure 3B As shown. Compared with the original gate electrode layer 120 (shown by the dotted line), the shape and position of the gate electrode layer 120 are also changed. As described above, the voltage difference between the voltages VG1 and VG2 causes electromigration, causing the shape and position of the gate electrode layer 120 to change. Similarly, if the voltage VG1 is less than the voltage VG2, the gate electrode layer 120 is shifted to the right, as shown in FIG. Figure 3B According to some embodiments, if the voltage VG1 is greater than the voltage VG2 , the gate electrode layer 120 is shifted to the left.

[0144] like Figure 3A As shown, before programming of the OTP memory cell 102, the gate electrode layer 120 has a thickness T3 from the edge of the end 106-1 of the gate electrode layer 120 to the channel layer 116' in the X direction, and a thickness T4 from the edge of the end 106-2 of the gate electrode layer 120 to the channel layer 116' in the X direction. In some embodiments, the thickness T3 is equal to the thickness T4, such as Figure 3A After programming of the OTP memory cell 102, the thickness T3 of the gate electrode layer 120 changes to a thickness T3', and the thickness T4 of the gate electrode layer 120 changes to a thickness T4'.

[0145] In the case where the voltage VG1 is less than the voltage VG2 during programming, the thickness T3′ is less than the thickness T4′ after programming. Figure 3B. In other words, thickness T3 decreases to thickness T3', and thickness T4 increases to thickness T4'. Similarly, in the case where voltage VG1 is greater than voltage VG2 during programming, thickness T3' is greater than thickness T4' after programming. Similarly, after programming of OTP memory cell 102, the top surface of gate electrode layer 120 is non-planar, as described above. In some embodiments, after programming of OTP memory cell 102, gate electrode layer 120 has an inclined top surface, as Figure 3B shown.

[0146] Similarly, in some embodiments, the thickness T3 or T4 of the gate electrode layer 120 before programming is reduced to zero (0) after programming. For example, after programming in which the voltage VG1 is less than the voltage VG2, the thickness T3' of the gate electrode layer 120 is zero, as shown in FIG. Figure 3C In such an embodiment, the edge of the end portion 106-1 of the gate electrode layer 120 is aligned with the sidewall of the channel layer 116' after programming, as shown in FIG. Figure 3C shown.

[0147] Similarly, due to such a change in position and shape of the gate electrode layer 120, the gate control of the gate structure 106 changes. Therefore, the OTP memory device 100 (specifically, the transistor 103 in the OTP memory cell 102) has the first threshold voltage discussed above (which may be referred to as the threshold voltage Vth1) before programming, and has the second threshold voltage discussed above (which may be referred to as the threshold voltage Vth1') after programming. In this way, according to the read current of the transistor 103 in the OTP memory cell 102 during the period when the OTP memory cell 102 is read, it can be known whether the OTP memory cell 102 has been programmed.

[0148] Similarly, in a read operation of the OTP memory device 100, in order to read the OTP memory cell 102, the end 106-1 and the end 106-2 of the gate structure 106 (specifically, the gate electrode layer 120) are connected to a voltage of about 0V or slightly greater than 0V (through the gate contact window 110), one of the source / drain regions 104sd is connected to 0V (through the source / drain contact window 108), and the other of the source / drain regions 104sd is connected to the power supply voltage V through the source / drain contact window 108. DD , so that the transistor 103 in the OTP memory cell 102 generates a read current. If the OTP memory cell 102 is not programmed (i.e., the position and shape of the gate electrode layer 120 remain Figure 3AIf the OTP memory cell 102 has been programmed (i.e., the position and shape of the gate electrode layer 120 is changed to Figure 3B or Figure 3C , and the transistor 103 has the threshold voltage Vth1′ discussed above), then the current Iread1′ of the transistor 103 in the OTP memory cell 102 discussed above is read.

[0149] Similarly, since the threshold voltage Vth1 of the transistor 103 in the OTP memory cell 102 before programming is different from the threshold voltage Vth1′ of the transistor 103 in the OTP memory cell 102 after programming, the current Iread1 of the transistor 103 in the OTP memory cell 102 before programming is different from the current Iread1′ after programming. Therefore, according to the current value of the read current of the transistor 103 in the OTP memory cell 102, the logic state of the OTP memory cell 102 can be known. For example, if the read current of the transistor 103 in the OTP memory cell 102 is greater than 5 μA, the logic state of the OTP memory cell 102 is in the logic state “0”, and if the read current of the transistor 103 in the OTP memory cell 102 is less than 10 nA, the logic state of the OTP memory cell 102 is in the logic state “1”.

[0150] Figure 4 Some alternative embodiments according to the present invention show a top view (or layout) of an OTP memory device 200 having a plurality of OTP memory cells 202-1 to 202-3 (which may be collectively referred to as OTP memory cells 202). In some embodiments, each of the OTP memory cells 202-1 to 202-3 is similar to the OTP memory cell 102 discussed above. The OTP memory cells 202-1 to 202-3 individually include transistors 203-1, 203-2, and 203-3 (which may be collectively referred to as transistors 203), which are similar to the transistors 103 discussed above.

[0151] Similarly, Figure 4 As shown, each of the OTP memory cells 202-1 to 202-3 includes an active region 204, a gate structure 206, source / drain contacts 208, and a gate contact 210, which are similar to the active region 104, the gate structure 106, the source / drain contacts 108, and the gate contact 110 discussed above. Figure 4As shown, the OTP memory cells 202-1 to 202-3 are arranged in the X direction. Therefore, the active regions 204 of the OTP memory cells 202-1 to 202-3 are also arranged in the X direction. In addition, the gate structures 206 of the OTP memory cells 202-1 to 202-3 are also arranged in the X direction and aligned with each other in the X direction. Figure 4 The OTP memory device 200 shown includes three OTP memory cells 202-1 to 202-3, but it should be noted that the OTP memory device 200 may include more OTP memory cells similar to the OTP memory cell 202 arranged in the X direction. Other features and programming and reading mechanisms of the OTP memory cells 202-1 to 202-3 are also similar to the OTP memory cell 102 discussed above, and will not be discussed again here.

[0152] The difference between the OTP memory cell 102 and the OTP memory cells 202-1 to 202-3 is how to determine whether the OTP memory cell has been programmed. As described above, based on the current value of the read current of the transistor 103 in the OTP memory cell 102, it can be determined whether the OTP memory cell 102 is programmed, thereby determining the logic state of the OTP memory cell 102.

[0153] exist Figure 4In the illustrated embodiment, one of the OTP memory cells 202-1 to 202-3 is selected as a reference cell. For example, according to some embodiments, the OTP memory cell 202-1 is used as a reference cell. Such an OTP memory cell 202-1 will not be programmed (i.e., the OTP memory cell 202-1 always has the threshold voltage Vth1 discussed above), and will be compared with the other selected OTP memory cells 202 (i.e., the OTP memory cells 202-2 and 202-3) to obtain the logic state of the OTP memory cells 202 (i.e., the OTP memory cells 202-2 and 202-3). In other words, only one of the OTP memory cells 202-2 and 202-3 is selected at a time. If the OTP memory cell 202-2 is selected, the OTP memory cell 202-1 will be compared with the OTP memory cell 202-2, and if the OTP memory cell 202-3 is selected, the OTP memory cell 202-1 will be compared with the OTP memory cell 202-3. For example, if another selected OTP memory cell 202-2 or 202-3 has been programmed (in the manner discussed above), the OTP memory cell 202-2 or 202-3 has a threshold voltage Vthl' that is different from the threshold voltage Vthl, and the read current of the transistor 203-2 or 203-3 in the selected OTP memory cell 202-2 or 202-3 will be different from the read current of the transistor 203-1 in the OTP memory cell 202-1 during reading (in the manner discussed above). In other words, the current difference between the read current of the selected transistor 203-2 or 203-3 and the read current of the transistor 203-1 will be greater than a first predetermined threshold difference (e.g., 1×10 -10 A to 1×10 -6 A). If the selected OTP memory cell 202-2 or 202-3 is not programmed (the OTP memory cell 202-2 or 202-3 still has the threshold voltage Vth1 discussed above), the read current of the transistor 203-2 or 203-3 in the selected OTP memory cell 202-2 or 202-3 will be substantially the same as the read current of the transistor 203-1 in the OTP memory cell 202-1 during reading (in the manner discussed above). In other words, the current difference between the read current of the selected transistor 203-2 or 203-3 and the read current of the transistor 203-1 will be less than the first predetermined threshold difference. Therefore, based on the comparison, the logic state of the OTP memory cell 202 (which is not used as a reference cell) can be known.

[0154] For example, in a read operation of the OTP memory device 200, the OTP memory cell 202-1 is used as a reference cell. To read the OTP memory cell 202-2, the end 206-1 and the end 206-2 of the gate structure 206 (specifically, the gate electrode layer 120) of the OTP memory cell 202-1 and the end 206-3 and the end 206-4 of the gate structure 206 (specifically, the gate electrode layer 120) of the OTP memory cell 202-2 are connected to a voltage of about 0V or slightly greater than 0V (through the gate contact window 210), one of the source / drain regions 104sd of the OTP memory cell 202-1 is connected to 0V (through the source / drain contact window 208), and the other of the source / drain regions 104sd of the OTP memory cell 202-1 is connected to the power supply voltage V DD , one of the source / drain regions 104sd of the OTP memory cell 202-2 is connected to 0V (through the source / drain contact window 208), and the other of the source / drain regions 104sd of the OTP memory cell 202-2 is connected to the power supply voltage V DD , so that the transistor 203-1 in the OTP memory cell 202-1 generates a read current and the transistor 203-2 in the OTP memory cell 202-2 generates a read current. According to the difference between the read current of the transistor 203-2 and the read current of the transistor 203-1 (greater than or less than the first predetermined threshold difference), the logic state of the OTP memory cell 202-2 (not used as a reference cell) can be known.

[0155] Figure 5 A top view (or layout) of an OTP memory device 300 having an OTP memory cell 302 is shown in accordance with some alternative embodiments of the present invention. Figure 5 The illustrated OTP memory device 300 includes one OTP memory cell 302 , but it should be noted that the OTP memory device 300 may include more OTP memory cells similar to the OTP memory cell 302 arranged in multiple columns and rows into an OTP memory array.

[0156] The OTP memory cell 302 is similar to the OTP memory cell 102 discussed above, except that the OTP memory cell 302 is constructed by two transistors 303-1 and 303-2 (which may be collectively referred to as transistors 303). Therefore, the OTP memory cell 302 includes an active region 304-1 for the transistor 303-1 and an active region 304-2 for the transistor 303-2 (which may be collectively referred to as active regions 304), which extend longitudinally in the Y direction. The active regions 304 each also include a channel region 304ch and a source / drain region 304sd. Similarly, according to some embodiments, the source / drain region 304sd is disposed on opposite sides of the channel region 304ch in the Y direction.

[0157] The OTP memory cell 302 further includes gate structures 306-1 and 306-2 (collectively referred to as gate structures 306). The gate structures 306 extend longitudinally in the X direction to cross the active region 304, such as Figure 5 Similar to the gate structure 106 discussed above, the gate structures 306-1 and 306-2 are respectively disposed in the channel region 304ch (ie, FIG. 6A to FIG. 7B The active region 304 and the gate structure 306 are configured to provide transistors 303-1 and 303-2 for the OTP memory cell 302. In addition, it is noted that the gate structures 306-1 and 306-2 contact each other in the X direction. More specifically, as shown in FIG. Figure 5 As shown, the gate structure 306-1 has end portions 306e-1 and 306e-2 on opposite sides of the gate structure 306-1 (the gate electrode layer 320 of the gate structure 306-1) in the X direction, and the gate structure 306-2 has end portions 306e-3 and 306e-4 on opposite sides of the gate structure 306-2 (the gate electrode layer 320 of the gate structure 306-2) in the X direction, wherein the end portion 306e-2 of the gate structure 306-1 (the gate electrode layer 320 of the gate structure 306-1) contacts the end portion 306e-3 of the gate structure 306-2 (the gate electrode layer 320 of the gate structure 306-2) in the X direction.

[0158] In some embodiments, gate structures 306-1 and 306-2 are formed simultaneously. In some aspects, gate structures 306-1 and 306-2 can be considered together as one gate structure, such as gate structure 307. Figure 5 In some embodiments, gate structure 307 is a common gate structure and is shared by transistors 303 - 1 and 303 - 2 of OTP memory cell 302 .

[0159] Similarly, the OTP memory cell 302 further includes source / drain contacts 308 and a gate contact 310. Figure 5 As shown, the source / drain contact window 308 is disposed on the source / drain region 304sd of the active region 304, over the source / drain features (not shown) in the source / drain region 304sd, and electrically connected to the source / drain features. The gate contact window 310 is disposed on the gate structure 306 (gate structure 307), and electrically connected to the gate structure 306 (gate structure 307). More specifically, the gate contact window 310 is disposed on the end 306e-1 of the gate structure 306-1 and the end 306e-4 of the gate structure 306-2 (or the ends 306e-1 and 306e-4 of the gate structure 307), as shown in FIG. Figure 5 In some embodiments, the material of the source / drain contact window 308 is the same as the material of the source / drain contact window 108 discussed above.

[0160] In some embodiments, the transistor 303 in the OTP memory cell 302 may be a fin field effect transistor (FinFET). Fig. 6A Some embodiments according to the present invention show that before the OTP memory device 300 is programmed, Figure 5 FIG. 1 is an XZ cross-sectional view of an OTP memory device 300 having an OTP memory cell 302 along a line segment BB′, wherein the OTP memory cell 302 has a FinFET structure. Figure 5 As shown, OTP memory cell 302 further includes substrate 312 and isolation features 314, which are similar to substrate 112 and isolation features 114 discussed above, and the details will not be repeated here.

[0161] like Figure 5 and Fig. 6A As shown, in the case where the transistor 303 in the OTP memory cell 302 is a FinFET, the OTP memory cell 302 further includes a channel layer 316 in the channel region 304ch of the active region 304. More specifically, each of the transistors 303-1 and 303-2 in the OTP memory cell 302 has one channel layer, although there may be another appropriate number of nanostructures in one transistor 303 in the OTP memory cell 302. For example, there may be 2 to 3 channel layers 316 in one transistor 303. According to some embodiments, like the channel layer 116 discussed above, the channel layer 316 is above the substrate 312 and protrudes from the substrate 312. In addition, the channel layer 316 extends from the substrate 312 in the Z direction. In some embodiments, the channel layer 316 is between the isolation features 314 in the X direction, such as Fig. 6AIn some aspects, isolation features 314 surround channel layer 316. In some embodiments, channel layer 316 is formed from substrate 312. In some embodiments, the material of channel layer 316 is the same as the material of channel layer 116 discussed above.

[0162] like Figure 5 and Fig. 6A As shown, gate structure 306-1 joins active region 304-1 to construct transistor 303-1, and gate structure 306-2 joins active region 304-2 to construct transistor 303-1. In some aspects, gate structure 307 joins active regions 304-1 and 304-2 to construct transistors 303-1 and 303-2. Gate structure 306-1 surrounds channel layer 316 in channel region 304ch of active region 304-1, and gate structure 306-2 surrounds channel layer 316 in channel region 304ch of active region 304-2. In some aspects, gate structure 307 surrounds channel layer 316 in channel region 304ch of active regions 304-1 and 304-2. Gate structure 307 (including gate structures 306-1 and 306-2) has gate dielectric layer 318 and gate electrode layer 320. The gate dielectric layer 318 surrounds the channel layer 316, and the gate electrode layer 320 surrounds the gate dielectric layer 318 and the channel layer 316. More specifically, the gate dielectric layer 318 is on the top surface and sidewalls of the channel layer 316, such as Fig. 6A In some embodiments, the materials of the gate dielectric layer 318 and the gate electrode layer 320 are the same as the materials of the gate dielectric layer 118 and the gate electrode layer 120 discussed above.

[0163] like Fig. 6A As shown, according to some embodiments, the gate contact window 310 is above the gate electrode layer 320 of the gate structure 306 and is electrically connected to the gate electrode layer 320 of the gate structure 306. In addition, the gate contact window 310 is disposed on the end 306e-1 of the gate structure 306-1 and the end 306e-4 of the gate structure 306-2, as shown in FIG. Figure 5 As shown. In some aspects, the ends 306e-1 and 306e-4 may also represent the ends of the gate structure 307. In other words, according to some embodiments, the gate contact window 310 is disposed on the ends 306e-1 and 306e-4 of the gate structure 307. In some embodiments, the end 306e-1 of the gate structure 306-1 and the end 306e-4 of the gate structure 306-2 may also represent the ends of the gate electrode layer 320. In other words, the gate contact window 310 is disposed on the ends 306e-1 and 306e-4 of the gate electrode layer 320, as shown. Figure 5 and Fig. 6A shown.

[0164] Similar to the source / drain region 104sd discussed above, the source / drain region 304sd of the OTP memory cell 302 includes source / drain features. The source / drain features in the source / drain region 304sd are disposed on opposite sides of the corresponding gate structure 306 in the Y direction to form the transistor 303 in the OTP memory cell 302. The source / drain features may also be referred to as source / drain. In some embodiments, the source / drain features may refer to the source or drain individually or collectively, depending on the context. In some embodiments, the materials of the source / drain features are as discussed above.

[0165] As described above, according to some embodiments of the present invention, Fig. 6A The OTP memory device 300 of the FinFET structured OTP memory cell 302 is shown unprogrammed. Figure 6B According to some embodiments of the present invention, the OTP memory device 300 is programmed along Figure 5 FIG. 1 is an XZ cross-sectional view of the OTP memory device 300 having an OTP memory cell 302 along line segment BB′, wherein the OTP memory cell 302 has a FinFET structure.

[0166] Similar to the programming of the OTP memory cell 102 discussed above, the end 306e-1 and the end 306e-4 of the gate structure 306 (specifically, the gate electrode layer 320) are connected to different voltages respectively. Through the gate contact window 310, the end 306e-1 of the gate electrode layer 320 is connected to the voltage VG1 discussed above, and the end 306e-4 of the gate electrode layer 320 is connected to the voltage VG2 discussed above, so that the programming current is generated along the gate structure 306 (specifically, the gate electrode layer 320). In addition, the source / drain contact window 308 is floating during the programming of the OTP memory cell 302.

[0167] After the end portions 306e-1 and 306e-4 are connected to the voltages VG1 and VG2, respectively, and the source / drain contact window 308 is floating, the gate electrode layer 320 changes, such as Figure 6B As shown. Compared with the original gate electrode layer 320 (shown as a dotted line), the shape and position of the gate electrode layer 320 are changed. As described above, the voltage difference between the voltages VG1 and VG2 causes electromigration, so that the shape and position of the gate electrode layer 320 are changed. Similarly, if the voltage VG1 is less than the voltage VG2, the gate electrode layer 320 is shifted to the right, as shown in FIG. Figure 3B According to some embodiments, if the voltage VG1 is greater than the voltage VG2 , the gate electrode layer 320 is shifted to the left.

[0168] like Fig. 6AAs shown, before programming of the OTP memory cell 302, the gate electrode layer 320 has a thickness T5 from the edge of the end 306e-1 of the gate electrode layer 320 to the channel layer 316 in the X direction, and a thickness T6 from the edge of the end 306e-4 of the gate electrode layer 320 to the channel layer 316 in the X direction. In some embodiments, the thickness T5 is equal to the thickness T6. Fig. 6A After programming of the OTP memory cell 302, the thickness T5 of the gate electrode layer 320 changes to a thickness T5', and the thickness T6 of the gate electrode layer 320 changes to a thickness T6'.

[0169] In the case where the voltage VG1 is less than the voltage VG2 during programming, the thickness T5′ is less than the thickness T6′ after programming. Figure 6B . In other words, thickness T5 is reduced to thickness T5', and thickness T6 is increased to thickness T6'. Similarly, in the case where voltage VG1 is greater than voltage VG2 during programming, thickness T5' is greater than thickness T6' after programming. In addition, after programming of OTP memory cell 302, the top surface of gate electrode layer 320 is non-planar. In some embodiments, after programming of OTP memory cell 302, gate electrode layer 320 has an inclined top surface, such as Figure 6B In some embodiments, the thickness T5 or T6 of the gate electrode layer 320 before programming is reduced to zero (0) after programming (ie, the thickness T5' or the thickness T6' is zero (0)).

[0170] In addition, if Fig. 6A As shown, before programming of the OTP memory cell 302, the gate electrode layer 320 has a thickness Th1 from the top surface of the channel layer 316 of the transistor 303-1 to the top surface of the gate electrode layer 320 in the Z direction, and a thickness Th2 from the top surface of the channel layer 316 of the transistor 303-2 to the top surface of the gate electrode layer 320 in the Z direction. In some embodiments, the thickness Th1 is equal to the thickness Th2, such as Fig. 6A After programming of the OTP memory cell 302, the thickness Th1 of the gate electrode layer 320 changes to the thickness Th1', and the thickness Th2 of the gate electrode layer 320 changes to the thickness Th2'.

[0171] In the case where the voltage VG1 is less than the voltage VG2 during programming, the thickness Th1′ is less than the thickness Th2′ after programming. Figure 6B In other words, the thickness Th1 is reduced to the thickness Th1', and the thickness Th2 is increased to the thickness Th2'. Similarly, in the case where the voltage VG1 is greater than the voltage VG2 during programming, the thickness Th1' is greater than the thickness Th2' after programming.

[0172] Due to such a change in position and shape of the gate electrode layer 320, the gate control of the gate structure 306 (or the gate structure 307) changes. Therefore, the threshold voltages of the transistors 303-1 and 303-2 in the OTP memory cell 302 also change. More specifically, before programming, the transistor 303-1 has a third threshold voltage (which may be referred to as a threshold voltage Vth2), and the transistor 303-2 has a fourth threshold voltage (which may be referred to as a threshold voltage Vth3). After programming of the OTP memory cell 302, the transistor 303-1 has a fifth threshold voltage (which may be referred to as a threshold voltage Vth2'), and the transistor 303-2 has a sixth threshold voltage (which may be referred to as a threshold voltage Vth3'). In some embodiments, before programming, the threshold voltage Vth2 of the transistor 303-1 and the threshold voltage Vth3 of the transistor 303-2 are the same. In this way, whether the OTP memory cell 302 has been programmed can be known based on the read currents of the transistors 303 - 1 and 303 - 2 in the OTP memory cell 302 during the period when the OTP memory cell 302 is read.

[0173] In the read operation of the OTP memory device 300, in order to read the OTP memory cell 302, the end 306e-1 or the end 306e-4 of the gate structure 306 (gate structure 307) (specifically, the gate electrode layer 320) is connected to a voltage of about 0V or slightly greater than 0V, one of the source / drain regions 304sd of the active region 304-1 is connected to 0V and the other of the source / drain regions 304sd of the active region 304-1 is connected to the power supply voltage V DD , one of the source / drain regions 304sd of the active region 304-2 is connected to 0V and the other of the source / drain regions 304sd of the active region 304-2 is connected to the power supply voltage V DD , so that the transistors 303-1 and 303-2 in the OTP memory cell 302 generate a read current. If the OTP memory cell 302 has not been programmed, and the transistor 303-1 still has the threshold voltage Vth2 discussed above, and the transistor 303-2 still has the threshold voltage Vth3 discussed above (i.e., the position and shape of the gate electrode layer 320 remain the position and shape shown in FIG. 3A ), then the third read current (which may be referred to as current Iread2) of the transistor 303-1 in the OTP memory cell 302 and the fourth read current (which may be referred to as current Iread3) of the transistor 303-2 in the OTP memory cell 302 are read. If the OTP memory cell 302 has been programmed (i.e., the position and shape of the gate electrode layer 320 are changed to Figure 6BThe position and shape shown, and the transistor 303-1 has the threshold voltage Vth2' discussed above, and the transistor 303-2 has the threshold voltage Vth3' discussed above), then the fifth read current (which can be referred to as current Iread2') of the transistor 303-1 in the OTP memory cell 302 and the sixth read current (which can be referred to as current Iread3') of the transistor 303-2 in the OTP memory cell 302 are read.

[0174] As described above, the threshold voltage Vth2 of transistor 303-1 and the threshold voltage Vth3 of transistor 303-2 before programming are the same, and the threshold voltage Vth2' of transistor 303-1 and the threshold voltage Vth3' of transistor 303-2 after programming are different. As a result, if OTP memory cell 302 has been programmed, the read current of transistor 303-1 in OTP memory cell 302 will be different from the read current of transistor 303-2 in OTP memory cell 302 during reading (i.e., the current difference between the read current of transistor 303-1 and the read current of transistor 303-2 will be greater than the second predetermined threshold difference (e.g., at 1×10 -10 A to 1×10 -6 A). If the OTP memory cell 302 is not programmed (i.e., the transistor 303-1 still has the threshold voltage Vth2 discussed above, and the transistor 303-2 still has the threshold voltage Vth3 discussed above), then the read current of the transistor 303-1 in the OTP memory cell 302 will be substantially the same as the read current of the transistor 303-2 in the OTP memory cell 302 during reading (i.e., the current difference between the read current of the transistor 303-1 and the read current of the transistor 303-2 will be less than the second predetermined threshold difference).

[0175] Therefore, according to the comparison, it is possible to know the logic state of the OTP memory cell 302. For example, if the read current of the transistor 303-1 in the OTP memory cell 302 is different from the read current of the transistor 303-2 in the OTP memory cell 302, the logic state of the OTP memory cell 302 is at the logic state "0", and if the read current of the transistor 303-1 in the OTP memory cell 302 is approximately equal to the read current of the transistor 303-2 in the OTP memory cell 302, the logic state of the OTP memory cell 3102 is at the logic state "1".

[0176] The OTP memory cell 302 discussed above shows a FinFET structure. In some embodiments, the transistors 303 - 1 and 303 - 2 in the OTP memory cell 302 may be gate-all-around (GAA) transistors. Fig. 7A Some embodiments according to the present invention show that before the OTP memory device 300 is programmed, Figure 5 FIG. 1 is an XZ cross-sectional view of the OTP memory device 300 having an OTP memory cell 302 along line segment BB′, wherein the OTP memory cell 302 has a GAA structure. Fig. 7A The OTP memory cell 302 is shown with Fig. 6A The OTP memory cell 302 is similar to the OTP memory cell 302 shown, except that the OTP memory cell 302 includes more channel layers to construct a GAA structure. Fig. 7A As shown, each of transistors 303-1 and 303-2 in OTP memory cell 302 includes channel layers 316-1', 316-2', and 316-3' (collectively referred to as channel layers 316'). Channel layers 316' are suspended above substrate 312 and stacked in the Z direction.

[0177] Similar to the above discussion, the gate structure 306 wraps and / or surrounds the suspended, vertically stacked channel layers 316' in the channel region 304ch of the active region 304. More specifically, the gate dielectric layer 318 of the gate structure 306 (gate structure 307) surrounds each of the channel layers 316', and the gate electrode layer 320 of the gate structure 306 (gate structure 307) surrounds each of the gate dielectric layer 318 and the channel layer 316', as shown in FIG. Fig. 7A shown.

[0178] Similarly, according to some embodiments of the present invention, having Fig. 7A The OTP memory device 300 of the GAA structured OTP memory cell 302 is shown unprogrammed. Figure 7B Some embodiments according to the present invention show that after the OTP memory device 300 is programmed, Figure 5 FIG. 1 is an XZ cross-sectional view of the OTP memory device 300 having an OTP memory cell 302 along line segment BB′, wherein the OTP memory cell 302 has a GAA structure.

[0179] Similarly, in the programming operation of the OTP memory device 300, in order to program the OTP memory cell 302, the end 306e-1 and the end 306e-4 of the gate structure 306 (specifically, the gate electrode layer 320) are respectively connected to different voltages. Through the gate contact window 310, the end 306e-1 of the gate electrode layer 320 is connected to the voltage VG1 discussed above, and the end 306e-2 of the gate electrode layer 320 is connected to the voltage VG2 discussed above, so that a programming current is generated along the gate structure 306 (specifically, the gate electrode layer 320). In addition, the source / drain contact window 308 is floating during the programming of the OTP memory cell 302.

[0180] After the end portions 306e-1 and 306e-4 are connected to the voltages VG1 and VG2, respectively, and the source / drain contact window 308 is floating, the gate electrode layer 320 changes, such as Figure 7B As shown. Compared with the original gate electrode layer 320 (shown as a dotted line), the shape and position of the gate electrode layer 320 are also changed. As described above, the voltage difference between the voltages VG1 and VG2 causes electromigration, causing the shape and position of the gate electrode layer 320 to change. Similarly, if the voltage VG1 is less than the voltage VG2, the gate electrode layer 320 is shifted to the right, as shown in FIG. Figure 7B According to some embodiments, if the voltage VG1 is greater than the voltage VG2 , the gate electrode layer 320 is shifted to the left.

[0181] like Fig. 7A As shown, before programming of the OTP memory cell 302, the gate electrode layer 320 has a thickness T7 from the edge of the end 306e-1 of the gate electrode layer 320 to the channel layer 316' of the transistor 303-1 in the X direction, and a thickness T8 from the edge of the end 306e-4 of the gate electrode layer 320 to the channel layer 116' of the transistor 303-2 in the X direction. In some embodiments, the thickness T7 is equal to the thickness T8, as shown in FIG. Fig. 7A After programming of the OTP memory cell 302, the thickness T7 of the gate electrode layer 320 changes to a thickness T7', and the thickness T8 of the gate electrode layer 320 changes to a thickness T8'.

[0182] In the case where the voltage VG1 is less than the voltage VG2 during programming, the thickness T7′ is less than the thickness T8′ after programming. Figure 7B . In other words, thickness T7 is reduced to thickness T7', and thickness T8 is increased to thickness T8'. Similarly, in the case where voltage VG1 is greater than voltage VG2 during programming, thickness T7' is greater than thickness T8' after programming. In addition, after programming of OTP memory cell 302, the top surface of gate electrode layer 320 is non-planar. In some embodiments, after programming of OTP memory cell 302, gate electrode layer 320 has an inclined top surface, such as Figure 7B In some embodiments, the thickness T7 or T8 of the gate electrode layer 320 before programming is reduced to zero (0) after programming (ie, the thickness T7' or the thickness T8' is zero (0)).

[0183] In addition, if Fig. 7AAs shown, before programming of the OTP memory cell 302, the gate electrode layer 320 has a thickness Th3 from the topmost surface of the channel layer 316' of the transistor 303-1 to the top surface of the gate electrode layer 320 in the Z direction, and a thickness Th4 from the topmost surface of the channel layer 316' of the transistor 303-2 to the top surface of the gate electrode layer 320 in the Z direction. In some embodiments, the thickness Th3 is equal to the thickness Th4, as shown in FIG. Fig. 7A After programming of the OTP memory cell 302, the thickness Th3 of the gate electrode layer 320 changes to the thickness Th3', and the thickness Th4 of the gate electrode layer 320 changes to the thickness Th4'.

[0184] In the case where the voltage VG1 is less than the voltage VG2 during programming, the thickness Th3′ is less than the thickness Th4′ after programming. Figure 7B In other words, the thickness Th3 is reduced to the thickness Th3', and the thickness Th4 is increased to the thickness Th4'. Similarly, in the case where the voltage VG1 is greater than the voltage VG2 during programming, the thickness Th3' is greater than the thickness Th4' after programming.

[0185] Similarly, due to such a change in position and shape of the gate electrode layer 320, the gate control of the gate structure 306 (or the gate structure 307) changes. Therefore, before programming, the transistor 303-1 has a threshold voltage Vth2, and the transistor 303-2 has a threshold voltage Vth3. In some embodiments, before programming, the threshold voltage Vth2 of the transistor 303-1 and the threshold voltage Vth3 of the transistor 303-2 are the same. After programming of the OTP memory cell 302, the transistor 303-1 has a threshold voltage Vth2', and the transistor 303-2 has a threshold voltage Vth3', as described above. In this way, according to the read currents of the transistors 303-1 and 303-2 in the OTP memory cell 302 during the period when the OTP memory cell 302 is read, it can be known whether the OTP memory cell 302 has been programmed.

[0186] Similarly, in a read operation of the OTP memory device 300, in order to read the OTP memory cell 302, the end 306e-1 or the end 306e-4 of the gate structure 306 (gate structure 307) (specifically, the gate electrode layer 320) is connected to a voltage of about 0V or slightly greater than 0V, one of the source / drain regions 304sd of the active region 304-1 is connected to 0V and the other of the source / drain regions 304sd of the active region 304-1 is connected to the power supply voltage V DD , one of the source / drain regions 304sd of the active region 304-2 is connected to 0V and the other of the source / drain regions 304sd of the active region 304-2 is connected to the power supply voltage VDD , so that the transistors 303-1 and 303-2 in the OTP memory cell 302 generate a read current. If the OTP memory cell 302 has not been programmed (i.e., the position and shape of the gate electrode layer 320 remain the position and shape shown in FIG. 7A, and the transistor 303-1 still has the threshold voltage Vth2 discussed above, and the transistor 303-2 still has the threshold voltage Vth3 discussed above), then the current Iread2 of the transistor 303-1 and the current Iread3 of the transistor 303-2 in the OTP memory cell 302 are read. If the OTP memory cell 302 has been programmed (i.e., the position and shape of the gate electrode layer 320 are changed to Figure 7B The position and shape shown, and the transistor 303-1 has the threshold voltage Vth2' discussed above, and the transistor 303-2 has the threshold voltage Vth3' discussed above), then the Iread2' of the transistor 303-1 and the current Iread3' of the transistor 303-2 in the OTP memory cell 302 are read.

[0187] Similarly, the threshold voltage Vth2 of transistor 303-1 and the threshold voltage Vth3 of transistor 303-2 before programming are the same, and the threshold voltage Vth2' of transistor 303-1 and the threshold voltage Vth3' of transistor 303-2 after programming are different. As a result, if the OTP memory cell 302 has been programmed, the read current of transistor 303-1 in the OTP memory cell 302 will be different from the read current of transistor 303-2 in the OTP memory cell 302 during reading. If the OTP memory cell 302 has not been programmed, the read current of transistor 303-1 in the OTP memory cell 302 will be substantially the same as the read current of transistor 303-2 in the OTP memory cell 302 during reading.

[0188] Therefore, according to the comparison, it is possible to know the logic state of the OTP memory cell 302. For example, if the read current of the transistor 303-1 in the OTP memory cell 302 is different from the read current of the transistor 303-2 in the OTP memory cell 302, the logic state of the OTP memory cell 302 is at the logic state "0", and if the read current of the transistor 303-1 in the OTP memory cell 302 is approximately equal to the read current of the transistor 303-2 in the OTP memory cell 302, the logic state of the OTP memory cell 3102 is at the logic state "1".

[0189] Figure 8 and Fig. 9Top views (or layouts) of OTP memory devices 400 and 500 are shown according to some alternative embodiments of the present invention. Figure 8 and Fig. 9 The OTP memory devices 400 and 500 shown are similar to Figure 1 and Figure 5 The OTP memory devices 100 and 300 are similar except that more gate contact windows are provided at the ends of the gate structure (gate electrode layer). Figure 8 As shown, in order to enhance the electromigration effect, each of the ends 106-1 and 106-2 of the gate structure 106 (gate electrode layer 120) of the OTP memory cell 102 may include at least two gate contact windows 110. More specifically, two gate contact windows 110 are above the end 106-1 of the gate structure 106 (gate electrode layer 120) and electrically connected to the end 106-1 of the gate structure 106 (gate electrode layer 120), and another two gate contact windows 110 are above the end 106-2 of the gate structure 106 (gate electrode layer 120) and electrically connected to the end 106-2 of the gate structure 106 (gate electrode layer 120). The two gate contact windows 110 above the end 106-1 of the gate structure 106 are connected together to the voltage VG1 discussed above, and the other two gate contact windows 110 above the end 106-2 of the gate structure 106 are connected together to the voltage VG2 discussed above. As a result, the end 106 - 1 of the gate structure 106 is connected to the voltage VG1 through the two gate contacts 110 , and the end 106 - 2 of the gate structure 106 is connected to the voltage VG2 through the two gate contacts 110 .

[0190] Similarly, Fig. 9 As shown, each of the ends 306e-1 and 306e-4 of the gate structure 306 (gate electrode layer 320) of the OTP memory cell 302 includes two gate contact windows 310. The two gate contact windows 310 above the end 306e-1 of the gate structure 306-1 are connected together to the voltage VG1 discussed above, and the other two gate contact windows 310 above the end 306e-4 of the gate structure 306-2 are connected together to the voltage VG2 discussed above. In this way, the end 306e-1 of the gate structure 306-1 is connected to the voltage VG1 through the two gate contact windows 310, and the end 306e-4 of the gate structure 306-2 is connected to the voltage VG2 through the two gate contact windows 310.

[0191] Compared to the prior art, embodiments of the present invention provide multiple advantages, and it should be understood that other embodiments may provide different advantages, and it is not necessary to discuss all advantages here, and all embodiments have no specific advantages. For example, the embodiments discussed herein include an OTP memory device having an OTP memory cell, and the OTP memory cell has a FinFET or GAA structure. The OTP memory cell is programmed by an electromigration mechanism, so that the OTP memory cell can be constructed by one or two transistors, thereby obtaining an OTP memory cell with low occupied area / low area loss. In addition, due to the electromigration mechanism used for programming, the OTP memory cell can be programmed at a relatively lower voltage than the existing OTP memory cell. Therefore, the power consumption of the OTP memory cell is improved.

[0192] The foregoing text summarizes the features of many embodiments so that a person skilled in the art can better understand the present invention from various aspects. A person skilled in the art should understand and can easily design or modify other manufacturing processes and structures based on the present invention to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. A person skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the present invention. Various changes, substitutions or modifications may be made to the present invention without departing from the spirit and scope of the present invention.

Claims

1. A one-time programmable memory device, comprising: The first active area includes: A first channel region having a first channel layer; and A plurality of first source / drain regions are disposed on opposite sides of the first channel region in the Y direction, wherein the first source / drain region has a plurality of first source / drain features electrically connected to the first channel layer; A first gate dielectric layer surrounding the first channel layer; and a first gate electrode layer extending in the X direction and surrounding the first channel layer and the first gate dielectric layer, wherein the first thickness of the first gate electrode layer is equal to the second thickness of the first gate electrode layer, the first thickness is from the first edge of the first end of the first gate electrode layer to the first channel layer in the X direction, the second thickness is from the second edge of the second end of the first gate electrode layer to the first channel layer in the X direction, and the logic state of the one-time programmable memory device is in the first logic state, Wherein, in a first programming operation of the one-time programmable memory device, after the first end is connected to a first voltage and the second end is connected to a second voltage different from the first voltage, the first thickness is different from the second thickness, and the logic state of the one-time programmable memory device is in a second logic state different from the first logic state.

2. The one-time programmable memory device according to claim 1, The first voltage is lower than the second voltage. After the first end is connected to the first voltage and the second end is connected to the second voltage, the first thickness is smaller than the second thickness.

3. The one-time programmable memory device of claim 1 , wherein in a read operation of the one-time programmable memory device, the first end and the second end are connected to 0V, one of the first source / drain regions is connected to 0V, and the other of the source / drain regions is connected to a power supply voltage higher than 0V.

4. The one-time programmable memory device of claim 1 , wherein the one-time programmable memory device has a first threshold voltage before the first end is connected to the first voltage and the second end is connected to the second voltage, and has a second threshold voltage different from the first threshold voltage after the first end is connected to the first voltage and the second end is connected to the second voltage.

5. The one-time programmable memory device of claim 1 , further comprising: The second active region is arranged in the X direction with the first active region, and includes: a second channel region having a second channel layer; and A plurality of second source / drain regions disposed on opposite sides of the second channel region in the Y direction, wherein the second source / drain region has a plurality of second source / drain features electrically connected to the second channel layer; A second gate dielectric layer surrounding the second channel layer; and a second gate electrode layer extending in the X direction and surrounding the second channel layer and the second gate dielectric layer, Before the first end is connected to the first voltage and the second end is connected to the second voltage, the third thickness of the second gate electrode layer is equal to the first thickness, and the third thickness is from the third edge of the third end of the second gate electrode layer to the second channel layer in the X direction, Before the first end is connected to the first voltage and the second end is connected to the second voltage, the fourth thickness of the second gate electrode layer is equal to the second thickness, and the fourth thickness is from the fourth edge of the fourth end of the second gate electrode layer to the second channel layer in the X direction, After the first end is connected to the first voltage and the second end is connected to the second voltage, the first thickness is different from the third thickness, and the second thickness is different from the fourth thickness.

6. The one-time programmable memory device as claimed in claim 5, wherein in a read operation of the one-time programmable memory device, the first end, the second end, the third end, and the fourth end are connected to 0V, one of the first source / drain regions is connected to 0V, the other of the first source / drain regions is connected to a power supply voltage higher than 0V, one of the second source / drain regions is connected to 0V, and the other of the second source / drain regions is connected to the power supply voltage.

7. The one-time programmable memory device of claim 1 , further comprising: The second active region is arranged in the X direction with the first active region, and includes: a second channel region having a second channel layer; and A plurality of second source / drain regions disposed on opposite sides of the second channel region in the Y direction, wherein the second source / drain region has a plurality of second source / drain features electrically connected to the second channel layer; A second gate dielectric layer surrounding the second channel layer; and a second gate electrode layer extending in the X direction and surrounding the second channel layer and the second gate dielectric layer, wherein the second gate electrode layer has a third end and a fourth end on opposite sides of the second gate electrode layer in the X direction, and the third end of the second gate electrode layer contacts the second end of the first gate electrode layer in the X direction, Before the second programming operation of the one-time programmable memory device, the first thickness is equal to the third thickness of the second gate electrode layer, and the third thickness is from the third edge of the fourth end of the second gate electrode layer to the second channel layer in the X direction. Wherein in the above-mentioned second programming operation of the above-mentioned one-time programmable memory device, after the above-mentioned first end is connected to the above-mentioned first voltage and the above-mentioned fourth end is connected to the above-mentioned second voltage, the above-mentioned first thickness is different from the above-mentioned third thickness, and the above-mentioned logic state of the above-mentioned one-time programmable memory device is in the above-mentioned second logic state.

8. The one-time programmable memory device of claim 1 , further comprising: A first gate contact window and a second gate contact window, above the first end portion of the first gate electrode layer; as well as A third gate contact window and a fourth gate contact window are above the second end of the first gate electrode layer, The first end is connected to the first voltage through the first gate contact window and the second gate contact window, and the second end is connected to the second voltage through the third gate contact window and the fourth gate contact window.

9. The one-time programmable memory device of claim 1, wherein the first channel layer is above the substrate and protrudes from the substrate in a Z direction.

10. The one-time programmable memory device of claim 1, wherein the first channel layer is above the substrate and separated from the substrate in the Z direction, and wherein the first active region further comprises a second channel layer above the first channel layer and separated from the first channel layer in the Z direction.

11. The one-time programmable memory device of claim 1 , wherein after the first end is connected to the first voltage and the second end is connected to the second voltage, the first edge of the first end of the first gate electrode layer is aligned with a sidewall of the first channel layer.

12. A one-time programmable (OTP) memory device comprising: A first memory unit comprises: The first active area includes: A first channel region having a first channel layer; and a plurality of first source / drain regions disposed on opposite sides of the first channel region in the Y direction, wherein the first source / drain region has a plurality of first source / drain features electrically connected to the first channel layer; and A first gate structure extends in the X direction and is connected to the first active region to construct a first transistor. wherein before a first programming operation of the one-time programmable memory device, the first transistor has a first threshold voltage, and a logic state of the one-time programmable memory device is in a first logic state, wherein in the first programming operation of the one-time programmable memory device, the first end of the first gate structure is connected to a first voltage, and the second end of the first gate structure is connected to a second voltage different from the first voltage, so that a programming current is generated along the first gate structure, wherein the voltage difference between the first voltage and the second voltage is greater than the electromigration threshold, After the first programming operation of the one-time programmable memory device, the first transistor has a second threshold voltage different from the first threshold voltage, and the logic state of the one-time programmable memory device is in a second logic state different from the first logic state.

13. The one-time programmable memory device of claim 12 , wherein in a read operation of the one-time programmable memory device, the first end and the second end are connected to 0V, one of the first source / drain regions is connected to 0V, and the other of the source / drain regions is connected to a power supply voltage higher than 0V.

14. The one-time programmable memory device of claim 12, further comprising: A first gate contact window and a second gate contact window, above the first end of the first gate structure; as well as A third gate contact window and a fourth gate contact window are above the second end of the first gate structure, The first end is connected to the first voltage through the first gate contact window and the second gate contact window, and the second end is connected to the second voltage through the third gate contact window and the fourth gate contact window.

15. The one-time programmable memory device of claim 12, further comprising: A second memory unit comprises: The second active region is arranged in the X direction with the first active region, and includes: a second channel region having a second channel layer; and a plurality of second source / drain regions disposed on opposite sides of the second channel region in the Y direction, wherein the second source / drain regions have a plurality of second source / drain features electrically connected to the second channel layer; and A second gate structure extends in the X direction and is connected to the second channel region to construct a second transistor. wherein before the first programming operation of the one-time programmable memory device, the second transistor has the first threshold voltage, After the first programming operation of the one-time programmable memory device, the second transistor has the first threshold voltage different from the second threshold voltage of the first transistor.

16. The one-time programmable memory device as claimed in claim 15, wherein in a read operation of the one-time programmable memory device, the first end and the second end are connected to 0V, the third end and a fourth end of the second gate structure are connected to 0V, one of the first source / drain regions is connected to 0V, the other of the first source / drain regions is connected to a power supply voltage higher than 0V, one of the second source / drain regions is connected to 0V, and the other of the second source / drain regions is connected to the power supply voltage.

17. The one-time programmable memory device of claim 12, wherein the first memory unit further comprises: The second active region is arranged in the X direction with the first active region, and includes: a second channel region having a second channel layer; and a plurality of second source / drain regions disposed on opposite sides of the second channel region in the Y direction, wherein the second source / drain regions have a plurality of second source / drain features electrically connected to the second channel layer; and A second gate structure extends in the X direction and is connected to the second active region to construct a second transistor. wherein the second gate structure has a third end and a fourth end on opposite sides of the second gate structure in the X direction, the third end of the second gate structure contacts the second end of the first gate structure in the X direction, wherein before the second programming operation of the one-time programmable memory device, the first transistor has a third threshold voltage and the second transistor has a fourth threshold voltage, the third threshold voltage is the same as the fourth threshold voltage, and the logic state of the one-time programmable memory device is in the first logic state, wherein in a second programming operation of the one-time programmable memory device, the first end of the first gate structure is connected to the first voltage, and the fourth end of the second gate structure is connected to the second voltage different from the first voltage, so that a programming current is generated along the first gate structure and the second gate structure, Wherein, after the above-mentioned second programming operation of the above-mentioned one-time programmable memory device, the above-mentioned first transistor has a fifth threshold voltage different from the above-mentioned third threshold voltage, the above-mentioned second transistor has a sixth threshold voltage different from the above-mentioned fourth threshold voltage and the above-mentioned fifth threshold voltage, and the above-mentioned logic state of the above-mentioned one-time programmable memory device is in the above-mentioned second logic state different from the above-mentioned first logic state.

18. The one-time programmable memory device of claim 12, wherein the first channel layer is above the substrate and protrudes from the substrate in a Z direction.

19. The one-time programmable memory device of claim 12, wherein the first channel layer is above the substrate and separated from the substrate in the Z direction, and wherein the first active region further comprises a second channel layer above the first channel layer and separated from the first channel layer in the Z direction.

20. The one-time programmable memory device of claim 12 , wherein the first gate structure comprises a first gate dielectric layer surrounding the first channel layer, and a first gate electrode layer extending in the X direction and surrounding the first channel layer and the first gate dielectric layer, and after the first end of the first gate structure is connected to the first voltage and the second end of the first gate structure is connected to the second voltage, a first edge of the first gate electrode layer is aligned with a sidewall of the first channel layer.

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