LPDDR5 chip test method and adapter plate

Abstract

The invention discloses an LPDDR5 chip testing method and an adapter plate, and relates to the technical field of chip testing. The method comprises the following steps: designing an adapter plate according to the layout of an LPDDR5 chip; the periphery of the bottom of the adapter plate is subjected to groove milling, so that the adapter plate is divided into an upper layer part and a lower layer part, and four extension plates are formed; a test bonding pad is arranged on the surface of each extension plate; the test points of the line routing are led out to the surface of the adapter plate and are connected with the corresponding test bonding pads; welding an LPDDR5 chip on the surface of the adapter plate; obtaining a test circuit board; the bottom surface of the adapter plate is welded in the mounting area, so that the LPDDR5 chip is connected with the test circuit board through the adapter plate; the test bonding pad is connected with an oscilloscope, the test circuit board tests the LPDDR5 chip, and a test result is displayed through the oscilloscope. According to the method, various testing signals can be led to the oscilloscope through the testing bonding pad of the adapter plate, and accurate testing of the chip is achieved.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a LPDDR5 chip testing method and an adapter board. Background Art

[0002] LPDDR5, or Low Power Double Data Rate 5, is a low-power double data rate memory and a new generation of low-power memory technology with the characteristics of low power consumption, high data transfer rate, low latency and support for larger capacity. During the production process of LPDDR5 chips, they need to be tested to verify whether their various functions are normal. In the prior art, when testing LPDDR5 chips, the LPDDR5 chips are usually soldered to a test circuit board, and the chips are tested through the test circuit board. However, in this way, since the entire chip is soldered on the test circuit board, it is only possible to simply verify whether the LPDDR5 chip can work normally, and it is impossible to lead out the various test points of the LPDDR5 chip and conduct a more in-depth analysis of the various signals of the LPDDR5 chip to accurately evaluate the performance of the LPDDR5 chip. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a LPDDR5 chip testing method and an adapter board, which guide various test signals to an oscilloscope through the test pads of the adapter board to achieve accurate testing of the LPDDR5 chip.

[0004] In a first aspect, according to an LPDDR5 chip testing method according to an embodiment of the present invention, the method comprises the following steps: According to the layout of the LPDDR5 chip, an adapter board is designed; the number of layers of the adapter board is greater than two, the inner layer board of the adapter board is provided with a circuit routing, the surface of the adapter board is provided with a surface pad, the bottom surface of the adapter board is provided with a bottom pad, and the surface pad is connected to the bottom pad through a via; According to a preset depth and a preset width, grooves are milled around the bottom of the adapter plate, so that the adapter plate is divided into an upper layer and a lower layer, the surface area of ​​the upper layer is larger than the surface area of ​​the lower layer, and the surface around the upper layer protrudes from the surface around the lower layer, forming four extension plates; Disposing a test pad on the surface of each of the extension plates; Leading the test points of the line routing to the surface of the adapter board and connecting them to the corresponding test pads; Soldering the LPDDR5 chip on the surface of the adapter board; Obtain a test circuit board; the test circuit board is provided with a mounting area; Welding the bottom surface of the adapter board to the mounting area, so that the LPDDR5 chip is connected to the test circuit board through the adapter board; The test pad is connected to an oscilloscope, the test circuit board tests the LPDDR5 chip, and the test result is displayed through the oscilloscope.

[0005] According to some embodiments of the present invention, the adapter board is a six-layer board, including a top board, four inner-layer boards and a bottom board, the thickness of the bottom board is greater than the sum of the thicknesses of the top board and the four inner-layer boards; the steps of milling grooves around the bottom of the adapter board according to a preset depth and a preset width, so that the adapter board is divided into an upper layer and a lower layer, the surface area of ​​the upper layer is greater than the surface area of ​​the lower layer, and the surface of the upper layer protrudes from the surface of the lower layer to form four extension boards, include: According to a preset depth and a preset width, grooves are milled around the bottom of the bottom plate, so that the bottom of the bottom plate serves as the lower layer, and the top of the bottom plate, the top plate, and the four inner layer plates serve as the upper layer; wherein the preset depth is less than the thickness of the bottom plate; A gap is formed between any two adjacent extension plates.

[0006] According to some embodiments of the present invention, the step of leading the test point of the line routing to the surface of the adapter board and connecting it to the corresponding test pad includes: Lead out the WCK differential signal, RDQS differential signal and two random data single-ended signals of each channel of the LPDDR5 chip as the first signal test point; Lead out the clock differential signal, two random CA signals and two random CS signals of each channel of the LPDDR5 chip as the second signal test point; Lead out the VDDQ signal, VDD1 signal, VDD2H signal and VDD2L signal of the LPDDR5 chip as power supply test points; The first signal test point, the second signal test point and the power supply test point are all connected to the corresponding test pads. According to some embodiments of the present invention, the step of leading the test points of the line routing to the surface of the adapter board and connecting them to the corresponding test pads further includes: GND ground holes are evenly arranged around the WCK differential signal, the RDQS differential signal, the data single-ended signal, the clock differential signal, the CA signal, the CS signal, the VDDQ signal, the VDD1 signal, the VDD2H signal and the VDD2L signal to achieve ground package setting; Lead out the signal of the GND ground hole as a ground test point; Connect the ground test point to the corresponding test pad. According to some embodiments of the present invention, the test pad includes a signal test pad and a ground test pad, the first signal test point, the second signal test point and the power supply test point are respectively connected to the corresponding signal test pads, the ground test point is connected to the ground test pad, and the shape of the signal test pad is different from the shape of the ground test pad.

[0007] According to some embodiments of the present invention, the signal impedance of the WCK differential signal, the RDQS differential signal, and the clock differential signal is lower than 100Ω, the signal impedance of the data single-ended signal, the CA signal, and the CS signal is lower than 50Ω, and the routing width of the VDDQ signal, the VDD1 signal, the VDD2H signal, and the VDD2L signal is greater than 12 mil.

[0008] According to some embodiments of the present invention, the WCK differential signal, the RDQS differential signal, the data single-ended signal, the clock differential signal, the CA signal, the CS signal, the VDDQ signal, the VDD1 signal, the VDD2H signal, and the VDD2L signal are led out to the surface of the adapter board through the conductive blind holes of the 1-3 layers and connected to the corresponding test pads.

[0009] According to some embodiments of the present invention, the dielectric constant of the plate material of the adapter plate is lower than 3.71, and the dielectric loss factor is lower than 0.002 at a frequency of 1 GHz.

[0010] According to some embodiments of the present invention, the test pads are arranged around the periphery of the adapter board at equal intervals, and the interval between adjacent test pads is greater than 0.75 mm.

[0011] In the second aspect, according to the adapter board of the embodiment of the present invention, the number of layers of the adapter board is greater than two, the inner layer board of the adapter board is provided with circuit routing, the surface of the adapter board is provided with surface pads, the bottom surface of the adapter board is provided with bottom pads, and the surface pads are connected to the bottom pads through conductive holes; the adapter board is divided into an upper layer part and a lower layer part, the surface area of ​​the upper layer part is greater than the surface area of ​​the lower layer part, and the surface around the upper layer part protrudes from the surface around the lower layer part to form four extension plates, and the surface of each extension plate is provided with a test pad; the test points of the circuit routing are led out to the surface of the adapter board and connected to the corresponding test pads. The LPDDR5 chip testing method and adapter board according to the embodiments of the present invention have at least the following beneficial effects: by designing an adapter board and designing a test pad on the adapter board, the LPDDR5 chip can be soldered on the adapter board, and then the adapter board is soldered on the test circuit board, and the connection between the test circuit board and the LPDDR5 chip is achieved through the adapter board. During the process of testing the adapter board by the test circuit board, the various required test signals can be led to the oscilloscope through the test pad to achieve accurate testing of the LPDDR5 chip.

[0012] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 It is a structural schematic diagram of an adapter board according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the internal wiring of the adapter board according to an embodiment of the present invention; Figure 3 is a schematic top view of an adapter plate according to an embodiment of the present invention; Figure 4 A schematic front view of an adapter plate according to an embodiment of the present invention; Figure 5 This is a flowchart of the steps of the LPDDR5 chip testing method according to an embodiment of the present invention; Reference numerals: The adapter board 100 , the top board 110 , the inner board 120 , the bottom board 130 , the upper layer 140 , the lower layer 150 , the surface pads 200 , the test pads 300 , the signal test pads 310 , the ground test pads 320 , the extension board 400 , and the notch 410 . DETAILED DESCRIPTION

[0014] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and are not to be construed as limitations on the present application. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0015] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0016] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present invention and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0017] Reference to "embodiments" in the present invention means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0018] In the prior art, when testing the LPDDR5 chip, the LPDDR5 chip is usually soldered on a test circuit board and the chip is tested through the test circuit board. However, in this way, since the chip is soldered on the test circuit board, it is only possible to simply verify whether the LPDDR5 chip can work normally, and it is impossible to lead out the various test points of the LPDDR5 chip and conduct a more in-depth analysis of the various signals of the LPDDR5 chip to accurately evaluate the performance of the LPDDR5 chip.

[0019] To this end, an embodiment of the present invention provides an LPDDR5 chip testing method and an adapter board. By designing an adapter board and designing a test pad on the adapter board, the LPDDR5 chip can be soldered on the adapter board, and then the adapter board is soldered on a test circuit board. The connection between the test circuit board and the LPDDR5 chip is achieved through the adapter board. In the process of the test circuit board testing the adapter board, the required various test signals can be led to the oscilloscope through the test pad to achieve accurate testing of the LPDDR5 chip.

[0020] The LPDDR5 chip testing method and adapter board according to an embodiment of the present invention are described in detail below with reference to the accompanying drawings.

[0021] On the one hand, the embodiment of the present invention provides a transfer board 100, referring to Figures 1 to 4 , the number of layers of the adapter board 100 is greater than two layers, the inner layer board of the adapter board 100 is provided with a circuit trace (not shown in the figure), the surface of the adapter board 100 is provided with a surface pad 200, and the bottom surface of the adapter board 100 is provided with a bottom pad (not shown in the figure), and the surface pad 200 is connected to the bottom pad through a conductive hole; the adapter board 100 is divided into an upper layer 140 and a lower layer 150, the surface area of ​​the upper layer 140 is greater than the surface area of ​​the lower layer 150, and the surface of the upper layer 140 protrudes from the surface of the lower layer 150 to form four extension plates 400, and the surface of each extension plate 400 is provided with a test pad 300; the test point of the circuit trace is led out to the surface of the adapter board 100 and connected to the corresponding test pad 300.

[0022] It should be noted that the surface pads 200 and the bottom pads of the adapter board 100 correspond one to one, and the two are connected through a via hole to achieve the conduction of the circuits of each layer of the adapter board 100. At the same time, the design of the surface pads 200 and the bottom pads corresponds to the layout of the LPDDR5 chip. The circuit routing inside the adapter board 100 includes various circuits required by the LPDDR5 chip, such as power lines, data lines, clock lines, control lines, ground lines, etc. For the circuits that need to be tested, the test points of the corresponding circuit routing are led out to the surface of the adapter board 100 and connected to the corresponding test pads 300, such as Figure 2As shown. The surface pad 200 is connected to the bottom pad by a through hole to achieve the effect of electrical interconnection, and the signal test line segment of the line routing is led out in the middle layer to the surface test pad 300, that is, a T-shaped topology is adopted. The signal test line segment led out needs to be as short as possible to reduce the reflection caused by the T-shaped topology. When the LPDDR5 chip is to be tested, the LPDDR5 chip is first soldered to the surface of the adapter board 100, and then the adapter board 100 is soldered to the test circuit board, so that the test circuit board can drive the LPDDR5 chip to start working. During the operation of the LPDDR5 chip, for the items to be tested, the corresponding test pad 300 is connected to the oscilloscope, and the various waveforms in the working process of the LPDDR5 chip can be displayed and measured through the oscilloscope, thereby realizing various parameter tests of the LPDDR5 chip, such as testing whether the eye width and eye height of the eye diagram of the LPDDR5 chip meet the design standards, and testing whether the signal integrity of the LPDDR5 chip meets the requirements. At the same time, since the test circuit board is designed with a test circuit, capacitors, resistors, MOS tubes and other components are needed, in order to avoid the adapter board 100 from colliding with the components on the test circuit board when the adapter board 100 is installed on the test circuit board, such as Figure 4 As shown, the depth-controlled milling process is used to mill grooves around the bottom of the adapter plate 100, so that the adapter plate 100 is divided into an upper portion 140 and a lower portion 150, and the surface area of ​​the upper portion 140 is larger than the surface area of ​​the lower portion 150, forming a T shape as a whole. In this example, the total thickness of the adapter plate 100 is 2.4 mm, and the bottom is milled by 1.6 mm of thickness using the depth-controlled milling process, so as to avoid collision between the adapter plate 100 and the parts on the test circuit board after welding. It should be noted that the total thickness of the adapter plate 100 and the milled thickness can be adjusted according to actual needs, and are not limited to this.

[0023] According to the adapter board 100 of the embodiment of the present invention, by designing the circuit routing inside and designing the test pad 300 on the surface, when testing the LPDDR5 chip, the required signal can be easily led out through the test pad 300 and connected to the oscilloscope, so as to implement the test of the LPDDR5 chip, improve the test efficiency, and meet the test requirements of various test parameters. At the same time, the design of the adapter board 100 makes the welding of the LPDDR5 chip more convenient, and the adapter board 100 will not interfere with the components on the test circuit board.

[0024] Furthermore, if Figure 4As shown, in some embodiments of the present invention, the adapter board 100 adopts a six-layer board design, including a top plate 110, a four-layer inner plate 120 and a bottom plate 130, wherein the thickness of the bottom plate 130 is greater than the sum of the thicknesses of the top plate 110 and the four-layer inner plate 120; when the bottom of the adapter board 100 is milled, the bottom of the bottom plate 130 is milled, and the depth of the milling groove does not exceed the thickness of the bottom plate 130, so that the top plate 110 and the four-layer inner plate 120 are both located in the upper part 140 of the adapter board 100, avoiding affecting the line routing in the inner plate 120, and at the same time, the stacking spacing between the top plate 110 and the four-layer inner plate 120 is as small as possible, so as to achieve good signal shielding and impedance reference effects when testing the line routing. With regard to the selection of the board material of the adapter board 100, a high-speed board with good low dielectric constant and low dielectric loss tangent should be selected to reduce the loss during signal transmission. In this example, the dielectric constant of the plate material of the adapter plate 100 is lower than 3.71, and the dielectric loss factor is lower than 0.002 at a frequency of 1 GHz, meeting the requirements of high-speed signal transmission and low loss.

[0025] In order to test the LPDDR5 chip, it is necessary to select the key signals of the LPDDR5 chip as test points. In this example, the following signals are used as test points: For data lines: the WCK differential signal, RDQS differential signal and two random data single-ended signals of each channel of the LPDDR5 chip are brought out as the first signal test point; In terms of clock and address / control lines: the clock differential signal (CK), two random CA signals, and two random CS signals of each channel of the LPDDR5 chip are brought out as the second signal test point.

[0026] Power test point: Bring out the VDDQ, VDD1, VDD2H, and VDD2L of the LPDDR5 chip as power test points.

[0027] After selecting the above test points, all the test points are connected to the corresponding test pads 300 by routing. It should be noted that the WCK differential signal is the clock signal used for write operation in the LPDDR5 chip, that is, Write Clock, which is responsible for synchronizing the data transmission from the host to the LPDDR5 chip. The RDQS differential signal is a differential signal pair used for read operation in the LPDDR5 chip, which is used to synchronize the data transmission from the LPDDR5 chip to the host. The LPDDR5 chip achieves more efficient data transmission by introducing the WCK and RDQS signals. The combination of these two signals enables the LPDDR5 chip to achieve higher data transmission rates and better performance while maintaining low power consumption. The CA (Command / Address) signal is a signal used by the memory controller of the LPDDR5 chip to transmit commands, addresses, etc. to the memory device; the CS (Chip Select) signal is a signal used by the memory controller of the LPDDR5 chip to select a specific memory chip. In the LPDDR5 chip, there are usually multiple memory chips coexisting, and the CS signal is used to distinguish and control these chips. VDDQ, VDD1, VDD2H, and VDD2L are several voltage configuration interfaces of the LPDDR5 chip.

[0028] After selecting the first signal test point, the second signal test point and the power test point, the first signal test point, the second signal test point and the power test point also need to be connected to the ground test point as a basis to bring out the GND signal of the LPDDR5 chip as the ground test point.

[0029] like Figure 1 As shown, in some embodiments of the present invention, the signal test pad 310 corresponding to the first signal test point, the second signal test point and the power test point is designed as an elliptical pad, and the ground test pad 320 corresponding to the GND test point is designed as a rectangular pad, which is convenient for distinguishing and processing during the later test. It should be noted that the signal test pad 310 and the ground test pad 320 can also be designed as other shapes, as long as the shapes of the two are different. At the same time, each ground test pad 320 and the signal test pad 310 are arranged on the four extension plates 400 at equal intervals, and a spacing of more than 0.75mm is maintained to avoid collision of the test pens during the test. At the same time, a gap 410 is formed between any two adjacent extension plates 400, thereby leaving four corners corresponding to the four edges of the LPDDR5 chip, which is convenient for positioning the adapter board 100 when the adapter board 100 is soldered to the test circuit board.

[0030] In some embodiments of the present invention, due to the high thickness of the adapter board 100, the conductive hole connecting the surface pad 200 and the bottom pad needs to use a through hole with a hole diameter as large as possible to meet the diameter-to-depth ratio requirements in mechanical processing. The connecting via at the test pad 300 uses a 1-3 layer blind hole to connect the test pad 300 to the inner layer line routing to eliminate the reflection effect caused by the via stub. The differential signal of the adapter board 100 is controlled within 100Ω impedance, the single-ended signal is controlled within 50Ω impedance, the power routing is maintained at a routing width of more than 12mil, all routings are distributed in the inner layer, GND grounding is used, and GND ground holes are evenly punched around the signal to achieve the effect of signal shielding and reduce the crosstalk between high-speed signals.

[0031] According to the adapter board 100 of the embodiment of the present invention, by designing the circuit routing inside and designing the test pad 300 on the surface, when testing the LPDDR5 chip, the required signal can be easily led out through the test pad 300 and connected to the oscilloscope, so as to implement the test of the LPDDR5 chip, improve the test efficiency, and meet the test requirements of various test parameters. At the same time, the design of the adapter board 100 makes the welding of the LPDDR5 chip more convenient, and the adapter board 100 will not interfere with the components on the test circuit board. By designing the routing and vias of the adapter board 100, the design of the test pad, and the selection of the plate material, high-speed and high-quality signal transmission is achieved, and the accuracy of the test results is guaranteed.

[0032] On the other hand, based on the above-mentioned adapter board 100, the embodiment of the present invention also proposes a LPDDR5 chip testing method, such as Figure 5 As shown, the method comprises the following steps: Step S100: designing the adapter board 100 according to the layout of the LPDDR5 chip; Step S200: milling grooves around the bottom of the adapter plate 100 according to a preset depth and a preset width, so that the adapter plate 100 is divided into an upper portion 140 and a lower portion 150, the surface area of ​​the upper portion 140 is larger than the surface area of ​​the lower portion 150, and the surface around the upper portion 140 protrudes from the surface around the lower portion 150, forming four extension plates 400; Step S300: setting a test pad 300 on the surface of each extension board 400; Step S400: Leading the test points of the line routing to the surface of the adapter board 100 and connecting them to the corresponding test pads 300; Step S500: soldering the LPDDR5 chip to the surface of the adapter board 100; Step S600: obtaining a test circuit board; the test circuit board is provided with a mounting area; Step S700: soldering the bottom surface of the adapter board 100 to the mounting area, so that the LPDDR5 chip is connected to the test circuit board through the adapter board 100; Step S800: Connect the test pad 300 to the oscilloscope, test the LPDDR5 chip with the test circuit board, and display the test results through the oscilloscope.

[0033] Specifically, the surface of the adapter board 100 is provided with a surface pad 200, and the bottom is provided with a bottom pad. The surface pad 200 corresponds to the bottom pad one by one, and the two are connected through a via hole to realize the conduction of each layer of the circuit of the adapter board 100. At the same time, the design of the surface pad 200 and the bottom pad corresponds to the layout of the LPDDR5 chip, so that the adapter board 100 can realize the connection between the LPDDR5 chip and the test circuit board; the adapter board 100 is designed with a line routing inside, and the line routing includes various lines required by the LPDDR5 chip, such as power line, data line, clock line, control line, ground line, etc. For the circuit that needs to be tested, the test point of the corresponding line routing is led out to the surface of the adapter board 100 and connected to the corresponding test pad 300. The surface pad 200 is connected to the bottom pad by a via hole to achieve the effect of electrical interconnection, and the signal test line segment of the line routing is led out to the surface test point in the middle layer, that is, a T-shaped topology is adopted. The signal test line segment led out needs to be as short as possible to reduce the reflection caused by the T-shaped topology. When the LPDDR5 chip is to be tested, the LPDDR5 chip is first soldered to the surface of the adapter board 100, and then the adapter board 100 is soldered to the test circuit board, so that the test circuit board can drive the LPDDR5 chip to start working. During the operation of the LPDDR5 chip, for the items to be tested, the corresponding test pad 300 is connected to the oscilloscope, and the various waveforms in the operation process of the LPDDR5 chip can be displayed and measured through the oscilloscope, thereby realizing various parameter tests of the LPDDR5 chip, such as testing whether the eye width and eye height of the eye diagram of the LPDDR5 chip meet the design standards, and testing whether the signal integrity of the LPDDR5 chip meets the requirements. At the same time, since the test circuit board is designed with a test circuit, capacitors, resistors, MOS tubes and other components are needed, in order to avoid the adapter board 100 from colliding with the components on the test circuit board when the adapter board 100 is installed on the test circuit board, such as Figure 4As shown, the depth-controlled milling process is used to mill grooves around the bottom of the adapter plate 100, so that the adapter plate 100 is divided into an upper portion 140 and a lower portion 150, and the surface area of ​​the upper portion 140 is larger than the surface area of ​​the lower portion 150, forming a T shape as a whole. In this example, the total thickness of the adapter plate 100 is 2.4 mm, and the bottom is milled by 1.6 mm of thickness using the depth-controlled milling process, so as to avoid collision between the adapter plate 100 and the parts on the test circuit board after welding. It should be noted that the total thickness of the adapter plate 100 and the milled thickness can be adjusted according to actual needs, and are not limited to this.

[0034] It should be noted that the test circuit on the test circuit board is a conventional circuit for testing LPDDR5 chips, which belongs to the prior art and will not be described in detail here. At the same time, a mounting area is opened on the test circuit board for welding the adapter board 100 to avoid interference between the adapter board 100 and components in other areas of the test circuit board.

[0035] According to the LPDDR5 chip testing method of an embodiment of the present invention, an adapter board 100 is designed, and a test pad 300 is designed on the adapter board 100, so that the LPDDR5 chip can be soldered on the adapter board 100, and then the adapter board 100 is soldered on the test circuit board. The connection between the test circuit board and the LPDDR5 chip is achieved through the adapter board 100. In the process of testing the adapter board 100 by the test circuit board, the required various test signals can be led to the oscilloscope through the test pad 300 to achieve accurate testing of the LPDDR5 chip.

[0036] Furthermore, if Figure 4 As shown, in some embodiments of the present invention, the adapter board 100 is a six-layer board, including a top board 110, four inner boards 120 and a bottom board 130, and the thickness of the bottom board 130 is greater than the sum of the thicknesses of the top board 110 and the four inner boards 120. The above-mentioned step S200: according to a preset depth and a preset width, the bottom of the adapter board 100 is milled around so that the adapter board 100 is divided into an upper layer 140 and a lower layer 150, the surface area of ​​the upper layer 140 is greater than the surface area of ​​the lower layer 150, and the surface of the upper layer 140 protrudes from the surface of the lower layer 150 around the four extension boards 400, and the step includes the following two steps: (21) Milling grooves around the bottom of the bottom plate 130 according to a preset depth and a preset width, so that the bottom of the bottom plate 130 serves as the lower layer 150, and the top of the bottom plate 130, the top plate 110, and the four inner layer plates 120 serve as the upper layer 140; wherein the preset depth is less than the thickness of the bottom plate 130; (22) A gap 410 is formed between any two adjacent extension plates 400 .

[0037] Specifically, the adapter board 100 adopts a six-layer board design, including a top plate 110, four inner layers 120 and a bottom plate 130, wherein the thickness of the bottom plate 130 is greater than the sum of the thicknesses of the top plate 110 and the four inner layers 120; when the bottom of the adapter board 100 is milled, the bottom of the bottom plate 130 is milled, and the depth of the milling groove does not exceed the thickness of the bottom plate 130, so that the top plate 110 and the four inner layers 120 are both located in the upper part 140 of the adapter board 100 to avoid affecting the line routing in the inner layer 120. At the same time, the stacking spacing between the top plate 110 and the four inner layers 120 is as small as possible to achieve good signal shielding and impedance reference when testing the line routing. In terms of the board selection of the adapter board 100, a high-speed board with a good low dielectric constant and low dielectric loss tangent should be selected to reduce the loss during signal transmission. In this example, the dielectric constant of the plate of the adapter board 100 is lower than 3.71, and the dielectric loss factor is lower than 0.002 at a frequency of 1 GHz, which meets the requirements of high-speed transmission and low loss of signals. In this example, the total thickness of the adapter board 100 is 2.4 mm, and the bottom is milled by a controlled depth milling process to remove 1.6 mm of thickness, so as to avoid collision between the adapter board 100 and the parts on the test circuit board after welding. A gap 410 is formed between any two adjacent extension plates 400, so that four corners are left corresponding to the four edges of the LPDDR5 chip, which is convenient for positioning the adapter board 100 when welding the adapter board 100 to the test circuit board.

[0038] Further, in some embodiments of the present invention, the above-mentioned step S400: the step of leading the test point of the line routing to the surface of the adapter board 100 and connecting it to the corresponding test pad 300, includes the following four steps: (41) Lead out the WCK differential signal, RDQS differential signal and two random data single-ended signals of each channel of the LPDDR5 chip as the first signal test point; (42) The clock differential signal, two random CA signals and two random CS signals of each channel of the LPDDR5 chip are brought out as the second signal test point; (43) Lead out the VDDQ signal, VDD1 signal, VDD2H signal and VDD2L signal of the LPDDR5 chip as power supply test points; (44) Connect the first signal test point, the second signal test point and the power test point to the corresponding test pads 300.

[0039] In order to test the LPDDR5 chip, it is necessary to select the key signals of the LPDDR5 chip as test points. In this example, the following signals are used as test points: For data lines: the WCK differential signal, RDQS differential signal and two random data single-ended signals of each channel of the LPDDR5 chip are brought out as the first signal test point; In terms of clock and address / control lines: the clock differential signal (CK), two random CA signals, and two random CS signals of each channel of the LPDDR5 chip are brought out as the second signal test point.

[0040] Power test point: Bring out the VDDQ, VDD1, VDD2H, and VDD2L of the LPDDR5 chip as power test points.

[0041] After selecting the above test points, connect all the test points to the corresponding test pads 300 through routing. After selecting the first signal test point, the second signal test point and the power test point, the first signal test point, the second signal test point and the power test point also need to be connected to the ground test point as a basis, and the GND signal of the LPDDR5 chip is led out as the ground test point. To this end, the above step S400 also includes the following three steps: (45) GND holes are evenly arranged around the WCK differential signal, RDQS differential signal, data single-ended signal, clock differential signal, CA signal, CS signal, VDDQ signal, VDD1 signal, VDD2H signal and VDD2L signal to achieve ground wrapping; (46) Lead out the signal of the GND ground hole as a ground test point; (47) Connect the ground test point to the corresponding test pad 300.

[0042] It should be noted that for the wiring that needs to be tested, GND grounding treatment is adopted, and GND ground holes are evenly drilled around the signal to achieve the effect of signal shielding and reduce the crosstalk effect between high-speed signals.

[0043] like Figure 1As shown, in some embodiments of the present invention, the signal test pad 310 corresponding to the first signal test point, the second signal test point and the power test point is designed as an elliptical pad, and the ground test pad 320 corresponding to the GND test point is designed as a rectangular pad design, which is convenient for distinguishing and processing during later testing. It should be noted that the signal test pad 310 and the ground test pad 320 can also be designed as other shapes, as long as the shapes of the two are different. At the same time, each ground test pad 320 and the signal test pad 310 are equally spaced around the four extension plates 400, and a spacing of more than 0.75mm is maintained to avoid collision of the test pens during testing. At the same time, a gap 410 is formed between any two adjacent extension plates 400, thereby leaving four corners corresponding to the four edges of the LPDDR5 chip, which is convenient for positioning the adapter board 100 when the adapter board 100 is soldered to the test circuit board. Due to the high thickness of the adapter board 100, the via hole connecting the surface pad 200 and the bottom pad needs to use a through hole with a maximum aperture to meet the diameter-to-depth ratio requirement in machining. The connecting vias at the test pad 300 (i.e., vias for WCK differential signals, RDQS differential signals, data single-ended signals, clock differential signals, CA signals, CS signals, VDDQ signals, VDD1 signals, VDD2H signals, VDD2L signals, etc.) use 1-3 layers of blind vias to connect the test pads to the inner layer traces to eliminate the reflection effect caused by the via stub. The differential signals of the adapter board 100 (such as WCK differential signals, RDQS differential signals and clock differential signals, etc.) are controlled within 100Ω impedance, the single-ended signals (such as data single-ended signals, CA signals, CS signals, etc.) are controlled within 50Ω impedance, and the power supply lines (such as VDDQ signals, VDD1 signals, VDD2H signals, VDD2L signals, etc.) are kept at a line width of more than 12 mils.

[0044] According to the LPDDR5 chip testing method of the embodiment of the present invention, by designing the adapter board 100 and designing the test pad 300 on the adapter board 100, the LPDDR5 chip can be welded on the adapter board 100, and then the adapter board 100 is welded on the test circuit board, and the connection between the test circuit board and the LPDDR5 chip is realized through the adapter board 100. In the process of the test circuit board testing the adapter board 100, the required various test signals can be led to the oscilloscope through the test pad 300, so as to realize the accurate test of the LPDDR5 chip, improve the test efficiency, and meet the test requirements of various test parameters. At the same time, the design of the adapter board 100 makes the welding of the LPDDR5 chip more convenient, and the adapter board 100 will not interfere with the components on the test circuit board. By designing the routing and vias of the adapter board 100, the design of the test pad, and the selection of the plate, the high-speed and high-quality transmission of the signal is realized, and the accuracy of the test results is guaranteed.

[0045] On the other hand, an embodiment of the present invention further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the above-mentioned LPDDR5 chip testing method is implemented.

[0046] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0047] Although specific embodiments are described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any of the functions and / or processing capabilities described in conjunction with a particular device or component may be performed by any other device or component. In addition, although various exemplary implementations and architectures have been described according to embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.

[0048] Some aspects of the present disclosure are described above with reference to the block diagram and flow chart of the system, method, system and / or computer program product according to the exemplary embodiments.It should be understood that the combination of one or more blocks in the block diagram and the flow chart and the blocks in the block diagram and the flow chart can be realized by executing computer executable program instructions respectively.Equally, according to some embodiments, some blocks in the block diagram and the flow chart may not need to be executed in the order shown, or may not need to be executed in full.In addition, additional components and / or operations beyond those components and / or operations shown in the blocks in the block diagram and the flow chart may be present in certain embodiments.

[0049] Therefore, the blocks in the block diagrams and flow charts support the combination of devices for performing the specified functions, the combination of elements or steps for performing the specified functions, and the program instruction devices for performing the specified functions. It should also be understood that each block in the block diagrams and flow charts and the combination of blocks in the block diagrams and flow charts can be implemented by a special-purpose hardware computer system or a combination of special-purpose hardware and computer instructions that performs a specific function, element or step.

[0050] The program modules, applications, etc. described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the illustrative methods described herein) to be performed.

[0051] Software components can be encoded with any of various programming languages. An exemplary programming language can be a low-level programming language, such as an assembly language associated with a specific hardware architecture and / or an operating system platform. The software component comprising assembly language instructions may need to be converted to executable machine code by an assembler before being executed by hardware architecture and / or platform. Another exemplary programming language can be a higher-level programming language, which can be transplanted across multiple architectures. The software component comprising a higher-level programming language may need to be converted to an intermediate representation by an interpreter or a compiler before execution. Other examples of programming languages ​​include but are not limited to macro languages, shells or command languages, job control languages, scripting languages, database queries or search languages ​​or report writing languages. In one or more exemplary embodiments, the software component comprising the instruction of one of the above-mentioned programming language examples can be directly executed by an operating system or other software components, without first being converted into another form.

[0052] Software components may be stored as files or other data storage structures. Software components of similar type or related functions may be stored together, such as in a specific directory, folder, or library. Software components may be static (e.g., preset or fixed) or dynamic (e.g., created or modified at execution time).

[0053] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. A LPDDR5 chip testing method, characterized in that: The method comprises the following steps: According to the layout of the LPDDR5 chip, an adapter board is designed; the number of layers of the adapter board is greater than two, the inner layer board of the adapter board is provided with a circuit routing, the surface of the adapter board is provided with a surface pad, the bottom surface of the adapter board is provided with a bottom pad, and the surface pad is connected to the bottom pad through a via; According to a preset depth and a preset width, grooves are milled around the bottom of the adapter plate, so that the adapter plate is divided into an upper layer and a lower layer, the surface area of ​​the upper layer is larger than the surface area of ​​the lower layer, and the surface around the upper layer protrudes from the surface around the lower layer, forming four extension plates; Disposing a test pad on the surface of each of the extension plates; Leading the test points of the line routing to the surface of the adapter board and connecting them to the corresponding test pads; Soldering the LPDDR5 chip on the surface of the adapter board; Obtain a test circuit board; the test circuit board is provided with a mounting area; Welding the bottom surface of the adapter board to the mounting area, so that the LPDDR5 chip is connected to the test circuit board through the adapter board; The test pad is connected to an oscilloscope, the test circuit board tests the LPDDR5 chip, and the test result is displayed through the oscilloscope.

2. The LPDDR5 chip testing method according to claim 1, characterized in that: The adapter plate is a six-layer plate, including a top plate, four inner plates and a bottom plate, the thickness of the bottom plate is greater than the sum of the thicknesses of the top plate and the four inner plates; the steps of milling grooves around the bottom of the adapter plate according to a preset depth and a preset width, so that the adapter plate is divided into an upper layer and a lower layer, the surface area of ​​the upper layer is greater than the surface area of ​​the lower layer, and the surface of the upper layer protrudes from the surface of the lower layer to form four extension plates, including: According to a preset depth and a preset width, grooves are milled around the bottom of the bottom plate, so that the bottom of the bottom plate serves as the lower layer, and the top of the bottom plate, the top plate, and the four inner layer plates serve as the upper layer; wherein the preset depth is less than the thickness of the bottom plate; A gap is formed between any two adjacent extension plates.

3. The LPDDR5 chip testing method according to claim 1, characterized in that: The step of leading the test point of the line routing to the surface of the adapter board and connecting it to the corresponding test pad includes: Lead out the WCK differential signal, RDQS differential signal and two random data single-ended signals of each channel of the LPDDR5 chip as the first signal test point; Lead out the clock differential signal, two random CA signals and two random CS signals of each channel of the LPDDR5 chip as the second signal test point; Lead out the VDDQ signal, VDD1 signal, VDD2H signal and VDD2L signal of the LPDDR5 chip as power supply test points; The first signal test point, the second signal test point and the power supply test point are all connected to the corresponding test pads.

4. The LPDDR5 chip testing method according to claim 3, characterized in that: The step of leading the test points of the line routing to the surface of the adapter board and connecting them to the corresponding test pads also includes: GND ground holes are evenly arranged around the WCK differential signal, the RDQS differential signal, the data single-ended signal, the clock differential signal, the CA signal, the CS signal, the VDDQ signal, the VDD1 signal, the VDD2H signal and the VDD2L signal to achieve ground package setting; Lead out the signal of the GND ground hole as a ground test point; Connect the ground test point to the corresponding test pad.

5. The LPDDR5 chip testing method according to claim 4, characterized in that: The test pad includes a signal test pad and a ground test pad, the first signal test point, the second signal test point and the power test point are respectively connected to the corresponding signal test pads, the ground test point is connected to the ground test pad, and the shape of the signal test pad is different from that of the ground test pad.

6. The LPDDR5 chip testing method according to claim 3, characterized in that: The signal impedance of the WCK differential signal, the RDQS differential signal, and the clock differential signal is lower than 100Ω, the signal impedance of the data single-ended signal, the CA signal, and the CS signal is lower than 50Ω, and the routing width of the VDDQ signal, the VDD1 signal, the VDD2H signal, and the VDD2L signal is greater than 12 mil.

7. The LPDDR5 chip testing method according to claim 3, characterized in that: The WCK differential signal, the RDQS differential signal, the data single-ended signal, the clock differential signal, the CA signal, the CS signal, the VDDQ signal, the VDD1 signal, the VDD2H signal, and the VDD2L signal are led out to the surface of the adapter board through the conductive blind holes of the 1-3 layers and connected to the corresponding test pads.

8. The LPDDR5 chip testing method according to claim 1, characterized in that: The dielectric constant of the plate of the adapter plate is lower than 3.71, and the dielectric loss factor is lower than 0.002 at a frequency of 1 GHz.

9. The LPDDR5 chip testing method according to claim 1, characterized in that: The test pads are arranged around the circumference of the adapter board at equal intervals, and the interval between adjacent test pads is greater than 0.75 mm.

10. An adapter plate, characterized in that: The number of layers of the adapter board is greater than two, the inner layer board of the adapter board is provided with circuit routing, the surface of the adapter board is provided with surface pads, the bottom surface of the adapter board is provided with bottom pads, and the surface pads are connected to the bottom pads through conductive holes; the adapter board is divided into an upper layer and a lower layer, the surface area of ​​the upper layer is greater than the surface area of ​​the lower layer, and the surface around the upper layer protrudes from the surface around the lower layer to form four extension plates, and the surface of each extension plate is provided with a test pad; the test points of the circuit routing are led out to the surface of the adapter board and connected to the corresponding test pads.

Images