Embedded bridge component for semiconductor package

Abstract

Architecture and process flows for embedded bridge components for semiconductor packages are provided. Most of the substrate package fabrication may be completed using conventional processing steps to meet core geometries (e.g., 9 / 12) with associated equipment and clean room protocols. Individual, the bridge component is fabricated to be embedded into the substrate package at locations where high speed input / output (I / O) performance and high density (HD) geometry are required. The bridge component is fabricated as needed to meet the HD geometry (e.g., 3 / 3 or less). During assembly, the embedded bridge component may be attached into a cavity in the substrate package.

Description

Background Art

[0001] The demand for miniaturization of form factors and increased levels of integration for high performance is driving a complex packaging approach in the semiconductor industry. Reliable connections between dies in a semiconductor package that also provide the desired bandwidth present technical challenges. Therefore, continued improvements in semiconductor packaging architectures and methods that support high-speed signaling and miniaturization are expected. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 An example semiconductor package implementing at least one embedded organic bridge component according to various embodiments is shown.

[0003] Figure 2 Simplified cross-sectional illustrations of semiconductor package cores patterned with thick seeds and redistribution layers (RDLs) according to various embodiments are provided.

[0004] Figure 3 A device having additional RDLs built on upper and lower surfaces according to various embodiments is provided. Figure 2 Simplified cross-sectional illustration of an embodiment in FIG.

[0005] Figure 4 Creating a cavity in an upper surface of a semiconductor package die according to various embodiments is shown.

[0006] Figure 5 The placement of the organic bridge component into the cavity in the substrate package and its attachment therein is shown.

[0007] Figure 6 is a simplified illustration of a semiconductor package assembly implementing embodiments of an embedded organic bridge component in accordance with various embodiments.

[0008] Figure 7 is a simplified illustration of another semiconductor package assembly implementing an embedded organic bridge component having different features according to various embodiments.

[0009] Figure 8 is a simplified illustration of another semiconductor package assembly implementing an embedded organic bridge component having different features according to various embodiments.

[0010] Fig. 9 is a simplified illustration of another semiconductor package assembly implementing an embedded organic bridge component having different features according to various embodiments.

[0011] Fig.10 is a simplified illustration of another semiconductor package assembly implementing an embedded organic bridge component having different features according to various embodiments.

[0012] Fig.11Example methods for fabricating and implementing embedded organic bridge components according to various embodiments are shown.

[0013] Fig.12 is a top view of a wafer and die that can be included in a microelectronic assembly according to any embodiment disclosed herein.

[0014] Fig.13 is a simplified cross-sectional side view illustrating an implementation of an integrated circuit that may be included on a die in the various embodiments according to any of the embodiments disclosed herein.

[0015] Fig.14 is a cross-sectional side view of a microelectronic assembly that can include any of the embodiments disclosed herein.

[0016] Fig.15 is a block diagram of an example electrical device that may include any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0017] Integrating multiple integrated circuit (IC) components in a semiconductor package to meet high-speed signaling expectations often involves technical challenges that rely on one or more bridge components. A bridge component can support finer pitches than in the surrounding semiconductor substrate package and can be dedicated to communication between two heterogeneous IC dies.

[0018] The proposed technical solutions include separately manufacturing silicon components with high-density interconnects and fine pitch geometry, and then embedding the silicon components in the substrate package (embedded bridge approach). However, these silicon components can be expensive. Another proposed solution includes directly manufacturing high-density interconnects in the substrate package (i.e., high-density patterning). However, achieving adequate yields with substrate packaging while meeting the stringent warpage requirements for high-resolution exposure in the substrate package remains a technical challenge.

[0019] The embodiments described herein provide technical solutions to these technical challenges in the form of an architecture and process flow for an organic embedded bridge component for semiconductor packaging. This approach can be used in semiconductor substrate packages integrating heterogeneous dies configured for high-speed signaling, including electronic integrated circuits and photonic integrated circuits.

[0020] Advantageously, embodiments enable most substrate package manufacturing to be accomplished using conventional processing steps that meet core geometries and associated equipment and cleanroom standards, while areas of the substrate package that require high-speed input / output (I / O) performance and high-density (HD) geometries can be reserved for organic bridge components; separately (see Fig.111102), the organic bridge component is manufactured in a more stringent clean room environment with more precise equipment, so that HD geometry (e.g., 3 / 3) can be achieved. During assembly, the embedded organic bridge component can be placed in the cavity of the substrate package. These concepts are developed in more detail below.

[0021] Example embodiments are described below in conjunction with the accompanying drawings, in which like numbers represent similar elements. The figures are not necessarily drawn to scale, but may rely on the spatial orientation and relative positioning of features. It is understood that certain terms, such as "ceiling" and "floor", as well as "upper", "uppermost", "lower", "above", "below", "bottom", and "top", refer to the direction based on viewing the referenced figure. In addition, terms such as "front", "back", "rear", "side", "vertical" and "horizontal" can describe the orientation and / or position of parts of a component within a consistent but arbitrary reference system, which is clear by reference to the text and associated figures describing the component in question. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0022] As used herein, the term "adjacent" refers to layers or components that are in direct physical contact with each other, with no layers or components between them. For example, layer X adjacent to layer Y refers to the layer that is in direct physical contact with layer Y. In contrast, as used herein, the phrase (single or multiple) "located" (in the alternative, "located below," "located above / above," or "located next to" in the context of a first layer or component located on a second layer or component) includes (i) configurations in which a first layer or component is directly physically attached to (i.e., adjacent to) a second layer, and (ii) components and configurations in which a first layer or component is attached (e.g., coupled) to a second layer or component through one or more intervening layers or components.

[0023] The following detailed description is not intended to limit the application and use of the disclosed technology. It is obvious that novel embodiments can be practiced without every detail described herein. For the sake of brevity, well-known structures and devices can be shown in the form of block diagrams to facilitate their description.

[0024] Figure 1 A non-limiting example of is a semiconductor package 100 that integrates multiple heterogeneous dies and implements at least one organic embedded bridge component. The semiconductor package 100 includes an integrated circuit (IC) die 102, a first die 104, and a second die 106. The first die 104 and / or the second die 106 can be another electronic integrated circuit die (EIC) or a photonic integrated circuit die (PIC). In the case where the first die 104 or the second die 106 is a PIC, it can be in operable communication with an optional optical fiber array unit. Figure 1In a non-limiting example, the PIC die 104 is shown as being operably connected to a fiber array unit (FAU) 108. The die can be attached to a substrate 112. In various embodiments, the substrate 112 can include a printed circuit board, a film substrate, or another suitable substrate. In other package assembly and / or device embodiments, the substrate 112 can be further attached to a printed circuit board (PCB) 114; and in further embodiments, the multi-die assembly can include additional IC dies, generally represented as die 118. It can be understood that this arrangement of dies is only an example embodiment, and in other multi-die assemblies, there can be more or fewer PIC dies, more or fewer FAU components, more or fewer ICs, and the dies can be arranged in any pattern (e.g., square (e.g., 2×2, 4×4, 6×6), rectangular (e.g., 2×4, 3×5, 4×7)).

[0025] In various embodiments, such as when implemented in a package assembly or device, the die in the semiconductor package 100 can be overmolded with an encapsulant 116. The encapsulant 116 can include a molding compound, a dielectric material, a metal, a ceramic, a plastic, or a combination thereof. In addition, a thermal management solution (not shown) including a cooling component (such as a vapor chamber, a heat pipe, a heat sink, or a liquid-cooled cold plate) can be attached to the semiconductor package 100. As part of the thermal management solution, a thermally conductive layer interface material (TIM) can be located above the die 102. The TIM can be any suitable material, such as a thermal compound filled with silver particles, a thermal grease, a phase change material, an indium foil, or a graphite sheet. The thermal management solution can be a conformal solution that accommodates the height difference of the integrated circuit die (the thermal management solution provides cooling for the integrated circuit die). For example, the thermal management solution can include a substantially planar cooling component with a TIM of varying thickness between the cooling component and the integrated circuit die. In another example, the cooling component is non-planar, and the profile of the cooling component can vary with the thickness of the integrated circuit die (the cooling component provides cooling for the integrated circuit die). In such an embodiment, the TIM may have a substantially uniform thickness between the integrated circuit die and the cooling component having varying thicknesses.The thermal management solution may also include an integrated heat sink.

[0026] Dies 102, 104, 106, and 118 may be unpackaged integrated circuit dies and may alternatively be referred to as chips, chiplets, chip complexes, or chiplet complexes. The PIC employs at least some optical communications, and a fiber array unit (FAU) implements optical switching functions. Although the terms die, chip, and chiplet may be used interchangeably, the term chiplet is sometimes used to refer to an integrated circuit die that implements a subset of the functionality of a larger integrated circuit component. Although the illustration depicts the chiplets as having uniform sizes, in practice, the size (lateral dimensions as well as thickness) and shape of the chiplets may vary between chiplets; furthermore, the chiplets may vary by type / function (e.g., computing, memory, I / O, power management (controlling the delivery of power and / or providing power to components)). Any integrated circuit die, chip, or chiplet may implement any portion of the functionality of any processor unit described or referenced herein. Further, semiconductor package 100 may have any shape, such as a generally square shape, a generally rectangular shape, or a generally circular shape. The dashed lines narrow the focus area of ​​the substrate package 112 including the embedded organic bridge components 120 , 122 .

[0027] The disclosed embodiments of the embedded organic bridge component 120 are configured to be in the substrate package 112 (specifically, in a cavity in the substrate package, as described in more detail below). Unlike other bridge solutions, the provided embedded organic bridge component 120 can be manufactured using a dielectric material with a silicon filler or an Ajinomoto built-up film (ABF). The embedded organic bridge component 120 may include the same dielectric material (e.g., in the second region 130) as the dielectric material of the substrate package in which it is located (e.g., see the embodiments of the present invention in conjunction with the embodiment of the present invention). Figure 3 , dielectric materials discussed above, dielectric layers 324 and 330).

[0028] As used herein, a redistribution layer (RDL) is a metal or conductive trace or interconnect that connects or provides an electrical path between one area and another in a semiconductor package and is sufficient for electrical communication and / or for supplying power and ground. Embodiments of the embedded organic bridge component 120 may include the same trace or RDL material; however, they implement a high density or HD geometry, defined herein as a 3 / 3 or smaller geometry, meaning that the conductive traces 135 have a width 132 of three microns or less (interconnect line width) and are spaced apart from each other (spaces 134) by three microns or less. In contrast, the surrounding substrate package 112 may implement a larger "core geometry", such as a 9 / 12 geometry (meaning a conductive trace width of 9 microns and a spacing of 12 microns). In addition, as can be appreciated, the dimensions of the embedded organic bridge component 120 are smaller than the corresponding dimensions of the substrate package. The thickness 140 (or height in the ZX illustration) of the embedded organic bridge component 120 ranges from about 20% of the substrate package thickness to about 70% of the substrate package thickness, where about means plus or minus 10%. The lower surface 136 of the embedded organic bridge component 120 also has a conductive contact at the HD geometry on which a solder bump 138 may be placed to attach to the cavity in the substrate package 112 .

[0029] Therefore, in order to identify an embodiment of the present disclosure, a portion of the substrate package 112 can be observed, for example, using a SEM or TEM (transmission electron microscope), and an area where the RDL or the ratio of trace width and trace spacing transitions from a core geometry to an HD geometry can be identified, and it can be confirmed that the material of the area with the HD geometry includes a dielectric material. As described above, the dielectric material of the second region 130 of the embedded organic bridge component 120 can be the same as the dielectric material of the substrate package 112, or it can be different. Depending on the view in the SEM or TEM, a solder bump 138 at the lower surface 136 can be observed, which can be somewhere in the middle of the substrate package 112 (in the Z direction, as shown in FIG. 1 ). Figure 6-8 shown).

[0030] In some embodiments of the embedded organic bridge component 120, in addition to the fine pitch or HD wiring and interconnects described above, one or more additional electrical components 142 are implemented. A non-limiting example of an additional electrical component 142 that can be implemented in the embedded organic bridge component 120 is a trench capacitor. A trench capacitor can be identified by the silicon dioxide layer above the air gap / cavity, which has polysilicon walls and an oxide-nitride-oxide (ONO) layer (this will be on the side or ZX profile, as shown).

[0031] Figure 2-5 Various stages of fabrication are shown for achieving a substrate package of an embedded organic bridge component 120. This substrate view is sometimes referred to as a "substrate patch". Figure 5 The embedded organic bridge component 120 is shown placed into a cavity in a substrate package and attached therein. Figure 6-10 Some non-limiting examples of package assemblies are shown in which various embodiments of embedded organic bridge components are employed. Fig.11 A process flow for producing the embodiments described herein is provided.

[0032] As described, embodiments of the substrate package (substrate 112) generally include a core 202 layer, such as Figure 2 As shown. The core is fabricated to have a core geometry, and a redistribution layer (RDL) is patterned on one or both surfaces (at 1104). In various embodiments, the core 202 includes glass (as used herein, the glass may be an alkali-free alkaline earth borosilicate aluminate glass, such as a glass including aluminum, oxygen, boron, silicon, and an alkaline earth metal (e.g., beryllium, magnesium, calcium, strontium, barium, radium, such as a glass including SiO2, Al2O3, B2O3, and MgO), or a photosensitive glass (photoprocessable or photostructurable glass). In some embodiments, the photosensitive glass may be a glass belonging to the lithium silicate family of glasses (e.g., a glass including lithium, silicon, and oxygen) that includes metal particles, such as gold, silver, or other suitable metal particles. The core 202 may include multiple glass sheets bonded together by an adhesive layer. In various embodiments, the core 202 may have a thickness ranging from about 20 microns to about 1 mm, where about means plus or minus 10%.

[0033] In other embodiments, the core 202 layer may include an epoxy material or a combination of epoxy material and glass. As used herein, "epoxy material" may include epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic material, or polymer material such as polyimide.

[0034] The core 202 may be sandwiched between dielectric layers, the dielectric layers including corresponding redistribution layers (RDL); the dielectric layers are substantially coplanar with the upper surface of the substrate package; the core is located in the middle of the dielectric layers / the core is located laterally in the dielectric layers. In embodiment 200, a dielectric layer 208 having RDL conductive traces 206 is patterned and located on the upper surface of the core 202. Various embodiments may also have a dielectric layer 214 having RDL conductive traces 206 and patterned and located on the lower surface of the core 202. Dielectric layers 208 and 214 may include suitable nitrides or oxides, such as silicon dioxide (SiO2), carbon-doped silicon dioxide, fluorine-doped silicon dioxide, hydrogen-doped silicon dioxide, or silicon nitride. Dielectric layer 208 has vias or pillars 210, and dielectric layer 214 has vias or pillars 216. Embodiment 200 shows a core 202 patterned with through holes or through glass vias (TGVs) 204 that enable communication between the RDL in dielectric layer 208 and the RDL in dielectric layer 214. As shown in embodiment 250, posts or vias 210, 212, and 216 and TGVs 204 are substantially perpendicular (i.e., 90 degrees plus or minus 18 degrees) to the upper surface 211 of the substrate package or core 202. In various embodiments, at 1104, the first conductive RDL layer is referred to as a seed 220. The location for the intended cavity is shown centered with width 240.

[0035] The RDL / seed 220 may include a metal (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or a combination thereof) or another suitable conductive material. The seed 220 may have a thickness (measured in the Z direction in the figure) from about 1 micron to 10 microns. In various embodiments, the seed 220 may be substantially 5 microns. The RDL patterning may be performed using a modified semi-additive plating (MSAP) process for placing the seed 220.

[0036] A resist layer 218 is applied over portions of the seed 220 (at 1106) that are designated as cavities to be later filled with embedded organic bridge features, as further described in subsequent figures. At 1106, a protective coating 222 may be applied over the resist 218, followed by an etch that removes the seed in locations without resist.

[0037] In the completed substrate package, the cavity portion of the dielectric includes a smaller width, area, or volume of the entire substrate in question. Therefore, the width 240 is less than the width of the core 202 and the package substrate. In addition, the width 240 is a function of the width of the target organic embedded bridge component. These figures reflect cross-sectional views in which portions of the cavity are depicted as widths; however, in a top-down view, portions of the cavity would be shown as areas. In various embodiments, the width 240 can be about 5 microns to about 40 microns in the X direction (or Y direction out of the page) along the upper surface 211.

[0038] In 1108, and ref. Figure 3 , one or more additional dielectric layers 324 with RDL can be added to the upper surface surrounding the intended cavity area. In addition, one or more dielectric layers 330 can be added to the lower surface of the embodiment 250. In the non-limiting example embodiment 300, the dielectric layer 324 on the upper surface also includes another two layers of RDL conductive traces 328 and vias 326, and the dielectric layer 330 on the lower surface also includes another two layers of RDR conductive traces 328 and vias 326. The dielectric layers 324 and 330 with RDL can be manufactured according to conventional methods.

[0039] In various embodiments, dielectric layers 324 and 330 may include a dielectric material overlying the conductive trace material, such as a suitable nitride or oxide, such as silicon dioxide (SiO2), carbon-doped silicon dioxide (C-doped SiO2, also known as CDO or organic silicate glass, which is a material including silicon, oxygen and carbon), fluorine-doped silicon dioxide (F-doped SiO2, also known as fluorosilicate glass, which is a material including fluorine, silicon and oxygen), hydrogen-doped silicon dioxide (H-doped SiO2, which is a material including silicon, oxygen and hydrogen). In some embodiments, the dielectric layer includes a photoimageable dielectric (PID). In some embodiments, the dielectric layer includes an Ajinomoto deposited film (commonly referred to as ABF), which is a material including an organic resin matrix with different types of fillers (e.g., different sizes of silica fillers or different sizes of hollow fillers) to control the coefficient of thermal expansion (CTE) and / or electrical properties (e.g., dielectric constant (Dk), and / or dissipation factor (insertion loss) (Df)).

[0040] In some embodiments, it is advantageous for the dielectric layer (324, 330) to have a CTE that matches the CTE of the target die attached to the substrate or PCB (e.g., matches the CTE of silicon in IC die 102 or die 106). In some embodiments, the dielectric material can have a CTE that is close to (e.g., within 10%) the CTE of silicon. In other embodiments, the dielectric material can be any type of epoxy molding compound.

[0041] Additionally, at 1108, individual dielectric layers 324 and / or 330 may include a plurality of RDL conductive traces stacked therein. Figure 3 In the example shown, vertical conductive traces 326 and lateral traces 328 are located in dielectric layers 324 and 330 that are built up on the top surface or front side of core 202 and on the back side of core 202 (in the Z direction of the figure), respectively.

[0042] As with other RDL conductive traces described herein, via / vertical conductive trace 326 and lateral conductive trace 328 include conductive materials, such as metal (e.g., copper, aluminum, nickel, cobalt, iron, tin, gold, silver, or a combination thereof) or another suitable conductive material, and provide a conductive path from the start point to the end point of the corresponding trace. Dielectric layers 330 and 324 may be suitable nitrides or oxides, such as silicon dioxide (SiO2), carbon-doped silicon dioxide, fluorine-doped silicon dioxide, hydrogen-doped silicon dioxide, or silicon nitride.

[0043] In other embodiments, there may be more or fewer RDL layers in dielectric layer 324 and more or fewer RDL layers in dielectric layer 330 , and the number of RDLs in dielectric layer 324 does not necessarily match the number of RDLs in dielectric layer 330 .

[0044] At 1110, a cavity is formed in the substrate. In various embodiments, this is accomplished by removing dielectric material to expose the RDL above the seed crystal 220 (embodiment 400). A laser ablation process or a dry etching process can be used to remove the dielectric material and create a cavity located above the resist pattern 218. In other embodiments, the cavity is created in the dielectric material or even in a glass layer ("core") of the dielectric layer. Regardless of where the bottom of the cavity is located, the bottom of the cavity is (or has) a cavity bottom surface; the cavity bottom surface is where the embedded organic bridge component will be placed and attached. Although some figures show the cavity as having vertical walls, this is to simplify the drawings. In practice, as shown in FIG. Figure 4 As shown, the cavity wall 405 appears to slope inwardly from the upper surface toward the cavity bottom surface.

[0045] The cavity has a cavity depth 434 and a cavity width 432. The cavity depth 434 extends from the upper surface to the cavity floor and is a function of the thickness 140 of the embedded organic component to be used. As described above, the thickness 140 of the embedded organic bridge component 120 can range from about 20% of the thickness of the substrate package 112 to about 70% of the thickness of the substrate package 112, where about means plus or minus 10%. Reference Fig.10The cavity may have a cavity depth of 100 microns + / - 10% to 1000 microns + / - 10%, with the cavity bottom surface placed in the glass layer of the surrounding (core geometry RDL) dielectric, or even below the lower surface of the glass layer in the surrounding (core geometry RDL) dielectric (see e.g. Fig.11 , Example 1100).

[0046] As will be appreciated by those skilled in the art, the cavity depth 434 may be slightly greater than the thickness 140 of the embedded organic bridge component 120 to accommodate solder bumps and / or an adhesive layer (e.g., a bonding film) at the cavity floor that attaches the embedded organic bridge component 120 to the substrate package 112. In some embodiments, the embedded organic bridge component 120 is hybrid-bonded directly to the RDL in the cavity floor (see, e.g., Fig. 9 ).

[0047] As described above, the thickness 140 of the embedded organic bridge component can be greater than half (eg, >50%) of the thickness of the substrate package. Additionally, in those embodiments, the cavity floor can be located in the core 202 , or even below the core 202 (in the figure), extending into the dielectric / RDL layer 330 .

[0048] Task 1102 represents fabricating an embedded organic bridge component 120. In addition to fabricating an embedded organic bridge component 120 / 705 including high-speed I / O and HD geometries, the embedded organic bridge component 120 may also include other electrical components 142, such as trench capacitors 142. It will be appreciated that tasks 1104 through 1110 may be performed at the same fabrication site as tasks 1102 and 1112, or at a geographically different location; further, tasks 1102 / 1112 and 1104-1110 may be performed by different suppliers.

[0049] At 1114, the embedded organic bridge component 120 can be positioned in the cavity (embodiment 500) such that the solder bumps (when present) are aligned with the RDL conductive contacts and traces / RDL in the cavity (embodiment 550). In other embodiments, when using an adhesive, a bonding film (e.g., bonding film 710, Figure 7 ) or mixed bonding ( Fig. 9 ), the placement in the cavity is performed accordingly. In various embodiments, bottom filler 546 may also be added between the embedded organic bridge component 120 / 705 and the cavity bottom surface. As described herein, after the embedded organic bridge component 120 is placed, the cavity around it is filled with dielectric material; this is omitted in the figure to reduce image clutter.

[0050] At 1114, components of embodiments may support operational communication between each other and may provide functionality traditionally associated with a monolithic system-on-chip (SoC) in a multi-die package. In various embodiments, at least one electrical communication path from the first dielectric layer to the second dielectric layer via the TGV is a power routing.

[0051] At 1116, the substrate package can be subjected to further patch manufacturing, as shown in embodiment 700. For example, the upper surface 760 of the patch can be planarized, and more dielectric layers 780 with one or more RDLs therein can be added to the upper surface. In addition, overmolding and thermal solutions (not shown) can be added. In addition, solder bumps can be added to the lower surface 762, etc. At 1218, additional dies can be added, and optional mid-level interconnects can be added.

[0052] In various embodiments, the solder material for the solder bumps 782 for attaching the die IC 1 and the die IC 2 has a lower melting point than the solder for the solder bumps 138 on the embedded organic bridge component 120 / 705. In an embodiment, the solder material for the solder bumps 782 may be a solder alloy such as tin and gold. In another embodiment, the solder material for the solder bumps 138 may be tin, and the solder material for the solder bumps 782 may be a compound of tin and gold. This increases the reliability of the solder attachment of the embedded components (and by extension, any product including this embodiment) by preventing the embedded components from loosening or moving around when heat is applied to attach the die to the upper surface. In addition, at 1218, the components in the embodiment can support operational communication between each other.

[0053] Review and Compare Figure 1 and Figure 6, the upper surface of the substrate package will have a first conductive contact 692 in a first arrangement at a first pitch ("core pitch") and a second conductive contact 690 in a second arrangement at a second pitch ("bridge pitch" or HD pitch / geometry as described herein). The lower surface 662 of the substrate package has a third conductive contact in a third arrangement at a third pitch, which can be a ball grid array BGA or LGA pitch. In various embodiments, the second pitch is less than 3 microns + / - 20%, and the first pitch and the third pitch are greater than 8 microns + / - 20%. There is a dielectric material layer between the upper surface and the lower surface, and the dielectric material layer includes a first region dielectric layer 324 and a second region 130 (organic embedded bridge component). As described above, the first region dielectric layer 324 includes a first redistribution layer (RDL) having a width greater than 9 microns + / - 20% (conventional or core geometry, 9 / 12 geometry). The second region 130 includes a second redistribution layer (RDL) having a width less than three microns + / - 20% (HD geometry, 3 / 3 or less geometry). The first region and the second region abut each other substantially perpendicularly to the upper surface. Furthermore, we see that the first RDL provides an electrical path 698 between a first of the first conductive contacts and a first of the third conductive contacts; the second RDL provides an electrical path 694 between a first of the second conductive contacts and a second of the second conductive contacts; and in various embodiments, the second RDL also provides an electrical path 696 between a third of the second conductive contacts and a second of the third conductive contacts. Large arrows are used to illustrate some of these paths.

[0054] exist Figure 7 In the embodiment 700, some variations are shown. The features shown in the embodiment 700 need not be implemented together; they can be implemented together. Figure 6 , Figure 8 , Fig. 9 and Fig.10 and other features in the mix and match. As a first variation, as shown, the resist pattern 218 is omitted, and the embedded organic bridge component 705 (second dielectric region) can be directly attached to the cavity bottom surface via a bonding film 710. In various embodiments, the bonding film 710 can be an anisotropic bonding film to allow a conductive path in the vertical or Z direction. In another variation, the embedded organic component 705 has a core 702. The core 702 can include a glass or epoxy material, as described herein, and in this example can also be fabricated as a through-glass via (TGV) with a smaller HDL geometry, and a dielectric layer / RDL patterned on the upper and lower surfaces, also as described herein. In yet another variation, the embedded organic component 705 has one or more trench capacitors 707 in the glass core 702, including an ONO layer and a polysilicon layer, also as described above.

[0055] exist Figure 8 In the embodiment of the present invention, the embedded organic bridge component 805 is hybrid bonded to the cavity bottom surface in the cavity. The hybrid bonding can be detected by finding copper-copper (Cu-Cu) fused interconnects and dielectrics fused to dielectrics at the cavity bottom surface 810. Figure 8 Another feature shown in the figure is the location of the glass layer 802. The embodiment of the organic bridge component 805 configured with the glass layer 802 at the bottom improves hybrid bonding by providing a flat planar lower surface of the organic bridge component 805. The cavity around the organic bridge component 805 can be filled with a dielectric (omitted from the image to avoid obscuring the image). As shown, one or more layers of RDL / dielectric can be layered on top of the embedded organic bridge component 805.

[0056] exist Fig. 9 , embodiment 900 depicts an organic bridge component 905 in an open cavity configuration, wherein a glass layer 902 is located near or at an upper surface. The IC and die 2 are solder attached to the upper surface of the substrate package and the upper surface of the organic bridge component 905 without an intervening RDL / dielectric material. This configuration of the organic bridge component 905 is advantageous for an open cavity die attach embodiment because it can enhance the planarity of the upper surface and, based on this, reduce bump thickness variation (BTV) on the upper surface. As shown, when the glass layer 902 is located at the surface, the trench capacitor 907 in the glass layer 902 can be more easily manufactured, as shown.

[0057] Another feature depicted in embodiment 900 is an organic bridge component 905 having a thickness 909 such that it extends into the core 202 of the substrate package. In these embodiments, the lower layer of the RDL includes vias 911 and contacts having a larger core geometry (e.g., 9 / 12, as described above); this enables the lower surface of the organic bridge component 905 to attach to the via in the core 202.

[0058] Fig.10is an embodiment 1000 depicting an organic bridge component 1005 with the glass layer 1002 still located near the bottom. In this embodiment, the organic bridge component 1005 has a thickness such that it extends through the core 202 of the substrate package and into the bottom side of the core 202 or the lower dielectric layer 330 on the bottom side of the substrate package. In the manufacturing process, a cavity is created within the substrate package, the cavity having a cavity floor in the lower dielectric layer 330, and thus, the cavity includes an opening in the core 202. In these embodiments, the organic bridge component 1005 can include a multi-layer RDL with an HD geometry; when the organic bridge component 1005 is attached to the cavity floor in the lower dielectric layer 330, there is no need to convert the HD geometry (3 / 3 or less) to a core geometry in the body of the organic bridge component 1005. As previously described, there are a variety of ways to attach the organic bridge component 1005 to the cavity floor, such as by hybrid fusion and by solder attachment and bottom filling.

[0059] Thus, various non-limiting embodiments of embedded organic bridge components for semiconductor packaging have been described. Embodiments may exhibit different features in SEM / TEM images, such as a transition in the width / spacing of traces or RDLs from a traditional core (9 / 12) geometry to a high density (HD) (3 / 3 or less) geometry in a given area. For example, Figure 7 The dashed lines A-A' or B-B' and Fig.10 The dashed lines A-A' or BB' in the figure show some potential views through the ZX plane, and these transitions in width and spacing can be seen. Similar potential views can be realized in the XY plane. In addition, in various component and device embodiments, additional dies and / or components may be present. The following description provides additional details and context for various dies and various packaging components and device configurations that may be generated based on or using the provided embodiments.

[0060] Fig.12 1 is a top view of a wafer 1200 and die 1202 that may be included in any of the embodiments disclosed herein. Wafer 1200 may be composed of semiconductor material and may include one or more die 1202 formed on a surface of wafer 1200. After fabrication of integrated circuit components on wafer 1200 is complete, wafer 1200 may undergo a singulation process in which die 1202 are separated from one another to provide discrete "chips" or integrated circuit components for packaging. Individual die 1202 that include integrated circuit components may include one or more transistors (e.g., Fig.131340, discussed below), supporting circuitry that routes electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 1200 or die 1202 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. In addition, multiple devices may be combined on a single die 1202. For example, a memory array formed from multiple memory devices may be formed in conjunction with a processor unit (e.g., Fig.15 The processor unit 1502 of the chip or other logic configured to store information in the memory device or execute instructions stored in the memory array is on the same die 1202. In some embodiments, the die 1202 can be attached to a wafer 1200 including other dies, and the wafer 1200 is then singulated, which is a manufacturing process called die-to-wafer assembly technology.

[0061] Fig.13 1 is a cross-sectional side view of an integrated circuit 1300 that may be included in any of the embodiments disclosed herein. One or more integrated circuits 1300 may be included in one or more dies 1202 ( Fig.12 ). The integrated circuit 1300 may be formed on a die substrate 1302 (eg, Fig.12 1200) and may be included in a die (e.g., Fig.12 In the tube core 1202).

[0062] The die substrate 1302 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of the two). The die substrate 1302 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, alternative materials may be used to form the die substrate 1302, which may be combined with silicon or not combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Groups II-VI, III-V, or IV may also be used to form the die substrate 1302. Although several examples of materials that may form the die substrate 1302 are described herein, any material that may serve as a base for the integrated circuit 1300 may be used. The die substrate 1302 may be a monomerized die (e.g., Fig.12 of a die 1202) or a wafer (e.g., Fig.12 portion of the chip 1200).

[0063] The integrated circuit 1300 may include one or more device layers 1304 disposed on a die substrate 1302. The device layer 1304 may include features of one or more transistors 1340 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the die substrate 1302. The transistor 1340 may include, for example, one or more source and / or drain (S / D) regions 1320, a gate 1322 for controlling current flow between the S / D regions 1320, and one or more S / D contacts 1324 for routing electrical signals to or from the S / D regions 1320.

[0064] The gate 1322 may be formed of at least two layers (gate dielectric and gate electrode). The gate dielectric may include a layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide and / or high-k dielectric materials. High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium and zinc. Examples of high-k materials that may be used for gate dielectrics include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate. In some embodiments, when a high-k material is used, an annealing process may be performed on the gate dielectric to improve its quality.

[0065] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1340 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may include a stack of two or more metal layers, one or more of which are work function metal layers and at least one of which is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes.

[0066] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metal discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metal discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0067] In some embodiments, when viewed as a cross-section of transistor 1340 along the source-channel-drain direction, the gate electrode may include a U-shaped structure including a bottom portion substantially parallel to the surface of die substrate 1302 and two sidewall portions substantially perpendicular to the top surface of die substrate 1302. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of die substrate 1302 and not including sidewall portions substantially perpendicular to the top surface of die substrate 1302. In other embodiments, the gate electrode may include a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar non-U-shaped layers.

[0068] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to support the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and include deposition and etching processes. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0069] The S / D region 1320 may be formed within the die substrate 1302 adjacent to the gate 1322 of the individual transistor 1340. For example, the S / D region 1320 may be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be implanted into the die substrate 1302 by ion implantation to form the S / D region 1320. An annealing process to activate the dopant and further diffuse it into the die substrate 1302 may be performed after the ion implantation process. In the latter process, the die substrate 1302 may first be etched to form a recess at the location of the S / D region 1320. An epitaxial deposition process may then be performed to fill the recess with a material for fabricating the S / D region 1320. In some embodiments, the S / D region 1320 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials such as germanium or III-V materials or alloys may be used to form S / D region 1320. In further embodiments, S / D region 1320 may be formed using one or more layers of metals and / or metal alloys.

[0070] Electrical signals, such as power and / or input / output (I / O) signals, may be transmitted through one or more interconnect layers (in the device layer 1304) disposed on the device layer 1304. Fig.131306-1310) to and / or from devices (e.g., transistors 1340) of device layer 1304. For example, conductive features (e.g., gates 1322 and S / D contacts 1324) of device layer 1304 can be electrically coupled to interconnect structures 1328 of interconnect layers 1306-1310. One or more interconnect layers 1306-1310 can form a metallization stack (also referred to as an "ILD stack") 1319 of integrated circuit 1300.

[0071] Interconnect structure 1328 may be arranged within interconnect layers 1306-1310 to route electrical signals according to a variety of designs; in particular, the arrangement is not limited to Fig.13 The specific configuration of the interconnect structure 1328 depicted in FIG. Fig.13 A particular number of interconnect layers 1306 - 1310 are depicted in FIG. 1 , but embodiments of the present disclosure include integrated circuits having more or fewer interconnect layers than depicted.

[0072] In some embodiments, the interconnect structure 1328 may include wires 1328a and / or vias 1328b filled with a conductive material such as a metal. The wires 1328a may be arranged to route electrical signals in a direction substantially parallel to a plane of the surface of the die substrate 1302 on which the device layer 1304 is formed. For example, the wires 1328a may route electrical signals in a direction into and out of the page and / or in a direction across the page. The vias 1328b may be arranged to route electrical signals in a direction substantially perpendicular to a plane of the surface of the die substrate 1302 on which the device layer 1304 is formed. In some embodiments, the vias 1328b may electrically couple the wires 1328a of different interconnect layers 1306-1310 together.

[0073] The interconnect layers 1306-1310 may include a dielectric material 1326 disposed between interconnect structures 1328, such as Fig.13 1306-1310. In some embodiments, the dielectric material 1326 disposed between the interconnect structures 1328 in different ones of the interconnect layers 1306-1310 may have different compositions; in other embodiments, the composition of the dielectric material 1326 between different interconnect layers 1306-1310 may be the same. The device layer 1304 may also include a dielectric material 1326 disposed between the transistor 1340 and the bottom layer of the metallization stack. The dielectric material 1326 included in the device layer 1304 may have a different composition than the dielectric material 1326 included in the interconnect layers 1306-1310; in other embodiments, the composition of the dielectric material 1326 in the device layer 1304 may be the same as the dielectric material 1326 included in any one of the interconnect layers 1306-1310.

[0074] A first interconnect layer 1306 (referred to as metal 1 or "M1") can be formed directly on the device layer 1304. In some embodiments, the first interconnect layer 1306 can include lines 1328a and / or vias 1328b, as shown. The lines 1328a of the first interconnect layer 1306 can be coupled to contacts (e.g., S / D contacts 1324) of the device layer 1304. The vias 1328b of the first interconnect layer 1306 can be coupled to the lines 1328a of the second interconnect layer 1308.

[0075] A second interconnect layer 1308 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1306. In some embodiments, the second interconnect layer 1308 may include vias 1328b to couple the wires 1328 of the second interconnect layer 1308 with the wires 1328a of the third interconnect layer 1310. Although the wires 1328a and vias 1328b are structurally depicted as wires within individual interconnect layers for clarity, in some embodiments, the wires 1328a and vias 1328b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0076] A third interconnect layer 1310 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be sequentially formed on the second interconnect layer 1308 according to similar techniques and configurations as described in connection with the second interconnect layer 1308 or the first interconnect layer 1306. In some embodiments, interconnect layers that are "higher" (i.e., farther from the device layer 1304) in the metallization stack 1319 in the integrated circuit 1300 may be thicker than interconnect layers lower in the metallization stack 1319, with lines 1328a and vias 1328b in higher interconnect layers being thicker than lines 1328a and vias 1328b in lower interconnect layers.

[0077] The integrated circuit 1300 may include a solder resist material 1334 (eg, polyimide or a similar material) and one or more conductive contacts 1336 formed on the interconnect layers 1306-1310. Fig.13 , the conductive contact 1336 is illustrated as taking the form of a bonding pad. The conductive contact 1336 may be electrically coupled to the interconnect structure 1328 and configured to route electrical signals of the transistor (single or multiple) 1340 to an external device. For example, a solder joint may be formed on one or more conductive contacts 1336 to mechanically and / or electrically couple the integrated circuit die including the integrated circuit 1300 to another component (e.g., a printed circuit board). The integrated circuit 1300 may include additional or alternative structures to route electrical signals from the interconnect layers 1306-1310; for example, the conductive contact 1336 may include other similar features (e.g., pillars) that route electrical signals to external components.

[0078] In some embodiments where the integrated circuit 1300 is a double-sided die, the integrated circuit 1300 may include another metallization stack (not shown) on the opposite side of the device layer(s) 1304. The metallization stack may include a plurality of interconnect layers as discussed above with reference to the interconnect layers 1306-1310 to provide conductive paths (e.g., including conductive lines and vias) between the device layer(s) 1304 and additional conductive contacts (not shown) on the opposite side of the integrated circuit 1300 from the conductive contacts 1336.

[0079] In other embodiments where the integrated circuit 1300 is a double-sided die, the integrated circuit 1300 may include one or more through silicon vias (TSVs) through the die substrate 1302; these TSVs may contact the device layer(s) 1304 and may provide a conductive path between the device layer(s) 1304 and additional conductive contacts (not shown) on the side of the integrated circuit 1300 opposite the conductive contacts 1336. In some embodiments, the TSVs extending through the substrate may be used to route power and ground signals from conductive contacts on the side of the integrated circuit 1300 opposite the conductive contacts 1336 to the transistor 1340 and any other components integrated into the die 1300, and the metallization stack 1319 may be used to route I / O signals from the conductive contacts 1336 to the transistor 1340 and any other components integrated into the die 1300.

[0080] Multiple integrated circuits 1300 can be stacked with one or more TSVs in individual stacked devices, thereby providing a connection between one device in a device and any other device in the other devices in the stack. For example, one or more high bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die, and the TSVs in the HBM die can provide a connection between the individual HBM and the base integrated circuit chip. The conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine pitch solder bumps (microbumps).

[0081] Fig.14 14 is a cross-sectional side view of a microelectronic assembly 1400, which can include any of the embodiments disclosed herein. The microelectronic assembly 1400 includes a plurality of integrated circuit components disposed on a circuit board 1402 (which can be a motherboard, a system board, a mainboard, etc.). The microelectronic assembly 1400 can include components disposed on a first side 1440 of the circuit board 1402 and an opposing second side 1442 of the circuit board 1402; typically, the components can be disposed on one or both sides 1440 and 1442.

[0082] In some embodiments, circuit board 1402 may be a printed circuit board (PCB) comprising multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Individual metal layers include conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1402 (optionally in conjunction with other metal layers). In other embodiments, circuit board 1402 may be a non-PCB substrate. Fig.14 The microelectronic assembly 1400 shown in FIG. 1 includes a package-on-interposer structure 1436 coupled to a first side 1440 of a circuit board 1402 via a coupling member 1416. The coupling member 1416 can electrically and mechanically couple the package-on-interposer structure 1436 to the circuit board 1402 and can include solder balls (e.g., Fig.14 as shown), pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, an adhesive, a bottom fill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0083] The package-on-interposer structure 1436 may include an integrated circuit component 1420 coupled to the interposer 1404 via a coupling component 1418. The coupling component 1418 may take any suitable form for the application, such as those discussed above with reference to the coupling component 1416. Fig.14 A single integrated circuit component 1420 is shown in FIG. 1 , but multiple integrated circuit components may be coupled to interposer 1404; indeed, additional interposers may be coupled to interposer 1404. Interposer 1404 may provide an intermediate substrate for bridging circuit board 1402 and integrated circuit components 1420.

[0084] Integrated circuit component 1420 may be a packaged or unpackaged integrated circuit component that includes one or more integrated circuit dies (eg, Fig.12 The tube core 1202, Fig.13 integrated circuit 1300) and / or one or more other suitable components.

[0085] Unpackaged integrated circuit component 1420 includes solder bumps attached to contacts on the die. Solder bumps allow the die to be directly attached to insert 1404. In embodiments where integrated circuit component 1420 includes multiple integrated circuit dies, the dies may be of the same type (homogeneous multi-die integrated circuit component) or two or more different types (heterogeneous multi-die integrated circuit component). In addition to including one or more processor units, integrated circuit component 1420 may also include additional components such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memory, input / output (I / O) controller, or memory controller. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies separated from the integrated circuit die including the processor unit. These independent integrated circuit dies may be referred to as "chiplets". In embodiments where the integrated circuit component includes multiple integrated circuit dies, the interconnections between the dies may be provided by a packaging substrate, one or more silicon inserts, one or more silicon bridges embedded in the packaging substrate, or a combination thereof. The packaged multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0086] The interposer 1404 can extend the connection to a wider pitch, or reroute the connection to a different connection. For example, the interposer 1404 can couple the integrated circuit component 1420 to a set of ball grid array (BGA) conductive contacts of the coupling component 1416 for coupling to the circuit board 1402. Fig.14 In the illustrated embodiment, the integrated circuit component 1420 and the circuit board 1402 are attached to opposite sides of the interposer 1404; in other embodiments, the integrated circuit component 1420 and the circuit board 1402 may be attached to the same side of the interposer 1404. In some embodiments, three or more components may be interconnected through the interposer 1404.

[0087] In some embodiments, the insert 1404 can be formed as a PCB, including multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the insert 1404 can be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic fillers, ceramic materials, or polymer materials such as polyimide. In some embodiments, the insert 1404 can be formed of alternative rigid or flexible materials, which can include the same materials as those used in the semiconductor substrate described above, such as silicon, germanium, and other III-V and IV materials. The insert 1404 may include metal interconnects 1408 and vias 1410, including but not limited to through-hole vias 1410-1 (extending from the first side 1450 of the insert 1404 to the second side 1454 of the insert 1404), blind vias 1410-2 (extending from the first side 1450 or the second side 1454 of the insert 1404 to the internal metal layer) and buried vias 1410-3 (connecting the internal metal layer).

[0088] In some embodiments, interposer 1404 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, interposer 1404 including a silicon interposer may also include one or more routing layers to route connections on a first side of interposer 140 to an opposite second side of interposer 1404.

[0089] The interposer 1404 may also include embedded devices 1414, including passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 1404. The interposer package structure 1436 may take the form of any of the interposer package structures known in the art.

[0090] Integrated circuit assembly 1400 may include integrated circuit component 1424 coupled to first side 1440 of circuit board 1402 via coupling component 1422. Coupling component 1422 may take the form of any of the embodiments discussed above with reference to coupling component 1416, and integrated circuit component 1424 may take the form of any of the embodiments discussed above with reference to integrated circuit component 1420.

[0091] Fig.14The illustrated integrated circuit assembly 1400 includes a package-on-package structure 1434 coupled to a second side 1442 of a circuit board 1402 via a coupling component 1428. The package-on-package structure 1434 may include an integrated circuit component 1426 and an integrated circuit component 1432 coupled together via a coupling component 1430 such that the integrated circuit component 1426 is disposed between the circuit board 1402 and the integrated circuit component 1432. The coupling components 1428 and 1430 may take the form of any embodiment of the coupling component 1416 described above, and the integrated circuit components 1426 and 1432 may take the form of any embodiment of the integrated circuit component 1420 described above. The package-on-package structure 1434 may be configured according to any package-on-package structure known in the art.

[0092] Fig.15 1400, an integrated circuit component 1420, an integrated circuit 1300, an integrated circuit die 1202, or a structure disclosed herein. Fig.15 1500, but any one or more of these components may be omitted or duplicated to suit the application. In some embodiments, some or all of the components included in the electrical device 1500 may be attached to one or more motherboards, mainboards, printed circuit boards, or system boards. In some embodiments, one or more of these components are manufactured onto a single system-on-chip (SoC) die. In various embodiments, the electrical device 1500 is surrounded by or integrated with a housing.

[0093] Furthermore, in various embodiments, the electrical device 1500 may not include Fig.15 , but the electrical device 1500 may include an interface circuit system for coupling to one or more components. For example, the electrical device 1500 may not include the display device 1506, but may include a display device interface circuit system (e.g., a connector and driver circuit system), and the display device 1505 may be coupled to the display device interface circuit system. In another set of examples, the electrical device 1500 may not include the audio input device 1524 or the audio output device 1508, but may include an audio input or output device interface circuit system (e.g., a connector and supporting circuit system), and the audio input device 152 or the audio output device 1508 may be coupled to the audio input or output device interface circuit system.

[0094] The electrical device 1500 may include one or more processor units 1502 (e.g., one or more processor units). As used herein, the term "processor unit," "processing unit," or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1502 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general purpose GPUs (GPGPUs), accelerated processing units (APUs), field programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Therefore, a processor unit may be referred to as an XPU (or xPU).

[0095] The electrical device 1500 may include a memory 1504, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase change non-voltage memory), solid-state memory, and / or a hard disk drive. In some embodiments, the memory 1504 may include memory located on the same integrated circuit die as the processor unit 1502. The memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0096] In some embodiments, the electrical device 1500 may include one or more processor units 1502 that are heterogeneous or asymmetric with another processor unit 150 in the electrical device 1500. There may be various differences between the processor units 1502 in the system in terms of a range of merit metrics including architectural, microarchitectural, thermal, power consumption characteristics, etc. These differences may effectively manifest themselves as asymmetry and heterogeneity between the processor units 1502 in the electrical device 1500.

[0097] In some embodiments, the electrical device 1500 may include a communication component 1512 (e.g., one or more communication components). For example, the communication component 1512 may manage wireless communications for transferring data to and from the electrical device 1500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data using modulated electromagnetic radiation over a non-solid medium. The term "wireless" does not mean that the associated devices do not contain any wires, although in some embodiments they may not contain wires.

[0098] The communication component 1512 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE802.16-2005 amendment), Long Term Evolution (LTE) project and any amendments, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, which is an abbreviation standing for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed IEEE 802.16 standard conformance and interoperability testing. The communication component 1512 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1512 can operate according to GSM Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1512 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocol designated as 3G, 4G, 5G and higher. In other embodiments, the communication component 1512 can operate according to other wireless protocols. The electrical device 1500 may include an antenna 1522 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0099] In some embodiments, the communication component 1512 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., IEEE 802.3 Ethernet standard). As described above, the communication component 1512 can include multiple communication components. For example, the first communication component 1512 can be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, while the second communication component 1512 can be dedicated to longer-range wireless communications such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication component 1512 can be dedicated to wireless communications, while the second communication component 1512 can be dedicated to wired communications.

[0100] The electrical device 1500 may include a battery / power circuitry 1514. The battery / power circuitry 1514 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electrical device 1500 to an energy source separate from the electrical device 1500 (e.g., AC line power).

[0101] The electrical device 1500 may include a display device 1506 (or corresponding interface circuitry, as described above). The display device 1506 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0102] The electrical device 1500 may include an audio output device 1508 (or corresponding interface circuitry, as described above). The audio output device 1508 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0103] The electrical device 1500 may include an audio input device 1524 (or corresponding interface circuitry, as described above). The audio input device 1524 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a musical instrument digital interface (MIDI) output). The electrical device 1500 may include a global navigation satellite system (GNSS) device 1518 (or corresponding interface circuitry, as described above), such as a global positioning system (GPS) device. The GNSS device 1518 may communicate with a satellite-based system and may determine the geographic location of the electrical device 1500 based on information received from one or more GNSS satellites, as is known in the art.

[0104] The electrical device 1500 may include another output device 1510 (or corresponding interface circuitry, as described above). Examples of other output devices 1510 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0105] The electrical device 1500 may include another input device 1520 (or corresponding interface circuitry, as described above). Examples of other input devices 1520 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monoscopic or stereo camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device (such as a mouse, a stylus, a touch screen, a proximity sensor, a microphone, a barcode reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a PPG (photoplethysmography) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0106] The electrical device 1500 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a two-in-one convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable game console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray or base computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a fixed game console, a smart TV, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system as part of a vehicle, a smart appliance, a consumer electronic product or equipment, a manufacturing equipment). In some embodiments, the electrical device 1500 may be any other electronic device that processes data. In some embodiments, the electrical device 1500 may include multiple discrete physical components. Given the range of devices that the electrical device 1500 may be in various embodiments, in some embodiments, the electrical device 1500 may be referred to as a computing device or a computing system.

[0107] Although at least one embodiment has been given in the foregoing detailed description, it will be appreciated that there are a large number of variations. It will also be appreciated that the disclosed embodiments are merely examples and are not intended to limit the scope, applicability, or configuration of the present disclosure in any way. On the contrary, the above detailed description will provide a convenient roadmap for implementing the disclosed embodiments to those skilled in the art. Various changes may be made to the functions and arrangements of the elements without departing from the scope of the present disclosure as set forth in the appended claims and their legal equivalents.

[0108] As used herein, phrases such as "an embodiment," "various embodiments," and "some embodiments" indicate that some embodiments may have some, all, or none of the features described for other embodiments. "First," "second," "third," and the like describe a common object and represent different instances of similar objects being referenced; unless otherwise specified, they do not imply a given order, either in time or space, in ranking, or in any other manner. According to the patent application, "connected" refers to elements that are in direct physical or electrical contact with each other, and "coupled" refers to elements that cooperate or interact with each other, and coupled elements may or may not be in direct physical or electrical contact. In addition, synonyms such as the terms "include," "comprise," "have," and the like are used to indicate non-exclusive inclusion.

[0109] As used in the present application and claims, a list of items connected by the term "at least one" or the term "one or more" may mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean: A; B; C; A and B; A and C; B and C; or A, B, and C. Similarly, the phrase "one or more of A, B, and C" may mean: A; B; C; A and B; A and C; B and C; or A, B, and C.

[0110] As used in this application and in the claims, the phrase "an individual of" or "each of" preceding a list of items recited or stated as having a property, characteristic, etc. means that all items in the list have the recited or recited property, characteristic, etc. For example, the phrase "an individual of A, B, or C includes a sidewall" or "A, B, or C each includes a sidewall," means that A includes a sidewall, B includes a sidewall, and C includes a sidewall.

[0111] The theories of operation, scientific principles, or other theoretical descriptions stated herein with reference to the devices or methods disclosed herein are provided for better understanding and are not intended to limit their scope. The devices and methods in the appended claims are not limited to those devices and methods that function in the manner described by such theories of operation.

[0112] Unless otherwise specified, a term or value modified by the word "substantially" includes arrangements, orientations, spacings or positions that differ from the meaning of the unmodified term or value by plus or minus 20%. A term or value modified by the word "about" includes values ​​that are 10% less than the term or value to 10% greater than the term or value, including both endpoints.

[0113] As used herein, the term "electronic component" may refer to an active electronic circuit (eg, a processing unit, a memory, a storage device, a FET) or a passive electronic circuit (eg, a resistor, an inductor, a capacitor).

[0114] As used herein, the term "integrated circuit component" may refer to an electronic component configured on a semiconductor material to perform a function. An integrated circuit (IC) component may include any computing system component described or referenced herein or any other computing system component, such as a processor unit (e.g., a system on a chip (SoC), a processor core, a graphics processor unit (GPU), an accelerator, a chipset processor), an I / O controller, a memory, or a network interface controller, and may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0115] A non-limiting example of an unpackaged integrated circuit component includes a single monolithic integrated circuit die (referred to herein simply as a "die"); the die may include solder bumps attached to contacts on the die. When present on the die, the solder bumps or other conductive contacts may enable the die to be directly attached to a printed circuit board (PCB) or other substrate.

[0116] A non-limiting example of a packaged integrated circuit component includes one or more integrated circuit dies mounted on a package substrate, wherein the integrated circuit die and the package substrate are enclosed in a housing material, such as metal, plastic, glass, or ceramic. The housing typically includes an integrated heat sink (IHS); the packaged integrated circuit component typically has bumps, leads, or pins attached to the package substrate (directly or by wires attaching the bumps, leads, or pins to the package substrate) for attaching the packaged integrated circuit component to a printed circuit board (or motherboard or base board) or another component.

[0117] The following examples relate to additional embodiments of the technology disclosed herein.

[0118] Example

[0119] Example 1 is a substrate package comprising: an upper surface comprising a first conductive contact portion in a first arrangement at a first spacing and a second conductive contact portion in a second arrangement at a second spacing; a lower surface comprising a third conductive contact portion in a third arrangement at a third spacing; wherein the second spacing is less than 3 microns + / - 20%, and the first spacing and the third spacing are greater than 8 microns + / - 20%; a first region of a first dielectric material between the upper surface and the lower surface; a second region of a second dielectric material between the upper surface and the lower surface; wherein the first region and the second region are adjacent to each other substantially perpendicular to the upper surface; wherein the first region comprises a first redistribution layer (RDL) having a width greater than 9 microns + / - 20%; wherein the second region comprises a second redistribution layer (RDL) having a width less than three microns + / - 20%; wherein the first RDL provides an electrical path between a first first conductive contact in the first conductive contact portion and a first third conductive contact in the third conductive contact; and wherein the second RDL provides an electrical path between a first second conductive contact in the second conductive contact portion and a second second conductive contact in the second conductive contact portion.

[0120] Example 2 includes the subject matter of Example 1, wherein the second RDL further provides at least a portion of an electrical path between a third of the second conductive contacts and a second of the third conductive contacts.

[0121] Example 3 includes the subject matter of Example 1, wherein the first dielectric material and the second dielectric material are the same.

[0122] Example 4 includes the subject matter of Example 1, wherein the first dielectric material and the second dielectric material are different.

[0123] Example 5 includes the subject matter of any of Examples 1-4, further comprising a first lateral glass layer having a through glass via (TGV) in the first region.

[0124] Example 6 includes the subject matter of Example 5, wherein the first lateral glass layer has a thickness in a range from 100 microns + / - 10% to 1.5 millimeters + / - 10%.

[0125] Example 7 includes the subject matter of Example 5, wherein the first lateral glass layer extends below the second region, and further comprises: a cavity floor formed in the first lateral glass layer below the second region; and wherein the second RDL in the second region is capable of being operatively coupled to some of the TGVs in the cavity floor.

[0126] Example 8 includes the subject matter of any of Examples 1-4, further comprising a lateral epoxy layer in the first RDL.

[0127] Example 9 includes the subject matter of Example 1, wherein the first RDL and the second RDL include copper.

[0128] Example 10 includes the subject matter of Example 5 or Example 7, further comprising a second glass layer having a through-glass via in the second region.

[0129] Example 11 includes the subject matter of any of Examples 1-10, further comprising: a portion of the first region extending below the second region; and a cavity having a cavity floor formed in the portion of the first region below the second region.

[0130] Example 12 includes the subject matter of Example 11, wherein the second region is attached via a bonding film in the cavity floor.

[0131] Example 13 includes the subject matter of Example 11, wherein the second region is attached via a hybrid bond or a solder bump in the cavity floor.

[0132] Example 14 includes the subject matter of Example 13, wherein the second RDL is operably coupled to the first RDL in the cavity bottom surface.

[0133] Example 15 includes the subject matter of Example 11, wherein the second RDL is operatively coupled to the third arrangement of conductive contacts through the portion of the first region.

[0134] Example 16 includes the subject matter of any of Examples 1-15, further comprising: a layer of a third dielectric material between the lower surface and the first region and the second region.

[0135] Example 17 includes the subject matter of any of Examples 1-16, further comprising: a first integrated circuit die attached to the first portion of the second conductive contact and the first conductive contact; and a second integrated circuit die attached to the second portion of the second conductive contact.

[0136] Example 18 is a packaging assembly including the substrate package described in any one of Examples 1-17, further including: a first integrated circuit die attached to the first portion of the second conductive contact and the first conductive contact; a second integrated circuit die attached to the second portion of the second conductive contact; and a solder ball attached to the third conductive contact.

[0137] Example 19 includes the subject matter of Example 18, further comprising a printed circuit board (PCB) attached to the solder balls.

[0138] Example 20 is a method comprising: manufacturing a substrate package having a layer of dielectric material between an upper surface and a lower surface, wherein the dielectric material has a first redistribution layer (RDL) therein having a pitch greater than 9 microns + / - 20%, and wherein the upper surface includes a first conductive contact portion in a first arrangement at a first pitch and a second conductive contact portion in a second arrangement at a second pitch; producing a cavity having a cavity bottom surface in the dielectric material; manufacturing an organic bridge component of a second RDL having a pitch of three microns + / - 10% or less; and attaching the organic bridge component to the cavity bottom surface to create an electrical path between individuals of the second conductive contacts at the upper surface.

Claims

1. A substrate package, comprising: an upper surface including first conductive contacts in a first arrangement at a first spacing and second conductive contacts in a second arrangement at a second spacing; a lower surface including third conductive contacts in a third arrangement at a third spacing; wherein the second spacing is less than 3 microns + / - 20%, and the first spacing and the third spacing are greater than 8 microns + / - 20%; a first region of a first dielectric material between the upper surface and the lower surface; a second region of a second dielectric material between the upper surface and the lower surface; wherein the first region and the second region are adjacent to each other substantially perpendicularly to the upper surface; wherein the first region comprises a first redistribution layer (RDL) having a width greater than 9 microns + / - 20%; wherein the second region includes a second redistribution layer (RDL) having a width less than three microns + / - 20%; wherein the first RDL provides an electrical path between a first one of the first conductive contacts and a first one of the third conductive contacts; and The second RDL provides an electrical path between a first one of the second conductive contacts and a second one of the second conductive contacts.

2. The substrate package according to claim 1, wherein: The second RDL also provides at least a portion of an electrical path between a third of the second conductive contacts and a second of the third conductive contacts.

3. The substrate package according to claim 1, wherein: The first dielectric material and the second dielectric material are the same.

4. The substrate package according to claim 1, wherein: The first dielectric material and the second dielectric material are different. 5 . The substrate package of claim 1 , further comprising a first lateral glass layer having a through glass via (TGV) in the first region.

6. The substrate package according to claim 5, wherein: The thickness of the first transverse glass layer is in the range of 100 micrometers + / - 10% to 1.5 millimeters + / - 10%. 7 . The substrate package of claim 5 , further comprising a second glass layer having a through-glass via in the second region.

8. The substrate package according to claim 5, wherein: The first transverse glass layer extends below the second region and further comprises: a cavity bottom surface formed in the first lateral glass layer below the second region; and The second RDL in the second region can be operatively coupled to some of the TGVs in the cavity bottom surface. 9 . The substrate package of claim 8 , further comprising a second glass layer having a through-glass via in the second region. 10 . The substrate package of claim 1 , further comprising a lateral epoxy material layer in the first RDL.

11. The substrate package according to claim 1, wherein: The first RDL and the second RDL include copper.

12. The substrate package according to claim 1, further comprising: a portion of the first region extending below the second region; as well as A cavity has a cavity bottom surface formed in the portion of the first region below the second region.

13. The substrate package according to claim 2, further comprising: a portion of the first region extending below the second region; as well as A cavity has a cavity bottom surface formed in the portion of the first region below the second region.

14. The substrate package according to claim 5, further comprising: a portion of the first region extending below the second region; as well as A cavity has a cavity bottom surface formed in the portion of the first region below the second region.

15. The substrate package according to claim 8, further comprising: a portion of the first region extending below the second region; as well as A cavity has a cavity bottom surface formed in the portion of the first region below the second region.

16. The substrate package according to claim 9, further comprising: a portion of the first region extending below the second region; as well as A cavity has a cavity bottom surface formed in the portion of the first region below the second region.

17. The substrate package according to claim 16, wherein: The second region is attached by a bonding film in the cavity bottom surface.

18. The substrate package according to claim 16, wherein: The second region is attached by hybrid bonding or solder bumps in the cavity bottom surface.

19. The substrate package according to claim 13, wherein: The second RDL can be operatively coupled to the first RDL in the cavity bottom surface.

20. The substrate package according to claim 16, wherein: The second RDL is operatively coupled to the third arranged conductive contacts through the portion of the first region.

21. The substrate package according to claim 1, further comprising: A layer of a third dielectric material is between the lower surface and the first region and the second region.

22. The substrate package according to claim 1, further comprising: a first integrated circuit die attached to a first portion of the second conductive contact and the first conductive contact; as well as A second integrated circuit die is attached to the second portion of the second conductive contact.

23. A package assembly comprising the substrate package according to claim 1, further comprising: a first integrated circuit die attached to a first portion of the second conductive contact and the first conductive contact; a second integrated circuit die attached to a second portion of the second conductive contact; as well as A solder ball is attached to the third conductive contact.

24. The package assembly of claim 23, further comprising a printed circuit board (PCB) attached to the solder balls.

25. A method comprising: manufacturing a substrate package having a layer of dielectric material between an upper surface and a lower surface, wherein the dielectric material has a first redistribution layer (RDL) therein having a pitch greater than 9 microns + / - 20%, and wherein the upper surface includes first conductive contacts in a first arrangement at a first pitch and second conductive contacts in a second arrangement at a second pitch; creating a cavity having a cavity floor in the dielectric material; fabricating an organic bridge feature of a second RDL having a pitch less than or equal to three microns + / - 10%; and The organic bridge member is attached to the cavity bottom surface, thereby creating an electrical path between individuals of the second conductive contacts at the upper surface.

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