Semiconductor measurement structure

Abstract

The present application relates to a semiconductor measurement structure, comprising: a semiconductor substrate, in which an active area is arranged; a plurality of periodically arranged measurement structure patterns, wherein the measurement structure patterns include a groove located in the active area and a protrusion located on one side of the groove; along the direction perpendicular to the surface of the semiconductor substrate, the cross-sectional width of the measurement structure pattern is defined as the measurement pattern width, wherein the measurement pattern width is the sum of the cross-sectional width of the groove and the cross-sectional width of the protrusion, and the measurement pattern width is less than the measurement resolution limit of a measurement machine. The present application realizes rapid online monitoring of semiconductor measurement structures, and at the same time realizes online monitoring of silicon etching depth in the active area; by making the measurement pattern width less than the measurement resolution limit of the measurement machine, the area of ​​the semiconductor measurement structure is reduced, and the measurement speed of the semiconductor measurement structure is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor measurement structure. Background Art

[0002] As the size of semiconductor process technology gradually decreases, the advantages of optical critical dimension (OCD) measurement method are becoming more and more obvious. OCD measurement method can not only measure the thickness of two-dimensional (2D) critical dimensions, but also measure the cross-sectional structure (3D Profile) of semiconductor devices, with the advantages of fast measurement speed, accurate measurement results, and non-destructiveness.

[0003] For critical dimensions of 28nm and below, in order to further improve the voltage resistance of MOS devices, a longer channel and thicker oxide layer thickness are usually set in the MOS device, and a shallow trench isolation structure (STI) is set in the middle for isolation. For example, for a 28V MOS device, the corresponding channel length is greater than 2um. For the MOS device described above, the silicon etching depth above the active area (AA) is particularly critical.

[0004] The general film thickness measurement method cannot monitor the silicon (Si) etching depth, and can only be measured through a transmission electron microscope (TEM). However, using TEM to measure the silicon etching depth will slow down the process advancement speed and cannot monitor the online process in real time. At the same time, since the critical dimension size of MOS devices is much larger than the resolution limit of OCD measurement (Pitch < 2um), it is impossible to directly perform OCD measurement on the cross-sectional structure of MOS devices. Summary of the invention

[0005] Based on this, it is necessary to provide a semiconductor measurement structure to reduce the area of ​​the semiconductor measurement structure and facilitate online monitoring of the etching depth in the active area.

[0006] The present application provides a semiconductor measurement structure, comprising:

[0007] A semiconductor substrate, wherein an active region is disposed in the semiconductor substrate;

[0008] A plurality of periodically arranged measurement structure patterns, wherein the measurement structure patterns include a groove located in the active area and a protrusion located on one side of the groove;

[0009] The cross-sectional width of the measurement structure pattern in a direction perpendicular to the surface of the semiconductor substrate is defined as the measurement pattern width, wherein the measurement pattern width is the sum of the cross-sectional width of the groove and the cross-sectional width of the protrusion, and the measurement pattern width is less than the measurement resolution limit value of a measurement machine.

[0010] In one embodiment, the semiconductor measurement structure includes several groups of graphics, each group of graphics includes several measurement structure graphics, and when the semiconductor measurement structure includes at least two groups of measurement structure graphics, the size parameters of all the measurement structure graphics in the same group are the same, the cross-sectional widths of the grooves of any two groups of the measurement structure graphics are different, and the measurement graphic widths of any two groups of the measurement structure graphics are also different.

[0011] In one embodiment, the dimensional parameters include a cross-sectional width of the groove and a cross-sectional width of the protrusion.

[0012] In one embodiment, a single measurement structure pattern includes a plurality of grooves arranged in parallel and spaced apart, and a convex portion is provided on the same side of each groove, wherein different grooves have different cross-sectional widths, and different convex portions have the same cross-sectional width;

[0013] The measurement pattern width is the sum of the cross-sectional widths of all the grooves and the cross-sectional widths of all the protrusions.

[0014] In one embodiment, when there are at least two trenches with different cross-sectional widths in the semiconductor measurement structure, the trenches with different cross-sectional widths respectively correspond to different trench depths, and the trench depth is the cross-sectional depth of the trench along a direction perpendicular to the surface of the semiconductor substrate.

[0015] In one of the embodiments, in any of the grooves, the groove depth increases as the cross-sectional width of the groove increases.

[0016] In one embodiment, the measurement resolution limit value is less than or equal to 2 μm.

[0017] In one embodiment, the semiconductor substrate comprises:

[0018] a substrate, wherein the active region is located within the substrate;

[0019] A first dielectric layer, located on one side of the substrate;

[0020] A second dielectric layer, located on a side of the first dielectric layer away from the substrate;

[0021] The trench penetrates the second dielectric layer and the first dielectric layer and extends into the active area.

[0022] In one embodiment, the measurement machine includes an OCD measurement machine.

[0023] In one embodiment, the semiconductor metrology structure is located within a scribe line of a wafer.

[0024] The unexpected effect of the present application is: by setting a periodically arranged measurement structure pattern on the semiconductor substrate and making the measurement pattern width smaller than the measurement resolution limit of the measurement machine, the variation law of the groove etching is obtained by spectral fitting, so as to analyze and obtain the actual etching depth of the grooves with different size parameters in the semiconductor device, thereby realizing rapid online monitoring of the semiconductor measurement structure and realizing online monitoring of the silicon etching depth in the active area; by making the measurement pattern width smaller than the measurement resolution limit of the measurement machine, the area of ​​the semiconductor measurement structure is reduced, and the measurement speed of the semiconductor measurement structure is effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 It is a schematic diagram of the structure of a semiconductor device in the related art.

[0027] Figure 2 A schematic cross-sectional structure diagram of a semiconductor measurement structure provided in one embodiment of the present application when all measurement structure patterns are the same.

[0028] Figure 3 A schematic top view of a semiconductor measurement structure provided in one embodiment of the present application when all measurement structure patterns are the same.

[0029] Figure 4 A schematic top view of a semiconductor measurement structure provided in one embodiment of the present application includes at least two groups of measurement structure patterns.

[0030] Figure 5 A schematic cross-sectional structure diagram of a semiconductor measurement structure provided in one embodiment of the present application, wherein a single measurement structure pattern includes a plurality of trenches with different cross-sectional widths.

[0031] Figure 6A schematic top view of a semiconductor measurement structure provided in one embodiment of the present application includes a plurality of trenches with different cross-sectional widths in a single measurement structure pattern.

[0032] Explanation of the reference numerals: 100 - substrate; 101 - shallow trench isolation structure; 102 - silicon etching trench; 110 - oxide layer; 120 - silicon nitride layer; 200 - semiconductor base; 201 - active area; 202 - first dielectric layer; 203 - second dielectric layer; 210 - measurement structure pattern; 211 - trench; 212 - protrusion. DETAILED DESCRIPTION

[0033] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0035] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0036] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0037] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] Figure 1 FIG. 1 is a schematic diagram of a semiconductor device in a related art. Figure 1 The semiconductor device includes a substrate 100 , an oxide layer 110 located on the substrate 100 , and a silicon nitride layer 120 located on the oxide layer 110 , wherein a shallow trench isolation structure 101 (Shallow Trench Isolation, STI) and a silicon etching trench 102 are formed in the substrate 100 .

[0039] However, since the critical dimension size of semiconductor devices is much larger than the resolution limit of the optical critical dimension (OCD) measurement machine (Pitch < 2um), the area that can be monitored by the OCD measurement machine during the measurement process (i.e. Figure 1 The area selected by the middle dotted line is too small, and only part of the surface of the shallow trench isolation structure 101 and part of the surface of the silicon etching trench 102 are shown, and the overall structure of the semiconductor device cannot be shown, so it is difficult to obtain the accurate etching depth of the silicon etching trench 102 based on the measurement area.

[0040] In order to solve the above problems, the present application provides a semiconductor measurement structure to reduce the area of ​​the semiconductor measurement structure, which helps to achieve online monitoring of the etching depth in the active area.

[0041] Figure 2 A schematic diagram of a semiconductor measurement structure provided in one embodiment of the present application. Figure 3 for Figure 2 The schematic diagram of the top view of the measurement structure pattern in the semiconductor measurement structure shown. Figure 2 and Figure 3 In one embodiment of the present application, a semiconductor measurement structure includes: a semiconductor substrate 200 and a plurality of periodically arranged measurement structure patterns 210, wherein an active area 201 (Active Area, AA) is provided in the semiconductor substrate 200; the measurement structure pattern 210 includes a groove 211 located in the active area 201 and a protrusion 212 located on one side of the groove 211; along a direction perpendicular to the surface of the semiconductor substrate 200, a cross-sectional width of the measurement structure pattern 210 is defined as a measurement pattern width W, wherein the measurement pattern width W is the sum of a cross-sectional width A of the groove 211 and a cross-sectional width B of the protrusion 212, and the measurement pattern width W is less than a measurement resolution limit value of a measurement machine.

[0042] The semiconductor measurement structure as described above, by setting a periodically arranged measurement structure pattern on the semiconductor substrate and making the measurement pattern width smaller than the measurement resolution limit of the measurement machine, obtains the variation law of trench etching through spectral fitting, thereby analyzing and obtaining the actual etching depth of the trenches with different size parameters in the semiconductor device, thereby realizing rapid online monitoring of the semiconductor measurement structure and realizing online monitoring of the silicon etching depth in the active area; by making the measurement pattern width smaller than the measurement resolution limit of the measurement machine, the area of ​​the semiconductor measurement structure is reduced, and the measurement speed of the semiconductor measurement structure is effectively improved.

[0043] Continue reading Figure 2 In one embodiment, in one embodiment, the semiconductor substrate 200 includes a substrate (not shown in the figure), a first dielectric layer 202 and a second dielectric layer 203, wherein the active region 201 is located in the substrate, the first dielectric layer 202 is located on one side of the substrate (i.e., the first dielectric layer 202 is located on one side of the active region 201), and the second dielectric layer 203 is located on a side of the first dielectric layer 202 away from the substrate (i.e., the second dielectric layer 203 is located on a side of the first dielectric layer 202 away from the active region 201). The trench 211 penetrates the second dielectric layer 203 and the first dielectric layer 202 and extends into the active region 201.

[0044] In one embodiment, the material of the active region 201 includes silicon material, the material of the first dielectric layer 202 includes silicon oxide or other oxides, and the material of the second dielectric layer 203 includes silicon nitride. In other embodiments of the present application, the materials of different parts of the semiconductor measurement structure can be selected according to actual needs, and the present application does not limit this.

[0045] See also Figure 2 and Figure 3 In one embodiment, the dimensional parameters of multiple measurement structure patterns 210 in the semiconductor measurement structure (including at least the cross-sectional width A and the cross-sectional depth H of the groove 211 and the cross-sectional width B of the protrusion 212) are exactly the same, and the multiple measurement structure patterns are arranged periodically at equal intervals to reduce the error value of the measurement result of the measurement machine.

[0046] See also Figure 3 In one embodiment, the cross-sectional width A of the groove 211 of the measurement structure pattern 210 is the same as the cross-sectional width B of the protrusion 212, that is, the ratio of the cross-sectional width A of the groove 211 to the cross-sectional width B of the protrusion 212 is 1:1. In other embodiments of the present application, the ratio of the cross-sectional width A of the groove 211 to the cross-sectional width B of the protrusion 212 can be set according to the measurement resolution limit of the measurement machine and the actual width of the groove to be measured in the semiconductor device to ensure the accuracy of the subsequent measurement structure. Optionally, the ratio of the cross-sectional width A of the groove 211 to the cross-sectional width B of the protrusion 212 ranges from 1:1 to 1:10.

[0047] See also Figure 2 In one embodiment, the semiconductor measurement structure includes a plurality of groups of patterns, each group of patterns includes a plurality of measurement structure patterns 210, and when the semiconductor measurement structure includes at least two groups of measurement structure patterns 210, the size parameters of all measurement structure patterns 210 in the same group are the same, and the cross-sectional widths of the grooves 211 of any two groups of measurement structure patterns 210 are different, and the measurement pattern widths of any two groups of measurement structure patterns 210 are also different. Optionally, the size parameters include the cross-sectional width of the grooves 211 and the cross-sectional width of the protrusions 212.

[0048] Figure 4 The schematic diagram of the top view of the semiconductor measurement structure includes at least two groups of measurement structure patterns. Figure 4 The semiconductor measurement structure includes two sets of measurement structure patterns 210 ( Figure 4 The same group of measurement structure patterns 210 are located in the same row), and the size parameters of all measurement structure patterns 210 in the same group are the same.

[0049] Continue reading Figure 4, exemplarily, the cross-sectional width of the groove 211 of the measurement structure graphics 210 in the first group of graphics (i.e., the first row) is A1, the cross-sectional width of the protrusion 212 of the measurement structure graphics 210 in the first group of graphics is B1, and the measurement graphic width of the measurement structure graphics 210 in the first group of graphics is W1; the cross-sectional width of the groove 211 of all the measurement structure graphics 210 in the second group of graphics (i.e., the second row) is A2, the cross-sectional width of the protrusion 212 of all the measurement structure graphics 210 in the second group of graphics is B2, and the measurement graphic width of all the measurement structure graphics 210 in the second group of graphics is W2.

[0050] At the same time, the cross-sectional widths of the grooves 211 of different groups (ie, different rows) of the measurement structure patterns 210 are different (ie, A1 A2), different groups of measurement structure patterns 210 have different measurement pattern widths (ie, W1 Optionally, the cross-sectional widths of the protrusions 212 of different groups of measurement structure patterns 210 are the same (ie, B1=B2).

[0051] It should be noted that by simultaneously setting up several groups of measurement structure graphics with different size parameters in the semiconductor measurement structure, the area occupied by the semiconductor measurement structure is effectively reduced to ensure that the measurement machine can perform a one-time measurement of the semiconductor measurement structure and obtain the required measurement results; at the same time, simultaneously setting up several groups of measurement structure graphics with different size parameters in the semiconductor measurement structure helps to simultaneously monitor silicon etching grooves with different sizes in semiconductor devices, thereby expanding the application scope of the semiconductor measurement structure, saving process costs, and improving measurement efficiency.

[0052] Figure 5 A schematic cross-sectional structure diagram of a semiconductor measurement structure provided in one embodiment of the present application, wherein a single measurement structure pattern includes a plurality of trenches with different cross-sectional widths. Figure 6 A schematic top view of a semiconductor measurement structure provided in one embodiment of the present application includes a plurality of trenches with different cross-sectional widths in a single measurement structure pattern.

[0053] In one embodiment, a single measurement structure pattern includes a plurality of grooves arranged in parallel and spaced apart, and a protrusion is provided on the same side of each groove, wherein different grooves have different cross-sectional widths, different protrusions have the same cross-sectional width, and the measurement pattern width is the sum of the cross-sectional widths of all grooves and the cross-sectional widths of all protrusions.

[0054] For example, see Figure 5 and Figure 6, a single measurement structure pattern 210 includes three grooves 211 arranged in parallel at intervals, and a protrusion 212 is provided on the same side of each groove 211. Among them, different grooves 211 have different cross-sectional widths, different protrusions 212 have the same cross-sectional width, and the width W of the measurement pattern is the sum of the cross-sectional widths of all grooves 211 and the cross-sectional widths of all protrusions 212, that is, W = A1 + A2 + A3 + B1 + B2 + B3.

[0055] It should be noted that by setting multiple grooves with different cross-sectional widths in a single measurement structure pattern, the area occupied by the semiconductor measurement structure is effectively reduced to ensure that the measurement machine can perform a one-time measurement on the semiconductor measurement structure and obtain the required measurement results; it helps to simultaneously monitor the silicon etching grooves with different sizes in the semiconductor device, thereby expanding the applicable range of the semiconductor measurement structure, saving process costs, and improving measurement efficiency.

[0056] Continue to refer to Figure 5 , in one embodiment, when there are at least two grooves 211 with different cross-sectional widths in the semiconductor measurement structure, the groove depths corresponding to the grooves 211 with different cross-sectional widths are different, and the groove depth is the cross-sectional depth of the groove 211 in the direction perpendicular to the surface of the semiconductor substrate 200. Exemplarily, Figure 5 the cross-sectional widths among the three grooves 211 in satisfy A1 < A2 < A3, and correspondingly, the groove depths among the three grooves 211 satisfy H1 < H2 < H3. Optionally, in any groove 211, the groove depth increases as the cross-sectional width of the groove 211 increases.

[0057] In one embodiment, the aspect ratio of the groove (i.e., the ratio of the groove depth to the cross-sectional width of the groove) is the same as the aspect ratio of the silicon etching groove in the semiconductor device. In other embodiments of the present application, the size parameters of the待测 grooves in different regions of the semiconductor device can be measured by using the semiconductor measurement structure, as long as it is ensured that the size parameters of the grooves in the measurement structure pattern are the same as the size parameters of the待测 grooves. The present application does not limit this.

[0058] In one embodiment, the semiconductor measurement structure is located in a scribe line of a wafer. Optionally, the grooves in the semiconductor measurement structure and the待测 grooves to be measured in the semiconductor device are simultaneously fabricated in the same process to obtain the size parameters of the待测 grooves in the semiconductor device by measuring the size parameters of the grooves in the semiconductor measurement structure.

[0059] In one embodiment, the measuring machine includes an optical critical dimension (OCD) measuring machine, that is, an OCD measuring machine. Optionally, the measurement resolution limit value range of the OCD measuring machine is less than or equal to 2 μm.

[0060] It should be noted that, in the semiconductor measurement structure described above, the width of the measurement pattern is smaller than the measurement resolution limit, thereby ensuring that the measurement machine can achieve online measurement of the trench to be measured in the semiconductor device by measuring the semiconductor measurement structure. The periodic arrangement of the measurement structure pattern helps to calculate a stable deviation value (Bias) to feedback the measurement results.

[0061] In addition, under the premise that the width of the measured pattern is less than the measurement resolution limit, constructing grooves with different size parameters and performing spectrum fitting can obtain the variation law of groove etching, which is helpful to fit and give the actual etching depth of grooves with different size parameters in semiconductor devices. By combining with the detection results of transmission electron microscopy, the variation relationship between the etching conditions of the grooves in the semiconductor measurement structure and the actual etching conditions of the corresponding grooves in the semiconductor device can be corrected, so as to realize parameter monitoring of the groove structure in the semiconductor device by monitoring the semiconductor measurement structure, so as to monitor the process stability of the semiconductor device in real time.

[0062] The unexpected effect of the present application is: by setting a periodically arranged measurement structure pattern on the semiconductor substrate and making the measurement pattern width smaller than the measurement resolution limit of the measurement machine, the variation law of the groove etching is obtained by spectral fitting, so as to analyze and obtain the actual etching depth of the grooves with different size parameters in the semiconductor device, thereby realizing rapid online monitoring of the semiconductor measurement structure and realizing online monitoring of the silicon etching depth in the active area; by making the measurement pattern width smaller than the measurement resolution limit of the measurement machine, the area of ​​the semiconductor measurement structure is reduced, and the measurement speed of the semiconductor measurement structure is effectively improved.

[0063] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0064] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0065] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the application. It should be noted that, for a person of ordinary skill in the art, several modifications and improvements may be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A semiconductor measurement structure, characterized in that: include: A semiconductor substrate, wherein an active region is disposed in the semiconductor substrate; A plurality of periodically arranged measurement structure patterns, wherein the measurement structure patterns include a groove located in the active area and a protrusion located on one side of the groove; The cross-sectional width of the measurement structure pattern in a direction perpendicular to the surface of the semiconductor substrate is defined as the measurement pattern width, wherein the measurement pattern width is the sum of the cross-sectional width of the groove and the cross-sectional width of the protrusion, and the measurement pattern width is less than the measurement resolution limit value of a measurement machine.

2. The semiconductor measurement structure according to claim 1, characterized in that: The semiconductor measurement structure includes several groups of graphics, each group of graphics includes several measurement structure graphics, and when the semiconductor measurement structure includes at least two groups of measurement structure graphics, the size parameters of all the measurement structure graphics in the same group are the same, the cross-sectional widths of the grooves of any two groups of the measurement structure graphics are different, and the measurement graphic widths of any two groups of the measurement structure graphics are also different.

3. The semiconductor measurement structure according to claim 2, characterized in that: The size parameters include a cross-sectional width of the groove and a cross-sectional width of the protrusion.

4. The semiconductor measurement structure according to claim 1, wherein: A single measurement structure pattern comprises a plurality of grooves arranged in parallel and spaced apart, and a convex portion is provided on the same side of each groove, wherein different grooves have different cross-sectional widths, and different convex portions have the same cross-sectional width; The measurement pattern width is the sum of the cross-sectional widths of all the grooves and the cross-sectional widths of all the protrusions.

5. The semiconductor measurement structure according to claim 2 or 4, characterized in that: When there are at least two trenches with different cross-sectional widths in the semiconductor measurement structure, the trenches with different cross-sectional widths respectively correspond to different trench depths, and the trench depth is the cross-sectional depth of the trench along a direction perpendicular to the surface of the semiconductor substrate.

6. The semiconductor measurement structure according to claim 5, characterized in that: In any of the grooves, the groove depth increases as the cross-sectional width of the groove increases.

7. The semiconductor measurement structure according to claim 1, wherein: The measurement resolution limit value is less than or equal to 2 μm.

8. The semiconductor measurement structure according to claim 1, wherein: The semiconductor substrate comprises: a substrate, wherein the active region is located within the substrate; A first dielectric layer, located on one side of the substrate; A second dielectric layer, located on a side of the first dielectric layer away from the substrate; The trench penetrates the second dielectric layer and the first dielectric layer and extends into the active area.

9. The semiconductor measurement structure according to claim 1, wherein: The measuring machine includes an OCD measuring machine.

10. The semiconductor measurement structure according to claim 1, wherein: The semiconductor measurement structure is located in a dicing path of a wafer.

Images