Time sequence adjusting unit and method and related equipment

Abstract

The invention provides a time sequence adjusting unit, a time sequence adjusting method and related equipment, which are applied to the technical field of computers, the time sequence adjusting unit comprises an enabling unit and at least one delay unit, each delay unit is connected in series in a signal transmission path, the enabling unit provides a corresponding enabling signal for each delay unit, and the enabling signal is transmitted to the signal transmission path. And the delay unit responds to the obtained enable signal, and prolongs the propagation duration of the communication signal in the signal transmission path based on the time sequence violation duration of the signal transmission path to which the delay unit belongs. According to the time sequence adjusting unit provided by the invention, the propagation duration of the communication signal can be prolonged according to the time sequence violation duration only by connecting one delay unit in series in the signal transmission path, so that the time sequence violation is repaired, and compared with the prior art, the number of units inserted into a chip for repairing the time sequence violation is greatly reduced, and the time sequence adjusting efficiency is improved. Therefore, the occupation of the chip space is effectively reduced, and the effective utilization rate of the chip space is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a timing adjustment unit, method and related equipment. Background Art

[0002] In integrated circuit design, communication signals are transmitted through data transmission paths. In actual applications, due to the short transmission time of communication signals or the clock imbalance between different units in the data transmission channel, timing violations such as difficulty in meeting the hold time requirements often occur. For example, in order to repair the timing, the prior art usually needs to add a buffer in the corresponding data transmission path to extend the signal propagation time in order to meet the hold time requirements in the timing design.

[0003] However, the inventors have discovered that, using the prior art timing violation repair method, when repairing some data transmission paths with larger timing violations, it is necessary to insert many buffers, even dozens of buffers, which takes up a large chip area and easily leads to excessive local density of the chip, making it impossible to insert other functional units, thus seriously reducing the effective utilization of the chip space. Summary of the invention

[0004] In view of this, the present application is dedicated to providing a timing adjustment unit, method and related equipment to solve the problem of excessive use of buffers in the prior art leading to low chip space utilization.

[0005] In a first aspect, the present application provides a timing adjustment unit, which is applied to a semiconductor integrated circuit. The timing adjustment unit includes: an enabling unit and at least one delay unit, wherein:

[0006] Each of the delay units is connected in series in a signal transmission path;

[0007] The enabling unit is connected to the enabling end of each of the delay units respectively, and provides a corresponding enabling signal to each of the delay units;

[0008] The delay unit responds to the obtained enable signal and extends the propagation time of the communication signal in the signal transmission path based on the timing violation time of the corresponding signal transmission path.

[0009] In an optional implementation, the enabling unit includes a pulse signal generating unit, and the enabling signal includes a pulse signal.

[0010] In an optional implementation, the pulse width of the pulse signal is determined based on the timing violation duration.

[0011] In an optional implementation, the pulse signal generating unit includes a clock terminal and at least one pulse terminal, wherein:

[0012] The clock terminal shown is used to receive a clock signal;

[0013] Each of the pulse ends is connected to at least one of the delay units;

[0014] The pulse signal generating unit generates a pulse signal based on the clock signal, and the duty ratios of the pulse signals outputted by the pulse terminals are different from each other.

[0015] In an optional implementation, the pulse signal generating unit and each of the signal transmission paths use the same clock signal.

[0016] In an optional implementation, the delay unit includes a D-type latch, wherein:

[0017] The signal latching path of the D-type latch is connected in series with the signal transmission path;

[0018] The enable terminal of the D-type latch serves as the enable terminal of the delay unit;

[0019] The D-type latch responds to the obtained enable signal and prolongs the latching time of the general signal in the signal transmission path based on the timing violation time of the corresponding signal transmission path, so as to prolong the propagation time of the communication signal in the signal transmission path.

[0020] In an optional implementation, the D-type latch receives the enable signal before receiving the communication signal.

[0021] In a second aspect, the present application provides a timing adjustment method, which is applied to a semiconductor integrated circuit, and the method comprises:

[0022] Obtaining a timing violation duration of a signal transmission path in the semiconductor integrated circuit;

[0023] Providing a timing adjustment unit, the timing adjustment unit comprising an enabling unit and at least one delay unit respectively connected to the enabling unit;

[0024] Connecting each of the delay units in series in a signal transmission path;

[0025] The enabling unit is configured according to the timing violation duration so that the enabling unit provides a corresponding enabling signal to each delay unit, and the enabling signal is used to drive each delay unit to extend the propagation duration of the communication signal in the corresponding signal transmission path based on the timing violation duration.

[0026] In an optional implementation, the enabling unit includes a pulse signal generating unit, and the enabling signal includes a pulse signal;

[0027] Configuring the enabling unit according to the timing violation duration includes:

[0028] The pulse width of the pulse signal generated by the pulse signal generating unit is configured according to the timing violation duration.

[0029] In a third aspect, the present application provides a semiconductor integrated circuit, comprising: at least one signal transmission path and a timing adjustment unit as described in any one of the first aspects of the present application, wherein:

[0030] The delay unit of the timing adjustment unit is connected in series in a signal transmission path where a timing violation exists.

[0031] In a fourth aspect, the present application provides a system on chip, comprising: a semiconductor integrated circuit as described in the third aspect of the present application.

[0032] In a fifth aspect, the present application provides an electronic device, comprising: a system on a chip as described in the fourth aspect of the present application.

[0033] Based on the above content, the timing adjustment unit provided by the present application includes an enabling unit and at least one delay unit, each delay unit is connected in series in a signal transmission path, the enabling unit provides corresponding enabling signals to each delay unit respectively, and the delay unit responds to the obtained enabling signal, and extends the propagation time of the communication signal in the signal transmission path based on the timing violation duration of the signal transmission path to which it belongs. Through the timing adjustment unit provided by the present application, only one delay unit needs to be connected in series in the signal transmission path, and the propagation time of the communication signal can be extended according to the timing violation duration, thereby repairing the timing violation. Compared with the prior art, the number of units inserted in the chip for repairing the timing violation is greatly reduced, thereby effectively reducing the occupation of the chip space and improving the effective utilization rate of the chip space. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 It is a structural schematic diagram of a data transmission path in an integrated circuit in the prior art.

[0036] Figure 2 It is a schematic diagram of a scenario of repairing timing violations in the prior art.

[0037] Figure 3 This is a structural block diagram of a timing adjustment unit provided in this application.

[0038] Figure 4 It is a structural schematic diagram of a pulse signal generating unit provided in the present application.

[0039] Figure 5 It is a waveform diagram of the pulse signal provided by the pulse signal generating unit provided in the present application.

[0040] Figure 6 It is a waveform diagram of repairing a timing violation using the timing adjustment power supply provided by the present application.

[0041] Figure 7 This is a structural block diagram of another timing adjustment unit provided in the present application.

[0042] Figure 8 This is a flow chart of a timing adjustment method provided by the present application.

[0043] Fig. 9 It is a structural block diagram of an electronic device provided by this application. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0045] In integrated circuit design, communication signals are transmitted through data transmission paths. Figure 1 As shown, a typical data transmission path in a semiconductor integrated circuit includes a register FF0 for sending data and a register FF1 for receiving data. For any register, a clock signal input terminal CK, a signal input terminal D, and a signal output terminal Q are configured. Register FF0 is connected to register FF1 through a connecting line. Furthermore, a logic unit may be provided in the connecting line to implement a preset data operation or data processing function. In practical applications, the logic unit is set according to the actual data processing requirements. In order to ensure the reliability of data transmission in the data transmission path, the requirements of the setup time and hold time of the timing path need to be met between register FF0 and register FF1. In practical applications, due to the short transmission time of the communication signal or the clock imbalance between different units in the data transmission channel, timing violation problems such as the difficulty in meeting the hold time requirements often occur.

[0046] Combination Figure 2As shown, in order to fix the timing violation and meet the requirement of holding time in timing design, the prior art usually needs to add a buffer in the corresponding data transmission path ( Figure 2 The inventors have found that the buffer can maintain the communication signal for a certain period of time. Therefore, when using the timing violation repair method of the prior art to repair some data transmission paths with large timing violations, it is necessary to insert many buffers, even dozens of buffers, which takes up a large chip area and easily leads to excessive local density of the chip, so that other functional units cannot be inserted, which seriously reduces the effective utilization rate of the chip space.

[0047] To solve the above problems, the present application provides a timing adjustment unit, which is applied to semiconductor integrated circuits. Through the timing adjustment unit provided by the present application, only a delay unit needs to be connected in series in the signal transmission path to extend the propagation time of the communication signal according to the timing violation duration, thereby repairing the timing violation. Compared with the prior art, the number of units inserted in the chip for repairing timing violations is greatly reduced, thereby effectively reducing the occupancy of the chip space and improving the effective utilization of the chip space.

[0048] See also Figure 3 As shown, the timing adjustment unit provided by the present application includes: at least one delay unit 10 and an enabling unit 20. It should be noted that, in order to facilitate the explanation of the principle of the timing adjustment unit provided by the present application to solve the timing violation, Figure 3 The illustrated embodiment is shown with one delay unit 10. As for the case where more than one delay unit is included, it will be expanded in detail in the subsequent content and will not be described in detail here.

[0049] Combination Figure 3 As shown, the delay unit 10 is configured with an enable terminal EN, a signal input terminal X, and a signal output terminal Y. It can be understood that the signal input terminal X and the signal output terminal Y of the delay unit 10 constitute the signal transmission path of the delay unit 10. In practical applications, the signal input terminal X of the delay unit is connected to the signal output terminal Q of the register FF0 located upstream in the signal transmission direction through the signal transmission path, and the signal output terminal Y of the delay unit is connected to the signal input terminal D of the register FF1 located downstream in the signal transmission direction through the signal transmission path (for ease of description, the logic unit set in the signal transmission path is omitted), so that the delay unit 10 is connected in series in the signal transmission path between the register FF0 and the register FF1.

[0050] Furthermore, the signal output end of the enable unit 20 is connected to the enable end EN of the delay unit 10. The enable unit 20 can provide a corresponding enable signal to the delay unit 10 according to the configuration. The delay unit 10 responds to the obtained enable signal and, based on the timing violation duration of the corresponding signal transmission path (i.e., the signal transmission path connected in series with the delay unit 10), extends the propagation time of the communication signal in the signal transmission path, thereby achieving the purpose of extending the holding time of the communication signal, thereby repairing the holding time violation.

[0051] To summarize, the timing adjustment unit provided in this embodiment and the delay unit are connected in series in the signal transmission path, the enable unit provides a corresponding enable signal to the delay unit, and the delay unit responds to the obtained enable signal to extend the propagation time of the communication signal in the signal transmission path based on the timing violation duration of the signal transmission path to which it belongs. With such a configuration, only one delay unit needs to be connected in series in the signal transmission path, and the propagation time of the communication signal can be extended according to the timing violation duration, thereby repairing the timing violation. Since the propagation time is extended based on the timing violation duration, the timing adjustment unit provided in this application only needs to connect one delay unit in series in the signal transmission path to meet different application scenarios, that is, application requirements with different timing violation durations. Compared with the prior art, the number of units inserted in the chip for repairing timing violations is greatly reduced, thereby effectively reducing the occupancy of chip space and improving the effective utilization of chip space.

[0052] In an optional embodiment, the enabling unit in the timing adjustment unit provided in the present application includes a pulse signal generating unit (Pulse Generator, PG), and accordingly, the enabling signal provided by the enabling unit is a pulse signal, and the pulse signal generating unit is configured with a clock end and at least one pulse end, wherein the pulse end is used as the signal output end of the enabling unit, and is connected to the enabling end of the corresponding delay unit, and the number of pulse ends to be set needs to be determined in combination with the number of signal transmission paths that require timing repair, and the specific composition of the pulse signal generating unit. The present application does not limit the specific number of pulse ends in the pulse signal generating unit. As for the specific implementation of the pulse signal generating unit, it can be implemented with reference to the relevant technology, and the present application does not make specific limitations on this.

[0053] In the actual use of the pulse signal generating unit, the clock terminal CL of the pulse signal generating unit is used to receive the clock signal, and each pulse terminal is used to connect at least one delay unit. It can be understood that when a pulse terminal is connected to more than one delay unit, the timing corresponding to the delay units connected to the same pulse terminal is the same, for example, the duration. Further, based on the obtained clock signal, a corresponding pulse signal is generated according to a preset duty cycle.

[0054] Combination Figure 5As shown, the clock end of the pulse signal generating unit receives the clock signal CLOCk, and generates pulse signals with different duty cycles through the internal signal conversion circuit. Figure 5 In the example shown, the pulse signal generating unit outputs a first pulse signal ECK11 through the pulse terminal ECK1, and correspondingly, outputs a second pulse signal ECK12 through the pulse terminal ECK2. It is understandable that in practical applications, the duty cycles of the pulse signals output by the pulse signal generating unit through different pulse terminals may be the same or different.

[0055] In application scenarios where different violation durations need to be repaired, pulse signals with different duty cycles can be provided in a variety of ways. In an optional implementation, the same pulse signal generating unit can be configured to output pulse signals with different duty cycles, that is, pulse signals with different duty cycles are output through each pulse end, and each pulse end is connected to at least one delay unit; in another optional implementation, if the semiconductor integrated circuit has a large space margin, multiple pulse signal generating units can be integrated in the semiconductor integrated circuit, and the duty cycles of the pulse signals provided by each pulse signal generating unit are different.

[0056] In an optional embodiment, the pulse signal generating unit and each signal transmission path in the semiconductor integrated circuit use the same clock signal. Such a setting helps to reduce the number of clock units set in the semiconductor integrated circuit, thereby ensuring more space for configuring other functional units and improving the integration of the semiconductor integrated circuit.

[0057] Furthermore, in an optional embodiment, the delay unit provided by the present application is implemented based on a latch, which is a storage unit circuit that is sensitive to pulse levels and can change state under the action of a specific input pulse signal. Latching is to temporarily store the communication signal to maintain a certain level state. The main function of the latch is caching, and secondly, it is used to complete the asynchronous problem between the high-speed controller and the slow peripheral. At the same time, it can also solve the problem that an input / output port can both output and input.

[0058] In the present application, a D-type latch can be selected as a delay unit. Combined with the basic structure of the D-type latch, it can be known that the D-type latch includes a signal input terminal, a signal output terminal and an enable terminal. The signal input terminal and the signal output terminal constitute the signal latch path of the D-type latch, and the enable terminal is used to control the signal propagation process of the signal latch path. As for the principle of the D-type latch latching the transmitted signal and the specific signal flipping process, it will not be described in detail here, and the details can be referred to the relevant technology. When applied to the timing adjustment unit provided in the present application, the signal input terminal of the D-type latch is used as the signal input terminal of the delay unit, and the signal output terminal of the D-type latch is used as the signal output terminal of the delay unit. Correspondingly, the enable terminal of the D-type latch is used as the enable terminal of the delay unit.

[0059] Based on the above content, referring to the connection mode of the delay unit described in the above embodiment, the signal latch path of the D-type latch is connected in series in the signal transmission path, and the enable end of the D-type latch is connected to the signal output end of the enable unit as the enable end of the delay unit, and receives the enable signal provided by the enable unit. Further, the D-type latch responds to the obtained enable signal and extends the latching time of the communication signal in the signal transmission path based on the timing violation time of the signal transmission path to which it belongs, so as to extend the propagation time of the communication signal in the signal transmission path.

[0060] Combine the following Figure 3 as well as Figure 6 The signal flipping process shown in the figure will introduce in detail the specific process of the timing adjustment power supply repairing the hold time violation provided by the present application.

[0061] In the signal transmission path formed by register FF0, register FF1 and the connecting line, the timing adjustment unit provided by the present application is configured, and the latch in the timing adjustment unit is connected in series in the signal transmission path. Specifically, the signal latch path of the D-type latch is connected in series in the signal transmission path, and the enable end of the D-type latch is connected to the pulse end of the pulse signal generating unit. The pulse signal generating unit, register FF0 and register FF1 work under the same clock signal drive, and output the pulse signal with the rising edge of the clock signal. In terms of timing configuration, it is required that the D-type The enable signal received by the latch enable terminal EN must arrive earlier than the communication signal received by the D-type latch signal input terminal X, that is, the moment when the D-type latch receives the enable signal is required to be earlier than the moment when the D-type latch receives the communication signal. Only with such a configuration can it be ensured that the level (or signal) of the signal output terminal Y of the D-type latch is reliably latched and will not change with the change of the signal received by the signal input terminal X, that is, when a high level pulse signal is received, the D-type latch latches the output signal, and the signal flip on the register FF0 side will not affect the hold timing of the next level FF1.

[0062] Combination Figure 6As shown, when the rising edge of the first clock signal CLOCk arrives, the register FF0 is delayed by a certain register unit, and the communication signal is output to the signal input terminal X of the D-type latch, and the communication signal is flipped from a low level to a high level. Based on the above content, the enable signal received by the enable terminal EN of the D-type latch comes from the pulse signal generating unit, and the pulse signal has set the enable terminal of the D-type latch to 1 before the rising edge of the communication signal provided by the register FF0 arrives. Therefore, there will be no signal flipping at the output terminal Y of the D-type latch, thereby not affecting the hold time check of the next level register FF1.

[0063] Furthermore, when the rising edge of the third clock signal CLOCK arrives, register FF0 outputs the communication signal to the signal input terminal X of the D-type latch after a certain register unit delay, and the communication signal flips to a low level. At this time, the high level of the pulse signal provided by the pulse signal generating unit is still continuing, and the D-type latch is in a latched state. The signal flip of its signal input terminal X will not be transmitted to the signal output terminal Y, and the original output communication signal (i.e., high level) will continue to be output, thereby extending the propagation time of the communication signal in the signal transmission path. Only when the pulse jumps from a high level to a low level, the D-type latch no longer latches the data, and the communication signal of the signal input terminal X is normally transmitted to the signal output terminal Y, and further transmitted to the register FF1, completing a communication signal delay function.

[0064] Based on the above process, it can be seen that the pulse width of the pulse signal provided by the pulse signal generating unit will affect the specific duration of extending the communication signal propagation. Figure 6 In the example shown, the time difference between the falling edge of the third pulse signal and the falling edge of the communication signal received by the D-type latch is the extended propagation time of the communication signal, that is, the time used to repair the hold time violation. Therefore, in practical applications, the duty cycle of the pulse signal should be determined based on the timing violation time of the signal transmission path, thereby ensuring that the propagation time of the communication signal is extended just enough to repair the hold time violation.

[0065] It is understandable that in Figure 6 In the example shown, when the falling edge of the first pulse signal and the second pulse signal arrives, the signal output end of the D-type latch will also change with the signal input end, but at this time the signal input end continues to receive a high level, and the received communication signal has not changed. Therefore, the level of the signal output end Y of the D-type latch will not change, and it will also continue to output a high level.

[0066] Furthermore, in practical applications, there are situations where multiple signal transmission paths that are relatively close to each other in a semiconductor integrated circuit have hold time violations at the same time. Since these signal transmission paths are relatively concentrated, if Figure 3The timing adjustment unit provided in the illustrated embodiment repairs the timing violations of each signal transmission path, which obviously occupies a large area of ​​the integrated circuit. To solve this problem, the present application provides another timing adjustment unit based on the aforementioned embodiment. The timing adjustment unit provided in this embodiment includes an enabling unit and two or more delay units, and each delay unit shares the enabling unit, thereby reducing the number of enabling units set.

[0067] Combination Figure 7 As shown, register FF0, register FF1 and the connection line between the two constitute a first signal transmission path, and correspondingly, register FF2, register FF3 and the connection line between the two constitute a second signal transmission path. The two are arranged close to each other in the integrated circuit, and both have a hold time violation. In this scenario, the timing adjustment unit includes an enable unit (i.e., the aforementioned pulse signal generation unit) and two delay units (i.e., the aforementioned D-type latch), each of which is connected in series in a signal transmission path, that is, delay unit 1 is connected in series to the first signal transmission path, and delay unit 2 is connected in series to the second signal transmission path. Further, the enable unit is connected to the enable end of each delay unit, respectively, and can provide a corresponding enable signal to each delay unit, respectively. Each delay unit responds to the obtained enable signal and extends the propagation time of the signal in the signal transmission path based on the timing violation duration of the signal transmission path to which it belongs. As for the specific process of each delay unit repairing the hold time violation of the signal transmission path to which it belongs, please refer to the aforementioned content and will not be repeated here.

[0068] Combining the above content and Figure 7 As shown, it can be seen that the timing adjustment unit provided in this embodiment has multiple delay units sharing one enable unit, and the same enable unit can provide enable signals for multiple delay units. Under the premise of repairing the timing violations of multiple signal transmission paths, the area occupied can be reduced as much as possible, which is of great significance for improving the space utilization of semiconductor integrated circuits.

[0069] It should be noted that in Figure 7 In the example shown, the enabling unit includes two pulse ends, each of which is connected to a delay unit. Based on this setting, the enabling unit can provide pulse signals corresponding to different duty cycles to each delay unit, thereby repairing signal transmission paths corresponding to different violation durations. It can be understood that in actual applications, any pulse end of the enabling unit can also be connected to two or more delay units, providing pulse signals corresponding to the same duty cycle to each delay unit, thereby simultaneously repairing multiple signal transmission paths corresponding to the same or similar violation durations, further reducing the units inserted in the chip for repairing timing violations, effectively reducing the occupation of chip space, and improving the effective utilization of chip space.

[0070] Furthermore, the present application also provides a timing adjustment method for repairing the hold time violation of the signal transmission path in the semiconductor integrated circuit. Figure 8 As shown, the timing adjustment method provided by the present application includes the following steps.

[0071] S100, obtaining a timing violation duration of a signal transmission path in a semiconductor integrated circuit.

[0072] In the process of designing semiconductor integrated circuit layout, it is necessary to use relevant design software to perform timing analysis on semiconductor integrated circuits to determine the hold time, setup time and other information of each signal transmission path in the semiconductor integrated circuit during the transmission of communication signals, and then determine whether there is a timing violation in each signal transmission path according to the design requirements, as well as the corresponding violation duration and other information. Based on this, in this application, the timing violation duration of each signal transmission path can be obtained through relevant design software. Of course, in this application, the violation duration of the hold time is mainly determined.

[0073] S110. Provide a timing adjustment unit.

[0074] In order to solve the timing violation problem of the semiconductor integrated circuit, the method provides a timing adjustment unit for the semiconductor integrated circuit, and the timing adjustment unit includes an enabling unit and at least one delay unit respectively connected to the enabling unit. As for the specific configuration of the enabling unit and the delay unit, and the connection relationship between the enabling unit and the delay unit, please refer to the above content for details, which will not be repeated here.

[0075] S120, connecting each delay unit in series in a signal transmission path.

[0076] The timing adjustment unit includes at least one delay unit, each of which is connected in series to a signal transmission path. Of course, the signal transmission paths connected in series to the delay units are different from each other, and the hold time violation of the signal transmission path is repaired by the delay unit.

[0077] S130 , configuring an enabling unit according to the timing violation duration.

[0078] Based on the foregoing, it can be known that each delay unit is controlled by an enabling unit. Therefore, before repairing the hold time violation, it is necessary to configure the enabling unit according to the timing violation duration of each signal transmission path in the integrated circuit, so that the enabling unit provides a corresponding enabling signal to each delay unit. Each delay unit responds to the obtained enabling signal and extends the propagation time of the communication signal in the corresponding signal transmission path based on the timing violation duration, thereby repairing the hold time violation of the corresponding signal transmission path.

[0079] In an optional embodiment, the enabling unit is implemented based on the pulse signal generating unit, and the pulse signal provided by the pulse signal generating unit is used as the enabling signal. Based on this, the pulse width of the pulse signal of the pulse signal generating unit can be configured according to the timing violation duration obtained in the above steps, thereby ensuring that the flipping of the pulse signal can control the delay unit to extend the propagation time of the communication signal in the signal transmission path based on the timing violation duration, thereby effectively repairing the timing violation.

[0080] As for the specific process of repairing the hold time violation of the signal transmission path through the timing adjustment unit, reference may be made to the relevant contents of the aforementioned embodiment, which will not be repeated here.

[0081] In summary, the timing adjustment method provided in the present embodiment configures a timing adjustment unit in the semiconductor integrated circuit after obtaining the timing violation duration of the signal transmission path in the semiconductor integrated circuit, and repairs the hold time violation of the signal transmission path through the timing adjustment unit. The timing adjustment unit includes an enabling unit and at least one delay unit, each of which is connected in series in a signal transmission path, and the propagation time of the communication signal in the signal transmission path is extended based on the timing violation duration of the signal transmission path to which it belongs. Only one delay unit needs to be connected in series in the signal transmission path to repair the timing violation, and the number of units inserted in the chip for repairing the timing violation is greatly reduced, thereby effectively reducing the occupation of the chip space and improving the effective utilization rate of the chip space.

[0082] The present application also provides a semiconductor integrated circuit, comprising: at least one signal transmission path and a timing adjustment unit provided in any one of the above embodiments, wherein:

[0083] The delay unit of the timing adjustment unit is connected in series in a signal transmission path where a timing violation exists.

[0084] The present application also provides a system on chip, comprising: the semiconductor integrated circuit provided by the aforementioned embodiment.

[0085] The present application also provides an electronic device, including: a system on chip as provided in the aforementioned embodiment.

[0086] Furthermore, the present application also provides another electronic device, which performs the timing adjustment method provided by the present application. Fig. 9 To describe the electronic device provided by the embodiment of the present invention, the electronic device provided by the embodiment may include: at least one processor 100, at least one communication interface 200, at least one memory 300 and at least one communication bus 400;

[0087] In the embodiment of the present invention, the number of the processor 100, the communication interface 200, the memory 300, and the communication bus 400 is at least one, and the processor 100, the communication interface 200, and the memory 300 communicate with each other through the communication bus 400; obviously, Fig. 9 The communication connections shown for the processor 100, the communication interface 200, the memory 300, and the communication bus 400 are merely optional;

[0088] Optionally, the communication interface 200 may be an interface of a communication module, such as an interface of a GSM module; the processor 100 may be a central processing unit CPU, or an application specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0089] The memory 300 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0090] The processor 100 is specifically used to execute the application program in the memory to implement the steps of the timing adjustment method described above.

[0091] In some embodiments, this embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., in which one or more instructions for implementing the above steps are stored, and when the one or more instructions are executed by one or more processors, the processors execute the timing adjustment method described above. For the relevant specific implementation, please refer to the above description, which will not be repeated here.

[0092] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the timing adjustment method according to various embodiments of the present application described in the above content of this specification.

[0093] The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0094] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0095] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0096] Flowcharts are used in this disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or following steps are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes.

[0097] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, etc. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any particular form of combination of hardware and software.

[0098] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0099] The above is an explanation of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure are described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A timing adjustment unit, characterized in that: Applied to a semiconductor integrated circuit, the timing adjustment unit comprises: an enabling unit and at least one delay unit, wherein: Each of the delay units is connected in series in a signal transmission path; The enabling unit is connected to the enabling end of each of the delay units respectively, and provides a corresponding enabling signal to each of the delay units; The delay unit responds to the obtained enable signal and extends the propagation time of the communication signal in the signal transmission path based on the timing violation time of the corresponding signal transmission path.

2. The timing adjustment unit according to claim 1, characterized in that: The enabling unit includes a pulse signal generating unit, and the enabling signal includes a pulse signal.

3. The timing adjustment unit according to claim 2, characterized in that: A pulse width of the pulse signal is determined based on the timing violation duration.

4. The timing adjustment unit according to claim 2, characterized in that: The pulse signal generating unit includes a clock terminal and at least one pulse terminal, wherein: The clock terminal shown is used to receive a clock signal; Each of the pulse ends is connected to at least one of the delay units; The pulse signal generating unit generates a pulse signal based on the clock signal.

5. The timing adjustment unit according to claim 4, characterized in that: The pulse signal generating unit and each of the signal transmission paths use the same clock signal.

6. The timing adjustment unit according to claim 1, characterized in that: The delay unit includes a D-type latch, wherein: The signal latching path of the D-type latch is connected in series with the signal transmission path; The enable terminal of the D-type latch serves as the enable terminal of the delay unit; The D-type latch responds to the obtained enable signal and extends the latching time of the communication signal in the signal transmission path based on the timing violation time of the corresponding signal transmission path, so as to extend the propagation time of the communication signal in the signal transmission path.

7. The timing adjustment unit according to claim 6, characterized in that: The time when the D-type latch receives the enable signal is earlier than the time when the communication signal is received.

8. A timing adjustment method, characterized in that: Applied to a semiconductor integrated circuit, the method comprises: Obtaining a timing violation duration of a signal transmission path in the semiconductor integrated circuit; Providing a timing adjustment unit, the timing adjustment unit comprising an enabling unit and at least one delay unit respectively connected to the enabling unit; Connecting each of the delay units in series in a signal transmission path; The enabling unit is configured according to the timing violation duration so that the enabling unit provides a corresponding enabling signal to each delay unit, and the enabling signal is used to drive each delay unit to extend the propagation duration of the communication signal in the corresponding signal transmission path based on the timing violation duration.

9. The timing adjustment method according to claim 8, characterized in that: The enabling unit includes a pulse signal generating unit, and the enabling signal includes a pulse signal; Configuring the enabling unit according to the timing violation duration includes: The pulse width of the pulse signal generated by the pulse signal generating unit is configured according to the timing violation duration.

10. A semiconductor integrated circuit, characterized in that: include: At least one signal transmission path and a timing adjustment unit as claimed in any one of claims 1 to 7, wherein: The delay unit of the timing adjustment unit is connected in series in a signal transmission path where a timing violation exists.

11. A system on chip, characterized in that: include: The semiconductor integrated circuit as claimed in claim 10.

12. An electronic device, characterized in that: include: The system on chip as claimed in claim 11.

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