High-voltage integrated circuit

Abstract

The invention provides a high-voltage integrated circuit. Comprising an RC filter circuit, a plurality of Schmidt circuits, a plurality of filters, a plurality of level switching circuits, a pulse circuit, a dead zone interlocking circuit, a time delay circuit, a bootstrap circuit, an under-voltage protection circuit, a temperature protection circuit, a current protection circuit, a fault logic control circuit, a fault output circuit, a high-voltage region driving circuit, a signal output circuit and an AND gate. The pulse circuit comprises a phase inverter, a first pulse generation circuit and a second pulse generation circuit, the delay circuit comprises a starting circuit, a current generation circuit, a delay control circuit, a comparison circuit and a buffer stage circuit which are electrically connected in sequence, and the input of the starting circuit is used for being connected with the signal input end. The output of the buffer stage circuit is used for being connected with the second input of the AND gate. The high-voltage integrated circuit is high in stability and reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of high-voltage integrated circuits, and in particular to a high-voltage integrated circuit. Background Art

[0002] High voltage integrated circuit, or HVIC, is an integrated circuit product that converts MCU signals into driving IGBT or MOS signals. HVIC integrates PMOS tubes, NMOS tubes, triodes, diodes, voltage regulator tubes, resistors, and capacitors to form Schmitt, low voltage level, high voltage level, pulse generation circuit, delay circuit, filter circuit, overcurrent protection circuit, overheat protection circuit, undervoltage protection circuit, bootstrap circuit and other circuits. The single pulse GEN circuit in the high-side drive circuit of the existing HVIC generates pulses at the rising and falling edges of the HIN signal to drive DMOS. The pulse width is generally several hundred nanoseconds, so that HIN corresponds to HO.

[0003] The single pulse GEN circuit in the existing HVIC high-side drive circuit generates pulses at the rising and falling edges of the HIN signal to drive the DMOS. The pulse width is generally several hundred nanoseconds, so that HIN corresponds to HO.

[0004] The pulse width of the traditional narrow pulse circuit increases with the temperature. It can be seen that the width of the narrow pulse increases by nearly one-fold in the range of -25℃ to 125℃. For LDMOS, which is short-circuited when turned on, too long a turn-on time will cause thermal breakdown of LDMOS, resulting in poor stability and reliability. Summary of the invention

[0005] The present invention provides a high-voltage integrated circuit, aiming to solve the problems of poor stability and reliability of existing high-voltage integrated circuits.

[0006] An embodiment of the present invention provides a high-voltage integrated circuit, comprising: an RC filtering circuit, a plurality of Schmitt circuits, a plurality of filters, a plurality of level conversion circuits, a pulse circuit, a dead zone interlocking circuit, a delay circuit, a bootstrap circuit, an undervoltage protection circuit, a temperature protection circuit, a current protection circuit, a fault logic control circuit, a fault output circuit, a high-voltage area driving circuit, a signal output circuit, and an AND gate; the RC filtering circuit is sequentially connected to the plurality of Schmitt circuits, the plurality of filters, the plurality of level conversion circuits, the dead zone interlocking circuit, the pulse circuit, and the delay circuit, the output of the pulse circuit is connected to the high-voltage area driving circuit, the output of the delay circuit is connected to the AND gate, and the AND gate is connected to The undervoltage protection circuit is connected to the high-voltage area driving circuit; the undervoltage protection circuit is used to connect the power supply voltage, the input of the undervoltage protection circuit is connected to the first end of the bootstrap circuit, the output of the undervoltage protection circuit is connected to the input of the fault logic control circuit, and the second end of the bootstrap circuit is connected to the high-voltage area driving circuit; the multiple level conversion circuits are also respectively connected to the temperature protection circuit and the current protection circuit, the current protection circuit is also connected to the input of the fault logic control circuit, the output of the fault logic control circuit is respectively connected to the pulse circuit and the first input of the AND gate, and the output of the AND gate is connected to the high-voltage area driving circuit; the input of the fault logic control circuit is also connected to the fault output circuit;

[0007] The pulse circuit includes an inverter, a first pulse generating circuit and a second pulse generating circuit, the input end of the inverter is used to connect to the signal input end, the output end of the inverter is connected to the input end of the first pulse generating circuit, and the output end of the first pulse generating circuit is used to output a rising edge pulse signal; the input end of the second pulse generating circuit is used to connect to the signal input end, and the output end of the second pulse generating circuit is used to output a falling edge pulse signal; the rising edge pulse signal and the falling edge pulse signal are respectively output to the high voltage area driving circuit;

[0008] The delay circuit includes: a start-up circuit, a current generating circuit, a delay control circuit, a comparison circuit and a buffer stage circuit which are electrically connected in sequence, the input of the start-up circuit is used to connect to the signal input terminal, and the output of the buffer stage circuit is used to connect to the second input of the AND gate.

[0009] Preferably, the startup circuit includes a transistor NM1, a transistor NM2, a first resistor, a transistor PM1, a transistor PM2, a transistor PM3, a transistor MM3, a transistor NM4, a transistor NM5, a transistor MM6 and a transistor NM7;

[0010] The first end of the first resistor is connected to the D pole of the transistor NM1 and to the supply voltage, the second end of the first resistor is respectively connected to the G pole of the transistor NM1 and the D pole of the transistor NM2, the D pole of the transistor NM2 is also connected to the G pole of the transistor NM2, and the S pole of the transistor NM2 is used to be connected to the VSS voltage terminal;

[0011] The D pole of the transistor PM1 is respectively connected to the D pole of the transistor PM2 and the D pole of the transistor PM3 and is connected to the power supply voltage; the G pole of the transistor PM1 is respectively connected to the G pole of the transistor PM2 and the G pole of the transistor PM3; the S pole of the transistor PM1 is connected to the D pole of the transistor NM3, the G pole of the transistor NM3 is connected to the G pole of the transistor NM4, the S pole of the transistor NM3 is respectively connected to the D pole of the transistor NM4 and the S pole of the transistor NM6, the S pole of the transistor NM4 and the S pole of the transistor NM7 are respectively connected to the VSS voltage terminal; the S pole of the transistor PM2 is connected to the D pole of the transistor NM6, the G pole of the transistor NM6 is connected to the G pole of the transistor NM7, the D pole of the transistor NM7 is respectively connected to the S pole of the transistor NM1 and the S pole of the transistor PM3; the G pole of the transistor PM1 is also connected to the circuit generating circuit.

[0012] Preferably, the current generating circuit comprises: a transistor PM4, a transistor NM8, a transistor NM9, a transistor NM10, a second resistor, a third resistor and a fourth resistor;

[0013] The first end of the second resistor is connected to the power supply voltage, the second end of the second resistor is respectively connected to the first end of the third resistor and the first end of the fourth resistor, and the second end of the third resistor is connected to the second end of the fourth resistor; the second end of the fourth resistor is also connected to the D pole of the transistor NM8, the G pole of the transistor NM8 is connected to the G pole of the transistor NM10, the S pole of the transistor NM8 is connected to the S pole of the transistor NM10, the S pole of the transistor NM9 is connected to the D pole of the transistor NM10, the G pole of the transistor NM9 is connected to the signal input end, the D pole of the transistor NM9 is connected to the S pole of the transistor PM4 and to the delay control circuit, the G pole of the transistor PM4 is connected to the G pole of the transistor PM3, and the D pole of the transistor PM4 is connected to the power supply voltage.

[0014] Preferably, the delay control circuit comprises: a transistor PM5, a fifth resistor, a sixth resistor, a seventh resistor and a first capacitor;

[0015] The G pole of the transistor PM5 is connected to the G pole of the transistor PM4, the D pole of the transistor PM5 is connected to the power supply voltage, the S pole of the transistor PM5 is connected to the first end of the fifth resistor, the second end of the fifth resistor is respectively connected to the first end of the sixth resistor and the first end of the seventh resistor, the second end of the sixth resistor is connected to the second end of the seventh resistor and connected to the VSS voltage terminal; the first end of the first capacitor is connected to the S pole of the transistor PM4, and the second end of the first capacitor is connected to the VSS voltage terminal.

[0016] Preferably, the comparison circuit comprises: a transistor PM6, a transistor PM7, a transistor NM11, a transistor NM12, a transistor NM13, a transistor NM14 and a transistor NM15;

[0017] The D pole of the transistor PM6 and the D pole of the transistor PM7 are respectively connected to the power supply voltage, the G pole of the transistor PM6 is respectively connected to the G pole of the transistor PM5 and the G pole of the transistor PM7, the S pole of the transistor PM6 is respectively connected to the D pole of the transistor NM11 and the D pole of the transistor NM12, the G pole of the transistor NM11 is connected to the first end of the first capacitor, the S pole of the transistor NM11 is connected to the D pole of the transistor NM13, the G pole of the transistor NM12 is connected to the S pole of the transistor PM5, the S pole of the transistor PM7 is connected to the D pole of the transistor NM15, the S pole of the transistor NM12 is respectively connected to the D pole of the transistor NM14, and the G pole of the transistor NM15 is respectively connected to the S pole of the transistor NM13 and the S pole of the transistor NM14, and the G pole of the transistor NM13 is connected to the G pole of the transistor NM14; the S pole of the transistor PM7 is also used to be connected to the buffer stage circuit.

[0018] Preferably, the buffer stage circuit comprises: a transistor PM8, a transistor PM9, a transistor NM16 and a transistor NM17;

[0019] The G pole of the transistor PM8 is respectively connected to the S pole of the transistor PM7 and the G pole of the transistor NM16; the D pole of the transistor PM8 and the D pole of the transistor PM9 are respectively connected to the supply voltage, the S pole of the transistor PM8 is connected to the D pole of the transistor NM16, the S pole of the transistor NM16 is connected to the S pole of the transistor NM17, the G pole of the transistor NM17 is respectively connected to the G pole of the transistor PM9 and the S pole of the transistor PM8, the S pole of the transistor PM9 is connected to the D pole of the transistor NM17, and the D pole of the transistor NM17 is also used to connect to the second input of the AND gate.

[0020] Preferably, the first pulse generating circuit includes a first amplifying circuit, a first regulating circuit and a first pulse output circuit, the input end of the first amplifying circuit is used to connect to the signal input end, the output end of the first amplifying circuit is connected to the first regulating circuit and the first pulse output circuit in sequence, and the first pulse output circuit is used to output the rising edge pulse signal.

[0021] Preferably, the second pulse generating circuit includes a second amplifying circuit, a second regulating circuit and a second pulse output circuit, the input end of the second amplifying circuit is used to connect to the signal input end, the output end of the second amplifying circuit is connected to the second regulating circuit and the second pulse output circuit in sequence, and the second pulse output circuit is used to output the falling edge pulse signal.

[0022] Compared with the prior art, the beneficial effect of the present invention is that the output end of the inverter is connected to the input end of the first pulse generating circuit, and the output end of the first pulse generating circuit is used to output a rising edge pulse signal; the input end of the second pulse generating circuit is used to connect the signal input end, and the output end of the second pulse generating circuit is used to output a falling edge pulse signal; the rising edge pulse signal and the falling edge pulse signal are respectively output to the high-voltage area driving circuit; the startup circuit is electrically connected to the current generating circuit, the delay control circuit, the comparison circuit and the buffer stage circuit in sequence, the input of the startup circuit is used to connect the signal input end, and the output of the buffer stage circuit is used to connect the second input of the AND gate. The precision delay generating circuit is used to replace the delay generating circuit in the pulse generating circuit, so that the generated narrow pulse width is less affected by the temperature and the power supply voltage, and finally the conduction time of the high-voltage LDMOS in the level shifting circuit tends to be stable at different temperatures, so as to improve the reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:

[0024] Figure 1 is a circuit diagram of a high voltage integrated circuit provided by an embodiment of the present invention;

[0025] Figure 2 is a circuit diagram of a delay circuit provided by an embodiment of the present invention;

[0026] Figure 3 It is a working principle diagram of the delay circuit provided by an embodiment of the present invention;

[0027] Figure 4 is a schematic diagram of current changes in a delay circuit provided by an embodiment of the present invention;

[0028] Figure 5 is a waveform diagram of a delay circuit provided by an embodiment of the present invention;

[0029] Figure 6 It is a module of the pulse circuit provided by an embodiment of the present invention;

[0030] Figure 7 is a circuit diagram of a pulse circuit provided by an embodiment of the present invention;

[0031] Figure 8 is a waveform diagram of a pulse circuit provided by an embodiment of the present invention;

[0032] Fig. 9 It is a schematic diagram of the low temperature drift coefficient of the delay circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0034] Combined with Figure 1-Figure 9As shown, an embodiment of the present invention provides a high-voltage integrated circuit, including: an RC filter circuit 0102, a plurality of Schmitt circuits 0103, a plurality of filters 0104, a plurality of level conversion circuits 0105, a pulse circuit 0107, a dead zone interlocking circuit 0106, a delay circuit 0108, a bootstrap circuit 0109, an undervoltage protection circuit 0110, a temperature protection circuit 0111, a current protection circuit 0112, a fault logic control circuit 0113, a fault output circuit 0114, a high-voltage area driving circuit 0115, a signal output circuit 0116 and an AND gate 0117; the RC filter circuit 0102 is sequentially connected to the plurality of Schmitt circuits 0103, the plurality of filters 0104, the plurality of level conversion circuits 0105, the dead zone interlocking circuit 0106, the pulse circuit 0107 and the delay circuit 0108, the output of the pulse circuit 0107 is connected to the high-voltage area driving circuit 0115, the output of the delay circuit 0108 is connected to the AND gate 0117, the AND gate 0117 is connected to the high-voltage area driving circuit 0115; the undervoltage protection circuit 0110 is used to connect the power supply voltage VCC, the input of the undervoltage protection circuit 0110 is connected to the first end of the bootstrap circuit 0109, the output of the undervoltage protection circuit 0110 is connected to the input of the fault logic control circuit 0113, and the second end of the bootstrap circuit 0109 is connected to the high-voltage area driving circuit 0115; the multiple level conversion circuits 0105 are also respectively connected to the temperature protection circuit 0111 and the current protection circuit 0112, the current protection circuit 0112 is also connected to the input of the fault logic control circuit 0113, the output of the fault logic control circuit 0113 is respectively connected to the pulse circuit 0107 and the first input of the AND gate 0117, and the output of the AND gate 0117 is connected to the high-voltage area driving circuit 0115; the input of the fault logic control circuit 0113 is also connected to the fault output circuit 0114.

[0035] Among them, HIN and LIN input drive signals pass through RC filter 0102, Schmitt circuit 0103, filter 0104, level conversion circuit 0105, dead zone interlock circuit 0106, and output HINa pulse signal. Pulse circuit 0107 outputs G1 and G2 short pulse signals respectively through the rising edge and falling edge of HINa pulse signal to drive UVWQ1 and UVWQ2 high-voltage DMOS. The high-voltage DMOS is turned on and off to trigger RS ​​trigger 005 to output pulse signal, which controls HO to output drive pulse signal; LINa pulse signal is output, which passes through RC delay circuit 0108 and AND gate 0117 to control LO to output drive pulse signal.

[0036] The output of the driving signals HO and LO are protected by the undervoltage protection circuit 0110, the temperature protection circuit 0111, the current protection ITRIP circuit 0112, and the fault logic control circuit 0113. The bootstrap circuit 0109 provides the bootstrap voltage to HO. The fault output circuit 0114 outputs the fault signal.

[0037] The pulse circuit 0107 includes an inverter 0201, a first pulse generating circuit 0202 and a second pulse generating circuit 0203, wherein the input end of the inverter 0201 is used to connect to the signal input end IN, the output end of the inverter 0201 is connected to the input end of the first pulse generating circuit 0202, and the output end of the first pulse generating circuit 0202 is used to output a rising edge pulse signal; the input end of the second pulse generating circuit 0203 is used to connect to the signal input end, and the output end of the second pulse generating circuit 0203 is used to output a falling edge pulse signal; the rising edge pulse signal and the falling edge pulse signal are respectively output to the high voltage area driving circuit 0115.

[0038] The delay circuit 0108 includes: a start-up circuit 0602, a current generating circuit 0603, a delay control circuit 0604, a comparison circuit 0605 and a buffer stage circuit 0606 which are electrically connected in sequence. The input of the start-up circuit 0602 is used to connect the signal input terminal, and the output of the buffer stage circuit 0606 is used to connect the second input of the AND gate. The precision delay generating circuit is used to replace the delay generating circuit in the pulse generating circuit, so that the generated narrow pulse width is less affected by the temperature and the power supply voltage, and finally the conduction time of the high-voltage LDMOS in the level shifting circuit tends to be stable at different temperatures to improve the reliability of the chip. Through 1, the high-precision delay generating circuit is designed, and the VIRTUOSO of CADENCE is used for layout design and MMSIM is used for DRC and LVS error checking; the high-precision delay generating circuit is integrated into the HVIC, and the circuit function simulation of the complete HVIC circuit and MMSIM are used for DRC and LVS error checking; the high-precision delay generating circuit layout is integrated into the HVIC layout, and the layout circuit connection is connected according to the circuit schematic diagram.

[0039] In this embodiment, the startup circuit 0602 includes a transistor NM1, a transistor NM2, a first resistor, a transistor PM1, a transistor PM2, a transistor PM3, a transistor MM3, a transistor NM4, a transistor NM5, a transistor MM6, and a transistor NM7;

[0040] The first end of the first resistor is connected to the D pole of the transistor NM1 and to the power supply voltage VCC, the second end of the first resistor is respectively connected to the G pole of the transistor NM1 and the D pole of the transistor NM2, the D pole of the transistor NM2 is also connected to the G pole of the transistor NM2, and the S pole of the transistor NM2 is used to be connected to the VSS voltage terminal;

[0041] The D pole of the transistor PM1 is respectively connected to the D pole of the transistor PM2 and the D pole of the transistor PM3 and is connected to the power supply voltage VCC; the G pole of the transistor PM1 is respectively connected to the G pole of the transistor PM2 and the G pole of the transistor PM3; the S pole of the transistor PM1 is connected to the D pole of the transistor NM3, the G pole of the transistor NM3 is connected to the G pole of the transistor NM4, the S pole of the transistor NM3 is respectively connected to the D pole of the transistor NM4 and the S pole of the transistor NM6, the S pole of the transistor NM4 and the S pole of the transistor NM7 are respectively connected to the VSS voltage terminal; the S pole of the transistor PM2 is connected to the D pole of the transistor NM6, the G pole of the transistor NM6 is connected to the G pole of the transistor NM7, the D pole of the transistor NM7 is respectively connected to the S pole of the transistor NM1 and the S pole of the transistor PM3; the G pole of the transistor PM1 is also connected to the circuit generating circuit.

[0042] In this embodiment, the current generating circuit 0603 includes: a transistor PM4, a transistor NM8, a transistor NM9, a transistor NM10, a second resistor, a third resistor and a fourth resistor;

[0043] The first end of the second resistor is connected to the power supply voltage VCC, the second end of the second resistor is respectively connected to the first end of the third resistor and the first end of the fourth resistor, and the second end of the third resistor is connected to the second end of the fourth resistor; the second end of the fourth resistor is also connected to the D pole of the transistor NM8, the G pole of the transistor NM8 is connected to the G pole of the transistor NM10, the S pole of the transistor NM8 is connected to the S pole of the transistor NM10, the S pole of the transistor NM9 is connected to the D pole of the transistor NM10, the G pole of the transistor NM9 is connected to the signal input end, the D pole of the transistor NM9 is connected to the S pole of the transistor PM4 and to the delay control circuit 0604, the G pole of the transistor PM4 is connected to the G pole of the transistor PM3, and the D pole of the transistor PM4 is connected to the power supply voltage VCC.

[0044] In this embodiment, the delay control circuit 0604 includes: a transistor PM5, a fifth resistor, a sixth resistor, a seventh resistor and a first capacitor;

[0045] The G pole of the transistor PM5 is connected to the G pole of the transistor PM4, the D pole of the transistor PM5 is connected to the power supply voltage VCC, the S pole of the transistor PM5 is connected to the first end of the fifth resistor, the second end of the fifth resistor is respectively connected to the first end of the sixth resistor and the first end of the seventh resistor, the second end of the sixth resistor is connected to the second end of the seventh resistor and connected to the VSS voltage terminal; the first end of the first capacitor is connected to the S pole of the transistor PM4, and the second end of the first capacitor is connected to the VSS voltage terminal.

[0046] In this embodiment, the comparison circuit 0605 includes: a transistor PM6, a transistor PM7, a transistor NM11, a transistor NM12, a transistor NM13, a transistor NM14 and a transistor NM15;

[0047] The D pole of the transistor PM6 and the D pole of the transistor PM7 are respectively connected to the power supply voltage VCC, the G pole of the transistor PM6 is respectively connected to the G pole of the transistor PM5 and the G pole of the transistor PM7, the S pole of the transistor PM6 is respectively connected to the D pole of the transistor NM11 and the D pole of the transistor NM12, the G pole of the transistor NM11 is connected to the first end of the first capacitor, the S pole of the transistor NM11 is connected to the D pole of the transistor NM13, the G pole of the transistor NM12 is connected to the S pole of the transistor PM5, the S pole of the transistor PM7 is connected to the D pole of the transistor NM15, the S pole of the transistor NM12 is respectively connected to the D pole of the transistor NM14, and the G pole of the transistor NM15 is respectively connected to the S pole of the transistor NM13 and the S pole of the transistor NM14, and the G pole of the transistor NM13 is connected to the G pole of the transistor NM14; the S pole of the transistor PM7 is also used to be connected to the buffer stage circuit 0606.

[0048] In this embodiment, the buffer stage circuit 0606 includes: a transistor PM8, a transistor PM9, a transistor NM16 and a transistor NM17;

[0049] The G pole of the transistor PM8 is respectively connected to the S pole of the transistor PM7 and the G pole of the transistor NM16; the D pole of the transistor PM8 and the D pole of the transistor PM9 are respectively connected to the power supply voltage VCC, the S pole of the transistor PM8 is connected to the D pole of the transistor NM16, the S pole of the transistor NM16 is connected to the S pole of the transistor NM17, the G pole of the transistor NM17 is respectively connected to the G pole of the transistor PM9 and the S pole of the transistor PM8, the S pole of the transistor PM9 is connected to the D pole of the transistor NM17, and the D pole of the transistor NM17 is also used to connect to the second input of the AND gate.

[0050] In a specific implementation, one end of the first resistor R1, the D poles of NM1, PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, and PM9 are connected together to VCC;

[0051] The other end of R1, the G pole of NM1, NM2 and the D pole of NM2 are connected together;

[0052] The S poles of NM2, NM4, NM7, NM8, NM13, NM14, NM15, NM16, and NM17, one end of capacitor C, one end of resistor RB1, and one end of resistor RA1 are connected together to VSS;

[0053] The S pole of PM1, the D pole of NM3, and the G poles of NM2 and NM4 are connected together;

[0054] The G poles of PM1, PM2, PM3, PM4, PM5, PM6, and PM7 are connected together;

[0055] The S pole of PM2 is connected to the D pole of NM6;

[0056] The S pole of NM1, the S pole of PM3, the G pole of NM6, the G pole of NM7 and the D pole of NM7 are connected together;

[0057] The other end of the resistor αRB, one end of the resistor RB and one end of the resistor RA are connected together;

[0058] The other end of the resistor RB, the other end of the resistor RA, NM8, the G pole of NM10 and the D pole of NM8 are connected together;

[0059] The S pole of PM4, the D pole of NM9, one end of capacitor C, and the G pole of NM11 are connected together;

[0060] The G pole of NM9 is connected to the input terminal IN;

[0061] The S pole of PM5, one end of resistor αRB1, and the G pole of NM12 are connected together;

[0062] The other end of the resistor αRB1, one end of the resistor RB1 and one end of the resistor RA1 are connected together;

[0063] The S pole of PM6, the D pole of NM11 and the D pole of NM12 are connected together;

[0064] The S pole of NM11, the D pole of NM13, the G pole of NM13 and the G pole of NM14 are connected together;

[0065] The S pole of NM12, the D pole of NM14 and the G pole of NM15 are connected together;

[0066] The S pole of PM7, the D pole of NM15, the G pole of PM8 and the G pole of NM16 are connected together;

[0067] The S pole of PM8, the D pole of NM16, the G pole of PM9 and the G pole of NM17 are connected together;

[0068] The S pole of PM9 is connected to the D pole of NM17 and led out as the output terminal OUT;

[0069] The working principle of the high-precision delay generation circuit can be illustrated by Figure 3-4 the schematic diagram, where I1 and I2 are PTAT currents and I3 is a PTSV current. As Figure 5 shown, when IN changes from high level to low level, the switch K1 closes ( Figure 2 NM9 in it is turned off), and I1 starts to charge the capacitor C. The change of Vcap can be expressed by the following formula:

[0070] Vcap(t) = I1 * t / C;

[0071] The comparator is used to compare the voltage on the capacitor with the reference voltage Vref. Vref is represented by the voltage drop formed by the PTAT current on the resistor and changes adaptively with the change of the current. When Vcap > Vref, OUT becomes low. The delay between OUT and IN is as follows:

[0072] t on ≈ (Vref * C) / I1 + τ;

[0073] where τ represents the intrinsic delay of the comparator. In the case where the capacitor C is relatively large and I1 is relatively small, ton >> τ. At this time, the delay time can be expressed as

[0074] t on ≈ (Vref * C) / I1;

[0075] Among them, Vref = I2 * R, and I1 and I1 are two completely equal currents copied through the current mirror. Therefore, the final delay ton can be expressed as:

[0076] ton = RC;

[0077] When IN changes from low to high, the switch K1 opens, and (I3 - I1) starts to discharge the capacitor C. The change of Vcap can be expressed by the following formula:

[0078] Vcap(t) = VCC - (I3 - I1) * t / C;

[0079] When Vcap < Vref, OUT becomes high. The delay between OUT and IN is as follows:

[0080] t off ≈((VCC-Vref)*C) / (I3-I1)+τ;

[0081] Where τ represents the intrinsic delay of the comparator. When the capacitance C is relatively large and I3-I1 is relatively small, toff>>τ. At this time, toff can be expressed as:

[0082] t off ≈((VCC-Vref)*C) / (I3-I1);

[0083] Since I3 is the PTSV current, that is, I3 = VCC / R, and Vref = I2×R = I1×R, the final toff delay can be expressed as:

[0084] t off ≈((VCC-Vref)*C) / (I3-I1)=((VCC-Vref)*C) / (VCC / R-Vref / R)=RC.

[0085] From on With t off It can be seen from the expression that in order to obtain a delay with a low temperature drift coefficient, a resistor with a low temperature drift coefficient and a capacitor with a low temperature drift coefficient must be obtained. Since the temperature drift coefficient of a capacitor is usually small, the key to the design is to construct a resistor with a low temperature coefficient. The present invention uses a series / parallel resistor construction method to achieve a low temperature drift coefficient, such as Fig. 9 As shown, RA is the Rnwell resistor with a positive temperature coefficient, and RB is the Rhr_poly resistor with a negative temperature coefficient. Therefore, combining these two types of resistors using a series / parallel method can achieve a resistor with a low temperature drift coefficient.

[0086] The temperature coefficient of the resistor used in the present invention is shown in Table 1 below;

[0087] Table 1 - Temperature coefficient of resistance

[0088]

[0089] Among them, by using the first-order Taylor approximation for the temperature characteristics of the resistor, the temperature characteristic coefficient TCP / S of the series / parallel resistor can be obtained as follows:

[0090] TC P / S =TC A *((RA / / RB)*RB / (RA+RB)) / (RA / / RB+

[0091] αRB)+TC B*((RA / / RB)*RB / (RA+RB)+αRB) / (RA / / RB+αRB);

[0092] Where ξ=1+RA / RB,γ=1+RB / RA,α is the adjustable coefficient. When TCP / S=0, that is:

[0093] α(1+RA / RB) 2 / (RA / RB)=-TC A +TC B -1;

[0094] The temperature drift coefficient of the constructed series / parallel resistor RP / S is 0. For example, when TCA=4.79*10-3 / K, TCB=-3.6*10-3 / K, RA, RB, and can be selected as 395K, 790K and 0.3 respectively to construct a target resistor with a temperature drift coefficient of 100ppm / ℃ and a resistance of 500K. Under the 0.5umBCD process, the comparison of the delay characteristics of the circuit of the present invention and the traditional solution with temperature changes is shown in Table 2.

[0095] Table 2 Delay temperature coefficient and delay matching temperature coefficient of the conventional RC delay generating circuit and the solution of the present invention;

[0096]

[0097] The statistical results in Table 2 show that the delay generation circuit proposed in this paper can achieve a temperature drift coefficient of 0.048ns / ℃. Comparison of characteristics with temperature changes. The statistical results in the following table show that the delay generation circuit proposed in this paper can achieve a temperature drift coefficient of 0.048ns / ℃.

[0098] In this embodiment, the first pulse generating circuit 0202 includes a first amplifying circuit 0301, a first regulating circuit 0302 and a first pulse output circuit 0303. The input end of the first amplifying circuit 0301 is used to connect to the signal input end, and the output end of the first amplifying circuit 0301 is connected to the first regulating circuit 0302 and the first pulse output circuit 0303 in sequence. The first pulse output circuit 0303 is used to output the rising edge pulse signal.

[0099] Among them, the first amplifier circuit 0301 includes: a transistor PM1, a transistor NM1, a first resistor R1 and a first capacitor C1; the G pole of the transistor PM1 is connected to the G pole of the transistor NM1, the D pole of the transistor PM1 is connected to the power supply voltage VCC, the S pole of the transistor PM1 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is respectively connected to the D pole of the transistor NM1, the S pole of the transistor NM1 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is respectively connected to the second end of the first resistor R1 for output to the first regulating circuit 0302, and the S pole of the transistor NM1 is also used to connect to the VSS voltage terminal.

[0100] Among them, the first regulating circuit 0302 includes: a transistor PM2, a transistor PM3, a transistor PM4, a transistor NM2, a transistor NM3 and a transistor NM4; the G pole of the transistor PM2 is respectively connected to the G pole of the transistor PM3, the G pole of the transistor NM2 and the G pole of the transistor NM3, and the G pole of the transistor PM3 and the G pole of NM3 are used to connect to the second end of the first capacitor; the S pole of the transistor PM2 is connected to the D pole of the transistor PM4, the G pole of the transistor PM4 is respectively connected to the S pole of the transistor PM3 and the G pole of the transistor NM4, the S pole of the transistor NM4 is connected to the S pole of the transistor NM2, the S pole of the transistor PM4 is used to connect to the VSS voltage terminal, and the D pole of the transistor NM4 is used to connect to the supply voltage VCC.

[0101] Among them, the first pulse output circuit 0303 includes: transistor PM5, transistor PM7, transistor PM8, transistor NM5, transistor NM7 and transistor NM8; the G pole of the transistor PM5 is connected to the G pole of the transistor NM5 and then connected to the G pole of the PM4, the D pole of the transistor PM1 is connected to the power supply voltage VCC, the S pole of the transistor PM1 is respectively connected to the D pole of the transistor NM5 and the G pole of the transistor PM8, and the S pole of the transistor NM5 is used to connect to the VSS voltage terminal; the G pole of the transistor PM7 is connected to the G pole of the transistor NM7, the D pole of the transistor PM7 is connected to the power supply voltage VCC, the S pole of the transistor PM7 is connected to the D pole of the transistor PM8, and the S pole of the transistor PM8 is respectively connected to the D pole of the transistor NM8 and the D pole of the transistor NM7, for outputting the rising edge pulse signal; the S pole of the transistor NM7 is connected to the S pole of the transistor NM8 and then connected to the VSS voltage terminal.

[0102] In this embodiment, the second pulse generating circuit 0203 includes a second amplifying circuit 0401, a second regulating circuit 0402 and a second pulse output circuit 0403. The input end of the second amplifying circuit 0401 is used to connect to the signal input end. The output end of the second amplifying circuit 0401 is connected to the second regulating circuit 0402 and the second pulse output circuit 0403 in sequence. The second pulse output circuit 0403 is used to output the falling edge pulse signal.

[0103] Specifically, the drive signal HIN is connected to the G poles of MOS tubes PM1, NM1, PM9, and NM9, the D poles of PM1, PM2, PM5, PM7, NM4, PM9, PM10, PM11, PM14, PM16, PM18, and NM13 are connected to VCC, the S pole of PM1 is connected to one end of the resistor R1, the G poles of PM2, PM3, NM2, and NM3, the D pole of NM1 and one end of the capacitor C1 are connected together, the S pole of PM2, the D pole of PM3 and PM4 are connected together. The D poles of capacitors C1 and C2 are connected together, the other end of capacitor C1, the other end of capacitor C2, the S poles of PM4, NM1, NM3, NM5, NM7, NM8, NM9, NM10, NM12, PM13, NM14, NM16, NM17, and NM18 are connected to VSS, the S pole of PM3, the D pole of NM2, the G pole of PM4, the G pole of NM4, the S pole of NM2, the D pole of NM3 and the S pole of NM4 are connected together, the S pole of PM5, the D pole of NM5, and the G pole of PM8 are connected to N The G pole of M8 is connected together, the S pole of PM7 is connected to the D pole of PM8, the S pole of PM9, the D pole of NM9, the G pole of PM18, the G pole of NM18, the G pole of PM10, the G pole of NM10, the G pole of PM7 and the G pole of NM7 are connected together, the S pole of PM10 is connected to one end of the resistor R2, the other end of the resistor R2, the G poles of PM11, PM12, NM11, NM12, the D pole of NM10 and one end of the capacitor C2 are connected together, PM11 The S pole of PM16 and the D pole of PM17 are connected together, and the S pole of PM18, the D pole of NM18, the G pole of PM16 and the G pole of NM16 are connected together. The S pole of PM18, the D pole of NM18, and the G pole of PM16 are connected together with the G pole of NM16.

[0104] The basic function of the pulse generation circuit is to generate a falling edge pulse of the input signal, and the input signal will form a rising edge pulse of the input signal after passing through the inverter and then the narrow pulse generation module. The working principle waveform of the narrow pulse generation module is as follows Figure 4When the input signal is a wide pulse signal, the delay of the rising edge of the input signal after passing through the delay circuit composed of the first stage PM1, NM1, R1 and C1 can be basically ignored, because NM1 will quickly release the charge on the capacitor C1; and the falling edge of the output signal, under the action of the resistor R1, the rising edge of point A rises slowly until the voltage at point A reaches the positive threshold V of the subsequent Schmitt trigger 0N After that, the signal at point B becomes high level. Finally, the input signal and the signal at point B are triggered by the "NOR gate" composed of PM7, PM8, NM7, and NM8 to form a falling edge trigger. The width of the narrow pulse here is the width of the R1C1 delay, as shown in the following formula:

[0105] tpulse=-RCln(VCC / (VCC-Von));

[0106] As one of the most common passive components, resistors are widely used in a wide range of applications, such as digital-to-analog converters, time delays, and bias circuits. In semiconductors, integrated resistors are usually correlated with the external temperature within a certain temperature range. The temperature coefficient of resistance is generally used to represent the correlation between the resistance value and temperature. The temperature coefficient of resistance αTCR refers to the relative change in resistance value when the temperature changes by 1°C, and the unit is ppm / °C. Usually, the correlation between resistance and temperature can be expressed as:

[0107] R(T)=R0(1+α TCR1 (TT r )+α TCR2 (TT r ) 2 ;

[0108] In the above formula, R0 represents the resistance value at temperature T=Tr, αTCR1 represents the first-order temperature coefficient of the resistor, αTCR2 represents the second-order temperature coefficient of the resistor, Tr represents the reference temperature, and both T and Tr represent thermodynamic temperature in K.

[0109] Among different types of resistors, Poly resistors have positive / negative temperature coefficients, and N-Well resistors have positive temperature coefficients. Among them, Poly resistors are resistors made of Poly layers used as MOS tube gates, and are divided into low-resistance Poly resistors and high-resistance Poly resistors. The temperature coefficient of Poly resistors can be positive or negative, mainly depending on the impurity ions (such as P+ or N+) injected into it, and a larger temperature coefficient can be obtained by reducing the doping concentration of impurity ions such as P+ / N+. For high-resistance Poly resistors, it is precisely because of its lower doping concentration that high-resistance Poly resistors usually have a larger negative temperature coefficient; while N-Well resistors are resistors realized by N-Well in the P substrate process, and usually have a larger square resistance value. It is precisely because N-Well resistors generally have a very low P+ doping concentration that they have a larger positive temperature coefficient, and like Poly resistors, a larger positive temperature coefficient can be obtained by reducing the P+ injection concentration. In a certain process, the high-resistance Poly resistor has a negative temperature coefficient of -3050ppm / ℃, and the N-Well resistor has a positive temperature coefficient of 5600ppm / ℃.

[0110] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.

[0111] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A high voltage integrated circuit, characterized in that: include: RC filtering circuit, multiple Schmitt circuits, multiple filters, multiple level conversion circuits, a pulse circuit, a dead zone interlocking circuit, a delay circuit, a bootstrap circuit, an undervoltage protection circuit, a temperature protection circuit, a current protection circuit, a fault logic control circuit, a fault output circuit, a high-voltage area drive circuit, a signal output circuit and an AND gate; the RC filtering circuit is sequentially connected to the multiple Schmitt circuits, the multiple filters, the multiple level conversion circuits, the dead zone interlocking circuit, the pulse circuit and the delay circuit, the output of the pulse circuit is connected to the high-voltage area drive circuit, the output of the delay circuit is connected to the AND gate, and the AND gate The gate is connected to the high-voltage area driving circuit; the undervoltage protection circuit is used to connect the power supply voltage, the input of the undervoltage protection circuit is connected to the first end of the bootstrap circuit, the output of the undervoltage protection circuit is connected to the input of the fault logic control circuit, and the second end of the bootstrap circuit is connected to the high-voltage area driving circuit; the multiple level conversion circuits are also respectively connected to the temperature protection circuit and the current protection circuit, the current protection circuit is also connected to the input of the fault logic control circuit, the output of the fault logic control circuit is respectively connected to the pulse circuit and the first input of the AND gate, and the output of the AND gate is connected to the high-voltage area driving circuit; The input of the fault logic control circuit is also connected to the fault output circuit; The pulse circuit comprises an inverter, a first pulse generating circuit and a second pulse generating circuit, the input end of the inverter is used to connect to the signal input end, the output end of the inverter is connected to the input end of the first pulse generating circuit, and the output end of the first pulse generating circuit is used to output a rising edge pulse signal; The input end of the second pulse generating circuit is used to connect to the signal input end, and the output end of the second pulse generating circuit is used to output a falling edge pulse signal; The rising edge pulse signal and the falling edge pulse signal are output to the high voltage area driving circuit respectively; The delay circuit includes: a start-up circuit, a current generating circuit, a delay control circuit, a comparison circuit and a buffer stage circuit which are electrically connected in sequence, the input of the start-up circuit is used to connect to the signal input terminal, and the output of the buffer stage circuit is used to connect to the second input of the AND gate.

2. The high voltage integrated circuit according to claim 1, characterized in that: The startup circuit includes a transistor NM1, a transistor NM2, a first resistor, a transistor PM1, a transistor PM2, a transistor PM3, a transistor MM3, a transistor NM4, a transistor NM5, a transistor MM6 and a transistor NM7; The first end of the first resistor is connected to the D pole of the transistor NM1 and to the supply voltage, the second end of the first resistor is respectively connected to the G pole of the transistor NM1 and the D pole of the transistor NM2, the D pole of the transistor NM2 is also connected to the G pole of the transistor NM2, and the S pole of the transistor NM2 is used to be connected to the VSS voltage terminal; The D pole of the transistor PM1 is respectively connected to the D pole of the transistor PM2 and the D pole of the transistor PM3 and is connected to the power supply voltage; the G pole of the transistor PM1 is respectively connected to the G pole of the transistor PM2 and the G pole of the transistor PM3; the S pole of the transistor PM1 is connected to the D pole of the transistor NM3, the G pole of the transistor NM3 is connected to the G pole of the transistor NM4, the S pole of the transistor NM3 is respectively connected to the D pole of the transistor NM4 and the S pole of the transistor NM6, the S pole of the transistor NM4 and the S pole of the transistor NM7 are respectively connected to the VSS voltage terminal; the S pole of the transistor PM2 is connected to the D pole of the transistor NM6, the G pole of the transistor NM6 is connected to the G pole of the transistor NM7, the D pole of the transistor NM7 is respectively connected to the S pole of the transistor NM1 and the S pole of the transistor PM3; the G pole of the transistor PM1 is also connected to the circuit generating circuit.

3. The high voltage integrated circuit according to claim 2, characterized in that: The current generating circuit includes: a transistor PM4, a transistor NM8, a transistor NM9, a transistor NM10, a second resistor, a third resistor and a fourth resistor; The first end of the second resistor is connected to the power supply voltage, the second end of the second resistor is respectively connected to the first end of the third resistor and the first end of the fourth resistor, and the second end of the third resistor is connected to the second end of the fourth resistor; the second end of the fourth resistor is also connected to the D pole of the transistor NM8, the G pole of the transistor NM8 is connected to the G pole of the transistor NM10, the S pole of the transistor NM8 is connected to the S pole of the transistor NM10, the S pole of the transistor NM9 is connected to the D pole of the transistor NM10, the G pole of the transistor NM9 is connected to the signal input end, the D pole of the transistor NM9 is connected to the S pole of the transistor PM4 and to the delay control circuit, the G pole of the transistor PM4 is connected to the G pole of the transistor PM3, and the D pole of the transistor PM4 is connected to the power supply voltage.

4. The high voltage integrated circuit according to claim 3, characterized in that: The delay control circuit includes: a transistor PM5, a fifth resistor, a sixth resistor, a seventh resistor and a first capacitor; The G pole of the transistor PM5 is connected to the G pole of the transistor PM4, the D pole of the transistor PM5 is connected to the power supply voltage, the S pole of the transistor PM5 is connected to the first end of the fifth resistor, the second end of the fifth resistor is respectively connected to the first end of the sixth resistor and the first end of the seventh resistor, the second end of the sixth resistor is connected to the second end of the seventh resistor and connected to the VSS voltage terminal; the first end of the first capacitor is connected to the S pole of the transistor PM4, and the second end of the first capacitor is connected to the VSS voltage terminal.

5. The high voltage integrated circuit according to claim 4, characterized in that: The comparison circuit includes: a transistor PM6, a transistor PM7, a transistor NM11, a transistor NM12, a transistor NM13, a transistor NM14 and a transistor NM15; The D pole of the transistor PM6 and the D pole of the transistor PM7 are respectively connected to the power supply voltage, the G pole of the transistor PM6 is respectively connected to the G pole of the transistor PM5 and the G pole of the transistor PM7, the S pole of the transistor PM6 is respectively connected to the D pole of the transistor NM11 and the D pole of the transistor NM12, the G pole of the transistor NM11 is connected to the first end of the first capacitor, the S pole of the transistor NM11 is connected to the D pole of the transistor NM13, the G pole of the transistor NM12 is connected to the S pole of the transistor PM5, the S pole of the transistor PM7 is connected to the D pole of the transistor NM15, the S pole of the transistor NM12 is respectively connected to the D pole of the transistor NM14, and the G pole of the transistor NM15 is respectively connected to the S pole of the transistor NM13 and the S pole of the transistor NM14, and the G pole of the transistor NM13 is connected to the G pole of the transistor NM14; the S pole of the transistor PM7 is also used to be connected to the buffer stage circuit.

6. The high voltage integrated circuit according to claim 5, characterized in that: The buffer stage circuit includes: a transistor PM8, a transistor PM9, a transistor NM16 and a transistor NM17; The G pole of the transistor PM8 is respectively connected to the S pole of the transistor PM7 and the G pole of the transistor NM16; the D pole of the transistor PM8 and the D pole of the transistor PM9 are respectively connected to the supply voltage, the S pole of the transistor PM8 is connected to the D pole of the transistor NM16, the S pole of the transistor NM16 is connected to the S pole of the transistor NM17, the G pole of the transistor NM17 is respectively connected to the G pole of the transistor PM9 and the S pole of the transistor PM8, the S pole of the transistor PM9 is connected to the D pole of the transistor NM17, and the D pole of the transistor NM17 is also used to connect to the second input of the AND gate.

7. The high voltage integrated circuit according to claim 1, wherein: The first pulse generating circuit includes a first amplifying circuit, a first regulating circuit and a first pulse output circuit. The input end of the first amplifying circuit is used to connect to the signal input end. The output end of the first amplifying circuit is connected to the first regulating circuit and the first pulse output circuit in sequence. The first pulse output circuit is used to output the rising edge pulse signal.

8. The high voltage integrated circuit according to claim 1, wherein: The second pulse generating circuit includes a second amplifying circuit, a second regulating circuit and a second pulse output circuit. The input end of the second amplifying circuit is used to connect to the signal input end. The output end of the second amplifying circuit is connected to the second regulating circuit and the second pulse output circuit in sequence. The second pulse output circuit is used to output the falling edge pulse signal.

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