Data recovery circuit, data recovery method and high-speed serial interface

Abstract

The invention discloses a data recovery circuit, a data recovery method and a high-speed serial interface, and the data recovery circuit comprises a rate tracking module, a sampling judgment module and a recovery data selection module. The rate tracking module is used for detecting the frequency of input data and generating a plurality of phase-shifted sampling clock signals with frequency information of the input data; the sampling judgment module is used for performing oversampling on input data according to the sampling clock signal so as to obtain parallel sampling data of multiple phases, and determining reference recovery data according to the parallel sampling data; the recovery data selection module is used for determining a clock recovery signal and target recovery data corresponding to the input data according to the reference recovery data. According to the data recovery circuit provided by the invention, the transmission rate of the input data can be self-adapted, and the clock signal and the transmission data can be recovered without depending on an external clock.

Description

Technical Field

[0001] The present application relates to the field of high-speed communication technology, and in particular to a data recovery circuit, a data recovery method and a high-speed serial interface. Background Art

[0002] In the field of high-speed communication technology, as the data bandwidth and data transmission rate of high-speed transmission protocols increase, not only the support of appropriate transmission media is required, but also the integrity of the signal during transmission needs to be ensured.

[0003] Existing high-speed communications mainly use high-speed serial transmission technology. The transmitter encodes the digital signal into a non-return-to-zero (NRZ) data stream and converts it into analog symbols representing different information, such as high and low levels or more levels, and sends them into the transmission line according to the requirements of the transmission protocol. At the receiving end, the receiver amplifies the received analog signal and restores the analog signal to a digital signal through a high-sensitivity sampling circuit. However, since the sender and the receiver do not have a shared clock signal for data synchronization, after receiving the data, the receiver needs to recover the clock signal from the received non-return-to-zero format data stream to achieve synchronous operation. Therefore, a clock data recovery circuit (CDR) is usually required to extract the clock signal from the received data.

[0004] However, the existing CDR circuit usually needs to know the data transmission rate in advance, and generates a reference clock signal according to the data transmission rate, samples the input data based on the preset reference clock signal, and then recovers the clock signal and original data in the input data from the sampled data. The existing CDR circuit design generally has difficulty in suppressing high-frequency jitter and low-frequency jitter in data transmission at the same time, and cannot achieve self-adaptation for unknown data transmission rates. Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. Summary of the invention

[0005] The purpose of the present application is to provide a data recovery circuit, a data recovery method and a high-speed serial interface, which can adapt to the transmission rate of input data and realize the recovery of clock signals and transmission data without relying on an external clock.

[0006] To achieve the above objectives: In a first aspect, an embodiment of the present application provides a data recovery circuit, including a rate tracking module, a sampling decision module and a recovery data selection module; The rate tracking module is used to detect the frequency of input data and generate a plurality of phase-shifted sampling clock signals having the frequency information of the input data; The sampling decision module is used to oversample the input data according to the sampling clock signal to obtain parallel sampling data of multiple phases, and determine reference recovery data according to the parallel sampling data; The recovery data selection module is used to determine the clock recovery signal and target recovery data corresponding to the input data according to the reference recovery data.

[0007] In one embodiment, the rate tracking module includes a frequency divider, a phase frequency detection unit, a charge pump unit, a low-pass filter and a multi-phase clock generation unit; wherein, The frequency divider is used to adjust the signal frequency of the input data according to a preset frequency division ratio to generate a reference clock signal; The phase frequency detection unit is used to detect the phase error and frequency error between the reference clock signal and the local clock signal; The charge pump unit is used to generate a current pulse signal according to the phase error and the frequency error; The low-pass filter is used to smooth the current pulse signal generated by the charge pump unit to generate a DC control signal; The multi-phase clock generating unit is used to adjust the local clock signal according to the DC control signal to generate a sampling clock signal that is proportional to the input data frequency.

[0008] In one embodiment, the phase frequency detection unit includes a phase detector and a frequency detector, the charge pump unit includes a first charge pump and a second charge pump, and the multi-phase clock generation unit is a multi-phase voltage-controlled oscillator; wherein, The output end of the phase detector is connected to the input end of the first charge pump, the output end of the first charge pump is connected to the input end of the low-pass filter, the output end of the low-pass filter is connected to the input end of the multi-phase voltage-controlled oscillator, and the output end of the multi-phase voltage-controlled oscillator is connected to the input end of the phase detector to form a phase tracking loop; The output end of the frequency discriminator is connected to the input end of the second charge pump, the output end of the second charge pump is connected to the input end of the low-pass filter, the output end of the low-pass filter is connected to the input end of the multi-phase voltage-controlled oscillator, and the output end of the multi-phase voltage-controlled oscillator is connected to the input end of the frequency discriminator to form a frequency tracking loop.

[0009] In one embodiment, the multi-phase voltage-controlled oscillator includes N stages of inverters connected in series, and is used to generate 2N phase-shifted sampling clock signals in each signal cycle of input data; wherein N is an odd number.

[0010] In one embodiment, the sampling decision module includes a multi-phase sampling unit and a data recovery decision unit; wherein, The multi-phase sampling unit includes a plurality of parallel samplers, each sampler receiving a sampling clock signal with a phase shift, and is used to obtain sampled data at different phases of the input data; The data recovery judgment unit is connected to the output end of the multi-phase sampling unit, and is used to determine the corresponding reference recovery data within the signal period of each input data through a preset judgment rule based on the sampled data at different phases.

[0011] In one embodiment, the restored data selection module includes a phase adjustment unit and a data selection unit respectively connected to the output end of the data recovery judgment unit; wherein, The phase adjustment unit is used to adjust the phase of the sampling clock signal offset according to the judgment result of the data recovery judgment unit to determine the best sampling clock phase, and determine the clock recovery signal of the target recovery data according to the best sampling clock phase; The data selection unit is also connected to the phase adjustment unit, and is used to determine target recovery data according to the reference recovery data, and output the target recovery data according to the clock recovery signal.

[0012] In one embodiment, the data selection unit includes a FIFO storage unit for storing reference recovery data determined according to the parallel sampling data.

[0013] In a second aspect, an embodiment of the present application provides a data recovery method, including: Generate a plurality of sampling clock signals with phase shifts according to the frequency of the input data; Oversampling the input data according to the sampling clock signal to obtain parallel sampling data of multiple phases; Based on the parallel sampled data, determining reference restored data by a preset decision rule; According to the reference recovery data, a clock recovery signal and target recovery data corresponding to the input data are determined.

[0014] In one embodiment, the step of generating a plurality of sampling clock signals with phase shifts according to the frequency of the input data includes: According to a preset frequency division ratio, adjusting the signal frequency of the input data to generate a reference clock signal; Obtaining a phase error and a frequency error between the reference clock signal and the local clock signal; generating a current pulse signal according to the phase error and the frequency error; Performing smoothing and filtering processing on the current pulse signal and generating a DC control signal; The local clock signal is adjusted according to the DC control signal to generate a sampling clock signal that is proportional to the input data frequency.

[0015] In a third aspect, an embodiment of the present application provides a high-speed serial interface, including the data recovery circuit as described above.

[0016] The data recovery circuit, data recovery method and high-speed serial interface provided by the embodiment of the present application detect the frequency of the input data through the rate tracking module, and generate a sampling clock signal with multiple phase offsets having the frequency information of the input data; the input data is oversampled based on the sampling clock signal through the sampling decision module to obtain parallel sampling data of multiple phases, and the reference recovery data is determined based on the parallel sampling data; the clock recovery signal and target recovery data corresponding to the input data are determined based on the reference recovery data through the recovery data selection module. In this way, the transmission rate of the input data can be adaptively adjusted, and the recovery of the clock signal and the transmission data can be achieved without relying on the external clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of the structure of a data recovery circuit provided in an embodiment of the present application.

[0019] Figure 2 A schematic diagram of the structure of the rate tracking module provided in an embodiment of the present application.

[0020] Figure 3 A schematic diagram of the structure of a multi-phase voltage-controlled oscillator provided in an embodiment of the present application.

[0021] Figure 4 A schematic diagram of high-frequency noise filtering of oversampled data provided in an embodiment of the present application.

[0022] Figure 5 A flowchart of a data recovery method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0024] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0025] It should be understood that, although the terms first, second, third, etc. may be used to describe various information in this article, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this article, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "at the time of..." or "when..." or "in response to determination". Furthermore, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising", "including" indicate that there are described features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Thus, “A, B, or C” or “A, B and / or C” means “any of the following: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition will occur only when a combination of elements, functions, steps, or operations are inherently mutually exclusive in some manner.

[0026] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and it can be performed in other orders. Moreover, at least a portion of the steps in the figure may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0027] It should be noted that, in this article, step codes such as S101, S102, etc. are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the sequence. When implementing the step, those skilled in the art may execute S102 first and then S101, etc., but these should all be within the scope of protection of this application.

[0028] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0029] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0030] See also Figure 1 , is a data recovery circuit provided in an embodiment of the present application, the data recovery circuit is applied to the receiving end of high-speed serial communication, and the data recovery circuit includes a rate tracking module 110, a sampling decision module 120 and a recovery data selection module 130.

[0031] Among them, the rate tracking module 110 is used to detect the frequency of the input data and generate a sampling clock signal with multiple phase offsets having the frequency information of the input data; the sampling decision module 120 is used to oversample the input data according to the sampling clock signal to obtain parallel sampling data of multiple phases, and determine the reference recovery data according to the parallel sampling data; the recovery data selection module 130 is used to determine the clock recovery signal and target recovery data corresponding to the input data according to the reference recovery data.

[0032] In one embodiment of the present application, the rate tracking module 110 includes a frequency divider 111, a phase frequency detection unit 112, a charge pump unit 113, a low-pass filter 114 and a multi-phase clock generation unit 115. The frequency divider 111 is used to adjust the signal frequency of the input data according to a preset frequency division ratio to generate a reference clock signal; the phase frequency detection unit 112 is used to detect the phase error and frequency error between the reference clock signal and the local clock signal; the charge pump unit 113 is used to generate a current pulse signal according to the phase error and the frequency error; the low-pass filter 114 is used to smooth the current pulse signal generated by the charge pump unit to generate a DC control signal; the multi-phase clock generation unit 115 is used to adjust the local clock signal according to the DC control signal to generate a sampling clock signal that is proportional to the input data frequency.

[0033] Specifically, the frequency divider 111 can perform pre-frequency division processing on the input data received by the high-speed serial communication interface, and according to the set frequency division ratio, the input data can be output to the phase frequency detection unit 112 at an integral multiple of the output frequency as a reference clock signal, and the phase frequency detection unit 112 determines the relationship between the input data after pre-frequency division processing and the oscillation frequency of the multi-phase clock generation unit 115 to determine the frequency error and phase error between the reference clock signal and the local clock signal generated by the multi-phase clock generation unit 115, and outputs a corresponding pulse signal according to the phase error and the frequency error, drives the charge pump unit 113 to generate a control current, and removes high-frequency noise after smoothing through the low-pass filter 114, and only retains the DC component used to adjust the oscillation frequency of the multi-phase clock generation unit 115, and then controls the multi-phase clock generation unit 115 to generate a frequency signal that is the same as the input data or has an equal proportional relationship, as the sampling clock signal required for sampling. In this embodiment, when sampling the input data, it is not necessary to know the data transmission rate in advance, and the rate of the input data can also be automatically locked, and no external clock is required, and the sampling clock signal corresponding to the input data can be obtained by adaptively following the input rate of the data.

[0034] See also Figure 2 , is a structural diagram of a rate tracking module provided in an embodiment of the present application. In this embodiment, the phase frequency detection unit 112 includes a phase detector (PD) and a frequency detector (PF), the charge pump unit 113 includes a first charge pump (CHG1) and a second charge pump (CHG2), and the multi-phase clock generation unit 115 is a multi-phase voltage-controlled oscillator (VCO).

[0035] The output end of the phase detector (PD) is connected to the input end of the first charge pump (CHG1), the output end of the first charge pump (CHG1) is connected to the input end of the low-pass filter (LPF), the output end of the low-pass filter (LPF) is connected to the input end of the multi-phase voltage-controlled oscillator (VCO), and the output end of the multi-phase voltage-controlled oscillator (VCO) is connected to the input end of the phase detector (PD) to form a phase tracking loop to lock the phase information of the input data.

[0036] The output end of the frequency discriminator (PF) is connected to the input end of the second charge pump (CHG2), the output end of the second charge pump (CHG2) is connected to the input end of the low-pass filter (LPF), the output end of the low-pass filter (LPF) is connected to the input end of the multi-phase voltage-controlled oscillator (VCO), and the output end of the multi-phase voltage-controlled oscillator (VCO) is connected to the input end of the frequency discriminator (PF) to form a frequency tracking loop to lock the frequency information of the input data.

[0037] In one embodiment of the present application, a multi-phase voltage-controlled oscillator includes N stages of inverters connected in series, and is used to generate 2N phase-shifted sampling clock signals in each signal period of input data; wherein N is an odd number.

[0038] See also Figure 3 In a specific embodiment of the present application, the multi-phase voltage-controlled oscillator includes nine inverters connected in series, each inverter can provide a 180-degree phase reversal, so the nine inverters connected in series can provide 18 different phase sampling signals, each phase differing by 20 degrees, and by adjusting the control voltage of the multi-phase voltage-controlled oscillator (VCO), switching between these phases can be achieved to achieve precise control of the oscillation frequency. The design of the inverters connected in series can also help reduce phase noise, so that the noise characteristics of each inverter can be averaged, thereby improving the frequency stability of the oscillator.

[0039] In one embodiment of the present application, Figure 1 As shown, the sampling decision module 120 includes a multi-phase sampling unit 121 and a data recovery decision unit 122. The multi-phase sampling unit 121 includes a plurality of parallel samplers, each of which receives a sampling clock signal with a phase shift, and is used to obtain sampled data at different phases of the input data; the data recovery decision unit 122 is connected to the output end of the multi-phase sampling unit 121, and is used to determine the corresponding reference recovery data within the signal period of each input data through a preset decision rule based on the sampled data at different phases.

[0040] Specifically, in the process of the data recovery judgment unit 122 judging the parallel sampled data, different strategies can be adopted to select the data sampling rate and phase, and determine the selection conditions of the correct data, so as to extract the correct reference recovery data and filter out the high-frequency noise in the data stream. For example, a strategy of M consecutive phase sampling data being consistent can be adopted, where M is an adjustable parameter. Such a strategy can enhance the robustness of the system and reduce misjudgments caused by noise or interference; or the edge of the data stream can be detected and the sampling rate can be determined, and then the data is sampled using a fixed phase, so that the sampling point can be ensured to be located at the key point of the data change, thereby improving the accuracy of the judgment.

[0041] In a specific embodiment of the present application, the NRZ serial data stream (SerialData) received through the high-speed serial interface and the sampled data (SampData) obtained by sampling through 18 parallel samplers are as follows: Figure 4 As shown, it is necessary to determine the correct reference recovery data from the sampled data through a preset decision rule. For example, in this implementation, the continuously output sampled data are counted, and every 9 sampled data are a sampled data group. The sampled data with a logic level of 1 and the sampled data with a logic level of 0 in each sampled data group are counted respectively. When the number of sampled data with a logic level of 1 is greater than the number of sampled data with a logic level of 0, it is determined that the logic level of the reference recovery data corresponding to the sampled data group is 1; when the number of sampled data with a logic level of 0 is greater than the number of sampled data with a logic level of 1, it is determined that the logic level of the reference recovery data corresponding to the sampled data group is 0.

[0042] It should be noted that the possibility of erroneous data codes is not limited to Figure 4 As shown in , in some other embodiments, phenomena such as continuous error code jumps or edge error code jumps may also occur. Different decision rules can be designed according to different jitter conditions to filter out high-frequency error jumps in the signal.

[0043] In one embodiment of the present application, Figure 1 As shown, the recovery data selection module 130 includes a phase adjustment unit 131 and a data selection unit 132 respectively connected to the output end of the data recovery judgment unit 122. The phase adjustment unit 131 is used to adjust the phase of the sampling clock signal offset according to the judgment result of the data recovery judgment unit 122 to determine the best sampling clock phase, and determine the clock recovery signal of the target recovery data according to the best sampling clock phase; the data selection unit 132 is also connected to the phase adjustment unit 131, and is used to determine the target recovery data according to the reference recovery data, and output the target recovery data according to the clock recovery signal.

[0044] Specifically, the recovery data selection unit 130 is strongly correlated with the sampling decision module 120, and only the data that has passed the sampling decision module 120 can enter the recovery data selection module 130. The recovery data selection module 130 can select the most reliable reference recovery data as the final target recovery data for data analysis according to the actual situation of the obtained reference recovery data. In a specific embodiment of the present application, when the received sampling data is similar to 111110000_000001111_111110000_000001111, it indicates that the phase of the sampling clock needs to be adjusted by the phase adjustment unit 131, so that the sampling position of the sampling clock is advanced or postponed, ensuring that the sampling position of the sampling clock is located in the middle of the data, thereby improving the accuracy of data recovery.

[0045] In one embodiment of the present application, the data selection unit 132 includes a FIFO storage unit for storing reference recovery data determined according to the parallel sampling data. After the phase adjustment unit 131 determines the optimal sampling clock phase by adjusting the sampling clock phase, since there is generally a fixed phase difference between the sampling clock and the output data clock, it is necessary to first store the reference recovery data in the FIFO storage unit, convert the sampling clock signal into a correct clock recovery signal, and then control the FIFO storage unit to output the corresponding target recovery data according to the clock recovery signal.

[0046] The data recovery circuit provided in the embodiment of the present application detects the frequency of the input data through the rate tracking module, and generates a sampling clock signal with multiple phase offsets having the frequency information of the input data; the input data is oversampled based on the sampling clock signal through the sampling decision module to obtain parallel sampling data of multiple phases, and the reference recovery data is determined based on the parallel sampling data; the clock recovery signal and the target recovery data corresponding to the input data are determined based on the reference recovery data through the recovery data selection module. In this way, the transmission rate of the input data can be adaptively adjusted, and the recovery of the clock signal and the transmission data can be achieved without relying on the external reference clock, and while recovering the transmission data, the high-frequency jitter and low-frequency jitter in the data transmission can be effectively suppressed.

[0047] See also Figure 5 , is a data recovery method provided in an embodiment of the present application, applied to the data recovery circuit as described in the above embodiment, the data recovery method comprises: Step 210: Generate a plurality of sampling clock signals with phase shifts according to the frequency of the input data.

[0048] In one embodiment, step S210 specifically includes: adjusting the signal frequency of the input data according to a preset division ratio to generate a reference clock signal; obtaining a phase error and a frequency error between the reference clock signal and the local clock signal; generating a current pulse signal according to the phase error and the frequency error; smoothing and filtering the current pulse signal to generate a DC control signal; adjusting the local clock signal according to the DC control signal to generate a sampling clock signal that is proportional to the input data frequency.

[0049] Step 220: Oversample the input data according to the sampling clock signal to obtain parallel sampling data of multiple phases.

[0050] Step 230: Determine reference restored data based on the parallel sampled data by using a preset decision rule; Specifically, the preset decision rules include a strategy for determining a data sampling rate, a strategy for selecting an optimal sampling clock phase, and a selection condition for reference recovery data.

[0051] Step 240: Determine a clock recovery signal and target recovery data corresponding to the input data according to the reference recovery data.

[0052] Specifically, the phase of the sampling clock signal is adjusted by the phase adjustment unit, and after the best sampling clock phase is selected, the clock recovery signal of the target recovery data is determined according to the best sampling clock phase, and then the target recovery data is output according to the clock recovery signal.

[0053] Based on the same inventive concept as the above embodiments, an embodiment of the present invention further provides a high-speed serial interface, which includes the data recovery circuit as described in the above embodiments.

[0054] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0055] In this document, the terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion of elements other than those listed and may also include additional elements not expressly listed.

[0056] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A data recovery circuit, characterized in that: It includes a rate tracking module, a sampling decision module and a recovery data selection module; The rate tracking module is used to detect the frequency of input data and generate a plurality of phase-shifted sampling clock signals having the frequency information of the input data; The sampling decision module is used to oversample the input data according to the sampling clock signal to obtain parallel sampling data of multiple phases, and determine reference recovery data according to the parallel sampling data; The recovery data selection module is used to determine the clock recovery signal and target recovery data corresponding to the input data according to the reference recovery data.

2. The data recovery circuit according to claim 1, characterized in that: The rate tracking module includes a frequency divider, a phase frequency detection unit, a charge pump unit, a low-pass filter and a multi-phase clock generation unit; wherein, The frequency divider is used to adjust the signal frequency of the input data according to a preset frequency division ratio to generate a reference clock signal; The phase frequency detection unit is used to detect the phase error and frequency error between the reference clock signal and the local clock signal; The charge pump unit is used to generate a current pulse signal according to the phase error and the frequency error; The low-pass filter is used to smooth the current pulse signal generated by the charge pump unit to generate a DC control signal; The multi-phase clock generating unit is used to adjust the local clock signal according to the DC control signal to generate a sampling clock signal that is proportional to the input data frequency.

3. The data recovery circuit according to claim 2, characterized in that: The phase frequency detection unit includes a phase detector and a frequency detector, the charge pump unit includes a first charge pump and a second charge pump, and the multi-phase clock generation unit is a multi-phase voltage-controlled oscillator; wherein, The output end of the phase detector is connected to the input end of the first charge pump, the output end of the first charge pump is connected to the input end of the low-pass filter, the output end of the low-pass filter is connected to the input end of the multi-phase voltage-controlled oscillator, and the output end of the multi-phase voltage-controlled oscillator is connected to the input end of the phase detector to form a phase tracking loop; The output end of the frequency discriminator is connected to the input end of the second charge pump, the output end of the second charge pump is connected to the input end of the low-pass filter, the output end of the low-pass filter is connected to the input end of the multi-phase voltage-controlled oscillator, and the output end of the multi-phase voltage-controlled oscillator is connected to the input end of the frequency discriminator to form a frequency tracking loop.

4. The data recovery circuit according to claim 3, characterized in that: The multi-phase voltage-controlled oscillator includes N stages of inverters connected in series, and is used to generate 2N phase-shifted sampling clock signals in each signal cycle of input data; wherein N is an odd number.

5. The data recovery circuit according to claim 1, characterized in that: The sampling and decision module includes a multi-phase sampling unit and a data recovery and decision unit; wherein, The multi-phase sampling unit includes a plurality of parallel samplers, each sampler receiving a sampling clock signal with a phase shift, and is used to obtain sampled data at different phases of the input data; The data recovery judgment unit is connected to the output end of the multi-phase sampling unit, and is used to determine the corresponding reference recovery data within the signal period of each input data through a preset judgment rule based on the sampled data at different phases.

6. The data recovery circuit according to claim 5, characterized in that: The recovery data selection module includes a phase adjustment unit and a data selection unit respectively connected to the output end of the data recovery judgment unit; wherein, The phase adjustment unit is used to adjust the phase of the sampling clock signal offset according to the judgment result of the data recovery judgment unit to determine the best sampling clock phase, and determine the clock recovery signal of the target recovery data according to the best sampling clock phase; The data selection unit is also connected to the phase adjustment unit, and is used to determine target recovery data according to the reference recovery data, and output the target recovery data according to the clock recovery signal.

7. The data recovery circuit according to claim 6, characterized in that: The data selection unit includes a FIFO storage unit for storing reference recovery data determined according to the parallel sampling data.

8. A data recovery method, characterized in that: include: Generate a plurality of sampling clock signals with phase shifts according to the frequency of the input data; Oversampling the input data according to the sampling clock signal to obtain parallel sampling data of multiple phases; Based on the parallel sampled data, determining reference restored data by a preset decision rule; According to the reference recovery data, a clock recovery signal and target recovery data corresponding to the input data are determined.

9. The data recovery method according to claim 8, characterized in that: The method of generating a plurality of sampling clock signals with phase shifts according to the frequency of the input data comprises: According to a preset frequency division ratio, adjusting the signal frequency of the input data to generate a reference clock signal; Obtaining a phase error and a frequency error between the reference clock signal and the local clock signal; generating a current pulse signal according to the phase error and the frequency error; Performing smoothing and filtering processing on the current pulse signal and generating a DC control signal; The local clock signal is adjusted according to the DC control signal to generate a sampling clock signal that is proportional to the input data frequency.

10. A high-speed serial interface, characterized in that: The data recovery circuit comprises the data recovery circuit as claimed in any one of claims 1 to 7.

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