High temperature tolerant successive approximation analog-to-digital converter

Abstract

Provided is a high-temperature-resistant successive approximation analog-digital converter, which can be applied to the technical field of analog-digital conversion. The analog-digital converter comprises: a capacitor DAC module for sampling an analog signal; a comparator module for comparing the signal output by the capacitor DAC module and outputting a comparison result; a timing and control unit module for generating a clock signal and a timing control signal; a voltage reference module for providing a reference voltage for the chip; a successive approximation register module for gradually approximating the true value of the analog input signal and converting it into a digital parallel signal output; an output buffer module for buffering the parallel signal and outputting serial data; and a temperature zone regulation module for keeping the bias voltage signal of the comparator module and the voltage reference module relatively stable at different temperatures by adjusting the bias voltage signal. Data output is in the form of serial output, and the efficiency and reliability of data transmission are optimized by the timing control module.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of analog-to-digital conversion, and in particular to a high-temperature-resistant successive approximation register analog-to-digital converter. BACKGROUND

[0002] As the core of high-precision microelectronic systems, high-performance analog-to-digital converters (ADCs) are crucial to the reliability of electronic systems, high-precision devices, and communication networks. With the expansion of ultra-large-scale integrated circuits into extreme environments such as petrochemical industry, aerospace, automotive electronics, etc., there is an urgent need for ADC modules that can work stably under harsh conditions such as high temperature. Existing bulk silicon process ADCs face problems such as a sharp increase in leakage current, a decrease in threshold voltage, a decrease in mobility, and latch-up effects as the temperature rises, resulting in a working temperature lower than 175℃. Traditional methods extend the signal transmission line or add a complex cooling system to improve the use temperature of bulk silicon process ADCs, but extending the signal transmission line will lead to a decrease in reliability and an increase in electromagnetic interference; adding a complex cooling system will increase system complexity, power consumption, and cost. Although silicon carbide (SiC) technology is resistant to high temperature, it is expensive and complex, making it difficult to be widely commercialized. SUMMARY

[0003] (I) Technical problems to be solved

[0004] To solve the problem of performance degradation and reliability reduction of traditional SAR ADCs under high-temperature conditions in the prior art, ensure that the SAR ADCs can still maintain high-efficiency and stable conversion performance under extreme temperature conditions, thereby widening the application field of SAR ADCs and improving the reliability and durability of the overall system, embodiments of the present disclosure provide a high-temperature-resistant successive approximation register analog-to-digital converter. By using a silicon-on-insulator (SOI) manufacturing process to design the circuit, the sharp increase in leakage current under high temperature is effectively suppressed, the threshold voltage is stabilized, and the adverse effects of latch-up effects are completely eliminated; by controlling the external controllable logic signal, the internal temperature zone regulation module can be adjusted to achieve calibration in a wide temperature range and obtain good working performance; the data output adopts a serial output mode, and the efficiency and reliability of data transmission are optimized through a timing control module; and the buffers of the input and output ports effectively reduce the interference of external noise on the ADC signal, further improving the anti-interference ability and signal quality of the ADC.

[0005] (II) Technical solutions

[0006] In view of the above problems, embodiments of the present disclosure provide a high-temperature-resistant successive approximation register analog-to-digital converter.

[0007] According to a first aspect of the present disclosure, a high-temperature-resistant successive approximation analog-to-digital converter is provided, comprising: a capacitive DAC module, comprising a sample-and-hold circuit and a segmented capacitive array, wherein the sample-and-hold circuit is configured to sample an analog signal to obtain a sampled signal; the segmented capacitive array comprises a 6-bit low-segment capacitive array, a 6-bit high-segment capacitive array, and a bridge capacitor, and the low-segment capacitive array and the high-segment capacitive array are each composed of a binary-coded capacitive array; a comparator module configured to compare a signal output by the capacitive DAC module and output a comparison result; a timing and control unit module configured to generate a clock signal and a timing control signal; a voltage reference module connected to the capacitive DAC module and configured to provide a reference voltage for the chip; a successive approximation register module connected to the timing and control unit module, the capacitive DAC module, and the comparator module, and configured to control a binary search algorithm in the conversion process, gradually approximate the true value of the analog input signal, and convert it into a digital parallel signal output; and an output buffer module configured to buffer the parallel signal output by the successive approximation register module and output serial data through a serial port.

[0008] In some exemplary embodiments, further comprising: a temperature zone regulation module connected to the comparator module and the voltage reference module, and configured to select resistors with different resistances by an externally gated input signal, adjust the bias current output by the temperature zone regulation module, realize current calibration in a wide temperature zone range, and adjust the bias voltage signal of the comparator module and the voltage reference module to keep them relatively stable at different temperatures.

[0009] In some exemplary embodiments, the timing and control unit module comprises: a clock generation module configured to select an external clock signal or enable an internal clock signal according to an external clock selection signal, and output a selected clock signal, wherein the selected clock signal serves as a reference for synchronous operation of various modules of the circuit; and a control signal generation module configured to cooperate with the clock signal to ensure accurate timing of other functional modules, thereby realizing coordinated operation of the entire system.

[0010] In some exemplary embodiments, the control signal generation module comprises: a state control logic module configured to generate key logic control signals; and a clock control logic module configured to divide the clock signal selected by the clock generation module and generate a clock flag bit.

[0011] In some exemplary embodiments, the temperature zone regulation module comprises a decoder, an enabling circuit, and a reference circuit; the externally gated input signal received by the temperature zone regulation module comprises RSEL<1> and RSEL<0>; RSEL<1> and RSEL<0> are connected to the decoder to select resistors with different resistances, thereby regulating the bias voltage generated in the reference circuit and suppressing the influence caused by temperature drift; and the bias voltage generated by the reference circuit is directly connected to the comparator.

[0012] In some exemplary embodiments, the input signals of the control logic received by the state control logic module include a chip enable signal, a chip select signal and a data conversion control signal.

[0013] In some exemplary embodiments, the input signals of the control logic received by the clock control logic module include a chip input clock signal and a clock enable signal.

[0014] In some exemplary embodiments, the high-temperature-resistant successive approximation analog-to-digital converter uses a silicon-on-insulator manufacturing process to design the circuit.

[0015] In some exemplary embodiments, the digital parallel signal obtained during the conversion process of the successive approximation register module is fed back to the capacitor DAC module in real time as a reference for the comparison operation of the comparator module.

[0016] In some exemplary embodiments, the input signals of the output buffer module include an externally supplied serial clock signal to ensure that the serial data can be correctly and orderly output; and the input signals of the output buffer module also include the output enable signal of the timing and control unit module, which is used to control whether the serial data can be output.

[0017] In some exemplary embodiments, the logic operation flow of the analog-to-digital converter includes the following activation preparations: the chip enable signal is set to a high level state, and the chip select signal is maintained at a low level state to activate the chip to prepare to receive instructions; the sampling is triggered: the analog-to-digital converter starts the sampling process by the falling edge of the reset or the data conversion control signal; the data conversion: the state signal remains at a low level, indicating that the data is not ready; after the analog-to-digital converter starts the data conversion, the state signal switches to a high level state; the state signal changes from the high level state to the low level state, indicating that the data conversion has been completed and the current output data is ready, and the serial data can be read through the serial interface; the continuous processing: the falling edge of the data conversion control signal is applied again to link to the next data conversion period, realizing the continuous data acquisition and processing flow, wherein, when the data conversion control signal is at a low level state, the data output terminal presents a high impedance state to ensure the accuracy of data transmission and the stability of the circuit; and the data conversion control signal returns to a high level state after the sampling is triggered and before the data conversion is completed, to avoid retriggering.

[0018] (Three) beneficial effects

[0019] From the above technical solutions, it can be seen that the high-temperature-resistant successive approximation analog-to-digital converter provided by the embodiments of the present disclosure has at least one of the following beneficial effects:

[0020] (1) By using the silicon-on-insulator (SOI) manufacturing process to design the circuit, the surge of leakage current at high temperature is effectively suppressed, the threshold voltage is stabilized, and the adverse effects of latch-up are completely eliminated to ensure that the ADC can work stably in a wide temperature range of -50°C to 250°C.

[0021] (2) By controlling the external controllable logic signal, the internal temperature zone regulation module can be adjusted to realize calibration in a wide temperature range and obtain good working performance.

[0022] (3) The data output adopts a serial output mode, and the efficiency and reliability of data transmission are optimized through the timing control module.

[0023] (4) The buffer of the input and output ports effectively reduces the interference of external noise on the ADC signal, and further improves the anti-interference ability and signal quality of the ADC. BRIEF DESCRIPTION OF DRAWINGS

[0024] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure, taken in conjunction with the accompanying drawings, in which:

[0025] Figure 1 A structural schematic diagram of a high-temperature-resistant successive approximation ADC according to an embodiment of the present disclosure is schematically shown;

[0026] Figure 2 A running mechanism principle schematic diagram of a temperature zone regulation module according to an embodiment of the present disclosure is schematically shown;

[0027] Figure 3 A core circuit working principle schematic diagram of a temperature zone regulation module according to an embodiment of the present disclosure is schematically shown;

[0028] Figure 4 A simulation result diagram of a temperature calibration technology based on a resistance regulation mechanism in a full working temperature range according to an embodiment of the present disclosure is schematically shown;

[0029] Figure 5 An ADC output signal timing diagram according to an embodiment of the present disclosure is schematically shown;

[0030] Figure 6 A 12-bit serial data specific output timing diagram according to an embodiment of the present disclosure is schematically shown; and

[0031] Figure 7 A spectrum of an output signal of the ADC simulated at 200°C and a diagram of calculated dynamic performance indicators such as signal-to-noise ratio (SNR) and effective number of bits (ENOB) according to an embodiment of the present disclosure are schematically shown. DETAILED DESCRIPTION

[0032] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to specific embodiments and drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.

[0033] Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology realizes isolation of transistors and substrates by means of a SiO2 insulating layer, effectively suppresses high-temperature leakage current, stabilizes threshold voltage, and eliminates latch-up effect, and thus becomes a preferred solution for high-temperature ADC design. Since high-temperature successive approximation register analog-to-digital converters (SAR ADCs) meet most circuit performance requirements in terms of high sampling rate and resolution, designing a high-temperature, high-precision, and low-power SAR ADC chip becomes a technical challenge, and the introduction of SOI CMOS technology provides an innovative solution to this problem and has great application potential.

[0034] Figure 1 A structural schematic diagram of a high-temperature successive approximation register analog-to-digital converter according to an embodiment of the present disclosure is schematically shown.

[0035] As shown in Figure 1 A high-temperature successive approximation register analog-to-digital converter according to an embodiment of the present disclosure includes a capacitor DAC module, a comparator module, a timing and control unit module, a voltage reference module, and a successive approximation register module. The capacitor DAC module includes a sample-and-hold circuit and a segmented capacitor array. The sample-and-hold circuit is configured to sample an analog signal to obtain a sampled signal. The segmented capacitor array includes a 6-bit low-segment capacitor array, a 6-bit high-segment capacitor array, and a bridge capacitor. The low-segment capacitor array and the high-segment capacitor array are both composed of a binary-coded capacitor array. The comparator module is configured to compare a signal output by the capacitor DAC module and output a comparison result. The timing and control unit module is configured to generate a clock signal and a timing control signal. The voltage reference module is connected to the capacitor DAC module and configured to provide a reference voltage for the chip. Optionally, the reference voltage is 2.5 V. The successive approximation register module is connected to the timing and control unit module, the capacitor DAC module, and the comparator module. The successive approximation register module is configured to control a binary search algorithm in a conversion process, gradually approximate a true value of an analog input signal, and convert the true value into a digital parallel signal output. The digital parallel signal obtained by the successive approximation register module in the conversion process is fed back to the capacitor DAC module in real time as a reference for a comparison operation of the comparator module, thereby forming a closed-loop and self-calibrating conversion mechanism to ensure high precision and stability of a conversion result. The output buffer module buffers the parallel signal output by the successive approximation register module and outputs serial data through a serial port.

[0036] In some exemplary embodiments, the high-temperature-resistant successive approximation analog-to-digital converter uses a silicon-on-insulator (SOI) manufacturing process to design the circuit. The circuit is designed using the SOI manufacturing process, thereby effectively suppressing the surge of leakage current at high temperature, stabilizing the threshold voltage, and completely eliminating the adverse effects of latch-up.

[0037] In some exemplary embodiments, the timing and control unit module includes a clock generation module for selecting an external clock signal or enabling an internal clock signal according to an external clock selection signal (CLKSEL) and outputting the selected clock signal, wherein the selected clock signal serves as a reference for the synchronous operation of various modules of the circuit; and a control signal generation module closely coordinated with the clock signal to ensure the timing of other functional modules is accurate, thereby achieving the coordinated operation of the overall system. Optionally, the control signal generation module includes a state control logic module for generating a key logic control signal (STS), and a clock control logic module for dividing the clock signal selected by the clock generation module and generating a clock flag bit.

[0038] In some exemplary embodiments, the input signals of the state control logic module of the control logic include a chip enable signal (Chip Enable, CE), a chip select signal (Not chip select, NCS), and a data conversion control signal (Read / Not Convert, RNC); and / or the input signals of the clock control logic module of the control logic include a chip input clock signal (XCLKIN) and a clock selection signal (CLKSEL).

[0039] In some exemplary embodiments, the high-temperature-resistant successive approximation analog-to-digital converter further includes a temperature zone regulation module connected to the comparator module and the voltage reference module, which selects resistors of different resistances through an externally gated input signal, adjusts the bias current output by the temperature zone regulation module, realizes current calibration in a wide temperature range, and adjusts the bias voltage signals of the comparator module and the voltage reference module to keep them relatively stable at different temperatures, thereby effectively avoiding performance degradation or failure caused by temperature fluctuations. As a result, the ADC can maintain a normal and stable working state in a wide temperature range.

[0040] In order to more clearly help understand the technical content of the embodiments of the present disclosure, the functions of the above-mentioned signals are explained in detail as follows.

[0041] The chip enable signal CE enables the chip and enables the output when a high level is input, and disables the chip and makes the output in a high-impedance state when a low level is input.

[0042] Chip select signal NCS, when input low level, will select the chip and enable the output, high level will deselect the chip, and put the output in high impedance state.

[0043] Data conversion control signal RNC, from high level to low level conversion start analog signal to digital signal conversion, when keep low level, output is in high impedance mode.

[0044] State output signal STS, when output low level, indicates that the conversion has been completed, and the data is available at the output, output high level indicates that the conversion is in progress.

[0045] Chip input clock signal XCLKIN, when selected access external clock signal, used to provide clock signal for the chip.

[0046] Clock selection signal CLKSEL, when input high level, clock generation module selects access external clock signal, input low level enables internal clock signal.

[0047] In the embodiment of the present disclosure, the output buffer module requires an external supply of a serial clock signal (SCLK) to ensure that the serial data (SDOUT) can be correctly and orderly output; in addition, the module also receives the output enable signal (EN) from the timing and control unit module, which is a key control condition, directly determines whether SDOUT can be allowed to normally output.

[0048] Preferably, SCLK needs to provide at least 12 pulse period signals (STS is low) when XCLKIN frequency is 4MHz, and sampling frequency is 50KSPS, it is recommended that SCLK uses frequency of 1.6MHz.

[0049] In order to ensure that all serial 12-bit data can be correctly output, the relationship between serial clock frequency and sampling frequency should be as follows:

[0050] f SCLK ≥32f sample (1)

[0051] In the formula, f SCLK is the serial clock frequency, f sample is the sampling frequency, the formula requires at least 32 serial clock periods in one sampling, because the conversion time is much smaller than the output data time, so it can ensure that all serial 12-bit data is output in the output data time period and has time margin.

[0052] Figure 2 The schematic diagram of the operating mechanism principle of the temperature zone regulation module provided by the embodiment of the present disclosure is shown.

[0053] AsFigure 2 As shown, according to an embodiment of this disclosure, the temperature control module includes a decoder, a startup circuit, and a reference circuit. Optionally, the decoder includes a 2-4 decoder. The externally selected input signal received by the temperature control module includes: RSEL. <1> RSEL <0> .

[0054] The temperature control module consists of signal RSEL <1> RSEL <0> Signal control, RSEL <1> and RSEL <0> The decoder is connected to select resistors of different values ​​to regulate the bias voltage generated in the reference circuit, ensuring a stable bias voltage at different temperatures and mitigating the effects of temperature drift; the bias voltage generated by the reference circuit is directly connected to the comparator. RSEL <1> RSEL <0> The specific temperature ranges corresponding to different values ​​are shown in Table 1.

[0055] Table 1 shows the temperature ranges corresponding to different input signal values.

[0056]

[0057] As shown in Table 1, by controlling the input signal selected by the external gate and adjusting the internal temperature control module, calibration can be achieved in a wide temperature range from -50℃ to 250℃, resulting in good working performance.

[0058] Figure 3 The schematic diagram illustrates the working principle of the core circuit of the temperature control module according to an embodiment of the present disclosure.

[0059] like Figure 3 As shown, the core circuit of the temperature control module according to an embodiment of this disclosure is represented by a selectable resistor R within the dashed box. By adjusting resistor R, the output current at different temperatures can be controlled. To better facilitate understanding of the technical content of this disclosure, the following is a detailed explanation... Figure 3 This section details the process of achieving temperature calibration by changing the resistance value.

[0060] The substrate voltage V of transistors M1 and M2 B The voltage at point V3 is equal to the voltage at point V3. Since transistor M3 is connected as a diode, V3 = V. TH3 .

[0061] Furthermore, since the source voltages of transistors M1 and M2 are V1=V2=V OV4,5 V OV4,5 This is the overdrive voltage of transistors M4 and M5. Therefore, V SB1 =V SB2 = V TH3 -V OV4,5 .

[0062] V TH3 With V OV4,5The same trend with temperature change can guarantee that V SB1 V SB2 does not change with temperature change, and thus greatly weakens the body effect of M1 and M2 tubes, and provides more stable guarantee for the generated current reference.

[0063] In addition, affected by the M1 diode connection, V RP The voltage of V1 is V TH1 . Since V1=V2, V RP -V2= V TH1 , V RN -V2= V OV2 , the drain current I2 of M2 is (V RP - V RN ) / R=( V TH1 -V OV2 ) / R.

[0064] The calculation is as follows:

[0065] (2)

[0066] As can be seen, changing the size of the resistance R can adjust the value of the reference current I2, and thus calibrate the change of the bandgap reference current with temperature.

[0067] The stability of the bandgap reference output current can guarantee that the bias current of the voltage comparator remains stable with temperature change, and thus the bandwidth is large enough, so that the speed of the comparator does not decrease with the increase of temperature, and the working speed of the comparator in high temperature environment is guaranteed.

[0068] Figure 4 The simulation result figure of the temperature calibration technology based on resistance regulation mechanism in the full working temperature range according to the embodiment of the present disclosure is schematically shown.

[0069] As shown in Figure 4 , the abscissa axis represents the simulation temperature range, which is finely divided into four temperature intervals from-50℃ to 250℃ to cover a wide range of working environments; the ordinate axis corresponds to the bias current value output by the temperature zone regulation module, which will be converted into a bias voltage for accurate adjustment.

[0070] By using the gating resistance technology, the embodiment of the present disclosure can effectively calibrate the reference voltage under different temperature conditions, thereby significantly enhancing the output stability and reliability of the ADC in extreme or harsh working environments. An innovative temperature compensation strategy is demonstrated.

[0071] Figure 5 The timing diagram of the ADC output signal according to the embodiment of the present disclosure is schematically shown.

[0072] When describing the operational logic of the chip, we need to ensure that the interactions and conditional triggers between various signals have a clear logical sequence and cause-and-effect relationship. The following is a reorganization and optimization of the given information to enhance its logic.

[0073] First, let's clarify the basic operating premise of the chip:

[0074] When CE is high, the chip is in an active state, allowing further operations to be performed.

[0075] When NCS is low, the chip is selected, ensuring that operations are only performed on the current chip.

[0076] Next, we will describe the role of the data conversion control signal RNC and its relationship with ADC sampling:

[0077] When the RNC signal is triggered (i.e., pulled low), under the condition that CE is high and NCS is low, the ADC circuit begins to perform sampling operations and then outputs the converted data. After conversion is complete, STS will be low, indicating that the output data is now available and can be read.

[0078] Finally, we will explain the behavior control of the output signal:

[0079] The 12-bit serial output signal will enter a high impedance state (high impedance state) in three cases: one is when the CE signal is low, i.e., the chip is not activated; two is when the RNC signal is high and not in the data output stage (i.e., not in the sampling and waiting for data reading period); three is when STS is high during conversion.

[0080] Therefore, to trigger the next data conversion, you only need to pull the RNC signal low again, provided that CE remains high and NCS remains low. This ensures that the chip can continue to respond to conversion requests and perform new sampling and conversion processes after each RNC falling edge.

[0081] The logical operation flow of the chip follows the following precise and standardized steps to ensure efficient and stable data conversion and output. During chip operation, first ensure that CE is in a high state and NCS is maintained at a low level to activate the chip to prepare to receive instructions. Then, trigger the ADC to start the sampling process through reset or the falling edge of RNC. After this trigger action, RNC needs to return to the high level state before the ADC completes the conversion to avoid accidental re-triggering.

[0082] During the conversion, the state signal (STS) remains low, indicating that the data is not ready. Once the ADC completes the data conversion, the STS will quickly switch to high, marking the beginning of the data conversion period, which is the core period of ADC data processing. Subsequently, when the STS switches from high to low, it explicitly indicates that the conversion is complete, and the current output data is ready to be read through the 12-bit serial interface SDOUT.

[0083] After the above steps are completed, continuous and efficient data acquisition and processing flow can be achieved by seamlessly connecting to the next data conversion period by applying the falling edge of RNC again. Importantly, in the low state of RNC, the data output end will present a high impedance state, ensuring the accuracy of data transmission and the stability of the circuit.

[0084] wherein T1 represents the reaction time from the RNC low level to the STS high level; T2 represents the time for which the RNC remains low; T3 represents the ADC conversion time; T4 represents the reaction time from the output data being valid to the STS low level, at which the serial data output officially begins; and T5 represents the reaction time from the RNC low level to the start of the next analog-to-digital conversion to the output high impedance state.

[0085] Figure 6 A 12-bit serial data specific output timing diagram according to an embodiment of the present disclosure is schematically shown.

[0086] As shown in Figure 6 To restore the 12-bit serial data output by the ADC to 12-bit parallel data for subsequent data processing, the timing of the STS, SCLK, and SDOUT signals needs to be determined.

[0087] At the end of the conversion period (slightly earlier than the STS signal being pulled low), the SDOUT immediately produces valid output data. The data is first output as MSB, and the data is changed at the falling edge of each SCLK until the last bit of data.

[0088] After the 12-bit serial data is output, the SDOUT still has an output due to the presence of the SCLK signal and the RNC signal not being pulled low to trigger the next data conversion, but the output is a logic zero.

[0089] Until the RNC signal is pulled low to trigger the next data conversion, the output signal changes from outputting a logic zero to a high impedance state.

[0090] wherein T6 represents the reaction time from the output data being valid to the STS low level; and T7 represents the time from the STS low level to the rising edge of the first SCLK clock signal.

[0091] Figure 7Fig. 6 schematically shows a spectrum of an output signal of an ADC according to an embodiment of the present disclosure simulated at 200°C, and a graph of a calculated signal-to-noise ratio (SNR), effective number of bits (ENOB), and other dynamic performance indicators.

[0092] As shown in Fig. 6, the SNR of the output signal of the ADC according to an embodiment of the present disclosure simulated at 200°C is about 68.2 dB, and the ENOB is about 11.0 bits. Figure 7

[0093] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.​

Claims

1. A high-temperature resistant successive approximation analog-to-digital converter, characterized in that, include: The capacitor DAC module includes a sample-and-hold circuit and a segmented capacitor array. The sample-and-hold circuit is used to sample the analog signal to obtain the sampled signal. The segmented capacitor array includes a 6-bit low-segment capacitor array, a 6-bit high-segment capacitor array, and a bridge capacitor. Both the low-segment capacitor array and the high-segment capacitor array are composed of binary-coded capacitor arrays. The comparator module is used to compare the signal output by the capacitor DAC module and output the comparison result; The timing and control unit module is used to generate clock signals and timing control signals; A voltage reference module, connected to the capacitor DAC module, is used to provide a reference voltage for the chip's internal circuitry. The successive approximation register module is connected to the timing and control unit module, the capacitor DAC module, and the comparator module. It is used to control the binary search algorithm in the conversion process, gradually approximate the true value of the analog input signal, and convert it into a digital parallel signal output. The output buffer module buffers the parallel signals output by the successive approximation register module and outputs serial data via the serial port; and The temperature control module is connected to the comparator module and the voltage reference module. Through an externally selected input signal, it selects resistors of different resistance values ​​and adjusts the bias current output by the temperature control module to achieve current calibration over a wide temperature range. At the same time, it adjusts the bias voltage signals of the comparator module and the voltage reference module to keep them relatively stable at different temperatures.

2. The high-temperature resistant successive approximation analog-to-digital converter according to claim 1, characterized in that, The timing and control unit module includes: The clock generation module is used to select whether to access an external clock signal or enable an internal clock signal based on an external clock strobe signal, and output the selected clock signal, wherein the selected clock signal serves as a reference for the synchronous operation of various modules of the circuit. The control signal generation module works closely with the clock signal to ensure the accurate timing of other functional modules, thereby achieving coordinated operation of the entire system.

3. The high-temperature resistant successive approximation analog-to-digital converter according to claim 2, characterized in that, The control signal generation module includes: The state control logic module is used to generate key logic control signals; and The clock control logic module is used to divide the clock signal selected by the clock generation module and generate a clock flag bit.

4. The high-temperature resistant successive approximation analog-to-digital converter according to claim 1, characterized in that, The temperature control module includes a decoder, a startup circuit, and a reference circuit. The externally selected input signal received by the temperature control module includes: RSEL <1> RSEL <0> ; The RSEL <1> and the RSEL <0> Connecting the decoder allows for the selection of resistors with different resistance values ​​to regulate the bias voltage generated in the reference circuit, thus mitigating the effects of temperature drift; and The bias voltage generated by the reference circuit is directly connected to the comparator.

5. The high-temperature resistant successive approximation analog-to-digital converter according to claim 3, characterized in that, The state control logic module receives input signals for the control logic, including: chip enable signal, chip select signal, and data conversion control signal; and / or The clock control logic module receives the following input signals for the control logic: chip input clock signal and clock strobe signal.

6. The high-temperature resistant successive approximation analog-to-digital converter according to claim 1, characterized in that, The high-temperature resistant successive approximation analog-to-digital converter uses silicon-on-insulator (SiI) fabrication technology to design the circuit.

7. The high-temperature resistant successive approximation analog-to-digital converter according to claim 1, characterized in that, The digital parallel signal obtained during the successive approximation register module conversion process is fed back to the capacitor DAC module in real time as the reference for the comparison operation of the comparator module.

8. The high-temperature resistant successive approximation analog-to-digital converter according to claim 1, characterized in that, The input signals of the output buffer module include an externally supplied serial clock signal to ensure that serial data can be output correctly and in an orderly manner; and The input signal of the output buffer module also includes the output enable signal of the timing and control unit module, which is used to control whether the serial data can be output.

9. The high-temperature resistant successive approximation analog-to-digital converter according to claim 1, characterized in that, The logic operation process of the analog-to-digital converter includes: Activation preparation: Set the chip enable signal to a high level and keep the chip select signal at a low level to activate the chip and prepare it to receive commands. Triggered sampling: The analog-to-digital converter is triggered to start the sampling process by the falling edge of the reset or data conversion control signal; Data Conversion: The status signal remains low, indicating that the data is not yet ready; after the analog-to-digital converter starts data conversion, the status signal switches to a high level; when the status signal changes from a high level to a low level, it indicates that the data conversion is complete and the current output data is ready to be read through the serial interface. Continuous processing involves applying the falling edge of the data conversion control signal again to initiate the next data conversion cycle, thus achieving a continuous data acquisition and processing workflow. Specifically, when the data conversion control signal is at a low level, the data output terminal presents a high impedance state to ensure the accuracy of data transmission and the stability of the circuit; and After sampling is triggered and before data conversion is completed, the data conversion control signal returns to a high level to avoid re-triggering.

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