Data eye width expansion decision feedback equalizer and data eye width expansion method

Abstract

The invention discloses a data eye width expansion decision feedback equalizer and a data eye width expansion method, and relates to the technical field of digital signal processing, the decision feedback equalizer comprises a first numerical control delay unit, a second numerical control delay unit, an OR gate logic circuit, a NOR gate logic circuit, a data sampler and a decision feedback circuit; the first numerical control delay unit is used for delaying the positive phase signal and outputting and sending the positive phase signal to the OR gate logic circuit; the second numerical control delay unit is used for delaying the negative phase signal and outputting and sending the negative phase signal to the NOR gate logic circuit; the data sampler is used for outputting four paths of adopted data; and the decision feedback circuit is used for taking the odd bit signal as a first path of output signal and taking the even bit signal as a second path of output signal. According to the invention, data eye width expansion is realized, so that the jitter tolerance of the deserializer is effectively improved, and the bit error rate of the deserializer is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and in particular to a data eye width expansion decision feedback equalizer and a data eye width expansion method. Background Art

[0002] As the amount of in-vehicle video data increases and the rate of the serial-deserializer (SerDes) interface continues to increase, more solutions are needed to improve the quality of high-speed interface signals. Decision Feedback Equalizer (DFE) is one of the widely used solutions to effectively improve the quality of received signals. It can effectively improve the receiving performance of RX, especially in high-speed data transmission systems. However, as the data rate of the serdes (deserializer) interface continues to increase, the channel insertion loss and return loss become more and more serious, resulting in increased signal data clock jitter at the receiving end and reduced data eye width. The existing traditional DFE mainly solves the adjacent data amplitude distortion caused by inter-symbol interference, that is, equivalently increases the data eye height. However, when the receiver system narrows the data eye width due to factors such as noise introduced into the signal channel, radiation interference in the system, and large power supply fluctuations, the traditional DFE cannot solve such problems. Summary of the invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, the present invention provides a data eye width expansion decision feedback equalizer and a data eye width expansion method, which realizes data eye width expansion by expanding the data width and combining the decision feedback circuit structure, thereby effectively improving the jitter tolerance of the deserializer and reducing the bit error rate of the deserializer.

[0004] One aspect of the present invention provides a data eye width expansion decision feedback equalizer, comprising: A first digital control delay unit, a second digital control delay unit, an OR gate logic circuit, a NOR gate logic circuit, a data sampler and a decision feedback circuit; The first digital control delay unit is used to delay the positive phase signal of the input high-speed serial data differential signal, and input the delayed output signal and the input signal before the delay into the OR gate logic circuit, and the OR gate logic circuit outputs the first data signal, and the first data signal is a logic 1 width expansion signal; The second digital control delay unit is used to delay the negative phase signal of the input high-speed serial data differential signal, and input the delayed output signal and the input signal before the delay to the NOR gate logic circuit, and the NOR gate logic circuit outputs a second data signal, and the second data signal is a logic 0 width extension signal; a data sampler, configured to sample odd bits of the first data signal and the second data signal according to a first clock signal to obtain an odd bit signal of the first data signal and an odd bit signal of the second data signal; and sample even bits of the first data signal and the second data signal according to a second clock signal to obtain an even bit signal of the first data signal and an even bit signal of the second data signal, wherein the phase difference between the first clock signal and the second clock signal is 180 degrees; A decision feedback circuit is used to use the odd-numbered bit signals in the first data signal or the second data signal as the first output signal, and use the even-numbered bit signals in the first data signal or the second data signal as the second output signal; wherein the first output signal is determined to select the output of a logic 0 width extension signal or a logic 1 width extension signal according to the situation of the second output signal; and the second output signal is determined to select the output of a logic 0 width extension signal or a logic 1 width extension signal according to the situation of the first output signal.

[0005] Further, the decision feedback circuit includes a first selector, a first D flip-flop, a second selector and a second D flip-flop, wherein two input ends of the first selector are connected to the odd-numbered bit signal of the first data signal and the odd-numbered bit signal of the second data signal, and an enable control end of the first selector is connected to the output end of the second D flip-flop; two input ends of the second selector are connected to the even-numbered bit signal of the first data signal and the even-numbered bit signal of the second data signal, and an enable control end of the second selector is connected to the output end of the first D flip-flop; the data input end of the first D flip-flop is connected to the output end of the first selector, the clock input end of the first D flip-flop is connected to the first clock signal, and the output end of the first D flip-flop outputs the first output signal; the data input end of the second D flip-flop is connected to the output end of the second selector, the clock input end of the second D flip-flop is connected to the second clock signal, and the output end of the second D flip-flop outputs the second output signal.

[0006] Furthermore, the first digital control delay unit includes a first inverter, a second inverter and a first delay capacitor; the input end of the first inverter receives the positive phase signal of the input high-speed serial data differential signal, the output end of the first inverter is connected to the input end of the second inverter and the first end of the first delay capacitor, the second end of the first delay capacitor is grounded through the first switch, and the output end of the second inverter outputs the delayed positive phase signal; the second digital control delay unit includes a third inverter, a fourth inverter and a second delay capacitor; the input end of the third inverter receives the negative phase signal of the input high-speed serial data differential signal, the output end of the third inverter is connected to the input end of the fourth inverter and the first end of the second delay capacitor, the second end of the second delay capacitor is grounded through the second switch, and the output end of the fourth inverter outputs the delayed negative phase signal.

[0007] Furthermore, the first delay capacitor and the second delay capacitor are both 8-bit capacitor arrays, the first switch and the second switch are both 8-bit switches, and the 8-bit capacitor array and the 8-bit switch control the delay between input and output by controlling the size of the first delay capacitor or the second delay capacitor.

[0008] Furthermore, the size of the first delay capacitor or the second delay capacitor is controlled by an 8-bit digital control word.

[0009] Furthermore, the data sampler includes a sensitive amplifier and a set-reset latch; the sensitive amplifier is used to amplify the input first data signal and the second data signal, and sample and hold the amplified first data signal and the second data signal through the first clock signal and the second clock signal, so as to output a set signal and a reset signal to the set-reset latch; the set-reset latch is used to receive the set signal and the reset signal output by the sensitive amplifier, and output logic 1 or logic 0 according to the state of the set signal and the reset signal.

[0010] Furthermore, the sense amplifier is an 8-channel sense amplifier, and the set-reset latch is an 8-channel set-reset latch.

[0011] Another aspect of the present invention further provides a data eye width expansion method based on the above-mentioned data eye width expansion decision feedback equalizer, comprising: The positive phase signal of the input high-speed serial data differential signal is delayed by the first digital control delay unit, and the output signal after the delay and the input signal before the delay are input into the OR gate logic circuit together, and the OR gate logic circuit outputs the first data signal, and the first data signal is a logic 1 width expansion signal; The negative phase signal of the input high-speed serial data differential signal is delayed by the second digital control delay unit, and the output signal after the delay and the input signal before the delay are input to the NOR gate logic circuit together, and the NOR gate logic circuit outputs a second data signal, and the second data signal is a logic 0 width extension signal; Taking the first clock signal as a reference, sampling the odd bits of the first data signal and the second data signal through a data sampler to obtain an odd bit signal of the first data signal and an odd bit signal of the second data signal; taking the second clock signal as a reference, sampling the even bits of the first data signal and the second data signal through a data sampler to obtain an even bit signal of the first data signal and an even bit signal of the second data signal; the phase difference between the first clock signal and the second clock signal is 180 degrees; Through the decision feedback circuit, the odd-numbered bit signal in the first data signal or the second data signal is used as the first output signal, and the even-numbered bit signal in the first data signal or the second data signal is used as the second output signal; the first output signal is determined to select the output logic 0 width expansion signal or the logic 1 width expansion signal according to the situation of the second output signal; the second output signal is determined to select the output logic 0 width expansion signal or the logic 1 width expansion signal according to the situation of the first output signal.

[0012] Furthermore, the step of using the odd-numbered bit signal in the first data signal or the second data signal as the first output signal and the even-numbered bit signal in the first data signal or the second data signal as the second output signal through the decision feedback circuit includes: inputting the odd-numbered bit signal of the first data signal and the odd-numbered bit signal of the second data signal into a first selector, inputting the output signal of the first selector into the data input end of a first D flip-flop, inputting the first clock signal into the clock input end of the first D flip-flop, inputting the output signal of the second D flip-flop into the enable control end of the first selector, and using the output signal of the first D flip-flop as the first output signal; inputting the even-numbered bit signal of the first data signal and the even-numbered bit signal of the second data signal into a second selector, inputting the output signal of the second selector into the data input end of a second D flip-flop, inputting the second clock signal into the clock input end of a second D flip-flop, inputting the output signal of the first D flip-flop into the enable control end of the second selector, and using the output signal of the second D flip-flop as the second output signal.

[0013] Furthermore, the step of delaying the positive phase signal of the input high-speed serial data differential signal through the first digitally controlled delay unit includes: inputting the positive phase signal of the high-speed serial data differential signal to the input end of the first inverter, inputting the output signal of the first inverter to the input end of the second inverter and the first end of the first delay capacitor, grounding the second end of the first delay capacitor through a switch, and using the output signal of the second inverter as the delayed positive phase signal; the step of delaying the negative phase signal of the input high-speed serial data differential signal through the second digitally controlled delay unit includes: inputting the negative phase signal of the high-speed serial data differential signal to the input end of the third inverter, inputting the output signal of the third inverter to the input end of the fourth inverter and the first end of the second delay capacitor, grounding the second end of the delay capacitor through a switch, and using the output signal of the fourth inverter as the delayed negative phase signal.

[0014] The data eye width expansion decision feedback equalizer and data eye width expansion method provided by the present invention realize equivalent expansion of the data eye width by expanding the data width in combination with the decision feedback circuit structure, thereby effectively improving the jitter tolerance of the deserializer and reducing the bit error rate of the deserializer. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings: Figure 1 is a data eye width expansion timing diagram provided by an embodiment of the present application; Figure 2 It is a circuit structure diagram of a data eye width expansion decision feedback equalizer provided by an embodiment of the present application; Figure 3 is a circuit structure diagram of a digital control delay unit provided in one embodiment of the present application; Figure 4 is a circuit structure diagram of a data sampler provided by an embodiment of the present application; Figure 5 It is a flowchart of a data eye width expansion method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0018] It should be understood that although the terms first, second, third, etc. may be used to describe the acquisition modules in the embodiments of the present invention, the acquisition modules should not be limited to these terms. These terms are only used to distinguish the acquisition modules from each other.

[0019] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0020] It should be noted that the directional words such as "upper", "lower", "left", and "right" described in the embodiments of the present invention are described at the angles shown in the drawings and should not be understood as limiting the embodiments of the present invention. In addition, in the context, it should also be understood that when it is mentioned that an element is formed "on" or "under" another element, it can not only be formed directly "on" or "under" another element, but also be formed "on" or "under" another element indirectly through an intermediate element.

[0021] The differential signal in the prior art is also called the differential mode signal. Two signal lines are required for differential signal transmission. The two signal lines have equal amplitudes and opposite phases. The voltage difference between the two signal lines represents logic 0 and logic 1. Figure 1 , the logic 0 and logic 1 (hereinafter referred to as data 0 and data 1) of the normally input differential signal have the same width. In order to expand the data width, the present invention processes data 1 and data 0 respectively to form two output channels. Channel 1 expands the width of data 1 and compresses the width of data 0. Channel 2 expands the width of data 0 and compresses the width of data 1. The data with the expanded width is alternately selected through the decision feedback structure, thereby equivalently expanding the eye width of the input signal.

[0022] See also Figure 2 An embodiment of the present invention discloses a data eye width expansion decision feedback equalizer 100, comprising: A first digitally controlled delay unit 101 , a second digitally controlled delay unit 102 , an OR gate logic circuit 103 , a NOR gate logic circuit 104 , a data sampler 105 and a decision feedback circuit 106 .

[0023] Specifically, the first digital control delay unit 101 is used to delay the positive phase signal (INP terminal input signal) of the input high-speed serial data differential signal, and input the delayed output signal and the input signal before the delay to the OR gate logic circuit 103. Since the output of the OR gate logic circuit 103 is also logic 1 when any input is logic 1, the OR gate logic circuit 103 will output the logic 1 signal in the input delay signal, thus forming a width expansion of logic 1 (i.e., data 1). Similarly, the execution logic of the NOR gate logic circuit is opposite to that of the OR gate logic circuit, and it will output the logic 0 signal in the input delay signal, thus forming a width expansion of logic 0 (i.e., data 0).

[0024] Specifically, the second digital control delay unit 102 is used to delay the negative phase signal (INN terminal input signal) of the input high-speed serial data differential signal, and input the delayed output signal and the input signal before the delay to the OR gate logic circuit 103. Since the output of the OR gate logic circuit 103 is also logic 1 when any input is logic 1, the OR gate logic circuit 103 will output the logic 1 signal in the input delay signal, thus forming a width expansion of logic 1 (i.e., data 1). Similarly, the execution logic of the NOR gate logic circuit is opposite to that of the OR gate logic circuit, and it will output the logic 0 signal in the input delay signal, thus forming a width expansion of logic 0 (i.e., data 0).

[0025] See also Figure 3 Preferably, the first digital control delay unit 101 includes a first inverter 1011, a second inverter 1012 and a first delay capacitor 1013; the input end of the first inverter 1011 receives the positive phase signal INP of the input high-speed serial data differential signal, the output end of the first inverter 1011 is connected to the input end of the second inverter 1012 and the first end of the first delay capacitor 1012, the second end of the first delay capacitor 1013 is grounded through the first switch 1014, and the output end of the second inverter 1012 outputs the delayed positive phase signal. Figure 3 The second digital control delay unit 102 includes a third inverter 1021, a fourth inverter 1022 and a second delay capacitor 1023; the input end of the third inverter 1021 receives the negative phase signal INN of the input high-speed serial data differential signal, the output end of the third inverter 1021 is connected to the input end of the fourth inverter 1022 and the first end of the second delay capacitor 1023, the second end of the second delay capacitor 1023 is grounded through the second switch 1024, and the output end of the fourth inverter 1022 outputs the delayed negative phase signal.

[0026] More preferably, the first delay capacitor 1013 and the second delay capacitor 1023 are both 8-bit capacitor arrays, the first switch 1014 and the second switch 1024 are both 8-bit switches, and the 8-bit capacitor array and the 8-bit switch control the delay between input and output by controlling the size of the first delay capacitor 1013 or the second delay capacitor 1023. Furthermore, the size of the first delay capacitor 1013 or the second delay capacitor 1023 can be controlled by an 8-bit digital control word.

[0027] Further, the data 1 width extension channel and the data 0 width extension channel simultaneously transmit data to the data sampler 105, and the data sampler 105 uses two channels of ck0 and ck2 with a phase interval of 180° to sample the data of the two channels, the sampling clock ck0 samples the data at the odd positions of the two input data channels, and the sampling clock ck2 samples the data at the even positions of the two input data channels, thereby generating a total of four data channels, namely, the odd position data 1 extension channel inp1_ck0, the odd position data 0 extension channel inn1_ck0, the even position data 1 extension channel inp1_ck2, and the even position data 0 extension channel inn1_ck2. More preferably, the data sampler 105 uses four orthogonal signals ck0, ck1, ck2, and ck3 with a phase interval of 90° to sample the two input signals, and uses the clock signal ck0 to sample the data of the data 1 extension channel and the data 0 extension channel, respectively, to generate the output signals inp1_ck0 and inn1_ck0. Among them, inp1_ck0 is the data sampling output of ck0 for the data 1 extension path, and inn1_ck0 is the data sampling output of ck0 for the data 0 extension path data. The clock signal ck2 is also used to sample the data of the data 1 extension path and the data 0 extension path to generate output signals inp1_ck2 and inn1_ck2. Among them, inp1_ck2 is the data sampling output of ck2 for the data 1 extension, and inn1_ck2 is the data sampling output of ck2 for the data 0 extension path data. Ck0 and ck2 are clock signals with a phase difference of 180°. Ck1 and Ck3 also generate serial data transition band data edge_data for the data sampling of the input data 1 extension path and the data 0 extension path, respectively, and combine the output data odd and data even to provide phase lead and lag information to the phase detector in the CDR loop.

[0028] See also Figure 4, the data sampler 105 includes a sense amplifier 1051 and a set-reset latch 1052. The sense amplifier 1051 amplifies the input inp1 and inn1, and samples and holds the amplified inp1 and inn1 through ck0 and ck2, so as to output a set signal S and a reset signal R to the set-reset latch 1052. The set-reset latch 1052 is used to receive the set signal S and the reset signal R output by the sense amplifier 1051, and output a logic 1 or a logic 0 according to the state of the set signal S and the reset signal R. More preferably, the sense amplifier 1051 is an 8-channel sense amplifier, and the set-reset latch 1052 is an 8-channel set-reset latch.

[0029] Further, the decision feedback circuit 106 is used to use the odd-numbered bit signals in inp1_ck0 and inn1_ck0 as the first output signal, and use the even-numbered bit signals in inp1_ck2 and inn1_ck2 as the second output signal. Figure 2 , the 4-way output data inp1_ck0, inn1_ck0, inp1_ck2 and inn1_ck2 of the data sampler 105 are sent to the decision feedback circuit 106 composed of the first selector 1061, the first D flip-flop 1062, the second selector 1063 and the second D flip-flop 1064. The decision feedback circuit 106 controls the first selector 1061 and the second selector 1063 to select the data for expanding the width of data 1 or 0 according to the current data, so as to achieve the eye width expansion effect of the input high-speed serial signal. More specifically, the two input terminals of the first selector 1061 are connected to the inp1_ck0 and inn1_ck0, and the enable control terminal of the first selector 1061 is connected to the output terminal of the second D flip-flop 1064; the two input terminals of the second selector 1063 are connected to the inp1_ck2 and inp1_ck2, and the enable control terminal of the second selector 1063 is connected to the output terminal of the first D flip-flop 1062; the data input terminal of the first D flip-flop 1062 is connected to the output terminal of the first selector 1061, the clock input terminal of the first D flip-flop 1062 is connected to the first clock signal ck0, and the output terminal of the first D flip-flop 1062 outputs the first output signal. The data input terminal of the second D flip-flop 1064 is connected to the output terminal of the second selector 1063, the clock input terminal of the second D flip-flop 1064 is connected to the second clock signal ck2, and the output terminal of the second D flip-flop 1064 outputs the second output signal. The first output signal and the second output signal are signals after the data eye width is equivalently expanded.

[0030] The data eye width expansion decision feedback equalizer 100 provided by the present invention realizes equivalent expansion of the data eye width by expanding the data width and combining the decision feedback circuit structure, thereby effectively improving the jitter tolerance of the deserializer and reducing the bit error rate of the deserializer.

[0031] See also Figure 5 Another embodiment of the present invention further provides a data eye width expansion method, which is implemented based on the above-mentioned data eye width expansion decision feedback equalizer 100 and specifically includes: Step S101, delaying the positive phase signal of the input high-speed serial data differential signal through a first digital control delay unit, inputting the delayed output signal and the input signal before the delay into an OR gate logic circuit, and the OR gate logic circuit outputs a first data signal, and the first data signal is a logic 1 width expansion signal; Step S102, delaying the negative phase signal of the input high-speed serial data differential signal through the second digital control delay unit, inputting the delayed output signal and the input signal before the delay into the NOR gate logic circuit, and the NOR gate logic circuit outputs a second data signal, and the second data signal is a logic 0 width extension signal; Step S103, taking the first clock signal as a reference, sampling the odd bits of the first data signal and the second data signal through a data sampler to obtain an odd bit signal of the first data signal and an odd bit signal of the second data signal; taking the second clock signal as a reference, sampling the even bits of the first data signal and the second data signal through a data sampler to obtain an even bit signal of the first data signal and an even bit signal of the second data signal; the phase difference between the first clock signal and the second clock signal is 180 degrees; Step S104, through the decision feedback circuit, the odd-numbered bit signal in the first data signal or the second data signal is used as the first output signal, and the even-numbered bit signal in the first data signal or the second data signal is used as the second output signal; the first output signal is determined to select the output logic 0 width expansion signal or the logic 1 width expansion signal according to the situation of the second output signal; the second output signal is determined to select the output logic 0 width expansion signal or the logic 1 width expansion signal according to the situation of the first output signal.

[0032] Furthermore, step S104 further includes: Step S1041, inputting the odd-numbered bit signal of the first data signal and the odd-numbered bit signal of the second data signal into the first selector, inputting the output signal of the first selector into the data input terminal of the first D flip-flop, inputting the first clock signal into the clock input terminal of the first D flip-flop, inputting the output signal of the second D flip-flop into the enable control terminal of the first selector, and using the output signal of the first D flip-flop as the first output signal; Step S1042, input the even-numbered bit signal of the first data signal and the even-numbered bit signal of the second data signal to the second selector, input the output signal of the second selector to the data input terminal of the second D flip-flop, input the second clock signal to the clock input terminal of the second D flip-flop, input the output signal of the first D flip-flop to the enable control terminal of the second selector, and use the output signal of the second D flip-flop as the second output signal.

[0033] Further, step S101 also includes: inputting the positive phase signal of the high-speed serial data differential signal to the input end of the first inverter, inputting the output signal of the first inverter to the input end of the second inverter and the first end of the first delay capacitor, grounding the second end of the first delay capacitor through a switch, and using the output signal of the second inverter as the delayed positive phase signal; Furthermore, step S102 also includes: inputting the negative phase signal of the high-speed serial data differential signal to the input end of the third inverter, inputting the output signal of the third inverter to the input end of the fourth inverter and the first end of the second delay capacitor, grounding the second end of the delay capacitor through a switch, and using the output signal of the fourth inverter as the delayed negative phase signal.

[0034] The above description is only a preferred embodiment of the present invention. Those skilled in the art should understand that the scope of disclosure involved in the present invention is not limited to the technical solution formed by a specific combination of the above technical features, but also should cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present invention (but not limited to) to form a technical solution.

Claims

1. A data eye width expansion decision feedback equalizer, characterized in that: include: A first digital control delay unit, a second digital control delay unit, an OR gate logic circuit, a NOR gate logic circuit, a data sampler and a decision feedback circuit; The first digital control delay unit is used to delay the positive phase signal of the input high-speed serial data differential signal, and input the delayed output signal and the input signal before the delay into the OR gate logic circuit, and the OR gate logic circuit outputs the first data signal, and the first data signal is a logic 1 width expansion signal; The second digital control delay unit is used to delay the negative phase signal of the input high-speed serial data differential signal, and input the delayed output signal and the input signal before the delay to the NOR gate logic circuit, and the NOR gate logic circuit outputs a second data signal, and the second data signal is a logic 0 width extension signal; a data sampler, configured to sample odd bits of the first data signal and the second data signal according to a first clock signal to obtain an odd bit signal of the first data signal and an odd bit signal of the second data signal; and sample even bits of the first data signal and the second data signal according to a second clock signal to obtain an even bit signal of the first data signal and an even bit signal of the second data signal, wherein the phase difference between the first clock signal and the second clock signal is 180 degrees; A decision feedback circuit is used to use the odd-numbered bit signals in the first data signal or the second data signal as the first output signal, and use the even-numbered bit signals in the first data signal or the second data signal as the second output signal; wherein the first output signal is determined to select the output of a logic 0 width extension signal or a logic 1 width extension signal according to the situation of the second output signal; and the second output signal is determined to select the output of a logic 0 width extension signal or a logic 1 width extension signal according to the situation of the first output signal.

2. The data eye width expansion decision feedback equalizer according to claim 1, characterized in that: The decision feedback circuit includes a first selector, a first D flip-flop, a second selector and a second D flip-flop, wherein: Two input terminals of the first selector are connected to the odd-numbered bit signal of the first data signal and the odd-numbered bit signal of the second data signal, and an enable control terminal of the first selector is connected to the output terminal of the second D flip-flop; Two input terminals of the second selector are connected to the even-numbered bit signal of the first data signal and the even-numbered bit signal of the second data signal, and an enable control terminal of the second selector is connected to the output terminal of the first D flip-flop; A data input terminal of the first D flip-flop is connected to an output terminal of the first selector, a clock input terminal of the first D flip-flop is connected to the first clock signal, and an output terminal of the first D flip-flop outputs the first output signal; A data input terminal of the second D flip-flop is connected to an output terminal of the second selector, a clock input terminal of the second D flip-flop is connected to the second clock signal, and an output terminal of the second D flip-flop outputs the second output signal.

3. The data eye width expansion decision feedback equalizer according to claim 1, characterized in that: The first digital control delay unit includes a first inverter, a second inverter and a first delay capacitor; the input end of the first inverter receives the positive phase signal of the input high-speed serial data differential signal, the output end of the first inverter is connected to the input end of the second inverter and the first end of the first delay capacitor, the second end of the first delay capacitor is grounded through the first switch, and the output end of the second inverter outputs the delayed positive phase signal; The second digital control delay unit includes a third inverter, a fourth inverter and a second delay capacitor; the input end of the third inverter receives the negative phase signal of the input high-speed serial data differential signal, the output end of the third inverter is connected to the input end of the fourth inverter and the first end of the second delay capacitor, the second end of the second delay capacitor is grounded through the second switch, and the output end of the fourth inverter outputs the delayed negative phase signal.

4. The data eye width expansion decision feedback equalizer according to claim 3, characterized in that: The first delay capacitor and the second delay capacitor are both 8-bit capacitor arrays, the first switch and the second switch are both 8-bit switches, and the 8-bit capacitor array and the 8-bit switch control the delay between input and output by controlling the size of the first delay capacitor or the second delay capacitor.

5. The data eye width expansion decision feedback equalizer according to claim 4, characterized in that: The size of the first delay capacitor or the second delay capacitor is controlled by an 8-bit digital control word.

6. The data eye width expansion decision feedback equalizer according to claim 1, characterized in that: The data sampler includes a sense amplifier and a set-reset latch; The sense amplifier is used to amplify the input first data signal and the second data signal, and sample and hold the amplified first data signal and the second data signal through the first clock signal and the second clock signal, so as to output a set signal and a reset signal to the set-reset latch; The set-reset latch is used to receive the set signal and the reset signal output by the sense amplifier, and output logic 1 or logic 0 according to the states of the set signal and the reset signal.

7. The data eye width expansion decision feedback equalizer according to claim 6, characterized in that: The sense amplifier is an 8-channel sense amplifier, and the set-reset latch is an 8-channel set-reset latch.

8. A method for expanding the data eye width based on the data eye width expansion decision feedback equalizer according to any one of claims 1 to 7, characterized in that: include: The positive phase signal of the input high-speed serial data differential signal is delayed by the first digital control delay unit, and the output signal after the delay and the input signal before the delay are input into the OR gate logic circuit together, and the OR gate logic circuit outputs the first data signal, and the first data signal is a logic 1 width expansion signal; The negative phase signal of the input high-speed serial data differential signal is delayed by the second digital control delay unit, and the output signal after the delay and the input signal before the delay are input to the NOR gate logic circuit together, and the NOR gate logic circuit outputs a second data signal, and the second data signal is a logic 0 width extension signal; Taking the first clock signal as a reference, sampling the odd bits of the first data signal and the second data signal through a data sampler to obtain an odd bit signal of the first data signal and an odd bit signal of the second data signal; taking the second clock signal as a reference, sampling the even bits of the first data signal and the second data signal through a data sampler to obtain an even bit signal of the first data signal and an even bit signal of the second data signal; the phase difference between the first clock signal and the second clock signal is 180 degrees; Through the decision feedback circuit, the odd-numbered bit signal in the first data signal or the second data signal is used as the first output signal, and the even-numbered bit signal in the first data signal or the second data signal is used as the second output signal; the first output signal is determined to select the output logic 0 width expansion signal or the logic 1 width expansion signal according to the situation of the second output signal; the second output signal is determined to select the output logic 0 width expansion signal or the logic 1 width expansion signal according to the situation of the first output signal.

9. The data eye width expansion method according to claim 8, characterized in that: The step of using the odd-numbered bit signal in the first data signal or the second data signal as the first output signal and using the even-numbered bit signal in the first data signal or the second data signal as the second output signal through the decision feedback circuit includes: Inputting the odd-numbered bit signal of the first data signal and the odd-numbered bit signal of the second data signal to the first selector, inputting the output signal of the first selector to the data input terminal of the first D flip-flop, inputting the first clock signal to the clock input terminal of the first D flip-flop, inputting the output signal of the second D flip-flop to the enable control terminal of the first selector, and using the output signal of the first D flip-flop as the first output signal; The even-numbered bit signal of the first data signal and the even-numbered bit signal of the second data signal are input to the second selector, the output signal of the second selector is input to the data input terminal of the second D flip-flop, the second clock signal is input to the clock input terminal of the second D flip-flop, the output signal of the first D flip-flop is input to the enable control terminal of the second selector, and the output signal of the second D flip-flop is used as the second output signal.

10. The data eye width expansion method according to claim 8, characterized in that: The step of delaying the positive phase signal of the input high-speed serial data differential signal by the first digital control delay unit comprises: inputting the positive phase signal of the high-speed serial data differential signal to the input end of the first inverter, inputting the output signal of the first inverter to the input end of the second inverter and the first end of the first delay capacitor, grounding the second end of the first delay capacitor through a switch, and using the output signal of the second inverter as the delayed positive phase signal; The step of delaying the negative phase signal of the input high-speed serial data differential signal by the second digital control delay unit includes: inputting the negative phase signal of the high-speed serial data differential signal to the input end of the third inverter, inputting the output signal of the third inverter to the input end of the fourth inverter and the first end of the second delay capacitor, grounding the second end of the delay capacitor through a switch, and using the output signal of the fourth inverter as the delayed negative phase signal.

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