System and method for prototype verification of a circuit under test

Abstract

The present invention provides a system and method for prototype verification of a circuit under test. The system includes a packet generator, a perturbation circuit, the circuit under test, and a detection circuit, wherein the perturbation circuit, the circuit under test, and the detection circuit are implemented on a field programmable gate array. The packet generator outputs a plurality of standard packets, wherein each standard packet has a length that falls within a standard range. The perturbation circuit generates a plurality of perturbation packets to the circuit under test based on the plurality of standard packets, such that the circuit under test generates a plurality of output packets based on the plurality of perturbation packets, wherein any perturbation packet has a length that falls outside the standard range. The detection circuit verifies the operation of the circuit under test based on the plurality of perturbation packets and the plurality of output packets.

Description

Technical Field

[0001] This invention relates to network communication chips, and more particularly to a system and method for prototyping a circuit under test (e.g., a prototype circuit of a switch chip) using a field-programmable gate array (FPGA). Background Technology

[0002] In network communication systems, switches play a crucial role in data forwarding. Therefore, ensuring the reliability of the switch chip is a vital prerequisite for the normal operation of the entire network system. For a switch chip, the packets transmitted are generated internally, making them relatively controllable and less prone to errors; however, the packets received come from various types of external devices and cannot be controlled by internal software / hardware, thus making them more susceptible to unpredictable errors.

[0003] Conventional prototyping methods for field-programmable gate arrays (FPGAs) involve using an IXIA network tester to generate packets with lengths and gaps within corresponding standard ranges, and then sending these packets to the receive port of a prototype circuit of a switch chip (hereinafter referred to as the switch prototype circuit) to test the switch prototype circuit's packet processing capability. However, in real-world applications, switch chips may receive packets with various length or gap errors. Therefore, due to the limitations of the IXIA network tester used in conventional verification methods, it is currently impossible to confirm whether the switch chip can properly handle packets with incorrect packet formats.

[0004] Therefore, a novel method and corresponding system architecture are needed to simulate, with minimal or no side effects, various erroneous packets that a switch chip may receive (e.g., packets with incorrect lengths or incorrect packet gaps) on a field-programmable gate array, thereby improving the operational stability of the switch chip. Summary of the Invention

[0005] The purpose of this invention is to provide a system and method for prototyping a circuit under test (e.g., a prototype circuit of a switch chip) using a field-programmable gate array (FPGA) to ensure that the circuit under test can operate properly when receiving various arrangements of packets (e.g., packets with various lengths or various packet gaps).

[0006] At least one embodiment of the present invention provides a system for prototyping a field-programmable gate array (FPGA) of a circuit under test (DUT). The system includes a packet generator, a scrambling circuit, the DUT, and a detection circuit, wherein the scrambling circuit is coupled to the packet generator and the DUT, and the detection circuit is coupled to the scrambling circuit and the DUT. The packet generator is used to output one or more standard packets, each of which has a length falling within a standard range. The scrambling circuit is used to receive the one or more standard packets and generate one or more scrambled packets based on the standard packets for output to the DUT, causing the DUT to generate one or more output packets based on the scrambled packets, wherein the length of any one of the scrambled packets falls outside the standard range. The detection circuit is used to receive the one or more scrambled packets and the one or more output packets, and verify the operation of the DUT based on the one or more scrambled packets and the one or more output packets. Specifically, the scrambling circuit, the circuit under test, and the detection circuit are implemented on a field-programmable gate array.

[0007] At least one embodiment of the present invention provides a method for prototyping a circuit under test (DUT) using a field-programmable gate array (FPGA). The method includes: outputting one or more standard packets using a packet generator, wherein the length of each of the one or more standard packets falls within a standard range; receiving the one or more standard packets using a scrambling circuit, and generating one or more scrambling packets based on the one or more standard packets, wherein the length of any of the one or more scrambling packets falls outside the standard range; receiving the one or more scrambling packets using the DUT, and generating one or more output packets based on the one or more scrambling packets; and receiving the one or more scrambling packets and the one or more output packets using a detection circuit, and verifying the operation of the DUT based on the one or more scrambling packets and the one or more output packets. Furthermore, the scrambling circuit, the DUT, and the detection circuit are implemented on a field-programmable gate array (FPGA).

[0008] The system and method provided by embodiments of the present invention, by additionally configuring the scrambling circuit on the field-programmable gate array to generate scrambled packets with various lengths and packet gaps, allows for complete verification of the processing status of the switch chip when receiving various types of packets. Furthermore, embodiments of the present invention do not significantly increase additional costs. Therefore, the present invention can ensure the operational stability of the switch chip without or with minimal side effects. Attached Figure Description

[0009] Figure 1This is a schematic diagram of a system for prototyping a field-programmable gate array of a circuit under test, according to an embodiment of the present invention.

[0010] Figure 2 According to an embodiment of the present invention, a method for... Figure 1 The diagram illustrates the workflow of a method for prototyping a circuit under test using a field-programmable gate array.

[0011] Figure 3 According to an embodiment of the present invention Figure 2 An example of the workflow shown.

[0012] Figure 4A This is a schematic diagram of a portion of a workflow for length scrambling of packets according to an embodiment of the present invention.

[0013] Figure 4B This is a schematic diagram of another part of a workflow for length scrambling of packets according to an embodiment of the present invention.

[0014] Figure 4C This is a schematic diagram of another part of the workflow for length scrambling of packets according to an embodiment of the present invention.

[0015] Figure 5 This is a schematic diagram of a standard packet format according to an embodiment of the present invention.

[0016] Figure 6 This is a schematic diagram illustrating the workflow of content scrambling of the destination address field and the source address field of a standard packet according to an embodiment of the present invention.

[0017] Figure 7 This is a schematic diagram of a control scheme for a disturbance circuit operating in a certain mode according to an embodiment of the present invention. Detailed Implementation

[0018] Figure 1 This is a schematic diagram of a system 10 for prototyping a circuit under test (FPGA) 130 according to an embodiment of the present invention. The system 10 may include the FPGA 130, specifically representing a prototype circuit of a switch chip. In this embodiment, the system 10 may further include a packet generator 20 (e.g., an IXIA network test instrument), a scrambling circuit 100, a control register 110, a random number generator 120, and a detection circuit 140. The scrambling circuit 100, control register 110, random number generator 120, and detection circuit 140 may be implemented on a FPGA 50. Figure 1 As shown, the scrambling circuit 100 is coupled to the packet generator 20, the control register 110, the random number generator 120, and the circuit under test 130, and the detection circuit 140 is coupled to the scrambling circuit 100 and the circuit under test 130. Specifically, the packet generator 20 can be used to output one or more standard packets, such as the standard packet {P}. orig}, where the standard packet {P orig Each standard packet P in} orig The lengths of all packets fall within a standard range. For example, the standard packet output by the packet generator {P} orig Each standard packet P orig The length and inter-packet gap (IPG), such as the gap between any two packets, conform to a specific network communication specification. The scrambling circuit 100 can be used to receive standard packets {P}. orig}, and according to the standard packet {P orig} Generate one or more scrambling packets, such as scrambling packet {P} in} to the circuit under test 130, so that the circuit under test 130 according to the scrambling packet {P in Generate one or more output packets, such as n output packets {P} output through n ports P1, P2, ..., Pn of the circuit under test 130. out1}、{P out2}、…and {P outn}, where n is a positive integer, and the scrambling packet {P} in Any perturbing packet P of} in The length falls outside the standard range.

[0019] Figure 2 According to an embodiment of the present invention, a method for... Figure 1 The diagram illustrates the workflow of a method for prototyping a field-programmable gate array (FPGA) for the circuit under test (DUT) 130. It should be noted that... Figure 2 The workflow shown is for illustrative purposes only and is not intended to limit the invention. For example, one or more steps may be performed... Figure 2 The workflow shown has been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly if the overall result remains unchanged. Figure 2 Execute in the order shown.

[0020] In step S210, system 10 may use packet generator 20 to output one or more standard packets (e.g., standard packet {P}). orig}), wherein the length of each of the one or more standard packets falls within a standard range.

[0021] In step S220, system 10 may use scrambling circuit 100 to receive the one or more standard packets and generate one or more scrambling packets (e.g., scrambling packet {P}) based on the one or more standard packets. in}), wherein the length of any one of the one or more scrambling packets falls outside the standard range.

[0022] In step S230, the system 10 can use the circuit under test 130 to receive the one or more scrambling packets, and generate one or more output packets (e.g., output packet {P}) based on the one or more scrambling packets. out1}、{P out2}、…and {P outn}).

[0023] In step S240, the system 10 can use the detection circuit 140 to receive the one or more scrambling packets and the one or more output packets, and verify the operation of the circuit under test based on the one or more scrambling packets and the one or more output packets.

[0024] Disrupt packet {P in It may contain one or more of the following: at least one fragmented packet, at least one short packet, at least one long packet, and at least one normal packet. Specifically, the scrambling circuit 100 can scramble the standard packet {P} orig At least one standard packet P in} orig It is disassembled into multiple fragment packets, each of which is shorter than a minimum length within the standard range, and each fragment packet can be used as a scrambling packet P. in Examples. For instance, when the minimum packet length and maximum packet length defined by the specific network communication specification are 64 bits and 1518 bits respectively, the length of each fragment of the multiple fragmented packets is less than 64 bits. Additionally, the scrambling circuit 100 can scramble the standard packet {P} orig At least one standard packet P in} orig The length is reduced by one bit to produce at least one short packet, wherein the at least one short packet can serve as a scrambling packet P. in Examples. For instance, scrambling circuit 100 can scramble a standard packet P of length orig_len bits. orig Any bit in the packet is discarded to generate a short packet of length (orig_len-1) bits. Additionally, the scrambling circuit 100 can scramble the standard packet {P}. orig Multiple standard packets P in} orig The concatenation consists of at least one long packet, and the length of the at least one long packet may be greater than a maximum length within the standard range, wherein the at least one long packet may serve as a scrambling packet P. inFor example, when the minimum packet length and maximum packet length defined by the specific network communication specification are 64 bits and 1518 bits respectively, the scrambling circuit 100 can scramble a certain number or more standard packets P. orig These are concatenated into a long packet, such that the length of the long packet is greater than 1518 bits. Additionally, the scrambling circuit 100 can scramble the standard packet {P}. orig Any standard packet P in} orig Without any scrambling, it is directly output as a normal packet, which can be used as a scrambling packet P. in Examples. For instance, scrambling circuit 100 can scramble a standard packet P of length orig_len bits. orig The output is a normal packet with a length of orig_len bits.

[0025] As described above, the scrambling circuit 100 can generate different types of scrambling packets P, such as fragmented packets, short packets, long packets, and normal packets. in In this embodiment, the scrambling circuit 100 can receive a mode control signal PATTERN from the control register 110 to determine the scrambling mode to be executed by the scrambling circuit 100 based on the mode control signal PATTERN, wherein different scrambling modes can correspond to the different types of scrambling packets P mentioned above. in The permutations and combinations. For example, the mode control signal PATTERN can be a four-bit binary value (e.g., represented as 4'bxxxx). When PATTERN = 4'b0000, the scrambling circuit 100 can avoid scrambling the packet length to keep the packet length unchanged (e.g., scrambling packet P...). in The length is equal to the standard packet P origThe length of the packet is specified. When PATTERN = 4'b0001, the scrambling circuit 100 can generate a large number of fragmented packets and a small number of normal packets (e.g., the number of fragmented packets is greater than the number of normal packets). When PATTERN = 4'b0010, the scrambling circuit 100 can generate one fragmented packet followed by one normal packet. When PATTERN = 4'b0011, the scrambling circuit 100 can generate two fragmented packets followed by two normal packets. When PATTERN = 4'b0100, the scrambling circuit 100 can generate a large number of short packets and a small number of normal packets (e.g., the number of short packets is greater than the number of normal packets). When PATTERN = 4'b0101, the scrambling circuit 100 can alternately generate short packets and normal packets (e.g., each short packet is followed by a normal packet). When PATTERN = 4'b0110, the scrambling circuit 100 can generate a large number of long packets and a small number of normal packets (e.g., the number of long packets is greater than the number of normal packets). When PATTERN = 4'b0111, the scrambling circuit 100 can alternately generate long packets and normal packets (e.g., a normal packet follows each long packet). When PATTERN = 4'b1000, the scrambling circuit 100 can alternately generate long packets and short packets (e.g., a short packet follows each long packet). When PATTERN = 4'b1001, the scrambling circuit 100 can periodically generate the following packet combinations: a long packet followed by a fragmented packet or a normal packet, wherein the random number generator 120 can generate a random number to control whether a fragmented packet or a normal packet follows any long packet.

[0026] It should be noted that the details of controlling the operation mode of the scrambling circuit 100 with the pattern control signal PATTERN described above are for illustrative purposes only and are not intended to limit the invention. For example, the pattern control signal PATTERN can be a binary value of more than four bits or less than four bits. Furthermore, the arrangement of scrambling packets corresponding to each value can be varied. In addition, the length of fragmented packets and / or long packets can be controlled by random values. For example, the scrambling circuit 100 can generate multiple random numbers within a predetermined range (e.g., multiple random numbers generated by the random number generator 120 in the interval [0, 63] when the minimum packet length and maximum packet length defined by the specific network communication specification are 64 bits and 1518 bits, respectively) based on a set of random numbers within a predetermined range (e.g., multiple random numbers generated by the random number generator 120 in the interval [0, 63] when the minimum packet length and maximum packet length are 64 bits and 1518 bits, respectively). origThe packet is broken down into multiple fragment packets, with the lengths of these fragment packets corresponding to the lengths of the random numbers (e.g., the lengths of the fragment packets are randomly distributed). For example, the scrambling circuit 100 can generate at least one random number within a predetermined range (e.g., in the case where the minimum packet length and maximum packet length defined by the specific network communication specification are 64 bits and 1518 bits, respectively, at least one random number within the interval [1519, max_long_len] generated by the random number generator 120, where max_long_len can represent a positive integer greater than 1519 and can be written to at least one register in the random number generator 120) based on at least one random number within a predetermined range. orig The at least one long packet is concatenated such that the length of the at least one long packet is equal to the units digit of the at least one random number. In some embodiments, the length of the fragmented packets and / or long packets can be controlled by a fixed value. For example, the scrambling circuit 100 can concatenate the standard packet P according to a fixed number of fragmented packets in the interval [0, 63]. orig The packet is disassembled into multiple fragment packets, such that the length of each of the multiple fragment packets is equal to a fixed number of fragment packets. This fixed number can be written into at least one register within the scrambling circuit 100, but the invention is not limited thereto. For example, the scrambling circuit 100 can, based on a fixed number of long packets within the interval [1519, max_long_len], divide the corresponding number of standard packets P... orig The at least one long packet is connected in series such that the length of the at least one long packet is equal to a fixed number of long packets, wherein the fixed number of long packets can be written into at least one register in the scrambling circuit 100.

[0027] In some embodiments, the scrambling circuit 100 may scramble the standard packet P based on at least one packet gap random number within a predetermined range of packet gaps. orig The packet is broken down into multiple fragment packets such that the interval between any two adjacent fragment packets is equal to the at least one packet gap random number. For example, the random number generator 120 can generate the at least one packet gap random number within the interval [ipg_min, iPG_max] to allow the scrambling circuit 100 to divide the standard packet P according to the at least one packet gap random number. orig The packet is broken down into multiple fragment packets such that the interval between any two adjacent fragment packets is randomly distributed within the interval [ipg_min, ipg_max]. In some embodiments, the scrambling circuit 100 may scramble the standard packet P according to a fixed packet gap value. orig The fragments are broken down into multiple fragment packets, such that the interval between each group of adjacent fragment packets is equal to the fixed value of the packet gap.

[0028] In some embodiments, when the scrambling circuit 100 sends a standard packet Porig When disassembled into multiple fragment packets, the scrambling circuit 100 can disrupt the standard packet P. orig The source address is directly applied to the source address of each of the multiple fragmented packets, and the standard packet P is... orig The destination address is directly applied to the destination address of each of the plurality of fragmented packets. In some embodiments, the scrambling circuit 100 may replace the standard packet P with at least one alternative source address. orig The source address is used to determine the source address of at least one fragment packet among the plurality of fragment packets, and / or the destination address of the at least one standard packet is determined by replacing the destination address of the at least one standard packet with the alternative destination address.

[0029] Figure 3 According to an embodiment of the present invention, this invention provides a method based on the above-described disruption of operation, length disruption, and content disruption. Figure 2 The diagram shows an example of a workflow. It should be noted that... Figure 3 The workflow shown is for illustrative purposes only and is not intended to limit the invention. For example, one or more steps may be performed... Figure 3 The workflow shown has been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly if the overall result remains unchanged. Figure 3 Execute in the order shown.

[0030] In step S310, the system 10 may configure the control register 110 (e.g., set the value of the mode control signal PATTERN) to cause the scrambling circuit 100 to enter the corresponding packet scrambling mode.

[0031] In step S320, system 10 can control packet generator 20 to generate packets in the original correct format (e.g., standard packets P conforming to specific network communication specifications). orig Input disturbance circuit 100.

[0032] In step S330, system 10 can control scrambling circuit 100 to scramble packet length according to its scrambling mode (e.g., according to mode control signal PATTERN).

[0033] In step S340, system 10 can control scrambling circuit 100 to replace the contents of fragmented packets (e.g., replace standard packet P with a specific source / destination address). orig (Original source / destination address).

[0034] In step S350, system 10 can control scrambling circuit 100 to scramble packet {P} in The data is transmitted to the data receiving port of the circuit under test 130.

[0035] In step S360, system 10 can control the circuit under test 130 (e.g., the prototype circuit of a switch chip) to process packets (e.g., scrambled packets {P}). in After processing, the data is transmitted to the data transmission port (e.g., port P1, P2, ... and Pn).

[0036] In step S370, system 10 can output packets from scrambling circuit 100 (e.g., scrambling packet {P}). in}) and the packets output by the circuit under test 130 (e.g., output packets {P} output through ports P1, P2, ... and Pn respectively). out1}、{P out2}、…and {P outn The data is transmitted to the detection circuit 140 for statistical analysis to obtain the test results.

[0037] Figure 4A This is a schematic diagram of a portion of a workflow for length scrambling of packets according to an embodiment of the present invention. Figure 4B This is a schematic diagram of another part of a workflow for length scrambling of packets according to an embodiment of the present invention, and Figure 4C This is a schematic diagram of another part of a workflow for length scrambling of packets according to an embodiment of the present invention. It should be noted that... Figure 4A , Figure 4B and / or Figure 4C The workflow shown is for illustrative purposes only and is not intended to limit the invention. For example, one or more steps may be performed... Figure 4A , Figure 4B and / or Figure 4C The workflow shown has been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly if the overall result remains unchanged. Figure 4A , Figure 4B and / or Figure 4C Execute in the order shown.

[0038] Please refer to Figure 4A ,in Figure 4A Steps S400, S402, S404, S406, S408, S410, S412, S414, S416, S418 and S420 are shown below.

[0039] In step S400, packet generator 20 can generate a standard packet {P} orig} and the standard packet {P orig The signal is transmitted to the scrambling circuit 100, and the process begins.

[0040] In step S402, the scrambling circuit 100 may determine whether to send the received standard packet P based on the mode control signal PATTERN or its derivative signals. origDisruption is performed on fragmented packets. If the result is "yes", the process proceeds to step S602. If the result is "no", the process proceeds to step S404.

[0041] In step S404, the scrambling circuit 100 may determine whether to send the received standard packet P based on the mode control signal PATTERN or its derivative signals. orig The disturbance is a short packet. If the judgment result is "yes", the process proceeds to step S502. If the judgment result is "no", the process proceeds to step S406.

[0042] In step S406, the scrambling circuit 100 may determine whether to send the received standard packet P based on the mode control signal PATTERN or its derivative signals. orig The disturbance is a long packet. If the judgment result is "yes", the process proceeds to step S408. If the judgment result is "no", the process proceeds to step S414.

[0043] In step S408, the random number generator 120 can generate a random number long_len.

[0044] In step S410, the scrambling circuit 100 can determine whether a rising edge of a receive control signal rxdv has appeared. If the determination result is "yes" (indicating that the scrambling circuit 100 starts receiving and cascades multiple standard packets P), the scrambling circuit 100 can determine whether a rising edge of a receive control signal rxdv has appeared. orig The process proceeds to step S412. If the judgment result is "No" (meaning that the disruptive circuit 100 has not yet started receiving standard packets P), the process continues. orig The process returns to step S410 to perform the above judgment again.

[0045] In step S412, the scrambling circuit 100 can pull a transmission control signal txen high at the same time as the rising edge of the receiving control signal rxdv appears to indicate that the scrambling circuit 100 has started transmitting the long packet. In particular, the transmission control signal txen can be kept in the high bit position for long_len cycles and then pulled low, so that the scrambling circuit 100 can transmit a long packet with a length of long_len.

[0046] In step S414, the scrambling circuit 100 can determine whether the rising edge of the receive control signal rxdv has appeared. If the determination result is "yes" (meaning the scrambling circuit 100 starts receiving standard packets P with a length of ori_len), then... orig And the output is directly a normal packet), the process proceeds to step S416. If the judgment result is "no" (meaning that the disturbance circuit 100 has not yet started receiving standard packet P), the process continues. orig The process returns to step S414 and the above judgment is performed again.

[0047] In step S416, the scrambling circuit 100 can pull the transmission control signal txen high at the same time as the rising edge of the receiving control signal rxdv appears, so as to indicate that the scrambling circuit 100 has started transmitting the normal packet. In particular, the transmission control signal txen can be kept in the high bit quasi-ori_len for several cycles and then pulled low, so that the scrambling circuit 100 transmits a normal packet of length ori_len.

[0048] In step S418, the scrambling circuit S418 can determine whether the length scrambling operation has ended based on the mode control signal PATTERN or its derivative signals. If the determination result is "yes", the process proceeds to step S420. If the determination result is "no", the process proceeds to step S402.

[0049] Please refer to Figure 4B ,in Figure 4B Steps S502, S504, S506, S508, S510, S512 and S514 are shown below.

[0050] In step S502, the random number generator 120 can generate a random number drop_index.

[0051] In step S504, the scrambling circuit 100 can determine whether the rising edge of the receive control signal rxdv has appeared. If the determination result is "yes" (meaning the scrambling circuit 100 starts receiving standard packets P with a length of ori_len), then... orig The process proceeds to step S506. If the judgment result is "No" (meaning that the disruptive circuit 100 has not yet started receiving standard packet P), the process continues. orig The process returns to step S504 and the above judgment is performed again.

[0052] In step S506, the scrambling circuit 100 can maintain the transmission control signal txen at a low level (e.g., "0") for one cycle after the rising edge of the received control signal rxdv appears, and transmit a one-bit packet gap on the data line. Figure 4B (abbreviated as "IPG" in Chinese), and the data of the original packet (e.g., standard packet P) orig The data is stored in a first-in, first-out (FIFO) temporary register. Figure 4B (abbreviated as "FIFO" in Chinese).

[0053] In step S508, the scrambling circuit 100 can determine whether the current index value index is equal to drop_index (in Figure 4B(The text is labeled "index == drop_index?" for brevity). If the result is "yes" (meaning the data corresponding to the current index value is the bit data to be discarded), the process proceeds to step S512. If the result is "no" (meaning the data corresponding to the current index value is not the bit data to be discarded), the process proceeds to step S510.

[0054] In step S510, the scrambling circuit 100 can read the next data.

[0055] In step S512, the scrambling circuit 100 can skip the next data (that is, discard and not read the bit data corresponding to the current index value index), and then read the next data after the next data.

[0056] In step S514, the scrambling circuit 100 can continue to read the remaining data in the first-in-first-out register until the number of clock cycles in which the transmission control signal txen is continuously pulled high reaches (ori_len-1), so that the scrambling circuit 100 outputs a short packet with a length of (ori_len-1) bits.

[0057] Please refer to Figure 4C ,in Figure 4C Steps S602, S604, S606, S608, S610, S612, S614 and S616 are shown below.

[0058] In step S602, the scrambling circuit 100 can determine whether the packet length is a random number based on the pattern control signal PATTERN or its derivative signals. If the determination result is "yes", the process proceeds to step S604. If the determination result is "no", the process proceeds to step S606.

[0059] In step S604, the random number generator 120 can generate a random number frag_len.

[0060] In step S606, the scrambling circuit 100 can determine whether the currently generated fragment packet is the first fragment packet. If the determination result is "yes", the process proceeds to step S608. If the determination result is "no", the process proceeds to step S612.

[0061] In step S608, the scrambling circuit 100 can determine whether the rising edge of the receive control signal rxdv has appeared. If the determination result is "yes" (indicating that the scrambling circuit 100 has started receiving the standard packet P), then... orig (And by disassembling and running to generate fragment packets), the process proceeds to step S610. If the judgment result is "No" (indicating that the disruptive circuit 100 has not yet started receiving standard packets P), the process continues. orig The process returns to step S608 to perform the above judgment again.

[0062] In step S610, the scrambling circuit 100 can pull the transmission control signal txen high at the same time as the rising edge of the receiving control signal rxdv appears to indicate that the scrambling circuit 100 has started transmitting the fragment packet. In particular, the transmission control signal txen can be kept high for frag_len cycles and then pulled low, so that the scrambling circuit 100 transmits a fragment packet of length frag_len.

[0063] In step S612, the scrambling circuit 100 can determine the packet gap based on the mode control signal PATTERN or its derivative signals (in Figure 4C The process checks whether the length of the packet gap (IPG) is random. If the result is "yes", the process proceeds to step S614. If the result is "no", the scrambling circuit 100 uses a preset value as the packet gap length.

[0064] In step S614, the random number generator 120 can generate a random number ipg_len to allow the scrambling circuit to use the random number ipg_len as the packet gap length.

[0065] In step S616, the scrambling circuit 100 can send packet gaps.

[0066] Figure 5 A standard packet P according to an embodiment of the present invention orig A diagram illustrating packet format 700. (See diagram below.) Figure 5 As shown, standard packet P orig The packet format 700 may include multiple fields such as a destination address field (DMAC), a source address field (SMAC), multiple tag fields such as CPUTAG, OTAG, and ITAG, a length field (LENGTH), a data field (DATA), and a check field (FCS). In some embodiments, the scrambling circuitry 100 may target standard packet P. orig The DMAC field of the destination address and the SMAC field of the source address are scrambled.

[0067] Specifically, embodiments of the present invention aim to test whether a prototype circuit of a switch chip can identify the addresses of all scrambled packets. However, since fragmented packets are obtained by disassembling standard packets P... orig Therefore, most fragmented packets do not contain their own address information, but are obtained by copying the original packet (e.g., a standard packet P). orig The fragment information is obtained. For fragment packets that do not contain their own address information but whose length meets the condition, the scrambling circuit 100 can perform content scrambling, such as... Figure 6 As shown. Figure 6 According to an embodiment of the present invention, this invention is aimed at standard packet P.orig This is a diagram illustrating the workflow of content perturbation using the Destination Address Field (DMAC) and the Source Address Field (SMAC). It should be noted that... Figure 6 The workflow shown is for illustrative purposes only and is not intended to limit the invention. For example, one or more steps may be performed... Figure 6 The workflow shown has been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly if the overall result remains unchanged. Figure 6 Execute in the order shown.

[0068] In step S810, the scrambling circuit 100 can obtain fragment packets through length scrambling.

[0069] In step S820, the scrambling circuit 100 can determine whether the length of the fragment packet is greater than a predetermined number of bits (e.g., the total number of bits of the destination address field DMAC and the source address field SMAC, such as 12 bits). If the determination result is "yes" (meaning that this fragment packet has a complete destination address field DMAC and source address field SMAC), the process proceeds to step S830. If the determination result is "no" (meaning that this fragment packet does not have a complete destination address field DMAC and source address field SMAC and therefore cannot perform address substitution), the process proceeds to step S850.

[0070] In step S830, the scrambling circuit 100 can replace the content corresponding to the index value in the fragment packet within the range [0,5] (e.g., the content of the first to sixth bits) with DMAC_replace (e.g., replacing the content of the first to sixth bits). Figure 5 The destination address field shown is replaced with DMAC_replace.

[0071] In step S840, the scrambling circuit 100 can replace the content corresponding to the index value in the fragment packet within the range [6,11] (e.g., the content from the seventh to the twelfth bit) with SMAC_replace (e.g., replacing the content from the seventh bit to the twelfth bit). Figure 5 The destination address field SMAC shown is replaced with SMAC_replace.

[0072] In step S850, the scrambling circuit 100 has ended the above-mentioned content scrambling process for the destination address field DMAC and the source address field SMAC.

[0073] In addition, to ensure that the switch chip does not malfunction when receiving packets that are truncated exactly after the tag field, the scrambling circuit 100 can generate scrambled packets P containing only the destination address field DMAC, the source address field SMAC, and the tag fields CPUTAG, OTAG, and ITAG. inThe circuit under test (DUT) 130 is then consulted to determine whether it can properly handle such situations. For example, the mode control signal PATTERN can be configured to 4'b0001, and the scrambling circuit 100 is controlled to use the total length (e.g., 28 bits) of the destination address field DMAC, the source address field SMAC, and the tag fields CPUTAG, OTAG, and ITAG as the fixed length of the fragment packet (e.g., frag_len is fixed to 28), so that the fragment packet generated by the scrambling circuit 100 only contains the destination address field DMAC, the source address field SMAC, and the tag fields CPUTAG, OTAG, and ITAG.

[0074] In some embodiments, the detection circuit 140 can target the scrambling packet {P} output by the scrambling circuit 100. in} Perform statistics to obtain at least one first statistical result, and for the output packet {P} of the detection circuit 140. out1}、{P out2}、…and {P outn} Perform statistics to obtain at least one second statistical result, wherein the detection circuit 140 can compare the at least one first statistical result and the at least one second statistical result to verify whether they match, in order to verify the operation of the circuit under test 130 (e.g., packet processing / forwarding operation of a prototype switch chip).

[0075] For the scrambling packet {P} output by scrambling circuit 100 in The detection circuit 140 can count the total number of packets D_total_cnt whose source address is the input port of the circuit under test 130, whose destination address is within the range of the output port of the circuit under test 130 (e.g., P1 to Pn), whose packet length conforms to a specific network communication specification, whose checksum (e.g., the content of the FCS field) is correct, and / or whose packet gap length before the packet conforms to a specific network communication specification. Furthermore, the detection circuit 140 can count the number of packets D_P_cnt(k) corresponding to each port for the destination address, where k is any integer in the interval [1, n]. For the output packets {P} of the circuit under test 130... out1}、{P out2}、…and {P outnThe test circuit 140 can perform corresponding statistical operations to obtain the total number of packets S_total_cnt for all ports and the number of packets S_P_cnt(k) corresponding to each port. Therefore, the total number of packets D_total_cnt and the number of packets D_P_cnt(k) corresponding to each port can be used as an expected statistical result (e.g., the first statistical result mentioned above), while the total number of packets S_total_cnt and the number of packets S_P_cnt(k) corresponding to each port can be used as an actual statistical result (e.g., the second statistical result mentioned above). The detection circuit 140 can compare the expected statistical result with the actual statistical result (e.g., determine whether D_total_cnt equals S_total_cnt and D_P_cnt(k) equals S_P_cnt(k)) to determine whether the circuit under test 130 (e.g., the prototype circuit of the switch chip) can correctly handle various types of disruptive packets.

[0076] Figure 7 This is a schematic diagram of a control scheme when the mode control signal PATTERN is set to 4'b0110 according to an embodiment of the present invention. Specifically, in this mode, the scrambling circuit 100 can generate a large number of long packets and a small number of normal packets, wherein the number of long packets and normal packets can be controlled by random numbers generated by the random number generator 120. For example, the random number generator 120 can generate a random number long_len in the interval [1519, max_long_len], a random number ipg_len for packet gaps in the interval [ipg_min, ipg_max], a random number long_num_lot for long packets in the interval [32, 255], and a random number good_num_few for normal packets in the interval [1, 31].

[0077] When the scrambling circuit 100 detects that PATTERN equals 4'b0110, the scrambling circuit 100 can transition from the idle state (IDLE) to the long packet state (GEN_LONG). Upon detecting the rising edge of the receive control signal rxdv, the scrambling circuit 100 can pull the transmit control signal txen high and start timing to generate a timing result len_cnt, where len_cnt represents the number of cycles of the transmit control signal txen at the high level. When the timing result len_cnt reaches long_len, the scrambling circuit 100 can pull the transmit control signal txen low. During this period, the data output by the scrambling circuit 100 is the same as that of the original packet (e.g., a standard packet P). orig The sequence remains unchanged. At this point, a long packet of length long_len has been sent, and the long packet count result long_cnt has been incremented to 1.

[0078] After the transmission control signal txen is pulled low, the scrambling circuit 100 can start timing to generate a timing result ipg_cnt. When the timing result ipg_cnt equals the random number of packet gaps ipg_len, a packet gap of length ipg_len has been transmitted.

[0079] The scrambling circuit 100 can determine whether the long packet count result `long_cnt` has reached the long packet random number `long_num_lot`. If the long packet count result `long_cnt` is not equal to the long packet random number `long_num_lot`, it indicates that the long packet transmission operation has not yet ended, and the scrambling circuit 100 can continue to send long packets, while the random number generator can generate new random numbers to update `long_len` (making the length of each long packet randomly distributed). If the long packet count result `long_cnt` is equal to the long packet random number `long_num_lot`, it indicates that the specified number of long packets has been sent, and the scrambling circuit 100 can transition from the long packet state `GEN_LONG` to the normal packet state `GEN_GOOD` to begin sending normal packets.

[0080] In the normal packet state GEN_GOOD, when the scrambling circuit 100 detects the rising edge of the receive control signal rxdv, it can pull the transmit control signal txen high and start timing to generate a timing result len_cnt. When the timing result len_cnt reaches a preset value good_len, the scrambling circuit 100 can pull the transmit control signal txen low. During this period, the data output by the scrambling circuit 100 is different from the original packet (e.g., standard packet P). orig The sequence remains unchanged. At this point, a normal packet of length good_len has been sent, and the normal packet count result good_cnt has been incremented to 1.

[0081] The scrambling circuit 100 can determine whether the normal packet count result good_cnt has reached the normal packet random number good_num_few. If the normal packet count result good_cnt is not equal to the normal packet random number good_num_few, it means that the normal packet sending operation has not yet ended, and the scrambling circuit 100 can continue to send normal packets. If the normal packet count result good_cnt is equal to the normal packet random number good_num_few, it means that the specified number of normal packets has been sent, and the scrambling circuit 100 can enter the long packet state GEN_LONG from the normal packet state GEN_GOOD to start sending long packets.

[0082] As described above, the scrambling circuit 100 can continuously switch between the long packet state GEN_LONG and the normal packet state GEN_GOOD during operation in this mode until the scrambling operation ends. For example, when the scrambling circuit 100 detects that the mode control signal PATTERN has been switched to another value such as 4'b0000, the scrambling circuit 100 can return to the idle state.

[0083] In summary, the systems and methods provided by embodiments of the present invention can scramble original packets (e.g., compliant packets) using scrambling circuitry to generate various permutations and combinations of scrambled packets. This allows for field-programmable gate array prototyping of the switch chip prototype circuitry before switch chip manufacturing, ensuring that the switch chip will not malfunction in real-world applications due to encountering non-compliant packets. Furthermore, embodiments of the present invention do not significantly increase additional costs. Therefore, the present invention solves the problems of related technologies with little or no side effects.

[0084] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

[0085] [Symbol Explanation]

[0086] 10: System

[0087] 20: Packet Generator

[0088] 50: Field-programmable gate array

[0089] 100: Disruption of circuit

[0090] 110: Control Register

[0091] 120: Random Number Generator

[0092] 130: Circuit under test

[0093] 140: Detection Circuit

[0094] P orig Standard Packet

[0095] P in Disrupt packets

[0096] P out1 ,P out2 ,P outn Output packets

[0097] P1, P2, Pn: Ports

[0098] PATTERN: Mode control signal

[0099] S210~S240: Steps

[0100] S310~S370: Steps

[0101] S400~S420: Steps

[0102] S502~S514: Steps

[0103] S602~S616: Steps

[0104] 700: Packet Format

[0105] DMAC,SMAC,CPUTAG,OTAG,ITAG,LENGTH,DATA,FCS:field

[0106] S810~S850: Steps

[0107] IDLE, GEN_LONG, GEN_GOOD: Status

[0108] long_cnt, good_cnt: Counting results

[0109] long_num_lot: Random number in a long packet

[0110] good_num_few: Normal packet random number.

Claims

1. A system for prototyping a field-programmable gate array (FPGA) for a circuit under test, wherein, The system includes the circuit under test, and the system also includes: A packet generator is used to output one or more standard packets, wherein the length of each of the one or more standard packets falls within a standard range; A scrambling circuit, coupled to the packet generator and the circuit under test (DUT), is configured to receive the one or more standard packets and generate one or more scrambled packets based on the one or more standard packets for output to the DUT, so that the DUT generates one or more output packets based on the one or more scrambled packets, wherein the length of any one of the one or more scrambled packets falls outside the standard range; and A detection circuit, coupled to the scrambling circuit and the circuit under test, is used to receive one or more scrambling packets and one or more output packets, and to verify the operation of the circuit under test based on the one or more scrambling packets and one or more output packets; The scrambling circuit, the circuit under test, and the detection circuit are implemented on a field-programmable gate array.

2. The system according to claim 1, wherein, The scrambling circuit breaks down at least one of the one or more standard packets into multiple fragment packets, each of which is less than a minimum length within the standard range, and the one or more scrambling packets contain the multiple fragment packets.

3. The system according to claim 2, wherein, The scrambling circuit determines the source address of at least one fragment packet among the plurality of fragment packets by replacing the source address of the at least one standard packet with at least one substitute source address, or determines the destination address of at least one fragment packet among the plurality of fragment packets by replacing the destination address of the at least one standard packet with at least one substitute destination address.

4. The system according to claim 2, wherein, The scrambling circuit breaks down at least one standard packet into multiple fragment packets based on a plurality of random numbers within a predetermined range, such that the lengths of the multiple fragment packets are the plurality of random numbers respectively.

5. The system according to claim 2, wherein, The scrambling circuit breaks down at least one standard packet into multiple fragment packets according to a fixed number, such that the length of each of the multiple fragment packets is equal to the fixed number. Each of the one or more standard packets includes a destination address field, a source address field, multiple tag fields, a length field, a data field, and a check field. The total length of the destination address field, the source address field, and the multiple tag fields is equal to a predetermined number of bits. The scrambling circuit sets the fixed number to the predetermined number of bits so that at least one of the multiple fragment packets contains only the destination address field, the source address field, and the multiple tag fields.

6. The system according to claim 2, wherein, The scrambling circuit breaks down at least one standard packet into multiple fragment packets based on at least one random number within a predetermined range, such that the interval between any two adjacent fragment packets is equal to the at least one random number.

7. The system according to claim 1, wherein, The scrambling circuit reduces the length of at least one of the one or more standard packets by one bit to produce at least one short packet, and the one or more scrambling packets contain the at least one short packet.

8. The system according to claim 1, wherein, The scrambling circuit concatenates multiple standard packets from one or more standard packets into at least one long packet, the length of which is greater than a maximum length within the standard range, and the one or more scrambling packets contain the at least one long packet.

9. The system according to claim 1, wherein, The one or more scrambling packets include at least two of at least one fragmented packet, at least one short packet, at least one long packet, and at least one normal packet, wherein the length of the at least one fragmented packet is less than a minimum length within the standard range, the length of the at least one short packet is equal to the length of at least one of the one or more standard packets minus one bit, and the at least one normal packet is equal to any one of the one or more standard packets.

10. A method for prototyping a circuit under test using a field-programmable gate array, comprising: Use a packet generator to output one or more standard packets, where, The length of each of the one or more standard packets falls within a standard range; The one or more standard packets are received using a scrambling circuit, and one or more scrambling packets are generated based on the one or more standard packets, wherein the length of any one or more scrambling packets falls outside the standard range; The circuit under test receives one or more scrambling packets and generates one or more output packets based on the one or more scrambling packets. as well as A detection circuit is used to receive one or more scrambling packets and one or more output packets, and the operation of the circuit under test is verified based on the one or more scrambling packets and one or more output packets. The scrambling circuit, the circuit under test, and the detection circuit are implemented on a field-programmable gate array.

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