Semiconductor integrated circuit device and manufacturing method thereof
By designing an alternately stacked multi-layer bottom electrode structure in a semiconductor integrated circuit device and covering the resistive layer on its side surface, the problem of device reliability and conductive filament formation voltage in the prior art is solved, and higher stability and lower formation voltage are achieved.
Patent Information
- Application Number
- CN202411829472.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-12
- Publication Date
- 2025-03-14
AI Technical Summary
During the manufacturing process of the existing resistive random access memory, dry etching is prone to cause damage areas on the side walls of the resistive layer, resulting in device reliability problems. Under the demand for miniaturization, the adjustment space of the resistive region is limited, making it difficult to reduce the conductive filament formation voltage.
A semiconductor integrated circuit device is designed, wherein the bottom electrode is formed of a multi-layer structure in which at least two electrode materials alternate longitudinally, with a resistive layer covering the side surface of the bottom electrode and a top electrode covering the side surface of the resistive layer. With this structure, the number of stacked layers of the bottom electrode is increased, the area of the resistance change region is increased, and the formation voltage of the conductive filament is reduced.
It effectively improves the stability of device performance, reduces the formation voltage of conductive filaments, and simplifies the manufacturing process, avoiding damage areas caused by etching.
Smart Images
Figure CN119630001A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the semiconductor field, and in particular to a semiconductor integrated circuit device and a method for manufacturing the same. Background Art
[0002] The basic structure of resistance random access memory (RRAM) includes a bottom electrode, a resistance switching layer and a top electrode, which is usually a planar stacked sandwich structure, in which the area of the resistance switching region is basically equal to the planar area of the resistance random access memory, and the area of the resistance switching region is negatively correlated with the forming voltage of the conductive filaments. If the forming voltage needs to be adjusted, the size of the resistance random access memory must be adjusted in structure. However, the current demand for semiconductor devices tends to be miniaturized, resulting in very limited adjustment space for the resistance switching region, and it is not possible to reduce the forming voltage of the conductive filaments well.
[0003] In addition, during the manufacturing process of the planar resistive random access memory, dry etching easily produces a damaged area on the side wall of the resistive layer. The damaged area is a component of the resistive region and is prone to forming defects, causing reliability problems of the device. Summary of the invention
[0004] The present disclosure provides a semiconductor integrated circuit device and a method for manufacturing the same, so as to at least solve the above technical problems existing in the prior art.
[0005] According to a first aspect of the present disclosure, there is provided a semiconductor integrated circuit device, comprising a resistive switching layer, and a bottom electrode and a top electrode respectively located on two sides of the resistive switching layer and facing each other;
[0006] The bottom electrode comprises at least two bottom electrode layers formed by at least two electrode materials alternately in the longitudinal direction, and the bottom electrode layers formed by different electrode materials have different lateral dimensions;
[0007] The resistive switching layer conformally covers the side surface of the bottom electrode, and the top electrode conformally covers the side surface of the resistive switching layer.
[0008] In one embodiment, the etching rates of the at least two electrode materials are different.
[0009] In one possible implementation, the lowest bottom electrode layer of the at least two bottom electrode layers is formed of a specific electrode material, and an etching rate of the specific electrode material is greater than an etching rate of other electrode materials of the at least two electrode materials.
[0010] In one possible implementation, the semiconductor integrated circuit device further includes: an oxide-grabbing layer located between the bottom electrode and the resistive layer, or between the resistive layer and the top electrode.
[0011] In one possible embodiment, the semiconductor integrated circuit device also includes: an insulating layer located above the bottom electrode, the resistive layer also includes a portion that conformally covers the side surface of the insulating layer, and the upper surface of the insulating layer is flush with the upper surface of the resistive layer and the upper surface of the top electrode.
[0012] According to a second aspect of the present disclosure, there is provided a method for manufacturing a semiconductor integrated circuit device, the method comprising:
[0013] forming a bottom electrode on a substrate, wherein the bottom electrode comprises at least two bottom electrode layers formed by at least two electrode materials alternately in the longitudinal direction, and the bottom electrode layers formed by different electrode materials have different lateral dimensions;
[0014] A resistive switching layer is formed on a side surface of the bottom electrode, and a top electrode is formed on a side surface of the resistive switching layer, so that the bottom electrode and the top electrode are opposite to each other.
[0015] In one possible implementation manner, forming a bottom electrode on the substrate includes:
[0016] At least two bottom electrode layers are obtained by alternately depositing at least two electrode materials on a substrate layer by layer;
[0017] Depositing an insulating material on the at least two bottom electrode layers to form an insulating layer;
[0018] Etching holes in the at least two bottom electrode layers and the insulating layer to expose side surfaces of the at least two bottom electrode layers of each semiconductor integrated circuit device;
[0019] The at least two bottom electrode layers are etched to remove exposed portions of the at least two bottom electrode layers, so that the bottom electrode layers formed of different materials have different lateral dimensions, thereby obtaining the bottom electrode.
[0020] In one embodiment, forming a resistive switching layer on a side surface of the bottom electrode and forming a top electrode on a side surface of the resistive switching layer comprises:
[0021] Depositing a resistive switching layer material and a top electrode material on the bottom electrode and the insulating layer in sequence to form a resistive switching layer that fully covers the bottom electrode and the insulating layer, and a top electrode that fully covers the resistive switching layer;
[0022] The resistive layer material and the top electrode material above the insulating layer are removed to retain the portion of the resistive layer conformally covering the side surfaces of the bottom electrode and the insulating layer, and the portion of the top electrode conformally covering the side surface of the resistive layer.
[0023] In one possible implementation manner, after removing the resistive layer material and the top electrode material above the insulating layer, the method further comprises:
[0024] The tops of the insulating layer, the resistive layer and the top electrode are planarized so that the upper surface of the insulating layer is flush with the upper surface of the resistive layer and the upper surface of the top electrode.
[0025] In one possible implementation, the method further includes: forming an oxide capture layer between the bottom electrode and the resistive layer, or between the resistive layer and the top electrode.
[0026] The present invention discloses a semiconductor integrated circuit device and a manufacturing method thereof, wherein the semiconductor integrated circuit device comprises a resistive switching layer, and a bottom electrode and a top electrode respectively located on both sides of the resistive switching layer and opposite to each other, wherein the bottom electrode comprises at least two bottom electrode layers formed by at least two electrode materials alternately in the longitudinal direction, and the bottom electrode layers of different materials have different lateral dimensions; the resistive switching layer covers the side surface of the bottom electrode in a conformal manner; and the top electrode covers the side surface of the resistive switching layer in a conformal manner. Since the area of the resistive switching region is negatively correlated with the formation voltage, the resistive switching layer is covered on the side surface of the alternately stacked bottom electrode layer to form a vertical resistive switching region. By increasing the number of stacked layers of the bottom electrode, the area of the resistive switching region can be greatly increased, and the formation voltage of the conductive filament can be effectively reduced. The lateral dimensions of the bottom electrode layers of different electrode materials are different. By combining different electrode materials, the lateral dimensions of part of the bottom electrode layer can be broken through the limitation of the plane area of the resistive random access memory while maintaining the stability of the device structure, thereby further increasing the area of the resistive switching region. In addition, since the resistive switching region is located on the side wall of the resistive switching layer, it is formed by deposition, has not been etched, and there is no damaged area caused by etching, so the stability of the device performance can be effectively improved. The manufacturing process of the semiconductor integrated circuit device disclosed in the present invention is simple, and no additional photomask is required, thus simplifying the manufacturing process.
[0027] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which:
[0029] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.
[0030] Figure 1A schematic cross-sectional structure diagram of a semiconductor integrated circuit device according to an embodiment of the present disclosure is shown;
[0031] Figure 2 A schematic cross-sectional structure diagram of a semiconductor integrated circuit device according to another embodiment of the present disclosure is shown;
[0032] Figure 3 Shows Figure 2 The cross-sectional structure diagram of a certain stage in the manufacturing process of the semiconductor integrated circuit device of the embodiment shown;
[0033] Figure 4 Shows Figure 2 The cross-sectional structure diagram of a certain stage in the manufacturing process of the semiconductor integrated circuit device of the embodiment shown;
[0034] Figure 5 Shows Figure 2 The cross-sectional structure diagram of a certain stage in the manufacturing process of the semiconductor integrated circuit device of the embodiment shown;
[0035] Figure 6 Shows Figure 2 The cross-sectional structure diagram of a certain stage in the manufacturing process of the semiconductor integrated circuit device of the embodiment shown;
[0036] Figure 7 Shows Figure 2 The cross-sectional structure diagram of a certain stage in the manufacturing process of the semiconductor integrated circuit device of the embodiment shown;
[0037] Figure 8 Shows Figure 2 The illustrated embodiment is a schematic cross-sectional structure diagram of a certain stage in the manufacturing process of a semiconductor integrated circuit device. DETAILED DESCRIPTION
[0038] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.
[0039] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor integrated circuit device, such as Figure 1As shown, it includes a resistive layer 103, and a bottom electrode 102 and a top electrode 104 respectively located on both sides of the resistive layer 103 and opposite to each other, the bottom electrode 102 includes at least two bottom electrode layers formed by longitudinally alternating at least two electrode materials, such as a bottom electrode layer 201 and a bottom electrode layer 202, and the bottom electrode layers formed by different electrode materials have different lateral sizes; the resistive layer 103 conformally covers the side surface of the bottom electrode 102; the top electrode 104 conformally covers the side surface of the resistive layer 103.
[0040] The resistive switching layer may be made of one or more resistive switching materials. Commonly used resistive switching materials include transition metal oxides (TMOs) such as aluminum oxide (AlxOy), copper oxide (CuxOy), and hafnium oxide (HfxOy).
[0041] The bottom electrode and the top electrode may be made of any electrode material used to manufacture electrodes, including one or more of aluminum (Al), copper (Cu), gold (Au), platinum (Pt), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W) and tungsten nitride (WN). The thickness of the bottom electrode layer formed by different materials may be the same or different, and the present disclosure does not limit this. The number of layers of the bottom electrode can be reasonably set according to factors such as the size of the semiconductor integrated circuit device and the thickness of the bottom electrode layer, and the present disclosure does not limit this.
[0042] The resistive switching layer conformally covers the side surface of the bottom electrode, so that the area of the resistive switching region is substantially equal to the sum of the side areas of each bottom electrode layer. Therefore, by increasing the number of stacked layers of the bottom electrode, the area of the resistive switching region per unit space can be greatly increased, thereby effectively reducing the voltage for forming the conductive filaments. Moreover, since the resistive switching region is located on the side wall of the resistive switching layer and is formed by deposition without being etched, and there is no damaged area caused by etching, the stability of the device performance can be effectively improved.
[0043] In addition, in the disclosed embodiment, at least two electrode materials have different etching rates. Under the same conditions, the greater the etching rate of the material, the smaller the lateral size of the bottom electrode layer after etching. Therefore, the etching rate difference of the bottom electrode material can be utilized to uniformly etch after alternately depositing all the bottom electrode layers, thereby obtaining bottom electrode layers with different lateral sizes, simplifying the manufacturing process.
[0044] Preferably, the bottom electrode layer of the at least two bottom electrode layers is formed of a specific electrode material, and the etching rate of the specific electrode material is greater than the etching rate of the other electrode materials of the at least two electrode materials. Figure 1The material of the bottom electrode layer 201 can be titanium nitride (TiN), and the material of the bottom electrode layer 202 is tungsten (W). The etching rate of titanium nitride is usually greater than the etching rate of tungsten. Therefore, after etching under the same conditions, the lateral size of the bottom electrode layer 201 is smaller than the bottom electrode layer formed by other materials, such as the lateral size of the bottom electrode layer 202. The area of the resistive region is equal to the sum of the lateral areas of each bottom electrode layer, and is closely related to the perimeter of the cross section of the bottom electrode layer and the height of the bottom electrode layer. Therefore, when the lateral size of the bottommost bottom electrode layer 201 reaches the maximum limit of the planar area of the resistive random access memory, by stacking a bottom electrode layer 202 with a larger lateral size in height, the maximum limit of the planar area of the resistive random access memory can be broken through, and the area of the resistive region can be further increased.
[0045] In the disclosed embodiment, the bottom electrode may be an alternately stacked cylinder, whose cross section may be circular or elliptical, and the outer side of the bottom electrode is surrounded by a circular ring formed by the resistive switching layer and the top electrode; the bottom electrode may also be an alternately stacked cube, whose cross section is square or rectangular, and the outer side of the bottom electrode is surrounded by a square ring formed by the resistive switching layer and the top electrode. In theory, the cross section of the bottom electrode may be any suitable shape.
[0046] In another embodiment of the present disclosure, the semiconductor integrated circuit device further includes: an oxide-grabbing layer 105 located between the bottom electrode 102 and the resistive layer 103 , or located between the resistive layer 103 and the top electrode 104 .
[0047] Figure 2 The grabbing layer 105 is shown to be located between the bottom electrode 102 and the resistive layer 103. The grabbing layer 105 can also be arranged between the resistive layer 103 and the top electrode 104, and the present invention does not limit this. The material of the grabbing layer mainly includes metals such as titanium (Ti), hafnium (Hf), zirconium (Zr), and unsaturated metal oxides such as titanium oxide (TixOy) and hafnium oxide (HfxOy). The grabbing layer is used to capture oxygen in the resistive layer to form oxygen vacancies, and is a gain structure that makes the storage unit perform better.
[0048] In the embodiments of the present disclosure, Figure 2 As shown, the semiconductor integrated circuit device also includes: an insulating layer 106 located above the bottom electrode, and the resistive layer 103 also includes a portion that conformally covers the side surface of the insulating layer 106, that is, the resistive layer 103 conformally covers the side surfaces of the insulating layer 106 and the bottom electrode 102, and the upper surface of the insulating layer 106 is flush with the upper surface of the resistive layer 103 and the upper surface of the top electrode 104.
[0049] It should be understood that the bottom electrode is electrically connected to the first metal layer below the semiconductor device through the through hole of the substrate, and the top electrode is electrically connected to the second metal layer above the semiconductor device. By providing an insulating layer above the bottom electrode, the bottom electrode and the second metal layer can be effectively isolated to avoid short circuit after power is applied.
[0050] The insulating layer can be made of one or more insulating materials, such as nitride and oxide.
[0051] In another embodiment of the present disclosure, the semiconductor integrated circuit device may not include an insulating layer located above the bottom electrode. In this case, the upper surface of the bottom electrode is flush with the upper surface of the resistive layer and the upper surface of the top electrode, and the electrical connection between the top electrode and the second metal layer can be achieved through a through hole or a wire groove that only contacts the upper surface of the top electrode.
[0052] According to a second aspect of the embodiments of the present disclosure, a method for manufacturing a semiconductor integrated circuit device is provided, comprising: forming a bottom electrode on a substrate, the bottom electrode comprising at least two bottom electrode layers formed by at least two electrode materials alternately in the longitudinal direction, and the bottom electrode layers formed by different electrode materials have different lateral dimensions; forming a resistive switching layer on the side surface of the bottom electrode, and forming a top electrode on the side surface of the resistive switching layer so that the bottom electrode and the top electrode are opposite to each other. The method is used to manufacture Figure 1 or Figure 2 The semiconductor integrated circuit device shown.
[0053] According to an implementation mode of an embodiment of the present disclosure, a bottom electrode is formed on a substrate, including: alternately depositing at least two electrode materials layer by layer on the substrate to obtain at least two bottom electrode layers; depositing an insulating material on top of the at least two bottom electrode layers to form an insulating layer; etching holes in the at least two bottom electrode layers and the insulating layer to expose the side surfaces of the at least two bottom electrode layers of each semiconductor integrated circuit device; etching the at least two bottom electrode layers to remove the exposed portions of the at least two bottom electrode layers, so that the bottom electrode layers formed of different materials have different lateral dimensions, thereby obtaining the bottom electrode.
[0054] When at least two electrode materials are alternately deposited layer by layer on the substrate to obtain at least two bottom electrode layers, any applicable deposition process may be used, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD), etc. When the bottom electrode is etched to remove the exposed portions of the at least two bottom electrode layers, wet etching or dry etching may be used.
[0055] According to one embodiment of the present disclosure, a resistive layer is formed on the side surface of the bottom electrode, and a top electrode is formed on the side surface of the resistive layer, including: depositing a resistive layer material and a top electrode material on the bottom electrode and the insulating layer in sequence so that the resistive layer fully covers the bottom electrode and the insulating layer, and the top electrode fully covers the resistive layer; removing the resistive material and the top electrode material above the insulating layer to retain a portion of the resistive layer that conformally covers the side surfaces of the bottom electrode and the insulating layer, and a portion of the top electrode that conformally covers the side surfaces of the resistive layer.
[0056] The deposition process may be any applicable deposition process, such as atomic layer deposition. Any applicable process, such as an anisotropic etching process, may be used to remove the redundant resistive layer material and the top electrode material.
[0057] According to one embodiment of the present disclosure, after removing the resistive layer material and the top electrode material above the insulating layer, the method further includes: flattening the top of the insulating layer, the resistive layer and the top electrode so that the upper surface of the insulating layer is flush with the upper surface of the resistive layer and the upper surface of the top electrode.
[0058] The planarization process may use any applicable planarization process, preferably a chemical mechanical polishing (CMP) process.
[0059] In another embodiment of the present disclosure, the semiconductor integrated circuit device may not include an insulating layer, that is, after forming the resistive switching layer and the top electrode of the full coverage structure, the insulating layer material, the resistive switching layer material and the top electrode material above the bottom electrode are removed to retain the portion of the resistive switching layer that conformally covers the side surface of the bottom electrode, and the portion of the top electrode that conformally covers the side surface of the resistive switching layer; the top of the bottom electrode, the resistive switching layer and the top electrode are flattened to make the upper surface of the bottom electrode flush with the upper surface of the resistive switching layer and the upper surface of the top electrode. It should be understood that in order to achieve normal electrical connection and avoid short circuit after power-on, a dielectric layer can be deposited to cover the resistive switching structure, and a through hole or a wire groove can be etched in the dielectric layer above the top electrode so that the top electrode can be electrically connected through the through hole or the wire groove.
[0060] According to one embodiment of the present disclosure, the method further includes: forming a gripping oxide layer between the bottom electrode and the resistive layer, or between the resistive layer and the top electrode. Before depositing the resistive layer material, the gripping oxide layer material may be deposited on the bottom electrode to form the gripping oxide layer between the bottom electrode and the resistive layer; or, after depositing the resistive layer material and before depositing the top electrode material, the gripping oxide layer material may be deposited on the resistive layer to form the gripping oxide layer between the resistive layer and the top electrode. The gripping oxide layer material mainly includes metals such as titanium (Ti), hafnium (Hf), zirconium (Zr), and unsaturated metal oxides such as titanium oxide (TixOy) and hafnium oxide (HfxOy).
[0061] Combine the following Figures 3 to 8 describe Figure 2 The manufacturing process of the semiconductor integrated circuit device shown in FIG. 1 is as follows: the through hole 101 on the substrate 100 is planarized to obtain a Figure 3 The structure shown in the figure, then execute the following steps:
[0062] S1: at least two electrode materials are alternately deposited layer by layer on the substrate 100 to form a bottom electrode 102 including at least two bottom electrode layers (for example, a bottom electrode layer 201 and a bottom electrode layer 202), and an insulating material is deposited on the bottom electrode 102 to form an insulating layer 106, so as to obtain Figure 4 The structure shown;
[0063] S2: Etching holes in the bottom electrode 102 and the insulating layer 106 to isolate and expose the side surface of the bottom electrode 102 of each semiconductor integrated circuit device, and obtaining Figure 5 The structure shown;
[0064] S3: Etching the bottom electrode 102 by wet etching or dry etching to remove the exposed portions of at least two bottom electrode layers 201 and 202, and making use of the etching rate difference of different electrode materials to make the bottom electrode layers formed by different electrode materials have different lateral dimensions, so as to obtain Figure 6 The structure shown;
[0065] S4: depositing an oxygen-grabbing layer material, a resistive switching layer material and a top electrode material on the bottom electrode 102 and the insulating layer 106 in sequence, and forming an oxygen-grabbing layer 105, a resistive switching layer 103 and a top electrode 104 with a full coverage structure in sequence, Figure 7 The structure shown;
[0066] In step S4, the resistive switching layer material, the oxygen-grabbing layer material and the top electrode material may also be deposited in sequence to sequentially form the resistive switching layer, the oxygen-grabbing layer and the top electrode of the full-coverage structure.
[0067] S5: removing the redundant oxide-grabbing layer, the resistive switching layer and the top electrode by an anisotropic etching process, wherein the redundant oxide-grabbing layer, the resistive switching layer and the top electrode include a planar portion located above the insulating layer and a connecting portion between two adjacent semiconductor integrated circuit devices on the substrate;
[0068] S6: Use chemical mechanical polishing to planarize the top of the insulating layer 106, the resistive layer 103 and the top electrode 104, so that the upper surface of the insulating layer 106 is flush with the upper surface of the resistive layer 103 and the upper surface of the top electrode 104, and the following is obtained: Figure 8 The structure shown.
[0069] The advantages of the manufacturing method provided by the present disclosure include but are not limited to: utilizing the etching rate difference of different electrode materials to perform a single etching to obtain a bottom electrode layer with different lateral dimensions, thereby simplifying the manufacturing process and saving costs; the resistive region in the resistive layer is formed by deposition and does not include a damaged region formed by etching, which is beneficial to providing stability in device performance; the manufacturing method provided by the present disclosure has a simple process, does not generate additional masks, and is easy to implement, etc.
[0070] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.
[0071] The foregoing description is intended to enable any person skilled in the art to implement and use the present disclosure, and is provided in the context of a specific application and its requirements. In addition, the foregoing description of the embodiments of the present disclosure is given for the purpose of illustration and description only. They are not intended to be exhaustive or to limit the present disclosure to the disclosed form. Therefore, many modifications and variations will be apparent to practitioners skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the essence and scope of the present disclosure. In addition, the discussion of the foregoing embodiments is not intended to limit the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments shown, but will be given the widest scope consistent with the principles and features disclosed herein.
Claims
1. A semiconductor integrated circuit device, comprising a resistive switching layer, and a bottom electrode and a top electrode respectively located on two sides of the resistive switching layer and opposite to each other, characterized in that: The bottom electrode comprises at least two bottom electrode layers formed by at least two electrode materials alternately in the longitudinal direction, and the bottom electrode layers formed by different electrode materials have different lateral dimensions; The resistive switching layer conformally covers the side surface of the bottom electrode, and the top electrode conformally covers the side surface of the resistive switching layer.
2. The semiconductor integrated circuit device according to claim 1, wherein: The at least two electrode materials have different etching rates.
3. The semiconductor integrated circuit device according to claim 2, wherein: The lowermost bottom electrode layer of the at least two bottom electrode layers is formed of a specific electrode material, and an etching rate of the specific electrode material is greater than an etching rate of other electrode materials of the at least two electrode materials.
4. The semiconductor integrated circuit device according to claim 1, wherein: The semiconductor integrated circuit device further comprises: An oxide-grabbing layer is located between the bottom electrode and the resistive layer, or between the resistive layer and the top electrode.
5. The semiconductor integrated circuit device according to claim 1, wherein: The semiconductor integrated circuit device further comprises: An insulating layer is located above the bottom electrode, the resistive layer further comprising a portion conformally covering a side surface of the insulating layer, and an upper surface of the insulating layer is flush with an upper surface of the resistive layer and an upper surface of the top electrode.
6. A method for manufacturing a semiconductor integrated circuit device, characterized in that: The method comprises: forming a bottom electrode on a substrate, wherein the bottom electrode comprises at least two bottom electrode layers formed by at least two electrode materials alternately in the longitudinal direction, and the bottom electrode layers formed by different electrode materials have different lateral dimensions; A resistive switching layer is formed on a side surface of the bottom electrode, and a top electrode is formed on a side surface of the resistive switching layer, so that the bottom electrode and the top electrode are opposite to each other.
7. The method according to claim 6, characterized in that The step of forming a bottom electrode on the substrate comprises: At least two bottom electrode layers are obtained by alternately depositing at least two electrode materials on a substrate layer by layer; Depositing an insulating material on the at least two bottom electrode layers to form an insulating layer; Etching holes in the at least two bottom electrode layers and the insulating layer to expose side surfaces of the at least two bottom electrode layers of each semiconductor integrated circuit device; The at least two bottom electrode layers are etched to remove exposed portions of the at least two bottom electrode layers, so that the bottom electrode layers formed of different materials have different lateral dimensions, thereby obtaining the bottom electrode.
8. The method according to claim 7, characterized in that The step of forming a resistive switching layer on the side surface of the bottom electrode and forming a top electrode on the side surface of the resistive switching layer comprises: Depositing a resistive switching layer material and a top electrode material on the bottom electrode and the insulating layer in sequence, so that the resistive switching layer completely covers the bottom electrode and the insulating layer, and the top electrode completely covers the resistive switching layer; The resistive material and the top electrode material above the insulating layer are removed to retain the portion of the resistive layer conformally covering the side surfaces of the bottom electrode and the insulating layer, and the portion of the top electrode conformally covering the side surface of the resistive layer.
9. The method according to claim 8, characterized in that After removing the resistive layer material and the top electrode material above the insulating layer, the method further comprises: The tops of the insulating layer, the resistive layer and the top electrode are planarized so that the upper surface of the insulating layer is flush with the upper surface of the resistive layer and the upper surface of the top electrode.
10. The method according to claim 6, characterized in that The method further comprises: An oxide capture layer is formed between the bottom electrode and the resistive layer, or between the resistive layer and the top electrode.