Semiconductor discharge tube, manufacturing method thereof and overvoltage protection device

Abstract

The invention discloses a semiconductor discharge tube, a manufacturing method thereof and an overvoltage protection device. The semiconductor discharge tube comprises two doping structures and a substrate with a first conduction type, the first side of the substrate and the second side of the substrate are respectively provided with a doping structure; wherein the first side of the substrate is opposite to the second side of the substrate; the doped structure comprises a first doped region with a second conductive type, a second doped region with the second conductive type and at least one third doped region with the first conductive type; the second doped region is located in the first doped region, and the concentration of doped ions in the second doped region is far greater than the concentration of doped ions in the first doped region; the third doped region is located in the second doped region. According to the semiconductor discharge tube, the manufacturing method thereof and the overvoltage protection device, the voltage resistance of the semiconductor discharge tube can be improved, and the voltage locking range of the semiconductor discharge tube can be expanded.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor discharge tube and a manufacturing method thereof, and an overvoltage protection device. Background Art

[0002] Thyristor surge suppressor (TSS) is a switch type protection device made using the thyristor principle. As an important protection device, TSS can not only absorb the induced voltage generated by lightning and power on and off, but also absorb the overvoltage caused by accidental contact or erroneous operation between high voltage lines and signal lines.

[0003] However, existing semiconductor discharge tubes have problems such as low overall withstand voltage performance. Summary of the invention

[0004] The present invention provides a semiconductor discharge tube and a manufacturing method thereof, and an overvoltage protection device, which can improve the withstand voltage performance of the semiconductor discharge tube and also expand the range of the locking voltage of the semiconductor discharge tube.

[0005] According to one aspect of the present invention, a semiconductor discharge tube is provided, the semiconductor discharge tube comprising: two doping structures and a substrate having a first conductivity type;

[0006] The doping structure is disposed on the first side of the substrate and the second side of the substrate respectively; wherein the first side of the substrate and the second side of the substrate are disposed opposite to each other;

[0007] The doping structure includes a first doping region having a second conductivity type, a second doping region having the second conductivity type, and at least one third doping region having the first conductivity type;

[0008] The second doping region is located in the first doping region, and the concentration of doping ions in the second doping region is much greater than the concentration of doping ions in the first doping region;

[0009] The third doping region is located in the second doping region.

[0010] Optionally, the thickness of the substrate ranges from 150 μm to 450 μm;

[0011] The first distance ranges from 20μm to 30μm; the second distance ranges from 15μm to 25μm, and the second distance is smaller than the first distance; the third distance ranges from 30μm to 50μm; wherein, the first distance is the distance from the surface of the first doping region close to the substrate to the surface of the second doping region close to the substrate in the same doping structure; the second distance is the distance from the surface of the second doping region close to the substrate to the surface of the third doping region close to the substrate in the same doping structure; the third distance is the distance from the boundary of the vertical projection of the first doping region on the substrate to the boundary of the vertical projection of the second doping region on the substrate in the same doping structure.

[0012] Optionally, the doping structure further includes a doping ring having a first conductivity type;

[0013] The doping ring surrounds the first doping region;

[0014] The vertical projection of the first doped region on the substrate covers the inner boundary of the vertical projection of the doped ring on the substrate, wherein the inner boundary of the vertical projection of the doped ring on the substrate is the boundary closest to the second doped region among all boundaries of the vertical projection of the doped ring on the substrate.

[0015] Optionally, the concentration of the doping ions in the doping ring is in the range of 1Ω*cm to 3Ω*cm.

[0016] Optionally, the semiconductor discharge tube provided in this embodiment further includes two passivation layers;

[0017] The passivation layer is disposed on one side of the two doped rings away from the substrate;

[0018] Each of the passivation layers comprises a first passivation sublayer, a second passivation sublayer and a third passivation sublayer; the first passivation sublayer is located on a side of the doped ring away from the substrate; the second passivation sublayer is located on a side of the first passivation sublayer away from the substrate; the third passivation sublayer is located on a side of the second passivation sublayer away from the first passivation sublayer;

[0019] The material of the first passivation sublayer includes tetraethoxysilane, the material of the second passivation sublayer includes semi-insulating polysilicon; and the material of the third passivation sublayer includes silicon dioxide.

[0020] Optionally, the doping structure includes at least three third doping regions distributed at intervals.

[0021] Optionally, the semiconductor discharge tube provided in this embodiment further includes two metal layers; a metal layer is provided on a side of the third doping region in the two doping structures away from the substrate.

[0022] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

[0023] According to another aspect of the present invention, a method for manufacturing a semiconductor discharge tube is provided, the method comprising:

[0024] forming a substrate having a first conductivity type;

[0025] A doping structure is formed on the first side of the substrate and the second side of the substrate respectively; wherein the first side of the substrate is arranged opposite to the second side of the substrate; the doping structure includes a first doping region with a second conductivity type, a second doping region with the second conductivity type and at least one third doping region with the first conductivity type; the second doping region is located in the first doping region, and the concentration of doping ions in the second doping region is much greater than the concentration of doping ions in the first doping region; the third doping region is located in the second doping region.

[0026] According to another aspect of the present invention, an overvoltage protection device is provided. The overvoltage protection device includes the semiconductor discharge tube provided by any embodiment of the present invention.

[0027] An embodiment of the present invention provides a semiconductor discharge tube, which includes a two-layer doping structure and a substrate with a first conductivity type. A doping structure is provided on the first side of the substrate and the second side of the substrate. The doping structure includes a first doping region with a second conductivity type, a second doping region with a second conductivity type, and at least one third doping region with a first conductivity type. The second doping region is located in the first doping region, and the third doping region is located in the second doping region. In this embodiment, the concentration of doping ions in the second doping region is also set to be much greater than the concentration of doping ions in the first doping region. This setting increases the ion concentration in the short base region, so that the lightning resistance of the semiconductor discharge tube is enhanced, and the range of the locking voltage is also expanded. In summary, the semiconductor discharge tube provided in this embodiment can improve the withstand voltage performance of the semiconductor discharge tube, and can also expand the range of the locking voltage of the semiconductor discharge tube.

[0028] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 is a schematic structural diagram of a semiconductor discharge tube provided according to an embodiment of the present invention;

[0031] Figure 2 is a schematic structural diagram of another semiconductor discharge tube provided according to an embodiment of the present invention;

[0032] Figure 3 It is a schematic flow chart of a method for manufacturing a semiconductor discharge tube according to an embodiment of the present invention;

[0033] Figure 4 is a schematic structural diagram of another semiconductor discharge tube provided according to an embodiment of the present invention;

[0034] Figure 5 is a schematic structural diagram of an overvoltage protection device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] Figure 1is a schematic diagram of the structure of a semiconductor discharge tube provided according to an embodiment of the present invention, with reference to Figure 1 The semiconductor discharge tube provided in this embodiment includes two doping structures 120 and a substrate 110 with a first conductivity type; a doping structure 120 is respectively arranged on the first side of the substrate 110 and the second side of the substrate 110; wherein the first side of the substrate 110 and the second side of the substrate 110 are arranged opposite to each other; the doping structure 120 includes a first doping region 121 with a second conductivity type, a second doping region 122 with a second conductivity type and at least one third doping region 123 with a first conductivity type; the second doping region 122 is located in the first doping region 121, and the concentration of doping ions in the second doping region 122 is much greater than the concentration of doping ions in the first doping region 121; the third doping region 123 is located in the second doping region 122.

[0038] Specifically, the electrical properties of the first conductivity type and the second conductivity type are opposite. When the first conductivity type is N-type, the substrate 110 is an N-type substrate, which can be formed by doping a proper amount of pentavalent elements such as arsenic, phosphorus, and antimony in a pure intrinsic semiconductor such as germanium or silicon. When the first conductivity type is P-type, the substrate 110 is a P-type substrate, which can be formed by doping a proper amount of trivalent elements such as boron, indium, and gallium in a pure intrinsic semiconductor such as germanium or silicon.

[0039] The semiconductor discharge tube may include one third doping region 123, or may include a plurality of third doping regions 123 distributed at intervals. The third doping region 123 is an emission region of the semiconductor discharge tube.

[0040] The first doping region 121 and the second doping region 122 together constitute a short base region of the semiconductor discharge tube. The doping structure 120 is disposed on both the first side and the second side of the substrate 110. It can be seen that the semiconductor discharge tube provided in this embodiment is a double-base region semiconductor discharge tube. The doping structure 120 located on the first side of the substrate 110 can be symmetrical with the doping structure 120 located on the second side of the substrate 110.

[0041] The vertical projection of the first doping region 121 on the substrate 110 may cover the vertical projection of the second doping region 122 on the substrate 110, and the boundary of the first doping region 121 may not overlap with the boundary of the second doping region 122. The vertical projection of the second doping region 122 on the substrate 110 may cover the vertical projection of the third doping region 123 on the substrate 110.

[0042] The ions doped in the third doping region 123 may be the same type of ions as the ions doped in the substrate 110 , and the concentration of the doped ions in the third doping region 123 may be greater than the concentration of the doped ions in the substrate 110 .

[0043] The ions doped in the second doping region 122 can be the same ions as the ions doped in the first doping region 121. In this embodiment, the second doping region 122 is set in the first doping region 121, and the concentration of the doped ions in the second doping region 122 is much greater than the concentration of the doped ions in the first doping region 121, which can avoid the ion concentration in the short base region being weak and affecting the lightning resistance, and at the same time avoid the voltage failure caused by the excessive concentration distribution gradient in the short base region caused by the high voltage adjustment. The inventor has found that the semiconductor discharge tube provided in this embodiment can enhance the lightning resistance by 10% to 20% compared with the existing semiconductor discharge tube, and the range of the locking voltage can be expanded by 2% to 5%. It can be seen that the semiconductor discharge tube provided in this embodiment can improve the voltage resistance performance of the semiconductor discharge tube.

[0044] The present embodiment provides a semiconductor discharge tube, which includes a two-layer doping structure and a substrate with a first conductivity type. A doping structure is provided on the first side of the substrate and the second side of the substrate. The doping structure includes a first doping region with a second conductivity type, a second doping region with a second conductivity type, and at least one third doping region with a first conductivity type. The second doping region is located in the first doping region, and the third doping region is located in the second doping region. The present embodiment also sets the concentration of doping ions in the second doping region to be much greater than the concentration of doping ions in the first doping region, so that the ion concentration in the short base region is increased, so that the lightning resistance of the semiconductor discharge tube is enhanced, and the range of the locking voltage is also expanded. In summary, the semiconductor discharge tube provided in the present embodiment can improve the withstand voltage performance of the semiconductor discharge tube, and can also expand the range of the locking voltage of the semiconductor discharge tube.

[0045] Optional, continue to refer to Figure 1 , the thickness of the substrate 110 ranges from 150μm to 450μm; the first distance a ranges from 20μm to 30μm; the second distance b ranges from 15μm to 25μm, and the second distance b is smaller than the first distance a; the third distance c ranges from 30μm to 50μm; wherein, the first distance a is the distance from the surface of the first doping region 121 in the same doping structure 120 close to the substrate 110 to the surface of the second doping region 122 in the same doping structure 120 close to the substrate 110 to the surface of the third doping region 123 in the same doping structure 120 close to the substrate 110; the third distance c is the distance from the boundary of the vertical projection of the first doping region 121 on the substrate 110 to the boundary of the vertical projection of the second doping region 122 on the substrate 110 in the same doping structure 120.

[0046] Specifically, the thickness of the substrate 110 may be understood as the distance d between the surfaces of the two first doping regions 121 in the two doping structures 120 that are close to the substrate 110 .

[0047] The thickness of the substrate 110 is set to be in the range of 150μm to 450μm, the first distance a is in the range of 20μm to 30μm, the second distance b is in the range of 15μm to 25μm, and the second distance b is smaller than the first distance a, and the third distance c is in the range of 30μm to 50μm, which can further improve the withstand voltage performance of the semiconductor discharge tube.

[0048] Optional, Figure 2 is a schematic diagram of the structure of another semiconductor discharge tube provided according to an embodiment of the present invention, with reference to Figure 2 The doping structure also includes a doping ring 124 having a first conductivity type; the doping ring 124 surrounds the first doping region 121; the vertical projection of the first doping region 121 on the substrate 110 covers the inner boundary S1 of the vertical projection of the doping ring 124 on the substrate 110, wherein the inner boundary S1 of the vertical projection of the doping ring 124 on the substrate 110 is the boundary closest to the second doping region 122 among all boundaries of the vertical projection of the doping ring 124 on the substrate 110.

[0049] Specifically, the ions doped in the doping ring 124 may be the same ions as the ions doped in the substrate 110, and the concentration of the doping ions in the doping ring 124 is greater than the concentration of the ions doped in the substrate 110. The outer boundary of the doping ring 124 may coincide with the boundary of the substrate 110. The doping ring 124 may be manufactured simultaneously with the third doping region 123, and may be manufactured using the same manufacturing process. The vertical projection of the first doping region 121 on the substrate 110 covers the inner boundary S1 of the vertical projection of the doping ring 124 on the substrate 110, indicating that the vertical projection of the first doping region 121 on the substrate 110 partially coincides with the vertical projection of the doping ring 124 on the substrate 110. In this embodiment, the doping ring 124 of the first conductivity type is provided in the doping structure, which can prevent the semiconductor discharge tube from failing due to contamination, that is, to prevent the external ions from reacting with the ions in the semiconductor discharge tube, and to prevent the ions of the second conductivity type from entering the semiconductor discharge tube and causing the PN junction to be turned on.

[0050] Optionally, the concentration of the doping ions in the doping ring is in the range of 1Ω*cm to 3Ω*cm.

[0051] Specifically, the doping ions in the doping ring may be phosphorus ions, and the concentration of the phosphorus ions is in the range of 1Ω*cm to 3Ω*cm. Setting the concentration of the doping ions in the doping ring to be in the range of 1Ω*cm to 3Ω*cm can avoid the doping ions from reacting with the base region of the semiconductor discharge tube due to too low a concentration, and can also avoid increasing the process difficulty due to too high a doping concentration.

[0052] Optional, continue to refer to Figure 2The semiconductor discharge tube provided in this embodiment also includes two passivation layers 130; a passivation layer 130 is provided on the side of the two doped rings 124 away from the substrate 110; each passivation layer 130 includes a first passivation sublayer 131, a second passivation sublayer 132 and a third passivation sublayer 133; the first passivation sublayer 131 is located on the side of the doped ring 124 away from the substrate 110; the second passivation sublayer 132 is located on the side of the first passivation sublayer 131 away from the substrate 110; the third passivation sublayer 133 is located on the side of the second passivation sublayer 132 away from the first passivation sublayer 131; the material of the first passivation sublayer 131 includes tetraethoxysilane (TEOS), the material of the second passivation sublayer 132 includes semi-insulating polycrystalline silicon (SIPOS); the material of the third passivation sublayer 133 includes silicon dioxide (SIO2).

[0053] Specifically, the vertical projection of the passivation layer 130 on the substrate 110 completely covers the vertical projection of the doped ring 124 on the substrate 110, and can also cover a partial vertical projection of the first doped region 121 on the substrate 110, a partial vertical projection of the second doped region 122 on the substrate 110, and a partial vertical projection of the third doped region 123 on the substrate 110.

[0054] In this embodiment, the first passivation sublayer 131, the second passivation sublayer 132 and the third passivation sublayer 133 are sequentially arranged on the side of the doped ring 124 away from the substrate 110, which can improve the passivation ability of the passivation layer 130, thereby improving the problem that the semiconductor discharge tube is prone to failure due to weak passivation ability. The first passivation sublayer 131 in the passivation layer 130 is closest to the doped ring 124. The material of the first passivation sublayer 131 includes tetraethoxysilane, which can improve the compactness of the first passivation sublayer 131, thereby improving the anti-oxidation and anti-corrosion ability of the first passivation sublayer 131. The material of the second passivation sublayer 132 includes semi-insulating polycrystalline silicon, which can improve the blocking rate of the second passivation sublayer 132 to block ions from diffusing into the substrate 110. The material of the third passivation sublayer 133 includes silicon dioxide, which can improve the protection ability of the third passivation sublayer 133 to the second passivation sublayer 132, and can also improve the insulation ability of the third passivation sublayer 133 and the metal layer in the semiconductor discharge tube.

[0055] Optional, continue to refer to Figure 2 The doping structure includes at least three third doping regions 123 distributed at intervals.

[0056] Specifically, the second doping region 122 is located between two adjacent third doping regions 123. The doping structure includes at least three third doping regions 123 that are spaced apart from each other, which can further improve the lightning resistance of the semiconductor discharge tube.

[0057] Optional, continue to refer to Figure 2The semiconductor discharge tube provided in this embodiment further includes two metal layers 140 ; ​​the metal layer 140 is disposed on the side of the third doping region 123 in the two doping structures away from the substrate 110 .

[0058] Specifically, the metal layer 140 is adjacent to and connected to the corresponding third doping region 123, and the vertical projection of the metal layer 140 on the substrate 110 in the same doping structure covers the vertical projection of each third doping region 123 on the substrate 110. The metal layer 140 is an electrode of the semiconductor discharge tube. The material of the metal layer 140 may include four metals: aluminum, titanium, nickel and silver. The boundary of the metal layer 140 may be seamlessly adjacent to the passivation layer 130.

[0059] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

[0060] Specifically, when the first conductivity type is N type and the second conductivity type is P type, the first conductivity type is electron type and the second conductivity type is hole type. When the first conductivity type is P type and the second conductivity type is N type, the first conductivity type is hole type and the second conductivity type is electron type.

[0061] Figure 3 is a flow chart of a method for manufacturing a semiconductor discharge tube according to an embodiment of the present invention, with reference to Figure 3 The method for manufacturing a semiconductor discharge tube provided in this embodiment comprises the following steps:

[0062] S110 , forming a substrate having a first conductivity type.

[0063] S120. A doping structure is formed on the first side of the substrate and the second side of the substrate respectively; wherein the first side of the substrate and the second side of the substrate are arranged opposite to each other; the doping structure includes a first doping region with a second conductivity type, a second doping region with the second conductivity type and at least one third doping region with the first conductivity type; the second doping region is located in the first doping region, and the concentration of doping ions in the second doping region is much greater than the concentration of doping ions in the first doping region; the third doping region is located in the second doping region.

[0064] This embodiment provides a method for manufacturing a semiconductor discharge tube. The semiconductor discharge tube manufactured by the manufacturing method can improve the voltage resistance performance of the semiconductor discharge tube and can also expand the range of the locking voltage of the semiconductor discharge tube.

[0065] Next, this embodiment will introduce in detail another method for manufacturing a semiconductor discharge tube. The method can be used to manufacture a semiconductor discharge tube. Figure 4 The semiconductor discharge tube shown in the figure, the manufacturing method comprises the following steps:

[0066] S210 , selecting an N-type silicon wafer with a resistivity of 2Ω*cm to 30Ω*cm as the N-type substrate 210 .

[0067] Specifically, the N-type substrate 210 with a resistivity of 2Ω*cm to 30Ω*cm can improve the withstand voltage performance of the semiconductor discharge tube.

[0068] S220 , preparing a P-doped pattern region 221 and a P+ doped pattern region 222 on both sides of the N-type substrate 210 .

[0069] Specifically, preparing the P-doped pattern region 221 and the P+ doped pattern region 222 includes the following steps:

[0070] S221, growing an oxide layer on the surface of the N-type substrate 210. Further, at 1100° C. to 1200° C., a first set value of oxygen and a second set value of hydrogen are charged for a first set time to grow an oxide layer, and the thickness of the oxide layer ranges from 2 μm to 3 μm. The first set value may be 4 L, the second set value may be 2 L, and the first set time may be 15 hours.

[0071] S222 , patterning the oxide layer, and forming a P-doped pattern region 221 on the surface of the N-type substrate 210 .

[0072] Specifically, the P-doped pattern region 221 is of regional type and the doping ions may be boron. Further, boron pre-diffusion is performed first: using B 30 (Boron source) Liquid source, at the first set temperature for the second set time, while ventilating N: 5L~10L and O2: 100mL~400mL, the P-doped pattern area 221 is regional type and the block resistance is 30Ω*cm~70Ω*cm. Then perform boron re-expansion: at 1250℃~1270℃ for 6H~10H, fill with nitrogen: 5L-10L and oxygen: 4-6L during boron re-expansion, so that the P-junction depth of the regional doping structure is 30μm-50μm, and the oxide layer thickness is 1μm-2μm. Among them, the first set temperature can be 900℃, and the second set time can be 60min.

[0073] S223, patterning the oxide layer above the P-doped pattern area 221, forming a P+ doped pattern area 222 above the P-doped pattern area 221. The P+ doped pattern area 222 is regionally doped with boron, and the distance between the boundary of the vertical projection of the P+ doped pattern area 222 on the N-type substrate 210 and the boundary of the vertical projection of the P-doped pattern area 221 on the N-type substrate 210 is 30μm-50μm. The P+ doped pattern area 222 is formed by: firstly performing boron pre-expansion: using B 20(Boron source) liquid source, at the second set temperature for the third set time, while ventilating N: 5-10L O2: 100-400mL, the P+ doping pattern area 222 is regional type and the square resistance is 5-10Ω*cm. Then perform boron re-expansion: at 1250℃-1270℃ for the fourth set time, nitrogen: 5-10L and oxygen: 4-6L are filled during boron re-expansion, so that the P+ junction depth of the regional doping structure is 20μm-30μm, and the oxide layer thickness is 1-2um. Among them, B 20 The boron concentration is greater than B 30 The second set temperature may be 1100° C., the third set time may be 80 min, and the fourth set time may be 5 h.

[0074] In this embodiment, a P-doped pattern area 221 and a P+ doped pattern area 222 are formed on both sides of an N-type substrate 210 by processes such as photolithography and diffusion, and the boron ion concentration in the P+ doped pattern area 222 is much greater than the boron ion concentration in the P-doped pattern area 221 of the short base area, and the side of the P+ doped pattern area 222 is at a certain distance from the side of the P-doped pattern area 221, so that the withstand voltage of the P-doped pattern area 221 can be adjusted, while meeting the high concentration requirements of the short base area. Compared with the short base area formed by P- in the prior art, the withstand voltage of the P-doped pattern area 221 in this embodiment is stronger and can improve the breakdown voltage of the high-voltage discharge tube. The vertical projection of the P-doped pattern area 221 on the N-type substrate 210 covers the vertical projection of the P+ doped pattern area 222 on the N-type substrate 210.

[0075] S230 : forming at least three N-type emission patterns 223 in the P+ doping pattern region 222 and distributing a layer of N phosphorus ring region 224 around the P− doping pattern region 221 .

[0076] Specifically, the N-type emission pattern 223 uses phosphorus oxychloride (POCL3) for phosphorus diffusion. The formation of the N-type emission pattern 223 specifically includes: first, pre-expansion of phosphorus: diffuse at 1100°C-1200°C for the fifth set time, and then diffuse at 1150°C-1200°C for 100min-200min to form an N-type emission pattern 223 with a thickness of 10μm-15μm. Among them, the fifth set time can be 80min. The N-type emission pattern 223 can be made at the same time as the N phosphorus ring area 224, and made using the same manufacturing method.

[0077] S240, using a dry etching process to remove the entire oxide layer. TEOS oxide layer 231, semi-insulating polysilicon 232, and LTO oxide layer 233 are sequentially deposited on the entire surface to form a passivation protection layer 230, which can extend from the edge of the N-type substrate 210 to the side of the N-type emission pattern 223 away from the N-type substrate 210.

[0078] In the present embodiment, an N-type emission pattern 223 is provided above the P+ doped pattern area 222, and an N-phosphorus ring area 224 is distributed around the P-doped pattern area 221 to avoid failure due to contamination, and three passivation layers are distributed above the N-phosphorus ring area 224 to avoid failure due to weak passivation ability and improve product reliability.

[0079] S250, depositing metal material on the side of the N-type emission pattern 223 away from the N-type substrate 210 to form a metal transition layer, and patterning to form a metal electrode 240. The metal transition layer includes a four-layer structure of aluminum / titanium / nickel / silver, with an aluminum thickness of 1 um and a titanium thickness of The thickness of nickel is The thickness of silver is Finally, the alloy is subjected to a furnace temperature of 350 to 530°C and a working time of 10 to 30 minutes.

[0080] S260, test the manufactured semiconductor discharge tube, and after passing the test, carry out the processes of film pasting, knife wheel dicing and vacuum packaging in sequence.

[0081] The manufacturing method of the semiconductor discharge tube provided in this embodiment has corresponding beneficial effects with the semiconductor discharge tube provided in any embodiment of the present invention. For technical details not described in detail in this embodiment, please refer to a semiconductor discharge tube provided in any embodiment of the present invention.

[0082] The embodiment of the present invention also provides an overvoltage protection device. Figure 5 is a schematic diagram of the structure of an overvoltage protection device provided according to an embodiment of the present invention, with reference to Figure 5 The overvoltage protection device includes the semiconductor discharge tube 100 provided by any embodiment of the present invention.

[0083] Specifically, the overvoltage protection device further includes a power supply 200 and a circuit to be protected 300, wherein the two output terminals of the power supply 200 are electrically connected to the two input terminals of the circuit to be protected 300, respectively, and the two electrodes of the semiconductor discharge tube 100 are electrically connected to the two input terminals of the circuit to be protected 300, respectively. The power supply 200 may be an AC power supply or a DC power supply. During normal operation, the semiconductor discharge tube 100 is cut off, and the power supply 200 can supply power to the circuit to be protected 300 normally. When an overvoltage such as a lightning strike or surge interference occurs on the two output terminals of the power supply 200, the semiconductor discharge tube 100 will be turned on to discharge the surge current and surge voltage to prevent the circuit to be protected from being damaged by the overvoltage.

[0084] The overvoltage protection device provided by the embodiment of the present invention includes the semiconductor discharge tube in any embodiment of the present invention. Therefore, the overvoltage protection device provided by the embodiment of the present invention also has the beneficial effects described in any embodiment of the present invention, which will not be described in detail here.

[0085] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0086] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor discharge tube, characterized in that: include: two doping structures and a substrate having a first conductivity type; The doping structure is disposed on the first side of the substrate and the second side of the substrate respectively; wherein the first side of the substrate and the second side of the substrate are disposed opposite to each other; The doping structure includes a first doping region having a second conductivity type, a second doping region having the second conductivity type, and at least one third doping region having the first conductivity type; The second doping region is located in the first doping region, and the concentration of doping ions in the second doping region is much greater than the concentration of doping ions in the first doping region; The third doping region is located in the second doping region.

2. The semiconductor discharge tube according to claim 1, characterized in that: The thickness of the substrate ranges from 150 μm to 450 μm; The first distance ranges from 20μm to 30μm; the second distance ranges from 15μm to 25μm, and the second distance is smaller than the first distance; the third distance ranges from 30μm to 50μm; wherein, the first distance is the distance from the surface of the first doping region close to the substrate to the surface of the second doping region close to the substrate in the same doping structure; the second distance is the distance from the surface of the second doping region close to the substrate to the surface of the third doping region close to the substrate in the same doping structure; the third distance is the distance from the boundary of the vertical projection of the first doping region on the substrate to the boundary of the vertical projection of the second doping region on the substrate in the same doping structure.

3. The semiconductor discharge tube according to claim 1, characterized in that: The doping structure further includes a doping ring having a first conductivity type; The doping ring surrounds the first doping region; The vertical projection of the first doped region on the substrate covers the inner boundary of the vertical projection of the doped ring on the substrate, wherein the inner boundary of the vertical projection of the doped ring on the substrate is the boundary closest to the second doped region among all boundaries of the vertical projection of the doped ring on the substrate.

4. The semiconductor discharge tube according to claim 3, characterized in that: The concentration of the doping ions in the doping ring is in the range of 1Ω*cm to 3Ω*cm.

5. The semiconductor discharge tube according to claim 3, characterized in that: Also included are two passivation layers; The passivation layer is disposed on one side of the two doped rings away from the substrate; Each of the passivation layers comprises a first passivation sublayer, a second passivation sublayer and a third passivation sublayer; the first passivation sublayer is located on a side of the doped ring away from the substrate; the second passivation sublayer is located on a side of the first passivation sublayer away from the substrate; the third passivation sublayer is located on a side of the second passivation sublayer away from the first passivation sublayer; The material of the first passivation sublayer includes tetraethoxysilane, the material of the second passivation sublayer includes semi-insulating polysilicon; and the material of the third passivation sublayer includes silicon dioxide.

6. The semiconductor discharge tube according to claim 1, characterized in that: The doping structure includes at least three third doping regions distributed at intervals.

7. The semiconductor discharge tube according to claim 1, characterized in that: It also includes two metal layers; the third doping regions in the two doping structures are both provided with metal layers on one side away from the substrate.

8. The semiconductor discharge tube according to any one of claims 1 to 7, characterized in that: The first conductivity type is N type, and the second conductivity type is P type; or, the first conductivity type is P type, and the second conductivity type is N type.

9. A method for manufacturing a semiconductor discharge tube, characterized in that: include: forming a substrate having a first conductivity type; A doping structure is formed on the first side of the substrate and the second side of the substrate respectively; wherein the first side of the substrate is arranged opposite to the second side of the substrate; the doping structure includes a first doping region with a second conductivity type, a second doping region with the second conductivity type and at least one third doping region with the first conductivity type; the second doping region is located in the first doping region, and the concentration of doping ions in the second doping region is much greater than the concentration of doping ions in the first doping region; the third doping region is located in the second doping region.

10. An overvoltage protection device, characterized in that: A semiconductor discharge tube comprising any one of claims 1 to 8.

Images