Semiconductor structure and manufacturing method thereof

Abstract

A semiconductor structure includes a substrate, a gate structure disposed on the substrate, a pad oxide layer in contact with one side of the gate structure, a silicon oxide spacer in contact with the pad oxide layer, one end of the silicon oxide spacer forming a twisted profile, and a second end of the silicon oxide spacer forming a twisted profile. A silicon nitride spacer contacts the silicon oxide spacer and a trailing end of the silicon nitride spacer covers a portion of the twisted profile and a stress layer covers the silicon nitride spacer and the substrate.

Description

Technical Field

[0001] The invention relates to a semiconductor structure, in particular to a transistor structure with a twisted profile on a spacer and a manufacturing method thereof. Background Art

[0002] The electronics industry has a growing demand for smaller and faster electronic devices that can simultaneously support more and more complex and sophisticated functions. To meet these demands, there is a continuing trend in the integrated circuit industry to manufacture low-cost, high-performance, and low-power integrated circuits. To date, these goals have been largely achieved by reducing the size of integrated circuits, thereby improving production efficiency and reducing associated costs.

[0003] For traditional metal oxide semiconductor field effect transistors, the carrier mobility may degrade due to the miniaturization of the device size, resulting in poor electrical properties, which in turn affects the operating bandwidth and is not suitable for high-speed operation scenarios. Generally speaking, under a fixed electric field, the amount of current flowing through the channel of a metal oxide semiconductor field effect transistor is proportional to the carrier mobility in the channel. Therefore, how to improve the carrier mobility in existing manufacturing process equipment to increase the performance of metal oxide semiconductor field effect transistors has become a major issue in the current semiconductor technology field. Summary of the invention

[0004] In view of this, the present invention provides a semiconductor structure and a manufacturing method that enables a stress layer to evenly apply stress to a channel region.

[0005] According to a preferred embodiment of the present invention, a semiconductor structure includes a substrate, a gate structure arranged on the substrate, a pad oxide layer contacting one side of the gate structure, a silicon oxide spacer contacting the pad oxide layer, wherein one end of the silicon oxide spacer forms a twisted profile, a silicon nitride spacer contacts the silicon oxide spacer and a tail end of the silicon nitride spacer covers part of the twisted profile, and a stress layer covers the silicon nitride spacer and the substrate.

[0006] According to another preferred embodiment of the present invention, a method for manufacturing a semiconductor structure includes providing a substrate, then forming a gate structure disposed on the substrate, then forming a pad oxide layer to contact one side of the gate structure, and then forming a silicon oxide spacer to contact the pad oxide layer, wherein one end of the silicon oxide spacer constitutes a twisted profile, and then forming a silicon nitride spacer to contact the silicon oxide spacer and a tail end of the silicon nitride spacer covers part of the twisted profile, and finally forming a stress layer to cover the gate structure, the silicon nitride spacer and the substrate.

[0007] In order to make the above-mentioned objectives, features and advantages of the present invention more clearly understood, the following is a detailed description of the preferred embodiments and the accompanying drawings. However, the following preferred embodiments and drawings are only for reference and explanation, and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 6 A schematic diagram of a semiconductor structure depicted in accordance with a preferred embodiment of the present invention;

[0009] Figure 7 It is a schematic diagram of a variation of a semiconductor structure according to a preferred embodiment of the present invention.

[0010] Explanation of symbols

[0011] 10: Base

[0012] 10a: Concavoconvex surface

[0013] 12: Virtual gate structure

[0014] 14: Gate dielectric layer

[0015] 16: Polysilicon layer

[0016] 18: Upper cover

[0017] 20: Pad oxide layer

[0018] 22a: lightly doped region

[0019] 22b: lightly doped region

[0020] 24: Silicon oxide spacer

[0021] 24a: Distorted Contour

[0022] 26: Silicon nitride spacer

[0023] 26': End

[0024] 26a: first silicon nitride spacer

[0025] 26b: Bottom

[0026] 26m: Middle part

[0027] 26t: Top

[0028] 28a: Source

[0029] 28b: Drain

[0030] 30a: Metal silicide

[0031] 30b: Metal silicide

[0032] 32: Stress layer

[0033] 34: Dielectric layer

[0034] 36: Groove

[0035] 38: Material layer

[0036] 40:Metal gate

[0037] 42: Interlayer dielectric layer

[0038] 44a: Conductive plug

[0039] 44b: Conductive plug

[0040] 44c: Conductive plug

[0041] 100:Semiconductor structure

[0042] D1: First thickness

[0043] D2: Second thickness

[0044] D3: The third thickness

[0045] STI: Shallow Trench Isolation

[0046] X: Direction DETAILED DESCRIPTION

[0047] Figures 1 to 6 A semiconductor structure is shown according to a preferred embodiment of the present invention.

[0048] like Figure 1 As shown, a substrate 10 is provided, and the substrate 10 includes a silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate, a silicon carbide substrate or a silicon-covered insulating substrate. A shallow trench isolation STI is buried in the substrate 10 to define an active (active) area. The shallow trench isolation STI can include silicon oxide, and then a dummy gate structure 12 is formed on the substrate 10. The dummy gate structure 12 includes a gate dielectric layer 14, a polysilicon layer 16 and a cap layer 18 stacked from bottom to top, and then a liner oxide layer 20 is formed to contact both sides of the dummy gate structure 12. The liner oxide layer 20 is preferably silicon oxide. Then, an ion implantation process is performed using the dummy gate structure 12 and the pad oxide layer 20 as masks to form a lightly doped region 22a / 22b in the substrate 10 on both sides of the dummy gate structure 12. When the ion implantation process is performed, the surface of the substrate 10 is damaged due to ion impact, so that the surface of the damaged substrate 10 forms a concave-convex surface 10a. The method for forming the pad oxide layer 20 can be to first form an oxide layer (not shown) and then perform a back etching to prepare it, but it is not limited to this.

[0049] like Figure 2 As shown, a first spacer material layer (not shown) and a second spacer material layer (not shown) are sequentially formed to cover the substrate 10, the liner oxide layer 20 and the dummy gate structure 12, the first spacer material layer is silicon oxide, and the second spacer material layer is silicon nitride. The first spacer material layer covers and fills the concave-convex surface 10a, and then a first dry etching is performed to etch the first spacer material layer and the second spacer material layer to form a silicon oxide spacer 24 and a first silicon nitride spacer 26a, and then an ion implantation process is performed using the dummy gate structure 12, the liner oxide layer 20, the silicon oxide spacer 24 and the first silicon nitride spacer 26a as masks to form a source 28a and a drain 28b in the substrate 10 on both sides of the dummy gate structure 12, and the implanted dopants may include N-type or P-type dopants, and then a metal silicide 30a / 30b is formed on the surface of the source 28a and the drain 28b respectively.

[0050] like Figure 3 As shown, a second dry etching is performed to etch the first silicon nitride spacer 26a, and after the second dry etching, a wet etching is performed to etch the first silicon nitride spacer 26a to form a silicon nitride spacer 26. According to a preferred embodiment of the present invention, the manufacturing process conditions of the second dry etching include etching using etching gas CF4 or CH3F, and the manufacturing process conditions of the wet etching include using phosphoric acid aqueous solution, etching at a temperature between 80°C and 150°C, and the concentration of the phosphoric acid aqueous solution is between 50% and 85%. According to different manufacturing process conditions of the second dry etching and wet etching, the thickness of the silicon nitride spacer 26 may also be different. For example, the silicon nitride spacer 26 is divided into a top 26t, a middle portion 26m and a bottom 26b. The bottom 26b is closer to the substrate 10, the top 26t is farther away from the substrate 10, and the middle portion 26m is located between the top 26t and the bottom 26b. A direction X is parallel to the surface of the substrate 10 directly below the dummy gate structure 12. Along the direction X, the top 26t includes a first thickness D1, the middle portion 26m includes a second thickness D2, and the bottom 26b includes a third thickness D3. The first thickness D1 is less than the second thickness D2, and the third thickness D3 is not less than the second thickness D2. Figure 3 In the example, the second thickness D2 is equal to the third thickness D3. Figure 7 In the embodiment, the third thickness D3 is greater than the second thickness D2.

[0051] Figure 4 To continue Figure 3 The production process steps, such as Figure 4As shown, a stress layer 32 is formed to cover the substrate 10, the pad oxide layer 20, the silicon oxide spacer 24, the silicon nitride spacer 26 and the dummy gate structure 12. The function of the stress layer 32 is to apply a tensile or contractive stress to the channel region (not shown) below the dummy gate structure 12. The stress layer 32 can also serve as an etching stop layer for subsequent dry etching of the conductive plug. The stress layer 32 is preferably silicon nitride. Then, a dielectric layer 34 is formed to cover the stress layer 32.

[0052] like Figure 5 As shown, a chemical mechanical polishing is performed to remove the stress layer 32 and the dielectric layer 34 above the dummy gate structure 12, so that the dummy gate structure 12 is exposed, and then the upper cover layer 18 and the polysilicon layer 16 in the dummy gate structure 12 are removed to form a groove 36. Figure 6 As shown, a material layer 38 is formed to fill the groove 36. The material layer 38 may include a work function layer and a buffer layer. The material layer 38 is preferably U-shaped. Then, a metal gate 40 is formed to fill the groove. The metal gate 40 includes tungsten or aluminum. Then, an interlayer dielectric layer 42 is formed to cover the stress layer 32, and then a conductive plug 44a / 44b / 44c is formed. The conductive plug 44a / 44b penetrates the interlayer dielectric layer 42, the dielectric layer 34 and the stress layer 32 and contacts the metal silicide 30a above the source 28a and the metal silicide 30b above the drain 28b respectively. The conductive plug 44c penetrates the interlayer dielectric layer 42 and contacts the metal gate 40. At this point, the semiconductor structure 100 of the present invention has been completed. The method for forming the conductive plug 44a / 44b / 44c may include, for example, first using a patterned mask to perform a dry etching to etch through the interlayer dielectric layer 42 and the dielectric layer 34, using the stress layer 32 as an etching stop layer, then using a wet etching and / or a dry etching to etch through the stress layer 32 to expose the metal silicide 30a / 30b on the surface of the source 28a and the drain 28b, and finally filling the conductive layer and planarizing it, but the present invention is not limited thereto. The conductive plug 44a / 44b / 44c includes aluminum or other metals, and the metal silicide 30a / 30b includes nickel silicide or other metal silicides.

[0053] like Figure 6As shown, a semiconductor structure 100 includes a substrate 10, a gate structure 46 is disposed on the substrate 10, the gate structure 46 includes a gate dielectric layer 14, a material layer 38 and a metal gate 40, the gate dielectric layer 14 contacts the substrate 10, the material layer 38 is disposed between the metal gate 40 and the gate dielectric layer 14, the gate dielectric layer 14 includes a high dielectric constant material, such as HfO2, HfSiO4, HfSiON or Al2O3, the material layer 38 includes a work function layer and a buffer For example, the material layer 38 may include TiN, TaN, TaAl or WN, the metal gate 40 includes Al, Ti, Ta, W or Cu, a liner oxide layer 20 contacts one side of the gate structure 46, the liner oxide layer 20 is preferably silicon oxide, a silicon oxide spacer 24 contacts the liner oxide layer 20, wherein one end of the silicon oxide spacer 24 forms a kink profile 24a, and the substrate 10 on both sides of the gate structure 46 each includes a concave-convex surface 10a (see Figure 1 ), the twisted profile 24a contacts and covers the concave-convex surface 10a, a silicon nitride spacer 26 contacts the silicon oxide spacer 24 and a tail end 26' of the silicon nitride spacer 26 covers part of the twisted profile 24a, so that the surface of the tail end 26' and the surface of the twisted profile 24a together form a surface without protrusions (pointed), and a stress layer 32 covers the gate structure 46, the silicon nitride spacer 26 and the substrate 10. The stress layer 32 can be silicon nitride.

[0054] In addition, two lightly doped regions 22a / 22b are respectively arranged in the substrate 10 on both sides of the gate structure 46, a source 28a and a drain 28b are respectively arranged in the substrate 10 on both sides of the gate structure 46, wherein the source 28a and the lightly doped region 22a partially overlap, and the drain 28b and the lightly doped region 22b partially overlap, and the lightly doped region 22a / 22b can extend to directly below the gate structure 46, and two metal silicides 30a / 30b are respectively arranged on the source 28a and the drain 28b, the stress layer 32 contacts the metal silicide 30a / 30b, and the conductive plugs 44a / 44b penetrate the stress layer 32 and contact the metal silicide 30a / 30b respectively.

[0055] Furthermore, the silicon nitride spacer 26 is divided into a top portion 26t, a middle portion 26m and a bottom portion 26b, the bottom portion 26b is closer to the substrate 10, the top portion 26t is farther away from the substrate 10, the middle portion 26m is located between the top portion 26t and the bottom portion 26b, the tail end 26' extends from the bottom portion 26b, a direction X is parallel to the surface of the substrate 10 located directly below the gate structure 46, the top portion 26t includes a first thickness D1, the middle portion 26m includes a second thickness D2, and the bottom portion 26b includes a third thickness D3, the first thickness D1, the second thickness D2 and the third thickness D3 are all along the direction X, the first thickness D1 is less than the second thickness D2, the third thickness D3 is not less than the second thickness D2, and the Figure 6 In the example, the second thickness D2 is equal to the third thickness D3, but in Figure 7 In the example, the third thickness D3 is greater than the second thickness D2.

[0056] Since the surface of the substrate is damaged when the lightly doped region is made, so that the surface of the substrate forms a concave-convex surface, the silicon oxide spacer covering the concave-convex surface will form a twisted profile, and the twisted profile will cause the subsequent stress layer to be unable to evenly apply stress to the channel region. Therefore, after the source and drain are completed, the present invention uses dry etching plus wet etching to thin the outermost spacer, which is also the silicon nitride spacer, so that the overall profile of the silicon nitride spacer can compensate for the twisted profile. The tail end of the silicon nitride spacer is used to cover and connect the twisted profile, so that the twisted profile is no longer a convex surface in the adjacent area, and combined with the profile of the silicon nitride spacer body, a surface without turning can be formed on both sides of the gate structure, so that the stress of the stress layer can be evenly applied to the channel region.

[0057] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor structure comprising: substrate; A gate structure is disposed on the substrate; a pad oxide layer contacting one side of the gate structure; A silicon oxide spacer contacts the pad oxide layer, wherein an end of the silicon oxide spacer forms a kink profile; A silicon nitride spacer contacts the silicon oxide spacer and a tail end of the silicon nitride spacer covers a portion of the twisted profile; and The stress layer covers the silicon nitride spacer and the substrate. 2 . The semiconductor structure as claimed in claim 1 , wherein the substrate on one side of the gate structure comprises a concave-convex surface, and the twisted profile contacts and covers the concave-convex surface. 3 . The semiconductor structure as claimed in claim 1 , wherein a surface of the tail end and a surface of the twisted profile together constitute a surface without a pointed point.

4. The semiconductor structure as claimed in claim 1, wherein the silicon nitride spacer is divided into a top, a middle portion and a bottom, the bottom is closer to the substrate, the top is farther away from the substrate, the middle portion is located between the top and the bottom, and the tail end extends from the bottom.

5. A semiconductor structure as described in claim 4, wherein a direction is parallel to the surface of the substrate located directly below the gate structure, the top portion includes a first thickness, the middle portion includes a second thickness, and the bottom portion includes a third thickness, the first thickness, the second thickness, and the third thickness are all along the direction, the first thickness is less than the second thickness, and the third thickness is not less than the second thickness. The semiconductor structure as claimed in claim 5 , wherein the third thickness is greater than the second thickness.

7. The semiconductor structure of claim 1, further comprising: Two lightly doped regions are respectively disposed in the substrate at two sides of the gate structure; A source electrode and a drain electrode are respectively arranged in the substrate on both sides of the gate structure; Two metal silicides are respectively disposed on the source and the drain, wherein the stress layer contacts the metal silicides; as well as Two conductive plugs penetrate the stress layer and contact the metal silicides respectively.

8. The semiconductor structure of claim 1, wherein the gate structure comprises: a gate dielectric layer contacting the substrate; and A metal gate is disposed above the gate dielectric layer.

9. A method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a gate structure disposed on the substrate; forming a pad oxide layer contacting one side of the gate structure; forming a silicon oxide spacer to contact the pad oxide layer, wherein an end of the silicon oxide spacer forms a kink profile; forming a silicon nitride spacer to contact the silicon oxide spacer and a tail end of the silicon nitride spacer to cover a portion of the twisted profile; and A stress layer is formed to cover the gate structure, the silicon nitride spacer and the substrate.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein the silicon nitride spacer is formed by: forming a first silicon nitride spacer; performing dry etching to etch the first silicon nitride spacer; and After the dry etching, wet etching is performed to etch the first silicon nitride spacer to form the silicon nitride spacer.

11. The method for manufacturing a semiconductor structure according to claim 10, further comprising: Before performing the dry etching, a first ion implantation process is performed to form a source electrode and a drain electrode in the substrate at both sides of the gate structure; Before performing the dry etching, two metal silicides are formed and disposed on the source and the drain respectively, wherein the stress layer contacts the metal silicides; and After forming the stress layer, two conductive plugs are formed to penetrate the stress layer and contact the source and the drain respectively.

12. The method for manufacturing a semiconductor structure as claimed in claim 10, wherein the dry etching process conditions include etching using etching gas CF4 or CH3F. 13 . The method for manufacturing a semiconductor structure as claimed in claim 10 , wherein the wet etching process conditions include using a phosphoric acid aqueous solution, etching at a temperature between 80° C. and 150° C., and the concentration of the phosphoric acid aqueous solution is between 50% and 85%.

14. The method for manufacturing a semiconductor structure according to claim 9, further comprising: performing a second ion implantation process after forming the liner oxide layer and before forming the silicon oxide spacer, the second ion implantation process comprising: Using the gate structure and the silicon oxide spacer as masks, ions are injected to form two lightly doped regions in the substrate on both sides of the gate structure, wherein during the ion implantation process, the surface of the substrate is destroyed to form the concave-convex surface, and the silicon oxide spacer contacts the concave-convex surface to form the twisted profile. 15 . The method for manufacturing a semiconductor structure as claimed in claim 9 , wherein a surface of the tail end and a surface of the twisted profile together constitute a surface without a pointed point.

16. The method for manufacturing a semiconductor structure as described in claim 9, wherein the silicon nitride spacer is divided into a top, a middle portion and a bottom, the bottom is closer to the substrate, the top is farther from the substrate, the middle portion is located between the top and the bottom, and the tail end extends from the bottom.

17. A method for manufacturing a semiconductor structure as described in claim 16, wherein the direction is parallel to the surface of the substrate located directly below the gate structure, the top portion includes a first thickness, the middle portion includes a second thickness, and the bottom portion includes a third thickness, the first thickness, the second thickness, and the third thickness are all along the direction, the first thickness is less than the second thickness, and the third thickness is not less than the second thickness. 18 . The method for manufacturing a semiconductor structure as claimed in claim 17 , wherein the third thickness is greater than the second thickness.

19. The method for manufacturing a semiconductor structure according to claim 9, wherein the gate structure comprises: a gate dielectric layer contacting the substrate; and A metal gate is disposed above the gate dielectric layer.

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