Trench LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor with ring gate structure and multi-surface high-K dielectric region

Abstract

The invention discloses a trench LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor with a ring gate structure and a multi-surface high-K dielectric region. The transistor comprises a substrate layer, a buried oxide layer, a silicon film layer and a device top layer. High-K medium thin layers with the same thickness and K value are arranged on the outer surface, except the bottom, of the silicon material in the silicon film layer; and the gate adopts a ring gate structure distributed around the source region. The large-area covered high-K dielectric thin layer is favorable for guiding electric flux and modulating the distribution of a circle of electric field of the annular groove, so that the distribution of the electric field around the groove is more uniform, the RESURF effect is improved, and the breakdown voltage of the device is favorably improved; meanwhile, the high-K medium is helpful to assist in depletion of the drift region, so that the doping concentration of the drift region is improved, and the on-resistance of the device is greatly reduced. In addition, the high-K dielectric thin layer is arranged in a surrounding manner, so that the gate electrode can be embedded in the high-K dielectric thin layer in a surrounding manner to form an annular gate structure; therefore, the problem that the source end of the device is broken down in advance due to the fact that the contacted high-K dielectric is too thick can be prevented.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor high-voltage power integrated circuit special devices, and in particular relates to a silicon trench LDMOS transistor on an insulating layer with a ring gate structure and a multi-faceted high-K dielectric structure. Background Art

[0002] One advantage of lateral double diffused field effect transistor (LDMOS) devices is that their gate, source and drain electrodes are all on the surface of the device, making it easy to integrate. Therefore, LDMOS devices are commonly used power devices in intelligent power integrated circuits. Especially in power management chips, such as DC / DC chips, AC / DC chips, DC / AC chips, etc., in these chips, LDMOS devices occupy most of the chip area. Therefore, to achieve high performance, low power consumption and miniaturization of chips, improving LDMOS devices in chips is a very important part. Because the on-resistance of LDMOS is much larger than that of vertical transistors (VDMOS) in practice, the device size is required to be larger under the rated withstand voltage, which increases the production cost. Therefore, in the device design process, the withstand voltage of the lateral LDMOS device is improved while reducing its on-state resistance, that is, to alleviate the breakdown voltage (BV) and specific on-resistance (R on,sp ) has practical significance. LDMOS devices based on silicon on insulator (SOI) occupy an important position in the field of power devices due to their fast conversion rate and low power consumption. With the continuous development of trench technology and high-K dielectrics, trench technology and high-K materials have also been applied to the design of power devices. The trench termination technology removes the curved junction part of the main junction by groove cutting, fills the trench with dielectric material, and transfers the high electric field to the dielectric area with lower dielectric constant but higher interface breakdown electric field, thereby improving the withstand voltage. High-K dielectrics guide the electric flux and optimize the electric field distribution of the device, effectively increasing the breakdown voltage of the device and reducing its specific on-resistance. The ring gate structure is conducive to preventing the premature breakdown of the source end of the device due to the excessive thickness of the high-K dielectric in contact with it. At the same time, the ring gate structure can also widen the conduction path of the device, thereby reducing the on-resistance of the device. Summary of the invention

[0003] The object of the present invention is to provide a lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor based on a silicon-on-insulator (SOI) substrate and having a trench, a ring gate structure, and a high-K dielectric structure at the edge of the silicon material in the silicon film layer.

[0004] The present invention provides a trench LDMOS transistor with a ring gate structure and a multi-faceted high-K dielectric region, comprising a substrate layer, a buried oxide layer, a silicon film layer and a device top layer stacked in sequence from bottom to top; the silicon film layer comprises a silicon material body, a trench and a high-K dielectric region; the trench enables the silicon material body to form a U-shaped structure; the silicon material body comprises a source region, a drift region and a drain region; The sides of the silicon material body are covered with a high-K dielectric region; the source region includes a source region P+ portion located in the central area of ​​the source region, and a source region N+ portion surrounding the source region P+ portion; the top layer of the device includes a gate electrode, a source electrode and a drain electrode; the gate electrode is a surrounding structure embedded in the high-K dielectric region, and is arranged around the source region; the source electrode and the drain electrode are respectively arranged on the source region and the drain region.

[0005] Preferably, the thickness and K value of the high-K dielectric region at different positions are equal.

[0006] Preferably, the width of the high-K medium is 0.8 μm to 0.97 μm.

[0007] Preferably, the K value of the high-K dielectric region is 50-250.

[0008] Preferably, the gate electrode is separated from the silicon material body by a high-K dielectric region.

[0009] Preferably, the source region and the drain region are arranged above the drift region and are respectively arranged on both sides of the trench; and a silicon body is arranged between the source region and the drift region.

[0010] Preferably, the drift region is doped with N-type doping and the doping concentration is 5×10 16 cm -3 ~1.4×10 18 cm -3 .

[0011] Preferably, the groove is made of silicon dioxide with a length of 1.5 μm to 3.5 μm and a thickness of 8 μm to 10.7 μm.

[0012] Preferably, the silicon film layer has a length of 7 μm to 9 μm, a width of 2 μm to 3 μm, and a thickness of 9 μm to 12 μm.

[0013] Preferably, the buried oxide layer is made of silicon dioxide with a thickness of 2 μm to 4 μm.

[0014] Preferably, the doping type of the substrate layer is P type, and the doping concentration is 1×10 14 ~1×10 15 cm -3 of silicon material.

[0015] The present invention has the following beneficial effects: 1. In the present invention, the outer surface of the silicon material in the silicon film layer except the bottom is covered with a thin layer of high-K dielectric area with the same thickness and K value; the high-K dielectric area covering the silicon material over a large area helps to guide the electric flux, modulate the distribution of the device electric field, make the electric field distribution around the groove more uniform, improve the RESURF effect, and help to increase the breakdown voltage of the device.

[0016] 2. In the present invention, since the high-K dielectric region covers all areas on the side of the U-shaped silicon material, the high-K dielectric region can completely surround the source region of the device, thereby providing a feasible basis for the ring gate structure embedded in the high-K dielectric region; and the ring gate structure surrounding the source region is beneficial to preventing the premature breakdown of the source end of the device due to the excessive thickness of the high-K dielectric in contact, thereby improving the breakdown voltage of the device.

[0017] 3. The ring gate structure adopted in the present invention can broaden the conduction path of the device, thereby reducing the specific on-resistance of the device.

[0018] 4. The high-K dielectric structure provided in the silicon film layer of the present invention helps to consume electrons in the drift region and assists in depleting the drift region, thereby increasing the doping concentration of the drift region and greatly reducing the specific on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a device structure diagram of Example 1 of the present invention.

[0020] Figure 2 This is a cross-sectional view of the device at z=1 according to Example 1 of the present invention.

[0021] Figure 3 This is a device structure diagram of comparative example 1.

[0022] Figure 4 This is a cross-sectional view of the device of Comparative Example 1 at z=1.

[0023] Figure 5 This is a comparison diagram of the electric field around the silicon film layer groove changing with position in Example 1 of the present invention and Comparative Example 1.

[0024] Figure 6 This is a comparison diagram of the effect of the thickness of the high-K dielectric at the edge of the silicon material of the silicon film layer of the present invention on the breakdown voltage of the device.

[0025] Figure 7 This is a comparison diagram of the effect of the thickness of the high-K dielectric at the edge of the silicon material of the silicon film layer of the present invention on the device's specific on-resistance.

[0026] Figure 8 This is a comparison diagram of the effect of the thickness of the high-K dielectric at the edge of the silicon material of the silicon film layer of the present invention on the FOM value of the device.

[0027] Fig. 9 This is a comparison diagram of the effect of the K value of the high-K dielectric at the edge of the silicon material of the silicon film layer of the present invention on the breakdown voltage of the device.

[0028] Fig.10 This is a comparison diagram of the effect of the K value of the high-K dielectric at the edge of the silicon material of the silicon film layer of the present invention on the device's specific on-resistance.

[0029] Fig.11 This is a comparison diagram of the effect of the K value of the high-K medium at the edge of the silicon material of the silicon film layer of the present invention on the FOM value of the device.

[0030] Fig.12 This is a comparison chart of the effect of the length of the silicon dioxide trench in the silicon film layer of the present invention on the breakdown voltage, specific on-resistance and FOM value of the device.

[0031] Fig.13 This is a comparison chart showing the effect of the thickness of the silicon dioxide trench in the silicon film layer of the present invention on the breakdown voltage, specific on-resistance and FOM value of the device.

[0032] Fig.14 The figure is a relationship diagram between breakdown voltage and specific on-resistance comparing Example 1 with other devices in the related field. DETAILED DESCRIPTION

[0033] The present invention is further described below with reference to the accompanying drawings and examples.

[0034] Example 1 like Figure 1 and 2 As shown, a double-sided high-K dielectric silicon trench LDMOS transistor on an insulating layer (denoted as DHK TSOILDMOS) includes a substrate layer 8, a buried oxide layer 7, a silicon film layer and a device top layer stacked in sequence from bottom to top. The LDMOS transistor has an overall device length of 9μm, an overall thickness of 25μm, and an overall width of 2μm; a silicon film layer thickness of 12μm; a buried oxide layer thickness of 3μm; and a substrate layer thickness of 10μm.

[0035] The substrate layer 8 is arranged at the bottom, and the doping type is P type, and the doping concentration is 7×10 14 cm -3 The substrate layer 8 is made of silicon material, and the thickness of the substrate layer 8 is 10 μm; the substrate layer 8 is provided with a buried oxide layer 7, and the buried oxide layer 7 is made of silicon dioxide material with a thickness of 3 μm.

[0036] The buried oxide layer 7 is provided with a silicon film layer, which includes a silicon material body, a groove 5 and a high-K dielectric region 9. The silicon material body includes a source region, a silicon body 3, a drift region 4 and a drain region 6. The groove 5 is arranged in the middle of the top surface of the silicon material body, so that the silicon material body forms a U-shaped structure. The sides of the silicon material body are covered with the high-K dielectric region 9.

[0037] The side surface of the silicon material body includes both the external surface along the positive and negative directions of the x and z axes and the surface at the connection between the silicon material body and the groove 5. Since the silicon material body is a U-shaped solid structure, the high-K dielectric area 9 that wraps the silicon material body forms a U-shaped shell structure that is open at the top and bottom. The thickness and K value of the high-K dielectric area 9 at different positions are equal.

[0038] The source region and the drain region 6 are respectively arranged on both sides of the trench 5, so that the source region, the trench 5 and the drain region 6 are arranged in sequence above the drift region 4 and along the length direction of the entire device; a silicon body 3 is arranged between the source region and the drift region 4. The cross-sectional shape of the silicon body 3 is the same as that of the source region. The source region includes a source region P+ part 2 located in the central area of ​​the source region, and a source region N+ part 1 surrounding the source region P+ part 2.

[0039] The source region N+ part 1 is made of silicon material, the doping type is N-type, and the doping concentration is 1×10 20 cm -3 , the width and thickness are both 0.75μm; the source region P+ part 2 is made of silicon material, the doping type is P type, and the doping concentration is 1×10 20 cm -3 , length and thickness are both 0.75 μm.

[0040] The silicon body 3 is made of silicon material with a length of 1.5 μm and a thickness of 0.75 μm, and the doping type is P type with a doping concentration of 1×10 17 cm -3 .

[0041] The drain region 6 is made of silicon material with a length of 2 μm and a thickness of 0.75 μm, and the doping type is N-type with a doping concentration of 1×10 20 cm -3 ; The doping type of drift region 4 is N-type, and the doping concentration is 1.1×10 18 cm -3 .

[0042] In this embodiment, the thickness t of the high-K dielectric region 9 is 0.95 μm, and the K value is 250; the depth L of the trench 5 (ie, the dimension along the thickness direction of the silicon film layer) is 2 μm, and the thickness is 10 μm.

[0043] The top layer of the device includes a gate electrode 10, a source electrode 11 and a drain electrode 12; the gate electrode 10 is a wraparound structure. The gate electrode 10 wraps around the source region and the silicon body 3, and is completely embedded in the high-K dielectric region 9, without direct contact with the source region and the silicon body 3; at this time, the high-K dielectric region 9 between the gate electrode 10 and the source region N+ part 1, the silicon body 3, and the drift region 4 can act as a gate isolation layer, thereby eliminating the structural processing flow of the gate oxide layer and simplifying the overall process complexity of the device.

[0044] The source electrode 11 is disposed on the source region and directly contacts the top surface of the source region. The drain electrode 12 is disposed on the drain region 6 and directly contacts the top surface of the drain region 6.

[0045] Comparative Example 1 like Figure 3 and 4 As shown, a double-sided high-K dielectric silicon trench LDMOS transistor on an insulating layer (denoted as DHK TSOILDMOS) is shown. The difference between this comparative example and Example 1 is that only high-K dielectric structures 9 are set on both sides of the silicon material body in the silicon film layer, and the thickness is 0.6μm; the top layer of the device adopts a traditional electrode structure, specifically, the gate electrode 10 does not adopt a ring gate structure; the length of the silicon dioxide trench is 5μm and the thickness is 11μm; the other parameters are consistent with Example 1. According to the test, under the structure of this comparative example, the optimal doping concentration of the drift region 4 is 1.4×10 16 cm -3 .

[0046] The device length direction is set as the X-axis direction, the device thickness direction is set as the Y-axis direction, and the device width direction is set as the Z-axis direction. Based on the three-dimensional TCAD software simulation, the following experiments are performed to obtain the performance of the LDMOS transistor provided in Example 1 and Comparative Example 1. In the simulation study, the substrate layer 8 is grounded.

[0047] The following is a description of the significant superiority of Example 1 over Comparative Example 1: The curve comparison of the electric field around the trench of the LDMOS transistor provided by Example 1 (DHK TSOI LDMOS) and Comparative Example 1 (CTSOI LDMOS) as a function of position is shown in FIG. Figure 5 As shown. Figure 5 It can be seen that the high-K dielectric region 9 existing on the outer surface of the silicon material body except the bottom surface in the silicon film layer of Example 1 can guide the electric flux (that is, more electric flux flows to the high-K dielectric), making the electric field outside the groove in the silicon film layer more uniform, thereby improving the RESURF effect of the device. At the same time, the ring gate structure in Example 1 is conducive to preventing the premature breakdown problem caused by the excessive thickness of the high-K dielectric in contact with the source end of the device, thereby improving the breakdown voltage of the device.

[0048] Determination process of the optimal values ​​of each key parameter in Example 1: The doping concentration of the drift region 4, the length and thickness of the trench 5, and the thickness and K value of the high-K dielectric region 9 of the LDMOS transistor provided in Example 1 are changed to study the influence of key parameters on the performance of the device, such as breakdown voltage, on-resistance and FOM value.

[0049] Figure 6 , Figure 7 and Figure 8Describe the effect of the thickness of the high-K dielectric region 9 at the edge of the silicon film layer on the device breakdown voltage, specific on-resistance and FOM value. At this time, the K value of the high-K dielectric is 250, the length of the silicon dioxide trench 5 is 2μm, the thickness is 10μm, and the other related parameters remain unchanged. In the figure, t HK is the thickness of the high-K dielectric region 9; when the thickness of the high-K dielectric region 9 is 0.95 μm, the concentration of the drift region 4 is 1×10 18 cm -3 When the device achieves the highest breakdown voltage of 770V and a lower on-resistance. The concentration of drift region 4 is further increased. When the doping concentration of drift region 4 is 1.1×10 18 cm -3 When the breakdown voltage drops slightly, the on-resistance decreases significantly, and the highest FOM value of 92.54MW / cm is obtained. 2 , showing the best overall performance.

[0050] Fig. 9 , Fig.10 and Fig.11 Describe the effect of the K value of the high-K dielectric region 9 at the edge of the silicon material of the silicon film layer on the breakdown voltage, specific on-resistance and FOM value of the device. At this time, the thickness of the high-K dielectric region 9 is 0.95μm, the length of the silicon dioxide trench 5 is 2μm, the thickness is 10μm, and the other relevant parameters remain unchanged. As can be seen from the figure, with the increase of the K value, the maximum breakdown voltage of the device gradually increases. At the same time, the optimal doping concentration of the device is also increasing, and it can have a lower on-resistance at this time. Therefore, as the K value of the high-K dielectric increases, the overall performance of the device will continue to improve.

[0051] Fig.12 The effect of the thickness of the silicon dioxide trench 5 of the device on the breakdown voltage, specific on-resistance and FOM value of the device is described. At this time, the thickness of the high-K dielectric region 9 is 0.95μm, the K value is 250, and the doping concentration of the drift region 4 is the optimal doping concentration corresponding to the silicon dioxide trench length. As can be seen from the figure, as the length of the silicon dioxide trench increases, the breakdown voltage and specific on-resistance of the device generally show an upward trend. When the silicon dioxide trench length is 2μm, the device has the highest FOM value (i.e., the best overall performance).

[0052] Fig.13 The effect of the thickness of the silicon dioxide trench 5 of the device on the breakdown voltage, specific on-resistance and FOM value of the device is described. At this time, the width of the high-K dielectric region 9 is 0.95μm, the K value is 250, and the doping concentration of the drift region 4 is the optimal doping concentration corresponding to the thickness of the silicon dioxide trench. As can be seen from the figure, as the thickness of the silicon dioxide trench increases, the breakdown voltage of the device first increases and then decreases, and the on-resistance generally shows an upward trend. When the thickness of the silicon dioxide trench is 10μm, the device has the highest FOM value (that is, the best overall performance).

[0053] Based on the above eight figures, it can be concluded that when the width of the high-K dielectric region 9 is 0.95μm, the K value is 250, the length of the silicon dioxide trench 5 is 2μm, and the thickness is 10μm, the device has a higher breakdown voltage and lower on-resistance, and the structure set with these parameters can show the best performance.

[0054] Fig.14 The figure is a relationship diagram of breakdown voltage and on-resistance comparing the present invention with other devices in the related field, such as MR-LDMOS, SCDT-LDMOS, HKGF-LDMOS, HKMF-LDMOS, and HKT-LDMOS. Fig.14 It can be seen that the design concept of the present invention is superior, and its performance exceeds the traditional Triple RESURF curve. Compared with other devices in the relevant field, it has a higher breakdown voltage and a lower on-resistance, and has more superior performance.

Claims

1. A trench LDMOS transistor with a ring gate structure and a multi-faceted high-K dielectric region, comprising a substrate layer (8), a buried oxide layer (7), a silicon film layer and a device top layer stacked in sequence from bottom to top; the silicon film layer comprises a silicon material body, a trench (5) and a high-K dielectric region (9); the silicon material body comprises a source region, a drift region (4) and a drain region (6); characterized in that: The side surfaces of the silicon material body are covered with a high-K dielectric region (9); the source region comprises a source region P+ portion (2) located in the central area of ​​the source region, and a source region N+ portion (1) surrounding the source region P+ portion (2); the top layer of the device comprises a gate electrode (10), a source electrode (11) and a drain electrode (12); the gate electrode (10) is in a surrounding structure embedded in the high-K dielectric region (9), and is arranged around the source region; the source electrode (11) and the drain electrode (12) are arranged on the source region and the drain region (6), respectively.

2. A trench LDMOS transistor having a gate-all-around structure and multi-faceted high-K dielectric regions according to claim 1, characterized in that: The thickness and K value of the high-K dielectric region (9) at different positions are equal.

3. A trench LDMOS transistor having a gate-all-around structure and multi-faceted high-K dielectric regions according to claim 2, characterized in that: The thickness of the high-K dielectric (9) is 0.8 μm to 0.97 μm; the K value of the high-K dielectric region (9) is 50 to 250.

4. A trench LDMOS transistor having a gate-all-around structure and multi-faceted high-K dielectric regions according to claim 2, characterized in that: The gate electrode (10) is separated from the silicon material body by a high-K dielectric region (9).

5. The trench LDMOS transistor with a gate-all-around structure and multi-faceted high-K dielectric regions according to claim 3, characterized in that: The source region and the drain region (6) are arranged above the drift region (4) and are respectively arranged on both sides of the trench (5); a silicon body (3) is arranged between the source region and the drift region (4).

6. The trench LDMOS transistor with a gate-all-around structure and multi-faceted high-K dielectric regions according to claim 1, characterized in that: The doping type of the drift region (4) is N-type, and the doping concentration is 5×10 16 cm -3 ~1.4×10 18 cm -3 .

7. The trench LDMOS transistor with a gate-all-around structure and multi-faceted high-K dielectric regions according to claim 1, characterized in that: The groove (5) is made of silicon dioxide with a length of 1.5 μm to 3.5 μm and a thickness of 8 μm to 10.7 μm.

8. The trench LDMOS transistor with a gate-all-around structure and multi-faceted high-K dielectric regions according to claim 1, characterized in that: The silicon film layer has a length of 7 μm to 9 μm, a width of 2 μm to 3 μm, and a thickness of 9 μm to 12 μm.

9. The trench LDMOS transistor with a gate-all-around structure and multi-faceted high-K dielectric regions according to claim 1, characterized in that: The buried oxide layer (7) is made of silicon dioxide with a thickness of 2 μm to 4 μm.

10. The trench LDMOS transistor with a gate-all-around structure and multi-faceted high-K dielectric regions according to claim 1, characterized in that: The doping type of the substrate layer (8) is P type, and the doping concentration is 1×10 14 ~1×10 15 cm -3 of silicon material.

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