Display device

Abstract

A display device according to an embodiment includes a substrate, a plurality of first pixels disposed in a first region included in a display region on the substrate, and a plurality of second pixels disposed in a second region different from the first region included in the display region. Each of the plurality of first pixels includes a first pixel circuit configured from a plurality of transistors, and a first display element driven by the first pixel circuit. Each of the plurality of second pixels includes a second pixel circuit comprising a plurality of transistors, and a second display element driven by the second pixel circuit. The number of transistors constituting the second pixel circuit is less than the number of transistors constituting the first pixel circuit.

Description

[0001] This application is based on Japanese Patent Application No. 2023-149097 (filing date: September 14, 2023) and claims priority from the present application, and the present application incorporates all the contents of the application by reference. Technical Field

[0002] An embodiment of the present invention relates to a display device. Background Art

[0003] In recent years, display devices using organic light emitting diodes (OLEDs) as display elements have been put into practical use, and electronic devices such as smartphones are known to include such display devices.

[0004] In such an electronic device, by adopting a configuration in which a camera is arranged on the back side of a display device (display area), the display area can be enlarged to a region overlapping with the camera.

[0005] However, in the case of such a configuration, light needs to be incident on the camera (the imaging element included therein) via the display device, and therefore, sufficient light transmittance needs to be ensured in the display device (the region overlapping the camera in the display region). Summary of the invention

[0006] An object of the present invention is to provide a display device capable of improving light transmittance.

[0007] The display device of the embodiment includes a substrate, a plurality of first pixels arranged in a first area included in a display area on the substrate, and a plurality of second pixels arranged in a second area different from the first area included in the display area. Each of the plurality of first pixels includes a first pixel circuit composed of a plurality of transistors and a first display element driven by the first pixel circuit. Each of the plurality of second pixels includes a second pixel circuit composed of a plurality of transistors and a second display element driven by the second pixel circuit. The number of transistors constituting the second pixel circuit is less than the number of transistors constituting the first pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a diagram showing a configuration example of a display device according to an embodiment.

[0009] Figure 2 A diagram showing an example of a layout of a plurality of sub-pixels included in a pixel.

[0010] Figure 3 FIG. 2 is a diagram showing another example of the layout of a plurality of sub-pixels included in a pixel.

[0011] Figure 4 It is along Figure 2 A schematic cross-sectional view of the display device taken along line AA in FIG.

[0012] Figure 5 It is a schematic enlarged cross-sectional view of the partition wall.

[0013] Figure 6 This is a schematic cross-sectional view for explaining a display element formed using partition walls.

[0014] Figure 7 This is a schematic cross-sectional view for explaining a display element formed using partition walls.

[0015] Figure 8 This is a schematic cross-sectional view for explaining a display element formed using partition walls.

[0016] Fig. 9 is a top view showing a portion of an electronic device in which a display device is embedded.

[0017] Fig.10 This is a diagram for explaining a pixel circuit arranged in the first display area.

[0018] Fig.11 This is a diagram for explaining a pixel circuit arranged in the second display area.

[0019] Fig.12 It is along Fig.11 A schematic cross-sectional view of the display device of BB in FIG.

[0020] Fig.13 This is a diagram showing an example of a circuit configuration of a pixel circuit arranged in the first display area.

[0021] Fig.14 This is a diagram showing an example of a circuit configuration of a pixel circuit arranged in the second display area.

[0022] Fig.15 is schematically shown with Fig.13 as well as Fig.14 A diagram showing the configuration of various wiring connections for a pixel circuit.

[0023] Fig.16 It is used to illustrate Fig.13 A diagram showing the operation of a pixel circuit.

[0024] Fig.17 It is used to illustrate Fig.14 A diagram showing the operation of a pixel circuit.

[0025] Fig.18 This is a diagram showing another example of the circuit configuration of the pixel circuit arranged in the first display area.

[0026] Fig.19 This is a diagram showing another example of the circuit configuration of the pixel circuit arranged in the second display area.

[0027] Fig. 20 is schematically shown with Fig.18 as well as Fig.19 A diagram showing the configuration of various wiring connections for a pixel circuit.

[0028] Fig.21 It is used to illustrate Fig.18 A diagram showing the operation of a pixel circuit.

[0029] Fig. 22 To illustrate that Fig.19 A diagram showing the operation of a pixel circuit.

[0030] The reference numerals are described as follows:

[0031] DSP display device, DA display area, DA1 first display area, DA2 second display area, NDA non-display area, PX pixel, SP, SP1, SP2, SP3 sub-pixel, AP, AP1, AP2, AP3 opening, LE, LE1, LE2, LE3 lower electrode, UE, UE1, UE2, UE3 upper electrode, OR, OR1, OR2, OR3 organic layer, SE, SE1, SE2, SE3 sealing layer, Tr1~Tr7 transistors, Cst holding capacitor, 5 ribs, 6 partition walls, 10 substrate, 11 insulating layer, 12 circuit layer, 13 insulating layer, 14 resin layer, 15 sealing layer, 16 resin layer, 20 display element, 61 lower part, 62 upper part, 200, 210 pixel circuit DETAILED DESCRIPTION

[0032] An embodiment will be described with reference to the drawings.

[0033] The present disclosure is only an example, and appropriate changes that maintain the main purpose of the invention and that are easily conceivable by those skilled in the art are of course included in the scope of the present invention. In addition, in order to make the description clearer, the width, thickness, shape, etc. of each part of the drawings are sometimes schematically shown compared to the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same figure mark is sometimes used to mark the constituent elements that perform the same or similar functions as the constituent elements described in the drawings that appeared in the previous text, and repeated detailed descriptions are appropriately omitted.

[0034] In addition, in the drawings, mutually orthogonal X-axis, Y-axis, and Z-axis are described as necessary for easy understanding. The direction along the X-axis is called the first direction X, the direction along the Y-axis is called the second direction Y, and the direction along the Z-axis is called the third direction Z. Observing various elements parallel to the third direction Z is called a top view.

[0035] The display device of this embodiment is an organic electroluminescent display device having an organic light emitting diode (OLED) as a display element, and can be mounted on an electronic device such as a smartphone. In addition, the electronic device on which the display device of this embodiment is mounted can also be a device other than a smartphone (for example, a tablet terminal, etc.).

[0036] Figure 1 1 is a diagram showing a configuration example of a display device DSP according to the present embodiment. The display device DSP has a display area DA for displaying an image and a non-display area NDA around the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0037] In the present embodiment, the shape of the substrate 10 in plan view is a rectangle, but the shape of the substrate 10 in plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0038] The display area DA includes a plurality of pixels PX arranged (configured) in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the plurality of sub-pixels SP include a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. In addition, the plurality of sub-pixels SP may include sub-pixels of other colors such as white together with the sub-pixels SP1, SP2, and SP3. In addition, the plurality of sub-pixels SP may also include sub-pixels of other colors instead of any one of the sub-pixels SP1, SP2, and SP3.

[0039] In addition, as will be described in detail later, each of the plurality of sub-pixels SP includes a pixel circuit and a display element driven by the pixel circuit. The pixel circuit is composed of, for example, a plurality of transistors (switching elements composed of thin film transistors). The display element is an organic light emitting diode as a light emitting element. For example, the sub-pixel SP1 has a display element that emits light in a red wavelength range, the sub-pixel SP2 has a display element that emits light in a green wavelength range, and the sub-pixel SP3 has a display element that emits light in a blue wavelength range.

[0040] Figure 2 An example of the layout of a plurality of sub-pixels SP (SP1, SP2, and SP3) included in a pixel PX is shown. Here, four pixels PX will be described.

[0041] The sub-pixels SP1, SP2, and SP3 constituting one pixel PX are respectively formed into substantially rectangular shapes extending in the second direction Y, and are arranged in the first direction X. If the two pixels PX arranged in the first direction X are focused on, the colors displayed in the adjacent sub-pixels SP are different from each other. In addition, if the two pixels PX arranged in the second direction Y are focused on, the colors displayed in the adjacent sub-pixels SP are the same. In addition, the areas of the sub-pixels SP1, SP2, and SP3 may be the same or different from each other.

[0042] Figure 3 Another example of the layout of the plurality of sub-pixels SP ( SP1 , SP2 , and SP3 ) included in the pixel PX is shown.

[0043] Sub-pixels SP1 and SP2 constituting one pixel PX are arranged in the second direction Y, sub-pixels SP1 and SP3 are arranged in the first direction X, and sub-pixels SP2 and SP3 are arranged in the first direction X. Sub-pixel SP1 is formed in a substantially rectangular shape extending in the first direction X, and sub-pixels SP2 and SP3 are formed in a substantially rectangular shape extending in the second direction Y. The area of ​​sub-pixel SP2 is larger than that of sub-pixel SP1, and the area of ​​sub-pixel SP3 is larger than that of sub-pixel SP2. In addition, the area of ​​sub-pixel SP1 may be the same as that of sub-pixel SP2.

[0044] If the focus is on two pixels PX arranged in the first direction X, in the region where sub-pixels SP1 and SP3 are alternately arranged, and in the region where sub-pixels SP2 and SP3 are alternately arranged, the colors displayed in the sub-pixels SP adjacent to each other in the first direction X are different from each other. On the other hand, if the focus is on two pixels PX arranged in the second direction Y, in the region where sub-pixels SP1 and SP2 are alternately arranged, the colors displayed in the sub-pixels SP adjacent to each other in the second direction Y are different from each other. In addition, in the region where a plurality of sub-pixels SP3 are arranged, the colors displayed in the sub-pixels SP adjacent to each other in the second direction are the same.

[0045] also, Figure 2 as well as Figure 3 The outer shapes of the sub-pixels SP1, SP2, and SP3 shown correspond to the outer shapes of the regions displaying colors (that is, light-emitting regions) in the sub-pixels SP, but the outer shapes are shown in a simplified manner and do not necessarily reflect the actual shapes.

[0046] Here, the display area DA in the present embodiment is provided with ribs and partitions, the details of which will be described later. The ribs have openings in the sub-pixels SP1, SP2, and SP3, respectively. The partitions are provided at the boundaries of adjacent sub-pixels SP, and overlap with the ribs when viewed from above. Specifically, the partitions are provided between the adjacent openings (sub-pixels SP) in the first direction X, and between the adjacent openings (sub-pixels SP) in the second direction Y. Thus, the partitions as a whole have a lattice shape formed in a manner of dividing the sub-pixels SP1, SP2, and SP3. In other words, the partitions, like the ribs, can also be said to have openings in the sub-pixels SP1, SP2, and SP3.

[0047] Figure 4 It is along Figure 2 A schematic cross-sectional view of the display device DSP taken along line AA in FIG. In the display device DSP, an insulating layer 11 called a primer layer is disposed on a light-transmitting substrate 10 such as glass (on the surface on which display elements and the like are disposed).

[0048] The insulating layer 11 has, for example, a three-layer stacked structure including a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxide film (SiO). In addition, the insulating layer 11 is not limited to a three-layer stacked structure. The insulating layer 11 may have a stacked structure having more than three layers, or may have a single-layer structure or a two-layer stacked structure.

[0049] The circuit layer 12 is disposed on the insulating layer 11 . The circuit layer 12 has a pixel circuit (various circuits and wirings) for driving the display elements included in each of the sub-pixels SP1 , SP2 , and SP3 as described above. The circuit layer 12 is covered with the insulating layer 13 .

[0050] The insulating layer 13 functions as a planarizing film that planarizes the unevenness generated by the circuit layer 12. Figure 4 Although not shown in the figure, a contact hole for connecting the lower electrode LE to the pixel circuit is provided in the insulating layer 13 .

[0051] The lower electrodes LE (LE1, LE2, and LE3) are arranged on the insulating layer 13. The ribs 5 are arranged on the insulating layer 13 and the lower electrodes LE. The end portions (parts) of the lower electrodes LE are covered by the ribs 5.

[0052] The partition wall 6 has a lower portion 61 disposed on the rib 5, and an upper portion 62 covering the upper surface of the lower portion 61. The upper portion 62 has a greater width than the lower portion 61 in the first direction X and the second direction Y. Thus, the partition wall 6 has a shape in which both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. This shape of the partition wall 6 can be called an overhanging shape.

[0053] The organic layer OR ( OR1 , OR2 , and OR3 ) and the upper electrodes UE ( UE1 , UE2 , and UE3 ) together with the lower electrodes LE ( LE1 , LE2 , and LE3 ) constitute a display element included in the sub-pixel SP.

[0054] like Figure 4 As shown, the organic layer OR1 includes a first organic layer OR1a and a second organic layer OR1b separated from each other. The upper electrode UE1 includes a first upper electrode UE1a and a second upper electrode UE1b separated from each other. The first organic layer OR1a passes through the opening AP1 (the opening of the rib 5 in the sub-pixel SP1) and contacts the lower electrode LE1, and covers a part of the rib 5. The second organic layer OR1b is located above the upper portion 62. The first upper electrode UE1a is opposite to the lower electrode LE1 and covers the first organic layer OR1a. Moreover, the first upper electrode UE1a contacts the side surface of the lower portion 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0055] In addition, if Figure 4 As shown, the organic layer OR2 includes a first organic layer OR2a and a second organic layer OR2b separated from each other. The upper electrode UE2 includes a first upper electrode UE2a and a second upper electrode UE2b separated from each other. The first organic layer OR2a contacts the lower electrode LE2 through the opening AP2 (the opening of the rib 5 in the sub-pixel SP2) and covers a portion of the rib 5. The second organic layer OR2b is located above the upper portion 62. The first upper electrode UE2a is opposite to the lower electrode LE2 and covers the first organic layer OR2a. Moreover, the first upper electrode UE2a contacts the side of the lower portion 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0056] In addition, if Figure 4 As shown, the organic layer OR3 includes a first organic layer OR3a and a second organic layer OR3b separated from each other. The upper electrode UE3 includes a first upper electrode UE3a and a second upper electrode UE3b separated from each other. The first organic layer OR3a contacts the lower electrode LE3 through the opening AP3 (the opening of the rib 5 in the sub-pixel SP3) and covers a portion of the rib 5. The second organic layer OR3b is located above the upper portion 62. The first upper electrode UE3a is opposite to the lower electrode LE3 and covers the first organic layer OR3a. Moreover, the first upper electrode UE3a contacts the side of the lower portion 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0057] exist Figure 4In the illustrated example, the sub-pixels SP1 , SP2 , and SP3 include cover layers CP1 , CP2 , and CP3 (optical path adjustment layers) for adjusting optical characteristics of light emitted from the light emitting layers of the organic layers OR1 , OR2 , and OR3 .

[0058] The cap layer CP1 includes a first cap layer CP1a and a second cap layer CP1b which are separated from each other. The first cap layer CP1a is located at the opening AP1 and is disposed on the first upper electrode UE1a. The second cap layer CP1b is located above the partition wall 6 and is disposed on the second upper electrode UE1b.

[0059] The cap layer CP2 includes a first cap layer CP2a and a second cap layer CP2b which are separated from each other. The first cap layer CP2a is located at the opening AP2 and is disposed on the first upper electrode UE2a. The second cap layer CP2b is located above the partition wall 6 and is disposed on the second upper electrode UE2b.

[0060] The cap layer CP3 includes a first cap layer CP3a and a second cap layer CP3b which are separated from each other. The first cap layer CP3a is located at the opening AP3 and is disposed on the first upper electrode UE3a. The second cap layer CP3b is located above the partition wall 6 and is disposed on the second upper electrode UE3b.

[0061] Sealing layers SE1, SE2 and SE3 are respectively arranged in sub-pixels SP1, SP2 and SP3. Sealing layer SE1 continuously covers the components of sub-pixel SP1 including the first cap layer CP1a, the partition wall 6 and the second cap layer CP1b. Sealing layer SE2 continuously covers the components of sub-pixel SP2 including the first cap layer CP2a, the partition wall 6 and the second cap layer CP2b. Sealing layer SE3 continuously covers the components of sub-pixel SP3 including the first cap layer CP3a, the partition wall 6 and the second cap layer CP3b.

[0062] exist Figure 4 In the example shown, the second organic layer OR1b, the second upper electrode UE1b, the second cover layer CP1b, and the sealing layer SE1 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the second organic layer OR2b, the second upper electrode UE2b, the second cover layer CP2b, and the sealing layer SE2 on the partition wall 6. In addition, the second organic layer OR2b, the second upper electrode UE2b, the second cover layer CP2b, and the sealing layer SE2 on the partition wall 6 between the sub-pixels SP2 and SP3 are separated from the second organic layer OR3b, the second upper electrode UE3b, the second cover layer CP3b, and the sealing layer SE3 on the partition wall 6.

[0063] The sealing layers SE1 , SE2 , and SE3 are covered with a resin layer 14 (planarization film). The resin layer 14 is covered with a sealing layer 15 . Furthermore, the sealing layer 15 is covered with a resin layer 16 .

[0064] The insulating layer 13 and the resin layers 14 and 16 are formed of an organic material. The rib 5, the sealing layer 15, and the SE (SE1, SE2, and SE3) are formed of an inorganic material such as silicon nitride (SiNx).

[0065] The lower portion 61 of the partition wall 6 is conductive. The upper portion 62 of the partition wall 6 may also be conductive. The lower electrode LE may be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), or may have a laminated structure of a metal material such as silver (Ag) and a conductive oxide. The upper electrode UE may also be formed of a conductive oxide such as ITO.

[0066] When the potential of the lower electrode LE is relatively higher than that of the upper electrode UE, the lower electrode LE is equivalent to an anode and the upper electrode UE is equivalent to a cathode. In addition, when the potential of the upper electrode UE is relatively higher than that of the lower electrode LE, the upper electrode UE is equivalent to an anode and the lower electrode LE is equivalent to a cathode.

[0067] The organic layer OR includes a pair of functional layers and a light-emitting layer disposed between the functional layers. For example, the organic layer OR has a structure in which a hole injection layer, a hole input layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order.

[0068] The cap layer CP (CP1, CP2 and CP3) is formed, for example, by a multilayer body of multiple transparent thin films. The multilayer body may also include a thin film formed of an inorganic material and a thin film formed of an organic material as multiple thin films. In addition, these multiple thin films have different refractive indices from each other. The material of the thin film constituting the multilayer body is different from the material of the upper electrode UE and also different from the material of the sealing layer SE. In addition, the cap layer CP may also be omitted.

[0069] A common voltage is supplied to the partition wall 6. The common voltage is supplied to the upper electrodes UE (first upper electrodes UE1a, UE2a, and UE3a) in contact with the side surface of the lower portion 61. The pixel voltage is supplied to the lower electrodes LE (LE1, LE2, and LE3) through the pixel circuits 1 included in each of the sub-pixels SP (SP1, SP2, and SP3).

[0070] If a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in a red wavelength range. If a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in a green wavelength range. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in a blue wavelength range.

[0071] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may also emit light of the same color (for example, white). In this case, the display device DSP may also include a color filter that converts the light emitted by the light-emitting layer into light of a color corresponding to the sub-pixels SP1, SP2, and SP3. In addition, the display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layer to generate light of a color corresponding to the sub-pixels SP1, SP2, and SP3.

[0072] Figure 5 6 is a schematic enlarged cross-sectional view of the partition wall 6. Figure 5 In FIG. 1 , elements other than the ribs 5 , the partition walls 6 , the insulating layer 13 , and the pair of lower electrodes LE are omitted. The pair of lower electrodes LE corresponds to any one of the lower electrodes LE1 , LE2 , and LE3 described above.

[0073] exist Figure 5 In the example shown, the lower portion 61 of the partition wall 6 includes a blocking layer (bottom portion) 611 disposed on the rib portion 5, and a metal layer (shaft portion) 612 disposed on the blocking layer 611. The blocking layer 611 is formed of a material different from that of the metal layer 612, for example, a metal material such as molybdenum (Mo), titanium (Ti), and titanium nitride (TiN). The metal layer 612 is formed thicker than the blocking layer 611. The metal layer 612 may be a single-layer structure or a stacked structure of different metal materials. As an example, the metal layer 612 is formed of, for example, aluminum (Al) or an aluminum alloy.

[0074] The upper portion (top portion) 62 is thinner than the lower portion 61. Figure 5 In the example shown, the upper portion 62 includes a first layer 621 disposed on the metal layer 612 and a second layer 622 disposed on the first layer 621. As an example, the first layer 621 is formed of titanium (Ti), and the second layer 622 is formed of ITO.

[0075] exist Figure 5 In the example shown, the width of the lower portion 61 decreases toward the upper portion 62. That is, the side surfaces 61a and 61b of the lower portion 61 are inclined with respect to the direction Z. The upper portion 62 includes an end 62a protruding from the side surface 61a and an end 62b protruding from the side surface 61b.

[0076] The protrusion amount D of the end portions 62a and 62b from the side surfaces 61a and 61b (hereinafter, referred to as the protrusion amount D of the partition wall 6) is, for example, 2.0 μm or less. The protrusion amount D of the partition wall 6 in the present embodiment corresponds to the distance between the lower end (blocking layer 611) of the side surfaces 61a and 61b and the end portions 62a and 62b in the width direction (first direction X or second direction Y) orthogonal to the third direction Z of the partition wall 6.

[0077] In addition, Figure 5 In the example shown, the side surface of the blocking layer 611 is aligned with the side surface of the metal layer 612 to form a plane without steps, but for example, the side surface of the blocking layer 611 may be slightly retreated relative to the side surface of the metal layer 612, or may protrude relative to the side surface of the metal layer 612. Figure 5 In the embodiment, the side surfaces of the blocking layer 611 and the metal layer 612 (that is, the side surfaces 61a and 61b of the lower portion 61) are inclined relative to the third direction Z, but the side surfaces may also be parallel to the third direction Z.

[0078] The structure of the partition wall 6 and the material of each part of the partition wall 6 can be appropriately selected in consideration of, for example, the method of forming the partition wall 6 .

[0079] Here, in this embodiment, the partition wall 6 is formed to divide the sub-pixel SP in a plan view. The organic layer OR is formed by, for example, an anisotropic or directional vacuum deposition method. However, when an organic material for forming the organic layer OR is deposited on the entire substrate 10 with the partition wall 6 disposed, the partition wall 6 has Figure 4 as well as Figure 5 Since the shape shown is shown, the organic layer OR is hardly formed on the side surface of the partition wall 6. Thus, the organic layer OR (display element) partitioned for each sub-pixel SP can be formed by the partition wall 6.

[0080] Figure 6 to Figure 8 6 is a schematic cross-sectional view for explaining a display element formed by using the partition wall 6. Figure 6 to Figure 8 In the figure, the substrate 10, the insulating layer 11 and the circuit layer 12 are omitted. Figure 6 to Figure 8 The sub-pixels SPα, SPβ, and SPγ shown correspond to any of the sub-pixels SP1, SP2, and SP3.

[0081] First, as described above, in the state where the partition wall 6 is arranged, Figure 6 As shown, an organic layer OR, an upper electrode UE, a cap layer CP, and a sealing layer SE are sequentially formed by evaporation relative to the entire substrate 10. The organic layer OR includes a light-emitting layer that emits light of a color corresponding to the sub-pixel SPα. The organic layer OR is separated into a first organic layer ORa that passes through the opening AP and contacts the lower electrode LE and a second organic layer Orb on the partition wall 6 by a suspended partition wall 6, the upper electrode UE is separated into a first upper electrode UEa that covers the first organic layer Ora and a second upper electrode UEb that covers the second organic layer Orb, and the cap layer CP is separated into a first cap layer CPa that covers the first upper electrode UEa and a second cap layer CPb that covers the second upper electrode UEb. The first upper electrode UEa contacts the lower portion 61 of the partition wall 6. The sealing layer SE continuously covers the first cap layer CPa, the second cap layer CPb, and the partition wall 6.

[0082] Next, if Figure 7 As shown in FIG. 1 , a resist R is formed on the sealing layer SE. The resist R covers the sub-pixel SPα. That is, the resist R is arranged directly above the first organic layer ORa, the first upper electrode UEa, and the first cover layer CPa located in the sub-pixel SPα. The resist R is also located directly above the second organic layer ORb, the second upper electrode UEb, and the second cover layer CPb on the partition wall 6 between the sub-pixel SPα and the sub-pixel SPβ, which are close to the sub-pixel SPα. That is, at least a portion of the partition wall 6 is exposed from the resist R.

[0083] Furthermore, by etching with the resist R as a mask, as Figure 8 As shown, the exposed portions of the organic layer OR, the upper electrode UE, the cap layer CP, and the sealing layer SE from the resist R are removed. Thus, a display element including the lower electrode LE, the first organic layer ORa, the first upper electrode UEa, and the first cap layer CPa is formed in the sub-pixel SPα. On the other hand, in the sub-pixels SPβ and SPγ, the lower electrode LE is exposed. In addition, the above-mentioned etching includes, for example, dry etching of the sealing layer SE, wet etching and dry etching of the cap layer CP, wet etching of the upper electrode UE, and dry etching of the organic layer OR.

[0084] When the display element of the sub-pixel SPα is formed as described above, the resist R is removed, and the display elements of the sub-pixels SPβ and SPγ are sequentially formed in the same manner as the sub-pixel SPα.

[0085] As described above for the sub-pixels SPα, SPβ, and SPγ, display elements of the sub-pixels SP1, SP2, and SP3 are formed, and further, the resin layer 14, the sealing layer 15, and the resin layer 16 are formed, thereby achieving Figure 4 The structure of the display device DSP is shown.

[0086] Here, it is assumed that the display device DSP of the present embodiment is used by being embedded in an electronic device such as a smartphone together with a camera.

[0087] Fig. 91 is a top view showing a part of an electronic device in which the display device DSP (display panel) of the present embodiment is embedded. As described above, in the display device DSP, the display area DA has a plurality of pixels PX (sub-pixels SP1, SP2, and SP3) arranged in a matrix in the first direction X and the second direction Y. In addition, the display device DSP has a display surface having the display area DA and a back surface opposite to the display surface (hereinafter referred to as the back surface of the display device DSP). In the electronic device in which the display device DSP of the present embodiment is embedded, it is assumed that a camera 100 for capturing an image is arranged on the back side of the display device DSP.

[0088] In this case, if Fig. 9 As shown, in order to enlarge the display area DA in the electronic device (display device DSP) (enlarge the range of the display area DA), it is considered to configure the camera 100 at a position overlapping with the display area DA (that is, multiple pixels PX).

[0089] Here, the sub-pixels SP (SP1, SP2, and SP3) arranged in the display area DA have a pixel circuit for driving the display element, and it is assumed that the pixel circuit is, for example, a 7Tr1C pixel circuit composed of seven transistors (Tr) and one holding capacitor (C). In this case, Fig.10 As shown, a pixel circuit 200 is configured in an area occupying most of the sub-pixels SP1, SP2 and SP3 when viewed from above. Due to the influence of the pixel circuit 200, the light transmittance of the area overlapping with the camera 100 (that is, the area including the pixel PX) is reduced, and there is a possibility that insufficient light is incident on the camera 100 (the imaging element therein) via the display device DSP.

[0090] In this case, for example, consider removing pixels PX in the area overlapping with the camera 100. However, only removing pixels PX may reduce the resolution of the area overlapping with the camera 100, and the display quality of the display device DSP may be reduced.

[0091] Therefore, in the present embodiment, the following configuration is adopted: with respect to the area DA1 (hereinafter referred to as the first display area DA1) which does not overlap with the camera 100 in the display area DA. Fig.10 The pixel circuit 200 (7Tr1C pixel circuit) shown in FIG. 1 is used to drive the display element. In the area DA2 (hereinafter referred to as the second display area DA2) overlapping with the camera 100 in the display area DA, as shown in FIG. Fig.11 As shown, for example, a pixel circuit 210 (4Tr1C pixel circuit) composed of four transistors and one holding capacitor is configured to drive the display element.

[0092] In the case of such a configuration, the pixel circuit 210 (4Tr1C pixel circuit) arranged in the second display area DA2 is simpler than the pixel circuit 200 (7Tr1C pixel circuit) arranged in the first display area DA1. Fig.11 As shown, in the second display area DA2, the area occupied by the pixel circuit 210 can be reduced, and the transmissive portion 220 corresponding to the area with high light transmittance can be arranged.

[0093] also, Fig.12 It is along Fig.11 A schematic cross-sectional view of the display device DSP taken along line BB in FIG. Fig.12 As shown, the display element (lower electrode LE1, organic layer OR1 and upper electrode UE1), cover layer CP1 and sealing layer SE1 are arranged in the region overlapping with the pixel circuit 210 (the region overlapping with the opening of the rib 5), but the display element, cover layer and sealing layer are not arranged in the region overlapping with the opening of the rib 5 in the transmission part 220. Fig.12 The circuit layer 12 is disposed at a position overlapping with the transmission portion 220, and sometimes, for example, wiring connected to a sub-pixel SP disposed near the transmission portion 220 is disposed in the circuit layer 12, but no pixel circuit 210 is disposed. In the second display area DA2, the area overlapping with the pixel circuit 210 and the transmission portion 220 are divided by the ribs 5 and the partitions 6 in the same manner as the sub-pixel SP.

[0094] According to such a transmissive portion 220 , a high light transmittance can be achieved without being affected by a display element or the like.

[0095] Hereinafter, the pixel circuit 200 arranged in the first display area DA1 and the pixel circuit 210 arranged in the second display area DA2 in this embodiment will be described.

[0096] Fig.13 FIG. 2 shows an example of a circuit configuration of a pixel circuit 200 disposed in the first display area DA1. Fig.13 As shown, the pixel circuit 200 is a 7Tr1C pixel circuit composed of seven transistors (hereinafter referred to as first to seventh transistors) Tr1 to Tr7 and one holding capacitor Cst.

[0097] In the following description, Fig.13 One of the source / drain terminals of each of the first to seventh transistors Tr1 to Tr7 shown is set as the first terminal, and the other is set as the second terminal. Fig.13 One terminal of the storage capacitor Cst (capacitance element realizing the storage capacitor Cst) shown is set as a first terminal, and the other terminal is set as a second terminal.

[0098] The first terminal of the first transistor Tr1 is connected to the first terminal of the second transistor Tr2 and the second terminal of the fifth transistor Tr5 via the node n3. The second terminal of the first transistor Tr1 is connected to the data signal line that supplies the data signal Data. The data signal Data is equivalent to a signal (pixel signal) written to the pixel. In addition, the first transistor Tr1 is, for example, an n-channel transistor.

[0099] The second transistor Tr2 is equivalent to a driving transistor (DRT) that supplies current to the display element 20 included in the sub-pixel SP (that is, the display element 20 driven by the pixel circuit 200). The first terminal of the second transistor Tr2 is connected to the first terminal of the first transistor Tr1 and the second terminal of the fifth transistor Tr5 via the node n3. The second terminal of the second transistor Tr2 is connected to the second terminal of the third transistor Tr3, the first terminal of the fourth transistor Tr4, and the first terminal of the seventh transistor Tr7 via the node n1. In addition, the second transistor Tr2 is, for example, an n-channel transistor.

[0100] The first terminal of the third transistor Tr3 is connected to the gate terminal of the second transistor Tr2 and the second terminal of the holding capacitor Cst via the node n2. The second terminal of the third transistor Tr3 is connected to the second terminal of the second transistor Tr2, the first terminal of the fourth transistor Tr4, and the first terminal of the seventh transistor Tr7 via the node n1. In addition, the third transistor Tr3 is, for example, an n-channel transistor.

[0101] The first terminal of the fourth transistor Tr4 is connected to the second terminal of the second transistor Tr2, the second terminal of the third transistor Tr3, and the first terminal of the seventh transistor Tr7 via the node n1. The second terminal of the fourth transistor Tr4 is connected to a power line that supplies a power supply voltage VDDEL. In addition, the fourth transistor Tr4 is, for example, a p-channel transistor.

[0102] The first terminal of the fifth transistor Tr5 is connected to the anode terminal of the display element 20. In addition, the first terminal of the fifth transistor Tr5 is connected to the first terminal of the sixth transistor Tr6 and the first terminal of the holding capacitor Cts via the node n4. The second terminal of the fifth transistor Tr5 is connected to the first terminal of the first transistor Tr1 and the first terminal of the second transistor Tr2 via the node n3. In addition, the fifth transistor Tr5 is, for example, a p-channel transistor.

[0103] The first terminal of the sixth transistor Tr6 is connected to the first terminal of the fifth transistor Tr5, the first terminal of the holding capacitor Cst, and the anode terminal of the display element 20 via the node n4. The second terminal of the sixth transistor Tr6 is connected to a power supply line for supplying the initialization voltage Vini. The sixth transistor Tr6 is, for example, an n-channel transistor.

[0104] The first terminal of the seventh transistor Tr7 is connected to the second terminal of the second transistor Tr2, the second terminal of the third transistor Tr3, and the first terminal of the fourth transistor Tr4 via the node n1. The second terminal of the seventh transistor Tr7 is connected to a power line that supplies a power supply voltage VSH. In addition, the seventh transistor Tr7 is, for example, an n-channel transistor.

[0105] In addition, if Fig.13 As shown, the gate terminal of the first transistor Tr1 is connected to the gate signal line supplied with the gate signal Scan2. The gate terminal of the third transistor Tr3 is connected to the gate signal line supplied with the gate signal Scan1. The gate terminals of the fourth to sixth transistors Tr4 to Tr6 are connected to the control signal line supplied with the control signal EM. The gate terminal of the seventh transistor Tr7 is connected to the gate signal line supplied with the gate signal Scan3.

[0106] The first terminal of the storage capacitor Cst is connected to the first terminal of the fifth transistor Tr5, the first terminal of the sixth transistor Tr6, and the anode terminal of the display element 20 via the node n4. The second terminal of the storage capacitor Cst is connected to the gate terminal of the second transistor Tr2 and the first terminal of the third transistor Tr3 via the node n2.

[0107] The anode terminal of the display element 20 is connected to the first terminal of the fifth transistor Tr5. In addition, the anode terminal of the display element 20 is connected to the first terminal of the sixth transistor Tr6 and the first terminal of the holding capacitor Cst via the node n4. The cathode terminal of the display element 20 is connected to a power line that supplies the power supply voltage VSSEL. The above-mentioned power supply voltage VDDEL is equivalent to the anode voltage supplied to the display element 20, and the power supply voltage VSSEL is equivalent to the cathode voltage supplied to the display element 20.

[0108] Fig.14 FIG. 2 shows an example of a circuit configuration of the pixel circuit 210 disposed in the second display area DA2. Fig.14 As shown, the pixel circuit 210 is a 4Tr1C pixel circuit composed of four transistors (hereinafter referred to as first to fourth transistors) Tr1 to Tr4 and one holding capacitor Cst.

[0109] In the following description, Fig.14 One of the source / drain terminals of each of the first to fourth transistors Tr1 to Tr4 shown is set as the first terminal, and the other is set as the second terminal. Fig.14 One terminal of the storage capacitor Cst (capacitance element realizing the storage capacitor Cst) shown is set as a first terminal, and the other terminal is set as a second terminal.

[0110] The first terminal of the first transistor Tr1 is connected to the gate terminal of the second transistor Tr2 and the second terminal of the storage capacitor Cst via the node n1. The second terminal of the first transistor Tr1 is connected to a data signal line for supplying a data signal Data. The first transistor Tr1 is, for example, an n-channel transistor.

[0111] The second transistor Tr2 is equivalent to a driving transistor (DRT) that supplies current to the display element 20 included in the sub-pixel SP (that is, the display element 20 driven by the pixel circuit 210). The first terminal of the second transistor Tr2 is connected to the first terminal of the third transistor Tr3, the first terminal of the holding capacitor Cst, and the anode terminal of the display element 20 via the node n2. The second terminal of the second transistor Tr2 is connected to the first terminal of the fourth transistor Tr4. In addition, the second transistor Tr2 is, for example, an n-channel transistor.

[0112] The first terminal of the third transistor Tr3 is connected to the first terminal of the second transistor Tr2 and the anode terminal of the display element 20 via the node n2. In addition, the first terminal of the third transistor Tr3 is connected to the first terminal of the holding capacitor Cst. The second terminal of the third transistor Tr3 is connected to a power line that supplies the initialization voltage Vini. In addition, the third transistor Tr3 is, for example, an n-channel transistor.

[0113] The first terminal of the fourth transistor Tr4 is connected to the second terminal of the second transistor Tr2. The second terminal of the fourth transistor Tr4 is connected to a power supply line that supplies a power supply voltage VDDEL. The fourth transistor Tr4 is, for example, a p-channel transistor.

[0114] In addition, if Fig.14 As shown, the gate terminal of the first transistor Tr1 and the gate terminal of the third transistor Tr3 are connected to a gate signal line to which a gate signal Scan1 is supplied. The gate terminal of the fourth transistor Tr4 is connected to a control signal line to which a control signal EM is supplied.

[0115] The first terminal of the storage capacitor Cst is connected to the first terminal of the second transistor Tr2 and the anode terminal of the display element 20 via the node n2. In addition, the first terminal of the storage capacitor Cst is connected to the first terminal of the third transistor Tr3. The second terminal of the storage capacitor Cst is connected to the first terminal of the first transistor Tr1 and the gate terminal of the second transistor Tr2 via the node n1.

[0116] The anode terminal of the display element 20 is connected to the first terminal of the second transistor Tr2, the first terminal of the third transistor Tr3, and the first terminal of the storage capacitor Cst via the node n2. The cathode terminal of the display element 20 is connected to a power line supplying a power supply voltage VSSEL.

[0117] As described above, the display device DSP of the present embodiment includes a substrate 10, a plurality of sub-pixels SP (first pixels) arranged in a first display area DA1 included in a display area DA on the substrate 10, and a plurality of sub-pixels SP (second pixels) arranged in a second display area DA2 included in the display area DA, and the number of transistors constituting a pixel circuit 210 (second pixel circuit) included in the sub-pixels SP arranged in the second display area DA2 is less than the number of transistors constituting a pixel circuit 200 (first pixel circuit) included in the sub-pixels SP arranged in the first display area DA1.

[0118] In the present embodiment, the first display area DA1 is an area arranged at a position not overlapping with the camera 100 , and the second display area DA2 is an area arranged at a position overlapping with the camera 100 .

[0119] In this embodiment, according to the above-mentioned configuration, the area of ​​the area occupied by the pixel circuit 210 per unit area in the second display area DA2 can be made smaller than the area of ​​the area occupied by the pixel circuit 200 per unit area in the first display area DA1, thereby improving the light transmittance in the second display area DA2.

[0120] Specifically, the second display area DA2 can be provided with a transmissive portion 220, which corresponds to a region overlapping with the opening AP of the rib 5 and is a region where the pixel circuit 210, the display element (the lower electrode LE, the light-emitting layer OR, and the upper electrode UE), the cap layer CP, and the sealing layer SE are not formed. In such a transmissive portion 220, a high light transmittance can be achieved, and therefore, the light transmittance in the second display area DA2 can be improved.

[0121] In addition, in the present embodiment, it is not necessary to thin out the pixels PX (sub-pixels SP1 , SP2 , and SP3 ), and therefore, the resolution in the second display area DA2 does not decrease.

[0122] Here, Fig.15 Schematically shows the arrangement of various wirings connected to the pixel circuit 200 arranged in the first display area DA1 and the pixel circuit 210 arranged in the second display area DA2. Fig.15 In FIG. 1 , only a data signal line for supplying a data signal Data, a gate signal line for supplying gate signals Scan1 to Scan3 , a control signal line for supplying a control signal EM, and a power supply line for supplying an initialization voltage Vini are shown.

[0123] like Fig.15As shown, the data signal line for supplying the data signal Data is arranged in the first direction X so as to extend in the second direction Y. In addition, the gate signal line for supplying the gate signals Scan1 to Scan3, the control signal line for supplying the control signal EM, and the power supply line for supplying the initialization voltage Vini are arranged in the second direction Y so as to extend in the first direction X.

[0124] In this embodiment, the transmissive portion 220 is disposed in the second display area DA2 as described above. However, if a large number of wirings are formed in the transmissive portion 220 (in the circuit layer 12 ), the light transmittance in the transmissive portion 220 may decrease.

[0125] In contrast, for example, according to the above Fig.13 The pixel circuit 200 shown and Fig.14 In the pixel circuit 210 shown, for example, a gate signal line for supplying a gate signal Scan1, a control signal line for supplying a control signal EM, and a power line for supplying an initialization voltage Vini are shared by the pixel circuits 200 and 210. Therefore, as long as only the gate signal lines for supplying gate signals Scan2 and Scan3 are formed (configured) in the transmission portion 220, it is possible to suppress the light transmittance in the transmission portion 220 from being reduced due to the influence of the wiring connected to the pixel circuit 200.

[0126] In other words, in this embodiment, pixel circuits 200 and 210 are installed in such a manner that a portion of the plurality of wirings connected to pixel circuit 200 is connected to pixel circuit 210 (that is, more signals can be used in common), thereby further improving the light transmittance in the second display area DA2.

[0127] The following briefly describes the Fig.13 The pixel circuit 200 (7Tr1C pixel circuit) shown in FIG. Fig.14 The operation of the pixel circuit 210 (4Tr1C pixel circuit) is shown.

[0128] In addition, the plurality of transistors constituting the pixel circuits 200 and 210 include n-channel transistors and p-channel transistors, but the n-channel transistor is a switch element that becomes an off state (non-conducting state) when a low (level) signal is supplied to the gate terminal, and becomes a conducting state (conducting state) when a high (level) signal is supplied to the gate terminal. On the other hand, the p-channel transistor is a switch element that becomes an off state (non-conducting state) when a high (level) signal is supplied to the gate terminal, and becomes a conducting state (conducting state) when a low (level) signal is supplied to the gate terminal.

[0129] First, refer to Fig.16,illustrate Fig.13 The operation of the pixel circuit 200 is shown. Fig.16 It shows that Fig.15 The timing chart shows an output example of gate signals Scan1 to Scan3 and control signal EM of pixel circuits 200 arranged in n-1 and n rows (sub-pixels SP arranged in the first display area DA1). Here, the operation of the pixel circuits 200 arranged in the n-1 row will be described.

[0130] exist Fig.16 In the illustrated period t0 , the control signal EM is at a low level. Therefore, among the seven transistors included in the pixel circuit 200 , the fourth transistor Tr4 and the fifth transistor Tr5 are in an on state, and the sixth transistor Tr6 is in an off state.

[0131] Furthermore, in the period t0 , the gate signals Scan1 to Scan3 are at a low level, and therefore the first transistor Tr1 , the third transistor Tr3 , and the seventh transistor Tr7 are in an off state.

[0132] Thus, the state in which the current controlled by the gate voltage of the second transistor Tr2 (the voltage supplied to the gate terminal of the second transistor Tr2 based on the data signal Data of the previous frame) is supplied to the display element 20 (OLED) is maintained.

[0133] Furthermore, at the timing when the period t0 ends, the control signal EM is switched from the low level to the high level.

[0134] Next, in Fig.16 In the period t1 shown, the control signal EM is at a high level, so the fourth transistor Tr4 and the fifth transistor Tr5 are in an off state, and the sixth transistor Tr6 is in an on state. In this case, the initialization voltage Vini is supplied to the node n4 via the sixth transistor Tr6, but the initialization voltage Vini is set to a value at which no current flows through the display element 20, so no current flows through the display element 20 in the period t1.

[0135] In addition, at the timing of the start of period t1, the gate signal Scan1 is switched from a low level to a high level. Therefore, during period t1, the third transistor Tr3 is in an on state. Moreover, after the end of period t0 and before the start of period t1, the gate signal Scan3 is switched from a low level to a high level. Therefore, during period t1, the seventh transistor Tr7 is in an on state. Thus, the power supply voltage VSH is supplied to the gate terminal of the second transistor Tr2 via the seventh transistor Tr7 and the third transistor Tr3. In this case, a voltage of VSH-Vini is applied to the holding capacitor Cst (between the first and second terminals), and the information of the previous frame is reset.

[0136] Furthermore, at the timing when the period t1 ends, the gate signal Scan3 is switched from the high level to the low level.

[0137] Next, in Fig.16 At the timing of the start of the period t2 shown, the gate signal Scan2 is switched from a low level to a high level. Therefore, during the period t2, the first transistor Tr1 is in an on state. In addition, during the period t2, the gate signal Scan3 is at a low level, so the seventh transistor Tr7 is in an off state.

[0138] In this case, the data signal Data (voltage Vdata corresponding to the signal) and the threshold voltage Vth of the second transistor Tr2 (that is, a voltage equivalent to Vdata+Vth) are supplied to the gate terminal of the second transistor Tr2 via the first transistor Tr1, the second transistor Tr2, and the third transistor Tr3. As a result, a voltage of Vdata+Vth-Vini is applied to the holding capacitor Cst, and information related to Vdata and Vth is written into the holding capacitor Cst.

[0139] Furthermore, at the timing when the period t2 ends, the gate signal Scan1 is switched from the high level to the low level.

[0140] Next, in Fig.16 In the period t3 shown, the gate signal Scan1 is at a low level, so the third transistor Tr3 is in an off state. In addition, the gate signal Scan2 is switched from a high level to a low level before the period t3 starts, so the first transistor Tr1 is in an off state. Moreover, at the timing when the period t3 starts, the control signal EM is switched from a high level to a low level. Therefore, the fourth transistor Tr4 and the fifth transistor Tr5 are in an on state, and the sixth transistor Tr6 is in an off state.

[0141] Here, if the first terminal of the second transistor Tr2 is set as the source terminal, the voltage Vgs between the gate terminal and the source terminal (node ​​n2 to node n3) of the second transistor Tr2 becomes the voltage (Vdata+Vth-Vini) of the holding capacitor Cst. In this case, the second transistor Tr2 becomes conductive, and the current flows from the power line (the power line supplying the power supply voltage VDDEL) connected to the second terminal of the fourth transistor Tr4 to the node n4. Along with this, the potential of the node n4 begins to rise, and when the potential exceeds the threshold of the display element 20 (OLED), the circuit begins to flow to the display element 20, and the display element 20 begins to emit light. Finally, when the current Ioled flowing to the display element 20 reaches the output current (the output current in the saturation region of the second transistor Tr2) Idrt given from the second transistor Tr2, the potential of the node n4 stops rising, and the display element 20 becomes a stable light-emitting state.

[0142] Here, when the voltage Vgs=Vdata+Vth-Vini between the gate terminal and the source terminal of the second transistor Tr2 is substituted into the TFT saturation formula, Idrt=1 / 2Cox*μ*W / L*(Vgs-Vth) 2 When Idrt(=Ioled)=1 / 2Cox*μ*W / L*(Vdata-Vini) 2 In addition, Cox is the gate electrostatic capacitance per unit area, μ is the carrier mobility, W is the channel width of the second transistor Tr2, and L is the channel length of the second transistor Tr2.

[0143] It can be seen from this that Idrt is a value that does not depend on the threshold voltage Vth of the second transistor Tr2 (that is, a current that does not depend on the threshold voltage Vth of the second transistor Tr2 flows through the display element 20), and the influence of the variation in the threshold voltage Vth on Idrt can be eliminated.

[0144] Right now, Fig.13 The pixel circuit 200 (7Tr1C pixel circuit) shown has a function of correcting the variation of the threshold voltage Vth of the second transistor Tr2 (hereinafter referred to as Vth correction function). The Vth correction function is mainly realized by the first transistor Tr1 and the seventh transistor Tr7.

[0145] In addition, it is explained here that Fig.16 The operation of the pixel circuits 200 arranged in the n-1 row shown is similar to the operation of the pixel circuits 200 arranged in the n row, and therefore, a detailed description thereof is omitted here.

[0146] Next, refer to Fig.17 ,illustrate Fig.14The operation of the pixel circuit 210 is shown. Fig.17 It shows that Fig.15 1 is a timing chart showing an output example of the gate signal Scan1 and the control signal EM of the pixel circuits 210 arranged in the n-1 row (the sub-pixels SP arranged in the second display area DA2).

[0147] exist Fig.17 In the period t10 shown, the control signal EM is at a low level, so the fourth transistor Tr4 is turned on among the four transistors included in the pixel circuit 210. In addition, in the period t10, the gate signal Scan1 is at a low level, so the first transistor Tr1 and the third transistor Tr3 are turned off.

[0148] Thus, the state in which the current controlled by the gate voltage of the second transistor Tr2 (the voltage supplied to the gate terminal of the second transistor Tr2 based on the data signal Data of the previous frame) is supplied to the display element 20 (OLED) is maintained.

[0149] Furthermore, at the timing when the period t10 ends, the control signal EM is switched from the low level to the high level.

[0150] Next, in Fig.17 In the period t11 shown, the control signal EM is at a high level, so the fourth transistor Tr4 is in an off state. In this case, the current flowing through the display element 20 is zero.

[0151] In addition, at the timing when the period t11 starts, the gate signal Scan1 is switched from the low level to the high level. Therefore, in the period t11, the first transistor Tr1 and the third transistor Tr3 are turned on.

[0152] In this case, the initialization voltage Vini is supplied to the node n2 via the third transistor Tr3 . The initialization voltage Vini is set to a value at which no current flows through the display element 20 . Therefore, no current flows through the display element 20 during the period t11 .

[0153] Furthermore, a data signal Data (voltage Vdata corresponding to the signal) is supplied from the data signal line to the node n1 via the first transistor Tr1. As a result, a voltage of Vdata-Vini is applied to the storage capacitor Cst, and information related to Vdata is written into the storage capacitor Cst.

[0154] Furthermore, at the timing when the period t11 ends, the gate signal Scan1 is switched from the high level to the low level.

[0155] Next, in Fig.17In the period t12 shown, the gate signal Scan1 is at a low level, so the first transistor Tr1 and the third transistor Tr3 are in an off state. In addition, the timing control signal EM is switched from a high level to a low level at the beginning of the period t12, so the fourth transistor Tr4 is in an on state.

[0156] Here, if the first terminal of the second transistor Tr2 is set as the source terminal, the voltage Vgs between the gate terminal and the source terminal (node ​​n1 to node n2) of the second transistor Tr2 becomes the voltage (Vdata-Vini) of the holding capacitor Cst. In this case, the second transistor Tr2 becomes conductive, and current flows from the power line (power line supplying the power supply voltage VDDEL) connected to the second terminal of the fourth transistor Tr4 to the node n2. Along with this, the potential of the node n2 begins to rise, and when the potential exceeds the threshold of the display element 20 (OLED), current begins to flow to the display element 20, and the display element 20 begins to emit light. Finally, when the current Ioled flowing to the display element 20 reaches the output current Idrt given from the second transistor Tr2, the potential of the node n2 stops rising, and the display element 20 becomes a stable light-emitting state.

[0157] Here, if the voltage Vgs=Vdata-Vini between the gate terminal and the source terminal of the second transistor Tr2 is substituted into the TFT saturation formula, Idrt=1 / 2Cox*μ*W / L*(Vgs-Vth) 2 , then Idrt(=Ioled)=1 / 2Cox*μ*W / L*(Vdata-Vini-Vth) 2 .

[0158] It can be seen from this that Idrt is a value depending on the threshold voltage Vth of the second transistor Tr2 (that is, a current depending on the threshold voltage Vth of the second transistor Tr2 flows through the display element 20 ), and the variation of the threshold voltage Vth affects Idrt.

[0159] Right now, Fig.14 The pixel circuit 210 (4Tr1C pixel circuit) shown is Fig.13 The pixel circuit 200 shown is different and can be said to have no Vth correction function as described above.

[0160] In addition, in the pixel circuit 200 and the pixel circuit 210, even if the data signal Data (Vdata) is the same, Idrt (Ioled) is different depending on whether the Vth correction function is present, so a brightness difference may occur between the first display area DA1 and the second display area DA2. In this case, for example, a bias may be applied to the data signal Data (Vdata signal) for correction, thereby eliminating the brightness difference generated between the first display area DA1 and the second display area DA2.

[0161] In addition, according to the above Fig.16 as well as Fig.17 The pixel circuits 200 and 210 are driven by the gate signal Scan1 and the control signal EM output (supplied) at the same timing from the common gate signal line and the control signal line. In this embodiment, a part of a plurality of wirings is shared, and a combination of the pixel circuits 200 and 210 that can be driven by the signals supplied at the same timing is adopted, thereby reducing the number of wirings arranged in the transmission portion 220, and improving the light transmittance in the second display area DA2.

[0162] In addition, in this embodiment, the pixel circuit 200 arranged in the first display area DA1 is described as Fig.13 The pixel circuit 7Tr1C shown in the figure has a pixel circuit 210 configured in the second display area DA2. Fig.14 4Tr1C pixel circuit shown in the figure, but in order to improve the light transmittance in the second display area DA2, the pixel circuits 200 and 210 can be configured in such a way that the area occupied by the pixel circuit 210 per unit area is smaller than the area occupied by the pixel circuit 200. Specifically, the pixel circuit 210 can be configured with a smaller number of transistors than the pixel circuit 200, and the pixel circuits 200 and 210 are not limited to Fig.13 as well as Fig.14 The circuit configuration is shown.

[0163] Next, another example of the circuit configuration of the pixel circuits 200 and 210 will be described. Fig.13 as well as Fig.14 , a case where the driving transistor is an n-channel transistor is described. Here, a case where the driving transistor is a p-channel transistor is described.

[0164] Fig.18 FIG. 2 shows another example of the circuit configuration of the pixel circuit 200 disposed in the first display area DA1. Fig.18 As shown, the pixel circuit 200 is a 7Tr1C pixel circuit composed of seven transistors (hereinafter referred to as first to seventh transistors) and one holding capacitor Cst.

[0165] In the following description, Fig.18 One of the source / drain terminals of each of the first to seventh transistors Tr1 to Tr7 shown is set as the first terminal, and the other is set as the second terminal. Fig.18 One terminal of the storage capacitor Cst (capacitance element realizing the storage capacitor Cst) shown is set as a first terminal, and the other terminal is set as a second terminal.

[0166] The first terminal of the first transistor Tr1 is connected to the second terminal of the second transistor Tr2 and the second terminal of the fourth transistor via the node n1. The second terminal of the first transistor Tr1 is connected to a data signal line that supplies a data signal Data. The first transistor Tr1 is, for example, a p-channel transistor.

[0167] The second transistor Tr2 is equivalent to a driving transistor (DRT) that supplies current to the display element 20 included in the sub-pixel SP (that is, the display element 20 driven by the pixel circuit 200). The first terminal of the second transistor Tr2 is connected to the second terminal of the third transistor Tr3 and the second terminal of the fifth transistor Tr5 via the node n3. The second terminal of the second transistor Tr2 is connected to the first terminal of the first transistor Tr1 and the second terminal of the fourth transistor Tr4 via the node n1. In addition, the second transistor Tr2 is, for example, a p-channel transistor.

[0168] The first terminal of the third transistor Tr3 is connected to the gate terminal of the second transistor Tr2, the first terminal of the seventh transistor Tr7, and the second terminal of the holding capacitor Cst via the node n2. The second terminal of the third transistor Tr3 is connected to the first terminal of the second transistor Tr2 and the second terminal of the fifth transistor Tr5 via the node n3. In addition, the third transistor Tr3 is, for example, a p-channel transistor.

[0169] The first terminal of the fourth transistor Tr4 is connected to the first terminal of the first transistor Tr1 and the second terminal of the second transistor Tr2 via the node n1. The second terminal of the fourth transistor Tr4 is connected to the first terminal of the holding capacitor Cst. In addition, the second terminal of the fourth transistor Tr4 is connected to a power line that supplies a power supply voltage VDDEL. In addition, the fourth transistor Tr4 is, for example, a p-channel transistor.

[0170] The first terminal of the fifth transistor Tr5 is connected to the first terminal of the sixth transistor Tr6 and the anode terminal of the display element 20 via the node n4. The second terminal of the fifth transistor Tr5 is connected to the first terminal of the second transistor Tr2 and the second terminal of the third transistor Tr3 via the node n3. In addition, the fifth transistor Tr5 is, for example, a p-channel transistor.

[0171] The first terminal of the sixth transistor Tr6 is connected to the first terminal of the fifth transistor Tr5 and the anode terminal of the display element 20 via the node n4. The second terminal of the sixth transistor Tr6 is connected to the second terminal of the seventh transistor Tr7. In addition, the second terminal of the sixth transistor Tr6 is connected to a power supply line for supplying a reset voltage Vrst. In addition, the sixth transistor Tr6 is, for example, a p-channel transistor.

[0172] The first terminal of the seventh transistor Tr7 is connected to the gate terminal of the second transistor Tr2 and the first terminal of the third transistor Tr3 via the node n2. In addition, the first terminal of the seventh transistor Tr7 is connected to the second terminal of the holding capacitor Cst. The second terminal of the seventh transistor Tr7 is connected to the second terminal of the sixth transistor Tr6. In addition, the second terminal of the seventh transistor Tr7 is connected to a power supply line for supplying a reset voltage Vrst. In addition, the seventh transistor Tr7 is, for example, a p-channel transistor.

[0173] In addition, if Fig.18 As shown, the gate terminals of the first transistor Tr1, the third transistor Tr3, and the sixth transistor Tr6 are connected to the gate signal line supplied with the gate signal Scan2. The gate terminals of the fourth transistor Tr4 and the fifth transistor Tr5 are connected to the control signal line supplied with the control signal EM. The gate terminal of the seventh transistor Tr7 is connected to the gate signal line supplied with the gate signal Scan1.

[0174] The first terminal of the holding capacitor Cst is connected to the second terminal of the fourth transistor Tr4. In addition, the first terminal of the holding capacitor Cst is connected to a power supply line that supplies the power supply voltage VDDEL. The second terminal of the holding capacitor Cst is connected to the gate terminal of the second transistor Tr2 and the first terminal of the third transistor Tr3 via the node n2. In addition, the second terminal of the holding capacitor Cst is connected to the first terminal of the seventh transistor Tr7.

[0175] The anode terminal of the display element 20 is connected to the first terminal of the fifth transistor Tr5 and the first terminal of the sixth transistor Tr6 via the node n4. The cathode terminal of the display element 20 is connected to a power line that supplies the power supply voltage VSSEL. The power supply voltage VDDEL is equivalent to the anode voltage supplied to the display element 20, and the power supply voltage VSSEL is equivalent to the cathode voltage supplied to the display element 20.

[0176] Fig.19 FIG. 2 shows another example of the circuit configuration of the pixel circuit 210 disposed in the second display area DA2. Fig.19 As shown, the pixel circuit 210 is a 2Tr1C pixel circuit composed of two transistors (hereinafter referred to as first and second transistors) Tr1 and Tr2 and one holding capacitor Cst.

[0177] In the following description, Fig.19 In the first and second transistors Tr1 and Tr2 shown in FIG. 1 , one of the source / drain terminals is set as the first terminal, and the other is set as the second terminal. Fig.19 One terminal of the storage capacitor Cst (capacitance element realizing the storage capacitor Cst) shown is set as a first terminal, and the other terminal is set as a second terminal.

[0178] The first terminal of the first transistor Tr1 is connected to the gate terminal of the second transistor Tr2 and the second terminal of the storage capacitor Cst via the node n1. The second terminal of the first transistor Tr1 is connected to a data signal line for supplying a data signal Data. The first transistor Tr1 is, for example, a p-channel transistor.

[0179] The second transistor Tr2 is equivalent to a driving transistor (DRT) that supplies current to the display element 20 included in the sub-pixel SP (that is, the display element 20 driven by the pixel circuit 210). The first terminal of the second transistor Tr2 is connected to the anode terminal of the display element 20. The second terminal of the second transistor Tr2 is connected to the first terminal of the holding capacitor Cst. In addition, the second terminal of the second transistor Tr2 is connected to a power line that supplies a power supply voltage VDDEL. In addition, the second transistor Tr2 is, for example, a p-channel transistor.

[0180] In addition, if Fig.19 As shown, a gate terminal of the first transistor Tr1 is connected to a gate signal line to which a gate signal Scan2 is supplied.

[0181] The first terminal of the storage capacitor Cst is connected to the second terminal of the second transistor Tr2. In addition, the first terminal of the storage capacitor Cst is connected to a power line that supplies the power supply voltage VDDEL. The second terminal of the storage capacitor Cst is connected to the first terminal of the first transistor Tr1 and the gate terminal of the second transistor Tr2 via the node n1.

[0182] The anode terminal of the display element 20 is connected to the first terminal of the second transistor Tr2. The cathode terminal of the display element 20 is connected to a power supply line that supplies a power supply voltage VSSEL.

[0183] According to the above Fig.18 as well as Fig.19 In the circuit configuration shown, the number of transistors constituting the pixel circuit 210 configured in the second display area DA2 is smaller than the number of transistors constituting the pixel circuit 200 configured in the first display area DA1, and the transmissive portion 220 can be configured in the second display area DA2, thereby improving the light transmittance in the second display area DA2.

[0184] In addition, the first display area DA1 is provided with Fig.18 The pixel circuit 200 shown in the figure is provided in the second display area DA2. Fig.19 In the case of the pixel circuit 210 shown, Fig. 20 As shown, the gate signal line for supplying the gate signal Scan2 can be shared by the pixel circuits 200 and 210 .

[0185] The following briefly explains the above Fig.18 The pixel circuit 200 (7Tr1C pixel circuit) shown in FIG. Fig.19 The operation of the pixel circuit 210 (2Tr1C pixel circuit) is shown.

[0186] First, refer to Fig.21 ,illustrate Fig.18 The operation of the pixel circuit 200 is shown. Fig.21 It shows that Fig. 20 1 is a timing chart showing an output example of the gate signals Scan1 and Scan2 and the control signal EM of the pixel circuits 200 arranged in the n-1 row (the sub-pixels SP arranged in the first display area DA1).

[0187] exist Fig.21 In the illustrated period t20 , the control signal EM is at a low level, and therefore, the fourth transistor Tr4 and the fifth transistor Tr5 among the seven transistors included in the pixel circuit 200 are in an on state.

[0188] Furthermore, in the period t20 , the gate signals Scan1 and Scan2 are at the high level, and therefore the first transistor Tr1 , the third transistor Tr3 , the sixth transistor Tr6 , and the seventh transistor Tr7 are in the off state.

[0189] Thus, the state in which the current controlled by the gate voltage of the second transistor Tr2 (the voltage supplied to the gate terminal of the second transistor Tr2 based on the data signal Data of the previous frame) is supplied to the display element 20 (OLED) is maintained.

[0190] Furthermore, at the timing when the period t20 ends, the control signal EM is switched from the low level to the high level.

[0191] Next, in Fig.21 In the illustrated period t21, the control signal EM is at a high level, so the fourth transistor Tr4 and the fifth transistor Tr5 are in an off state. In this case, the current flowing through the display element 20 is zero.

[0192] In addition, at the timing when the period t21 starts, the gate signal Scan1 is switched from the high level to the low level. Therefore, in the period t21, the seventh transistor Tr7 is turned on.

[0193] In this case, the reset voltage Vrst is supplied to the gate terminal of the second transistor Tr2 via the seventh transistor Tr7. In addition, a voltage of Vrst-VDDEL is applied to the storage capacitor Cst, and the information of the previous frame is reset.

[0194] Furthermore, at the timing when the period t21 ends, the gate signal Scan1 is switched from the low level to the high level.

[0195] Next, in Fig.21 In the period t22 shown, the gate signal Scan1 is at a high level, so the seventh transistor Tr7 is in an off state. In addition, at the timing when the period t22 starts, the gate signal Scan2 is switched from a high level to a low level. Therefore, the first transistor Tr1, the third transistor Tr3, and the sixth transistor Tr6 are in an on state.

[0196] In this case, the data signal Data (voltage Vdata corresponding to the signal) and the threshold voltage Vth of the second transistor Tr2 (that is, a voltage equivalent to Vdata+Vth) are supplied to the gate terminal of the second transistor Tr2 via the first transistor Tr1, the second transistor Tr2, and the third transistor Tr3. As a result, a voltage of Vdata+Vth-VDDEL is applied to the storage capacitor Cst, and information related to Vdata and Vth is written into the storage capacitor Cst.

[0197] In addition, the reset voltage Vrst is supplied to the node n4 (the anode terminal of the display element 20) via the sixth transistor Tr6, and the anode is reset.

[0198] Furthermore, at the timing when the period t22 ends, the gate signal Scan2 is switched from the low level to the high level.

[0199] Next, in Fig.21 In the period t23 shown, the gate signal Scan2 is at a high level, so the first transistor Tr1, the third transistor Tr3, and the sixth transistor Tr6 are in an off state. In addition, the timing control signal EM starting at the period t23 is switched from a high level to a low level. Therefore, the fourth transistor Tr4 and the fifth transistor Tr5 are in an on state.

[0200] Here, if the second terminal of the second transistor Tr2 is set as the source terminal, the voltage Vgs between the gate terminal and the source terminal (node ​​n1 to node n2) of the second transistor Tr2 becomes the voltage (Vdata+Vth-VDDEL) of the holding capacitor Cst. In this case, the second transistor Tr2 becomes conductive, and current flows from the power line (power line supplying the power supply voltage VDDEL) connected to the second terminal of the fourth transistor Tr4 to the node n4. Along with this, the potential of the node n4 begins to rise, and when the potential exceeds the threshold of the display element 20 (OLED), current begins to flow to the display element 20, and the display element 20 begins to emit light. Finally, when the current Ioled flowing through the display element 20 reaches the output current (output current in the saturation region of the second transistor Tr2) Idrt given by the second transistor Tr2, the potential of the node n4 stops rising, and the display element 20 becomes a stable light-emitting state.

[0201] Here, when the voltage Vgs=Vdata+Vth-VDDEL between the gate terminal and the source terminal of the second transistor Tr2 is substituted into the TFT saturation formula, Idrt=1 / 2Cox*μ*W / L*(Vgs-Vth) 2 When Idrt(=Ioled)=1 / 2Cox*μ*W / L*(Vdata-VDDEL) 2 .

[0202] It can be seen from this that Idrt is a value that does not depend on the threshold voltage Vth of the second transistor Tr2 (that is, a current that does not depend on the threshold voltage Vth of the second transistor Tr2 flows through the display element 20), and the influence of the variation in the threshold voltage Vth on Idrt can be eliminated.

[0203] Right now, Fig.18 The pixel circuit 200 (7Tr1C pixel circuit) shown can be said to have a function of correcting the variation in the threshold voltage Vth of the second transistor Tr2 (Vth correction function).

[0204] Next, refer to Fig. 22 ,illustrate Fig.19 The operation of the pixel circuit 210 is shown. Fig. 22 It is shown that for Fig. 20 1 is a timing chart showing an output example of the gate signal Scan2 of the pixel circuits 210 arranged in the n-1 row (the sub-pixels SP arranged in the second display area DA2).

[0205] exist Fig. 22 In the illustrated period t30 , the gate signal Scan2 is at a high level, and therefore, the first transistor Tr1 of the two transistors included in the pixel circuit 210 is in an off state.

[0206] Thus, the state in which the current controlled by the gate voltage of the second transistor Tr2 (the voltage supplied to the gate terminal of the second transistor Tr2 based on the data signal Data of the previous frame) is supplied to the display element 20 (OLED) is maintained.

[0207] Next, in Fig. 22 At the timing when the period t31 shown starts, the gate signal Scan2 is switched from the high level to the low level. Therefore, in the period t31, the first transistor Tr1 is in the on state.

[0208] In this case, a data signal Data (a voltage Vdata corresponding to the signal) is supplied from the data signal line to the node n1 via the first transistor Tr1. Thus, if the second terminal of the second transistor Tr2 is set as the source terminal, a voltage of Vdata-VDDEL is applied to the storage capacitor Cst (between the gate terminal and the source terminal of the second transistor Tr2), and information related to Vdata is written into the storage capacitor Cst.

[0209] Furthermore, at the timing when the period t31 ends, the gate signal Scan1 is switched from the low level to the high level.

[0210] Next, in Fig. 22 During the period t32 shown, the gate signal Scan2 is at a high level, so the first transistor Tr1 is in the off state. In this case, the voltage Vgs between the gate terminal and the source terminal of the second transistor Tr2 becomes the voltage (Vdata-VDDEL) of the holding capacitor Cst. In this case, the second transistor Tr2 becomes the on state, and current flows from the power line (the power line that supplies the power supply voltage VDDEL) connected to the second terminal (source terminal) of the second transistor Tr2 to the anode terminal of the display element 20. Along with this, the potential of the node between the first terminal (drain terminal) of the second transistor Tr2 and the anode terminal of the display element 20 begins to rise. When the potential exceeds the threshold of the display element 20 (OLED), current begins to flow to the display element 20, and the display element 20 begins to emit light. Finally, when the current Ioled flowing through the display element 20 reaches the output current Idrt given by the second transistor Tr2, the potential of the node between the first terminal (drain terminal) of the second transistor Tr2 and the anode terminal of the display element 20 stops rising, and the display element 20 enters a stable light-emitting state.

[0211] Here, if the voltage Vgs=Vdata-VDDEL between the gate terminal and the source terminal of the second transistor Tr2 is substituted into the TFT saturation formula, Idrt=1 / 2Cox*μ*W / L*(Vgs-Vth) 2, then Idrt(=Ioled)=1 / 2Cox*μ*W / L*(Vdata-VDDEL-Vth) 2 .

[0212] As can be seen from this, Idrt is a value that depends on the threshold voltage Vth of the second transistor Tr2 (that is, a current that depends on the threshold voltage Vth of the second transistor Tr2 flows through the display element 20 ), and the variation in the threshold voltage Vth affects Idrt.

[0213] Right now, Fig.19 The pixel circuit 210 (2Tr1C pixel circuit) shown in FIG. Fig.18 The pixel circuit 200 shown is different and can be said to have no Vth correction function as described above.

[0214] In addition, according to the above Fig.21 as well as Fig. 22 , the pixel circuits 200 and 210 are driven by the gate signal Scan2 output (supplied) at the same timing from the common gate signal line. Fig.18 The pixel circuit 200 shown and Fig.19 The combination of the pixel circuits 210 shown can also improve the light transmittance in the second display area DA2.

[0215] In addition, in this embodiment, it is assumed that the camera 100 (the imaging element included therein) is disposed on the back of the display device DSP, but this embodiment can be applied to a case where a sensor including a light receiving element that converts incident light into an electrical signal or a device having the sensor is disposed on the back of the display device DSP. That is, the DSP of this embodiment only needs to be configured to increase the light transmittance in a predetermined area of ​​the display area DA, and is not limited to being disposed on the back of the display device DSP.

[0216] Any display device implemented by a person skilled in the art after appropriately changing the design based on the display device described above as the embodiment of the present invention belongs to the scope of the present invention as long as it includes the gist of the present invention.

[0217] In the scope of the concept of the present invention, those skilled in the art can think of various variations, and it should be understood that these variations also belong to the scope of the present invention. For example, variations obtained by those skilled in the art appropriately adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes relative to the above-mentioned embodiments are also included in the scope of the present invention as long as they have the gist of the present invention.

[0218] In addition, other effects brought about by the forms described in the above embodiments that are clearly derived from the description of this specification or that can be appropriately thought of by a person skilled in the art should of course be understood to be brought about by the present invention.

Claims

1. A display device, characterized in that: have: Base material; A plurality of first pixels are arranged in a first area included in the display area on the substrate; and a plurality of second pixels arranged in a second area different from the first area and included in the display area, Each of the plurality of first pixels includes a first pixel circuit formed of a plurality of transistors and a first display element driven by the first pixel circuit. Each of the plurality of second pixels includes a second pixel circuit formed of a plurality of transistors and a second display element driven by the second pixel circuit. The number of transistors constituting the second pixel circuit is smaller than the number of transistors constituting the first pixel circuit.

2. The display device according to claim 1, characterized in that The second region is arranged at a position overlapping with a light receiving element that receives light via the display device.

3. The display device according to claim 1, characterized in that The first pixel circuit includes a transistor for realizing a function of correcting a variation in a threshold voltage of a driving transistor that supplies current to the first display element, among a plurality of transistors constituting the first pixel circuit. The second pixel circuit does not include a transistor for realizing a function of correcting a variation in a threshold voltage of a driving transistor that supplies current to the second display element, among a plurality of transistors constituting the second pixel circuit.

4. The display device according to claim 1, characterized in that A part of the plurality of wirings connected to the first pixel circuit is connected to the second pixel circuit.

5. The display device according to claim 1, characterized in that An area of ​​a region occupied by the second pixel circuit per unit area of ​​the second region is smaller than an area of ​​a region occupied by the first pixel circuit per unit area of ​​the first region.

6. The display device according to claim 1, characterized in that: Also available: ribs; and next door, The first display element and the second display element are composed of a lower electrode, an organic layer and an upper electrode. The lower electrode is disposed on the substrate. The rib has an opening overlapping with the lower electrode, The partition wall has a lower portion disposed on the rib portion and an upper portion protruding from a side surface of the lower portion. The organic layer passes through the opening to contact the lower electrode, The upper electrode is configured on the organic layer.

7. The display device according to claim 6, characterized in that: Also available: a cap layer disposed on the upper electrode; and A sealing layer is disposed on the cover layer.

8. The display device according to claim 7, characterized in that: In the second region, a region overlapping with the opening of the rib is arranged, and this region is a region where the second pixel circuit, the second display element, the cap layer, and the sealing layer are not formed.

9. A display device, characterized in that: have: Base material; A plurality of first pixels are arranged in a first area included in the display area on the substrate; and a plurality of second pixels arranged in a second area different from the first area and included in the display area, Each of the plurality of first pixels includes a first display element and a first pixel circuit for driving the first display element. Each of the plurality of second pixels includes a second display element and a second pixel circuit for driving the second display element. An area of ​​a region occupied by the second pixel circuit per unit area of ​​the second region is smaller than an area of ​​a region occupied by the first pixel circuit per unit area of ​​the first region.

10. The display device according to claim 9, characterized in that: The second region is arranged at a position overlapping with a light receiving element that receives light via the display device.

11. The display device according to claim 9, characterized in that The first pixel circuit includes a transistor for realizing a function of correcting a variation in a threshold voltage of a driving transistor that supplies current to the first display element, among a plurality of transistors constituting the first pixel circuit. The second pixel circuit does not include a transistor for realizing a function of correcting a variation in a threshold voltage of a driving transistor that supplies current to the second display element, among a plurality of transistors constituting the second pixel circuit.

12. The display device according to claim 9, characterized in that: A part of the plurality of wirings connected to the first pixel circuit is connected to the second pixel circuit.

13. The display device according to claim 9, characterized in that: Also available: ribs; and next door, The first display element and the second display element are composed of a lower electrode, an organic layer and an upper electrode. The lower electrode is disposed on the substrate. The rib has an opening overlapping with the lower electrode, The partition wall has a lower portion disposed on the rib portion and an upper portion protruding from a side surface of the lower portion. The organic layer passes through the opening to contact the lower electrode, The upper electrode is configured on the organic layer.

14. The display device according to claim 13, characterized in that: Also available: a cap layer disposed on the upper electrode; and A sealing layer is disposed on the cover layer.

15. The display device according to claim 14, characterized in that: In the second region, a region overlapping with the opening of the rib is arranged, and this region is a region where the second pixel circuit, the second display element, the cap layer, and the sealing layer are not formed.

Images