Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, the display panel comprises a substrate and a plurality of pixel circuits located on one side of the substrate, and each pixel circuit comprises a first type transistor and a first storage capacitor; the first type transistor comprises a first active layer and a first grid electrode, the first active layer comprises oxide, and the first grid electrode is located on the side, away from the substrate, of the first active layer; the first storage capacitor comprises a first capacitor plate and a second capacitor plate which are arranged in a laminated mode, and the first capacitor plate or the second capacitor plate and the first grid electrode are arranged on the same layer. The setting position of the capacitor plate in the first storage capacitor is adjusted, specifically, the first capacitor plate or the second capacitor plate in the first storage capacitor is adjusted to be arranged on the same layer as the first grid electrode in the first type transistor, the overall film layer thickness of the display panel can be reduced, and the process preparation cost of the display panel can also be reduced.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, display panels have been widely used in people's production and daily life. In order to better meet people's needs, the display panel can be adjusted, such as by adjusting some of the film layer structures, thereby improving the overall effect of the display panel. Summary of the Invention

[0003] This invention provides a display panel and a display device. By adjusting the first capacitor plate or the second capacitor plate in the first storage capacitor to be disposed in the same layer as the first gate in the first type of transistor, it is beneficial to reduce the overall film thickness of the display panel and also to reduce the manufacturing cost of the display panel.

[0004] In a first aspect, embodiments of the present invention provide a display panel, including a substrate and a plurality of pixel circuits located on one side of the substrate, wherein the pixel circuits include a first type of transistor and a first storage capacitor;

[0005] The first type of transistor includes a first active layer and a first gate, the first active layer includes an oxide, and the first gate is located on the side of the first active layer away from the substrate;

[0006] The first storage capacitor includes a first capacitor plate and a second capacitor plate stacked together, wherein the first capacitor plate or the second capacitor plate is disposed in the same layer as the first gate.

[0007] In a second aspect, embodiments of the present invention provide a display device including the display panel described in the first aspect.

[0008] This invention provides a display panel in which the pixel circuit includes a first type of transistor and a first storage capacitor. The first type of transistor includes a first active layer and a first gate, and the first storage capacitor includes a first capacitor plate and a second capacitor plate. In the first type of transistor, the first gate is located on the side of the first active layer away from the substrate. Furthermore, by configuring a portion of the structure in the first type of transistor and a portion of the structure in the first storage capacitor in the same layer, specifically by configuring either the first capacitor plate or the second capacitor plate in the same layer as the first gate, the overall film thickness of the pixel circuit can be reduced, which is beneficial for achieving a thinner display panel design and reducing the manufacturing cost of the display panel. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of exemplary embodiments of the present invention, the accompanying drawings used in describing the embodiments are briefly introduced below. Obviously, the accompanying drawings described are only a portion of the drawings of the embodiments to be described in this invention, and not all of the drawings. For those skilled in the art, other drawings can be obtained from these drawings without any creative effort.

[0010] Figure 1 This is a schematic diagram of the structure of the first type of display panel provided in an embodiment of the present invention;

[0011] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0012] Figure 3 The embodiment of the present invention provides Figure 2 The diagram shown illustrates the driving timing of the pixel circuit during one driving cycle.

[0013] Figure 4 This is a schematic diagram of the film structure of the first pixel circuit provided in the embodiment of the present invention;

[0014] Figure 5 This is a schematic diagram of the film layer structure of the first type of display panel provided in the embodiments of the present invention;

[0015] Figure 6 yes Figure 5 A schematic diagram of the first part of the structure;

[0016] Figure 7 yes Figure 5 A schematic diagram of the second part of the structure;

[0017] Figure 8 yes Figure 5 A schematic diagram of the third part of the structure;

[0018] Figure 9 yes Figure 5 A schematic diagram of the fourth part of the structure;

[0019] Figure 10 yes Figure 5 A schematic diagram of the fifth part of the structure;

[0020] Figure 11 yes Figure 5 A schematic diagram of the sixth part of the structure;

[0021] Figure 12 yes Figure 5 A schematic diagram of the seventh part of the structure;

[0022] Figure 13 yes Figure 5 A schematic diagram of the structure from the first part to the seventh part.

[0023] Figure 14 yes Figure 5 A schematic diagram of the eighth part of the structure;

[0024] Figure 15 yes Figure 5 A schematic diagram of the ninth part of the structure;

[0025] Figure 16 yes Figure 5 Schematic diagrams of the eighth and ninth parts of the structure;

[0026] Figure 17 This is a schematic diagram of the film layer structure of the second type of display panel provided in an embodiment of the present invention;

[0027] Figure 18 yes Figure 17 A schematic diagram of the first part of the structure;

[0028] Figure 19 yes Figure 17 A schematic diagram of the second part of the structure;

[0029] Figure 20 yes Figure 17 A schematic diagram of the third part of the structure;

[0030] Figure 21 yes Figure 17 A schematic diagram of the fourth part of the structure;

[0031] Figure 22 yes Figure 17 A schematic diagram of the fifth part of the structure;

[0032] Figure 23 yes Figure 17 A schematic diagram of the sixth part of the structure;

[0033] Figure 24 yes Figure 17 A schematic diagram of the seventh part of the structure;

[0034] Figure 25 yes Figure 17 A schematic diagram of the structure from the first part to the seventh part.

[0035] Figure 26 yes Figure 17 A schematic diagram of the eighth part of the structure;

[0036] Figure 27 yes Figure 17 A schematic diagram of the ninth part of the structure;

[0037] Figure 28 yes Figure 17 Schematic diagrams of the eighth and ninth parts of the structure;

[0038] Figure 29 This is a schematic diagram of the film structure of the second pixel circuit provided in an embodiment of the present invention;

[0039] Figure 30 This is a schematic diagram of the film layer structure of the third type of display panel provided in the embodiments of the present invention;

[0040] Figure 31 yes Figure 30 A schematic diagram of the first part of the structure;

[0041] Figure 32 yes Figure 30 A schematic diagram of the second part of the structure;

[0042] Figure 33 yes Figure 30 A schematic diagram of the third part of the structure;

[0043] Figure 34 yes Figure 30 A schematic diagram of the fourth part of the structure;

[0044] Figure 35 yes Figure 30 A schematic diagram of the fifth part of the structure;

[0045] Figure 36 yes Figure 30 A schematic diagram of the sixth part of the structure;

[0046] Figure 37 yes Figure 30 A schematic diagram of the eighth part of the structure;

[0047] Figure 38 yes Figure 30 A schematic diagram of the structure from the first part to the eighth part;

[0048] Figure 39 yes Figure 30 Schematic diagrams of the seventh and eighth parts of the structure;

[0049] Figure 40 yes Figure 30 A schematic diagram of the ninth part of the structure;

[0050] Figure 41 yes Figure 30 A schematic diagram of the tenth part of the structure;

[0051] Figure 42 This is a schematic diagram of the structure of the second type of display panel provided in an embodiment of the present invention;

[0052] Figure 43 yes Figure 42 Schematic diagram of the first type of partial membrane structure;

[0053] Figure 44 yes Figure 42 Schematic diagram of the second type of membrane structure;

[0054] Figure 45 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0055] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0056] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a system, product, or device comprising a series of units is not necessarily limited to those steps or units explicitly listed, but may include other units not explicitly listed or inherent to such products or devices.

[0057] Figure 1 This is a schematic diagram of the structure of the first type of display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 3 The embodiment of the present invention provides Figure 2 The diagram shown illustrates the driving timing of the pixel circuit within one driving cycle. Figure 4 This is a schematic diagram of the film layer structure of the first pixel circuit provided in the embodiment of the present invention, for reference. Figures 1 to 4 As shown, an embodiment of the present invention provides a display panel 10, which includes a substrate 100 and a plurality of pixel circuits 200 located on one side of the substrate 100. The pixel circuits 200 include a first type transistor 210 and a first storage capacitor 220. The first type transistor 210 includes a first active layer 211 and a first gate 212. The first active layer 211 includes oxide, and the first gate 212 is located on the side of the first active layer 211 away from the substrate 100. The first storage capacitor 220 includes a first capacitor plate 221 and a second capacitor plate 222 stacked together. The first capacitor plate 221 or the second capacitor plate 222 is disposed on the same layer as the first gate 212.

[0058] For details, please refer to Figure 1 As shown, the display panel 10 includes a pixel circuit 200, which is electrically connected to the light-emitting element 400 in the display panel 10 to drive the light-emitting element 400 and ensure that the light-emitting element 400 emits light for display.

[0059] The pixel circuits 200 can be configured in various ways, resulting in a variety of display panel 10 configurations. For example, refer to... Figure 2 As shown, the pixel circuit 200 is illustrated using a "6T1C" configuration. Based on the arrangement of the pixel circuit 200, those skilled in the art can make adaptive adjustments according to their needs. Optionally, refer to... Figure 2 As shown, the pixel circuit 200 may include a second light-emitting control transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, an initialization transistor T6, and a storage capacitor Cst. Optionally, the types of transistors in the pixel circuit 200 can be diverse. For example, the transistors may include low-temperature polysilicon (LTPS) transistors, which have advantages such as high switching speed, high carrier mobility, and low power consumption. The transistors may also include indium gallium zinc oxide (IGZO) transistors, which have advantages such as low leakage current. For example, in... Figure 2 In this example, the threshold compensation transistor T2, the driving transistor T3, and the initialization transistor T6 are oxide transistors, while the remaining transistors are low-temperature polysilicon transistors.

[0060] Specifically, for Figure 2 The timing operation of the provided pixel circuit 200 is referenced. Figure 3 For example, the first light-emitting control signal line (shown as EM1 in the figure), electrically connected to the control terminal of the second light-emitting control transistor T1, can control the second light-emitting control transistor T1 to turn on or off. The first scan signal line (shown as SN in the figure), electrically connected to the control terminal of the threshold compensation transistor T2, can control the threshold compensation transistor T2 to turn on or off. The third scan signal line (shown as SPX in the figure), electrically connected to the control terminal of the initialization transistor T6, can control the initialization transistor T6 to turn on or off. During the reset phase Ta of the pixel circuit 200, the first light-emitting control signal line (shown as EM1 in the figure) controls the second light-emitting control transistor T1 to turn on (at this time, the scan signal line connected to the control terminal of the second light-emitting control transistor T1 is at the enable level). Figure 2(Shown as low level in the diagram), the scan signal line (shown as SN in the diagram) controls the conduction of the threshold compensation transistor T2 (at this time, the scan signal line connected to the control terminal of the threshold compensation transistor T2 is at the enable level). Figure 2 (High level is indicated in the figure). The power signal in the positive power signal line PVDD connected to the input terminal of the second light-emitting control transistor T1 can be written into the gate of the driving transistor T3 through the second light-emitting control transistor T1 and the threshold compensation transistor T2, and the first node N1 is reset. Therefore, the potential of the control terminal of the driving transistor T3 is the power signal input to the positive power signal line PVDD. When the driving transistor T3 is an oxide transistor, the driving transistor T3 is also in the on state. The storage capacitor Cst can ensure the potential stability of the first node N1. At the same time, the third scan signal line (shown as SPX in the figure) controls the conduction of the initialization transistor T6 (at this time, the scan signal line connected to the control terminal of the initialization transistor T6 is at the enable level). Figure 2 (Shown at a high level in the figure), the reset signal in the initialization signal line VREF, which is electrically connected to the input terminal of the initialization transistor T6, can be transmitted to the fourth node N4 to reset the light-emitting element 400. Further, during the compensation preparation stage Tb, the pixel circuit 200 controls the second light-emitting control transistor T1 to turn off (at this time, the scan signal line connected to the control terminal of the second light-emitting control transistor T1 is at a disabled level). Figure 2 (shown as a high level in the image), the power signal in the positive power signal line PVDD connected to the input terminal of the second light-emitting control transistor T1 stops writing to the pixel circuit 200.

[0061] Furthermore, the second scan signal line (shown as SP in the figure) electrically connected to the control terminal of the data writing transistor T4 can control the data writing transistor T4 to be turned on or off. During the threshold compensation phase Tc, the pixel circuit 200 controls the data writing transistor T4 to be turned on (at this time, the scan signal line connected to the control terminal of the data writing transistor T4 is at an enable level). Figure 2 (Shown at a low level). Furthermore, the driving transistor T3 and threshold compensation transistor T2 are in the ON state, and the data signal line VDATA connected to the input terminal of the data writing transistor T4 is sequentially written to the first node N1 through the data writing transistor T4, driving transistor T3, and threshold compensation transistor T2. Simultaneously, the third scan signal line (shown as SPX in the figure) still controls the initialization transistor T6 to be on, resetting the light-emitting element 400. During the light-emitting preparation stage Td, the second scan signal line (shown as SP in the figure) controls the data writing transistor T4 to be off (at this time, the scan signal line connected to the control terminal of the data writing transistor T4 is at a non-enabled level). Figure 2(shown as high level in the diagram), and during the light emission preparation stage Td, the second scan signal line (shown as SP in the diagram) controls the threshold compensation transistor T2 to turn off (at this time, the scan signal line connected to the control terminal of the threshold compensation transistor T2 is at a disabled level). Figure 2 When the voltage level changes from high to low, the data signal provided by the data signal line VDATA stops writing to the pixel circuit 200. Simultaneously, the third scan signal line (shown as SPX in the figure) still controls the shutdown of the initialization transistor T6 (at this time, the scan signal line connected to the control terminal of the initialization transistor T6 is at a disabled level). Figure 2 When the voltage level changes from high to low, the reset of the light-emitting element 400 is stopped.

[0062] Furthermore, the first light-emitting control signal line (shown as EM2 in the figure), which is electrically connected to the control terminal of the first light-emitting control transistor T5, can turn the first light-emitting control transistor T5 on or off. During the light-emitting phase Te, the second light-emitting control signal line (shown as EM1 in the figure) controls the second light-emitting control transistor T1 to turn on, and the first light-emitting control signal line (shown as EM2 in the figure) controls the first light-emitting control transistor T5 to turn on. (At this time, the scan signal line connected to the control terminal of the first light-emitting control transistor T5 is at the enable level.) Figure 2 (Indicated by a low level). When the positive power signal line PVDD and the negative power signal line PVEE are connected, the driving transistor T3 generates a driving current that can be transmitted to the light-emitting element 400, thereby driving the light-emitting element 400 to emit light.

[0063] The display panel 10 is composed of multiple overlapping film layers, as shown in the reference. Figure 4 As shown, Figure 4 The film structure of the pixel circuit 200 shown can be a corresponding Figure 2 The provided pixel circuit 200. Specifically, the film structure of the pixel circuit 200, from the bottom to the light-emitting side of the display panel 10, can be, in sequence, a substrate 100, a buffer layer 101, a zeroth metal layer 102, a first insulating layer 103, a first semiconductor layer 104, a second insulating layer 105, a first metal layer 106, a third insulating layer 107, a second semiconductor layer 108, a fourth insulating layer 109, a second metal layer 1010, a fifth insulating layer 1011, a third metal layer 1012, a sixth insulating layer 1013, a fourth metal layer 1014, a seventh insulating layer 1015, a fifth metal layer 1016, an eighth insulating layer 1017, and an anode layer 1018. An insulating layer is added between adjacent metal film layers to provide signal isolation and planarization. As for the specific film structure of the pixel circuit 200, it can be adaptively adjusted according to actual needs, such as adding or removing some film layers. Moreover, any of the above film layers can contain at least one sub-layer. This embodiment of the invention does not impose specific limitations on this.

[0064] The pixel circuit 200 includes a first-type transistor 210, which comprises a first active layer 211 and a first gate 212. The first gate 212 is located on the side of the first active layer 211 away from the substrate 100; therefore, the first gate 212 can be understood as the top-gate structure in the first-type transistor 210. Further, the first active layer 211 comprises oxide; therefore, the first-type transistor 210 is an oxide transistor. For example, refer to... Figure 2 The driving transistor T3.

[0065] Furthermore, the pixel circuit 200 also includes a first storage capacitor 220, for example, referencing Figure 2 The storage capacitor Cst is used to ensure the potential stability of the first node N1, thus guaranteeing the driving effect of the display panel 10 on the light-emitting element 400. The first storage capacitor 220 includes a first capacitor plate 221 and a second capacitor plate 222. In the display panel 10 provided by this embodiment, one of the first capacitor plate 221 or the second capacitor plate 222 is arranged in the same layer as the first gate 212. That is, by adjusting the arrangement of one capacitor plate of the first storage capacitor 220 in the same layer as the top gate of the oxide transistor, the overall film thickness of the pixel circuit 200 can be reduced, lowering the manufacturing cost of the display panel and facilitating a thinner design for the display panel 10. For example, Figure 4 The example shown is that the first capacitor plate 221 and the first gate 212 are on the same layer.

[0066] Figure 5 This is a schematic diagram of the film layer structure of the first type of display panel provided in the embodiments of the present invention. Figure 6 yes Figure 5 A schematic diagram of the first part of the structure. Figure 7 yes Figure 5 A schematic diagram of the second part of the structure. Figure 8 yes Figure 5 A schematic diagram of the third part of the structure. Figure 9 yes Figure 5 A schematic diagram of the fourth part of the structure. Figure 10 yes Figure 5 A schematic diagram of the fifth part of the structure. Figure 11 yes Figure 5 A schematic diagram of the sixth part of the structure. Figure 12 yes Figure 5 A schematic diagram of the seventh part of the structure. Figure 13 yes Figure 5 A schematic diagram of the structure from the first part to the seventh part. Figure 14 yes Figure 5 A schematic diagram of the eighth part of the structure. Figure 15 yes Figure 5 A schematic diagram of the ninth part of the structure. Figure 16 yes Figure 5 Schematic diagrams of the eighth and ninth parts of the structure. If the pixel circuit 200 in the display panel 10 is... Figure 2 The pixel circuit 200 shown can be used as a reference for the film layer structure relationship of the display panel 10. Figure 5 It is shown, and Figures 6 to 12 , Figure 14 and Figure 15 Used to Figure 5 The different membrane layers are illustrated from bottom to top. It should be noted that... Figure 5 The provided schematic diagram of the film structure of the display panel is consistent with... Figure 4 The provided membrane layer diagram corresponds to the settings.

[0067] For details, please refer to Figure 2 ,refer to Figures 4 to 15 As shown, the pixel circuit 200 includes a first type transistor 210, which is an oxide transistor. Combined with... Figure 2 As shown, the first type transistor 210 in the pixel circuit 200 can be at least one of a threshold compensation transistor T2, a driving transistor T3, or an initialization transistor T6. (Referring to...) Figure 4 and Figure 9 As shown, the active layers of the threshold compensation transistor T2, the driving transistor T3, and the initialization transistor T6 are all located on the same layer, specifically on the film layer containing the second semiconductor layer 108. In other words, the first active layer 211 of the first type transistor 210 is located on the film layer containing the second semiconductor layer 108. Further, refer to reference 4 and... Figure 10 As shown, the gates of the threshold compensation transistor T2, the driving transistor T3, and the initialization transistor T6 are all located in the same layer, specifically in the film layer containing the second metal layer 1010. This means that the first gate 212 of the first type transistor 210 is located in the film layer containing the second metal layer 1010. The pixel circuit 200 also includes a first storage capacitor 220, as shown in the reference diagram. Figure 4 and Figure 10 As shown, in the first storage capacitor 220, the first capacitor plate 221 is located in the film layer where the second metal layer 1010 is located, as referenced. Figure 4 and Figure 11 As shown, the second capacitor plate 222 in the first storage capacitor 220 is located on the film layer containing the third metal layer 1012. Both the first capacitor plate 221 and the first gate 212 in the first type transistor 210 are located on the film layer containing the third metal layer 1012, so the first capacitor plate 221 and the first gate 212 are disposed on the same layer. Optionally, the second capacitor plate 222 can also be disposed on the same layer as the first gate 212. This further reduces the number of film layers occupied by the pixel circuit 200.

[0068] Figure 17 This is a schematic diagram of the film layer structure of the second type of display panel provided in an embodiment of the present invention. Figure 18 yes Figure 17 A schematic diagram of the first part of the structure. Figure 19 yes Figure 17 A schematic diagram of the second part of the structure. Figure 20 yes Figure 17 A schematic diagram of the third part of the structure. Figure 21 yes Figure 17 A schematic diagram of the fourth part of the structure. Figure 22 yes Figure 17 A schematic diagram of the fifth part of the structure. Figure 23 yes Figure 17 A schematic diagram of the sixth part of the structure. Figure 24 yes Figure 17 A schematic diagram of the seventh part of the structure. Figure 25 yes Figure 17 A schematic diagram of the structure from the first part to the seventh part. Figure 26 yes Figure 17 A schematic diagram of the eighth part of the structure. Figure 27 yes Figure 17 A schematic diagram of the ninth part of the structure. Figure 28 yes Figure 17 Schematic diagrams of the eighth and ninth parts of the structure. If the pixel circuit 200 in the display panel 10 is... Figure 2 The pixel circuit 200 shown can be used as a reference for the film layer structure relationship of the display panel 10. Figure 17 It is shown, and Figures 18 to 24 , Figure 26 and Figure 27 Used to Figure 17 The different membrane layers are illustrated from bottom to top. It should be noted that... Figure 17 The provided schematic diagram of the film structure of the display panel is consistent with... Figure 4 The provided membrane layer diagram corresponds to the settings.

[0069] For details, please refer to Figure 2 ,refer to Figures 17 to 28 As shown, the pixel circuit 200 includes a first type transistor 210, which is an oxide transistor. (The reference is missing from the original text.) Figure 4 and Figure 21 As shown, the active layers of the threshold compensation transistor T2, the driving transistor T3, and the initialization transistor T6 are all located on the same layer, specifically on the film layer containing the second semiconductor layer 108. In other words, the first active layer 211 of the first type transistor 210 is located on the film layer containing the second semiconductor layer 108. Further, refer to... Figure 4 and Figure 22As shown, the gates of the threshold compensation transistor T2, the driving transistor T3, and the initialization transistor T6 are all located in the same layer, specifically in the film layer containing the second metal layer 1010. This means that the first gate 212 of the first type transistor 210 is located in the film layer containing the second metal layer 1010. The pixel circuit 200 also includes a first storage capacitor 220, as shown in the reference diagram. Figure 4 and Figure 22 As shown, in the first storage capacitor 220, the first capacitor plate 221 is located in the film layer where the second metal layer 1010 is located, as referenced. Figure 4 and Figure 23 As shown, the second capacitor plate 222 in the first storage capacitor 220 is located on the film layer containing the third metal layer 1012. Both the first capacitor plate 221 and the first gate 212 in the first type transistor 210 are located on the film layer containing the third metal layer 1012, so the first capacitor plate 221 and the first gate 212 are disposed on the same layer. Optionally, the second capacitor plate 222 can also be disposed on the same layer as the first gate 212. This also demonstrates that the pixel circuit 200 reduces the number of film layers it occupies.

[0070] Figure 29 This is a schematic diagram of the film layer structure of the second pixel circuit provided in this embodiment of the invention. Furthermore, the overlapping arrangement of multiple film layers in the display panel 10 can also be referred to... Figure 29 As shown, Figure 29 The film structure of the pixel circuit 200 shown can be a corresponding Figure 2 The provided pixel circuit 200. Specifically, the film structure of the pixel circuit 200, from the bottom to the light-emitting side of the display panel 10, can be, in sequence, a substrate 100, a buffer layer 101, a zeroth metal layer 102, a first insulating layer 103, a first semiconductor layer 104, a second insulating layer 105, a first metal layer 106, a third insulating layer 107, a second semiconductor layer 108, a fourth insulating layer 109, a second metal layer 1010, a fifth insulating layer 1011, a third metal layer 1012, a sixth insulating layer 1013, a fourth metal layer 1014, a seventh insulating layer 1015, a fifth metal layer 1016, an eighth insulating layer 1017, a sixth metal layer 1019, a ninth insulating layer 1020, and an anode layer 1018. An insulating layer is added between adjacent metal film layers to provide signal isolation and planarization. As for the specific film structure of the pixel circuit 200, it can be adaptively adjusted according to actual needs, such as adding or removing some film layers. Moreover, any of the above film layers can contain at least one sub-layer. This embodiment of the invention does not impose specific limitations on this.

[0071] Figure 30 This is a schematic diagram of the film layer structure of the third type of display panel provided in the embodiments of the present invention. Figure 31 yes Figure 30 A schematic diagram of the first part of the structure. Figure 32 yes Figure 30 A schematic diagram of the second part of the structure. Figure 33 yes Figure 30 A schematic diagram of the third part of the structure. Figure 34 yes Figure 30 A schematic diagram of the fourth part of the structure. Figure 35 yes Figure 30 A schematic diagram of the fifth part of the structure. Figure 36 yes Figure 30 A schematic diagram of the sixth part of the structure. Figure 37 yes Figure 30 A schematic diagram of the eighth part of the structure. Figure 38 yes Figure 30 A schematic diagram of the structure from the first part to the eighth part. Figure 39 yes Figure 30 Schematic diagrams of the seventh and eighth parts of the structure. Figure 40 yes Figure 30 A schematic diagram of the ninth part of the structure. Figure 41 yes Figure 30 A schematic diagram of the tenth part of the structure. If the pixel circuit 200 in the display panel 10 is... Figure 2 The pixel circuit 200 shown can be used as a reference for the film layer structure relationship of the display panel 10. Figure 30 It is shown, and Figures 31 to 37 , Figure 40 and Figure 41 Used to Figure 30 The different membrane layers are illustrated from bottom to top. It should be noted that... Figure 30 The provided schematic diagram of the film structure of the display panel is consistent with... Figure 29 The provided membrane layer diagram corresponds to the settings.

[0072] For details, please refer to Figure 2 ,refer to Figures 30 to 41 As shown, the pixel circuit 200 includes a first type transistor 210, which is an oxide transistor. (The reference is missing from the original text.) Figure 4 and Figure 34 As shown, the active layers of the threshold compensation transistor T2, the driving transistor T3, and the initialization transistor T6 are all located on the same layer, specifically on the film layer containing the second semiconductor layer 108. In other words, the first active layer 211 of the first type transistor 210 is located on the film layer containing the second semiconductor layer 108. Further, refer to... Figure 4 and Figure 35 As shown, the gates of the threshold compensation transistor T2, the driving transistor T3, and the initialization transistor T6 are all located in the same layer, specifically in the film layer containing the second metal layer 1010. This means that the first gate 212 of the first type transistor 210 is located in the film layer containing the second metal layer 1010. The pixel circuit 200 also includes a first storage capacitor 220, as shown in the reference diagram. Figure 4 and Figure 35 As shown, in the first storage capacitor 220, the first capacitor plate 221 is located in the film layer where the second metal layer 1010 is located, as referenced. Figure 4 and Figure 36 As shown, the second capacitor plate 222 in the first storage capacitor 220 is located on the film layer containing the third metal layer 1012. Both the first capacitor plate 221 and the first gate 212 in the first type transistor 210 are located on the film layer containing the third metal layer 1012, so the first capacitor plate 221 and the first gate 212 are disposed on the same layer. Optionally, the second capacitor plate 222 can also be disposed on the same layer as the first gate 212. This also demonstrates that the pixel circuit 200 reduces the number of film layers it occupies.

[0073] Figure 2 The schematic diagram of the film layer structure of the display panel 10 corresponding to the pixel circuit 200 shown can be referred to. Figure 5 , Figure 17 or Figure 30 As shown, the co-layer arrangement of the first capacitor plate 221 and the first gate 212 helps reduce the overall film thickness of the display panel 10, thus facilitating a thinner design. Furthermore, the first capacitor plate 221 and the first gate 212 can be fabricated simultaneously using the same process during the manufacturing of the display panel 10, further reducing the manufacturing cost of the display panel 10.

[0074] In summary, the pixel circuit in the display panel provided by the embodiments of the present invention includes a first type of transistor and a first storage capacitor. By setting a portion of the structure in the first type of transistor and a portion of the structure in the first storage capacitor in the same layer, specifically setting one of the first capacitor plate or the second capacitor plate in the same layer as the first gate, the overall film thickness of the pixel circuit can be reduced, which is beneficial to realizing the thin design of the display panel and reducing the manufacturing cost of the display panel.

[0075] Continue to refer Figures 4 to 41 As shown, the first capacitor plate 221 or the second capacitor plate 222 reuses at least a portion of the first gate 212 of the first type transistor 210.

[0076] Furthermore, based on the arrangement of the first capacitor plate 221 and the first gate 212 in the same layer, at least a portion of the first capacitor plate 221 can reuse the first gate 212, or based on the arrangement of the second capacitor plate 222 and the first gate 212 in the same layer, at least a portion of the second capacitor plate 222 can reuse the first gate 212. In other words, the capacitor plate arranged in the same layer as the first gate 212 can further reuse the first gate 212, effectively reducing the overall space occupied by the metal film layer containing the first gate 212, further reducing the space occupied by the pixel circuit 200 in the display panel 10, and making the arrangement of the pixel circuit 200 more flexible.

[0077] Furthermore, in existing technologies, because the storage capacitor in the pixel circuit is independently configured—that is, the plates of the storage capacitor are additionally set—the area where the storage capacitor is located occupies a portion of the space. Simultaneously, the space occupied by the storage capacitor also compresses the space available for the scan signal lines. Due to the limitations on the routing of the scan signal lines, the first gate (i.e., the top gate) and the bottom gate of the driving transistor cannot both be electrically connected to the scan signal lines. Therefore, the top and bottom gates of the driving transistor need to be electrically connected vias to ensure the driving effect on the driving transistor. Thus, in existing display panels, the pixel circuit occupies a relatively large space because both the connecting vias and the plates of the storage capacitor occupy space.

[0078] In the display panel provided by this embodiment of the invention, the capacitor plate of the first storage capacitor 220 is reused with the first gate 212, which can save the space occupied by the first storage capacitor 220 in the display panel 10 and ensure that there is sufficient space for the scanning signal lines in the pixel circuit 200. For example, refer to... Figure 10 , Figure 22 or Figure 35 As shown, the first gate 212 (top gate) of the driving transistor T3 is multiplexed by the first capacitor plate 221. The space for the scan signal line (e.g., the first scan signal line SN) is not affected by the plate of the first storage capacitor 220. Both the first gate 212 and the second gate 213 of the driving transistor T3 can be electrically connected to the corresponding scan signal line. Therefore, the second gate 213 (bottom gate) of the driving transistor T3 does not need to be electrically connected to the first gate 212 through a via. This saves space occupied by the connection via, further reducing the space occupied by the pixel circuit 200 in the display panel. It also saves on the fabrication process of the connection via, improving fabrication efficiency.

[0079] For example, refer to Figures 4 to 16 As shown, please refer to the following for details. Figure 4 and Figure 10As shown, the example is illustrated by having the first capacitor plate 221 and the first gate 212 arranged on the same layer. The first gate 212 is present in the area where the first capacitor plate 221 is located; that is, at least a portion of the first capacitor plate 221 reuses the first gate 212. This is different from the case where the first capacitor plate 221 and the first gate 212 are arranged independently. Figure 10 The overall area of ​​the second metal layer 1010 shown can be effectively reduced, thereby reducing the space occupied by the pixel circuit 200 in the display panel 10 and improving the flexibility of the pixel circuit 200 setup.

[0080] For example, refer to Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 4 and Figure 22 As shown, the example is illustrated by having the first capacitor plate 221 and the first gate 212 arranged on the same layer. The first gate 212 is present in the area where the first capacitor plate 221 is located; that is, at least a portion of the first capacitor plate 221 reuses the first gate 212. This is different from the case where the first capacitor plate 221 and the first gate 212 are arranged independently. Figure 22 The overall area of ​​the second metal layer 1010 shown can be effectively reduced, thereby reducing the space occupied by the pixel circuit 200 in the display panel 10 and improving the flexibility of the pixel circuit 200 setup.

[0081] For example, refer to Figures 29 to 41 As shown, please refer to the following for details. Figure 29 and Figure 35 As shown, the example is illustrated by having the first capacitor plate 221 and the first gate 212 arranged on the same layer. The first gate 212 is present in the area where the first capacitor plate 221 is located; that is, at least a portion of the first capacitor plate 221 reuses the first gate 212. This is different from the case where the first capacitor plate 221 and the first gate 212 are arranged independently. Figure 35 The overall area of ​​the second metal layer 1010 shown can be effectively reduced, thereby reducing the space occupied by the pixel circuit 200 in the display panel 10 and improving the flexibility of the pixel circuit 200 setup.

[0082] For details, please refer to Figures 4 to 41 As shown, the second capacitor plate 221 is located on the side of the first capacitor plate 221 away from the substrate 100; the first gate 212 of at least a portion of the first type transistor 210 is reused in the first capacitor plate 221.

[0083] Among them, reference Figure 4 and Figure 29As shown, in the first storage capacitor 220, the first capacitor plate 221 is located on the side of the second capacitor plate 222 closer to the substrate 100. This can also be understood as the first capacitor plate 221 being the lower plate of the first storage capacitor 220, and the second capacitor plate 222 being the upper plate of the first storage capacitor 220. The first capacitor plate 221 and the first gate 212 are disposed on the same layer, allowing for partial reuse of the first gate 212 of the first type transistor 210 within the structure of the first capacitor plate 221. This reduces the space occupied by the pixel circuit 200 in the display panel 10 and improves the flexibility of the pixel circuit's configuration.

[0084] For example, refer to Figures 4 to 16 As shown, please refer to the following for details. Figure 4 and Figure 10 As shown, the first capacitor plate 221 is disposed in the same layer as the first gate 212, and is located in the film layer where the second metal layer 1010 is located. (Reference) Figure 4 and Figure 11 As shown, the second capacitor plate 222 is located in the film layer containing the third metal layer 1012; therefore, the second capacitor plate 221 is located on the side of the first capacitor plate 221 away from the substrate 100. Further, referring to… Figure 10 As shown, a portion of the first capacitor plate 221 serves as the first gate 212. By using a structure reuse method, the space occupied by the pixel circuit 200 in the display panel 10 can be reduced, and the arrangement of the pixel circuit 200 can be made more flexible.

[0085] For example, refer to Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 4 and Figure 22 As shown, the first capacitor plate 221 is disposed in the same layer as the first gate 212, and is located in the film layer where the second metal layer 1010 is located. (Reference) Figure 4 and Figure 23 As shown, the second capacitor plate 222 is located in the film layer containing the third metal layer 1012; therefore, the second capacitor plate 221 is located on the side of the first capacitor plate 221 away from the substrate 100. Further, referring to… Figure 22 As shown, a portion of the first capacitor plate 221 serves as the first gate 212. By using a structure reuse method, the space occupied by the pixel circuit 200 in the display panel 10 can be reduced, and the arrangement of the pixel circuit 200 can be made more flexible.

[0086] For example, refer to Figures 29 to 41 As shown, please refer to the following for details. Figure 29 and Figure 35 As shown, the first capacitor plate 221 is disposed in the same layer as the first gate 212, and is located in the film layer where the second metal layer 1010 is located. (Reference) Figure 29 and Figure 36As shown, the second capacitor plate 222 is located in the film layer containing the third metal layer 1012; therefore, the second capacitor plate 221 is located on the side of the first capacitor plate 221 away from the substrate 100. Further, referring to… Figure 35 As shown, a portion of the first capacitor plate 221 serves as the first gate 212. By using a structure reuse method, the space occupied by the pixel circuit 200 in the display panel 10 can be reduced, and the arrangement of the pixel circuit 200 can be made more flexible.

[0087] For details, please refer to [link / reference]. Figure 2 , Figures 4 to 41 As shown, the first type of transistor 210 includes a driving transistor T3; the first capacitor plate 221 or the second capacitor plate 222 multiplexes the first gate 212 of the driving transistor T3.

[0088] Furthermore, the first type of transistor 210 in the pixel circuit 200 may include a driving transistor T3. The first gate 212 of the driving transistor T3 has a large projected area onto the substrate 100. The first capacitor plate 221 or the second capacitor plate 222 can reuse the first gate 212 of the driving transistor T3. Therefore, the first capacitor plate 221 or the second capacitor plate 222 does not need to occupy additional space, which helps reduce the overall space occupied by the pixel circuit 200. Specifically, in the pixel circuit 200, the projected area of ​​the gate of the driving transistor T3 onto the substrate 100 side is larger than the projected area of ​​the gates of other transistors onto the substrate 100 side. Reusing the capacitor plate of the first storage capacitor 220 with the gate of the driving transistor T3 further reduces the overall space occupied by the pixel circuit 200.

[0089] For example, refer to Figures 4 to 16 As shown, please refer to the following for details. Figure 10 As shown, the first type transistor 210 includes a driving transistor T3, and the first gate 212 of the first type transistor 210 is the gate of the driving transistor T3. The first capacitor plate 221 reuses the first gate 212 of the driving transistor T3. Since the projected area of ​​the first gate 212 of the driving transistor T3 onto the substrate 100 side is larger than the projected area of ​​the gates of other transistors onto the substrate 100 side, the plate area of ​​the first capacitor plate 221 can be guaranteed.

[0090] For example, refer to Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 24As shown, the first type transistor 210 includes a driving transistor T3, and the first gate 212 of the first type transistor 210 is the gate of the driving transistor T3. The first capacitor plate 221 reuses the first gate 212 of the driving transistor T3. Since the projected area of ​​the first gate 212 of the driving transistor T3 onto the substrate 100 side is larger than the projected area of ​​the gates of other transistors onto the substrate 100 side, the plate area of ​​the first capacitor plate 221 can be guaranteed.

[0091] For example, refer to Figures 29 to 41 As shown, please refer to the following for details. Figure 35 As shown, the first type transistor 210 includes a driving transistor T3, and the first gate 212 of the first type transistor 210 is the gate of the driving transistor T3. The first capacitor plate 221 reuses the first gate 212 of the driving transistor T3. Since the projected area of ​​the first gate 212 of the driving transistor T3 onto the substrate 100 side is larger than the projected area of ​​the gates of other transistors onto the substrate 100 side, the plate area of ​​the first capacitor plate 221 can be guaranteed.

[0092] Continue to refer Figures 5 to 28 , Figures 30 to 41 As shown, the pixel circuit 200 also includes a second storage capacitor 230, which includes a third capacitor plate 231 and a fourth capacitor plate 232. The third capacitor plate 231 is disposed on the same layer as the first capacitor plate 221 and connected thereto, and the fourth capacitor plate 232 is disposed on the same layer as the second capacitor plate 222 and connected thereto.

[0093] The pixel circuit 200 may further include a second storage capacitor 230. When a portion of the electrode structure in the first storage capacitor 220 reuses the first gate 212, the space saved by the first storage capacitor 220 can be used to set up the second storage capacitor 240. (Refer to...) Figure 2 As shown, the storage capacitor Cst in the pixel circuit 200 can simultaneously include a first storage capacitor 220 and a second storage capacitor 230. Specifically, the second storage capacitor 230 can be disposed on the same layer as the first storage capacitor 220. The third capacitor plate 231 of the second storage capacitor 230 is on the same layer as the first capacitor plate 221 and electrically connected. The fourth capacitor plate 232 of the second storage capacitor 230 is on the same layer as the second capacitor plate 222 and connected. In this way, the placement of the second storage capacitor 230 will not increase the overall space occupied by the pixel circuit 200 in the display panel 10. At the same time, the electrical connection between the first storage capacitor 220 and the second storage capacitor 230 can also increase the overall capacitance value, further improving the stability of the potential of the first node N1, ensuring the driving effect of the pixel circuit 200 on the light-emitting element 400, and ensuring the overall display effect of the display panel 10.

[0094] For example, refer to Figures 4 to 16 As shown, please refer to the following for details. Figure 4 and Figure 10 As shown, the first capacitor plate 221 of the first storage capacitor 220 and the third capacitor plate 231 of the second storage capacitor 230 are both located on the film layer where the second metal layer 1010 is located, and the first capacitor plate 221 and the third capacitor plate 231 are electrically connected. (Reference) Figure 4 and Figure 11 As shown, the second capacitor plate 222 of the first storage capacitor 220 and the fourth capacitor plate 232 of the second storage capacitor 230 are both located on the film layer where the third metal layer 1012 is located, and the second capacitor plate 222 and the fourth capacitor plate 232 are electrically connected. Furthermore, in conjunction with... Figure 10 and Figure 11 As shown, the first storage capacitor 220 and the second storage capacitor 230 are electrically connected, which increases the overall capacitance value. The space occupied by the first storage capacitor 220 and the second storage capacitor 230 can be adaptively adjusted according to the space reserved in each film layer, reflecting the flexibility of the storage capacitor setting.

[0095] For example, refer to Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 4 and Figure 24 As shown, the first capacitor plate 221 of the first storage capacitor 220 and the third capacitor plate 231 of the second storage capacitor 230 are both located on the film layer where the second metal layer 1010 is located, and the first capacitor plate 221 and the third capacitor plate 231 are electrically connected. (Reference) Figure 4 and Figure 25 As shown, the second capacitor plate 222 of the first storage capacitor 220 and the fourth capacitor plate 232 of the second storage capacitor 230 are both located on the film layer where the third metal layer 1012 is located, and the second capacitor plate 222 and the fourth capacitor plate 232 are electrically connected. Furthermore, in conjunction with... Figure 24 and Figure 25 As shown, the first storage capacitor 220 and the second storage capacitor 230 are electrically connected, which increases the overall capacitance value. The space occupied by the first storage capacitor 220 and the second storage capacitor 230 can be adaptively adjusted according to the space reserved in each film layer, reflecting the flexibility of the storage capacitor setting.

[0096] For example, refer to Figures 29 to 41 As shown, please refer to the following for details. Figure 29 and Figure 35 As shown, the first capacitor plate 221 of the first storage capacitor 220 and the third capacitor plate 231 of the second storage capacitor 230 are both located on the film layer where the second metal layer 1010 is located, and the first capacitor plate 221 and the third capacitor plate 231 are electrically connected. (Reference) Figure 29 and Figure 36As shown, the second capacitor plate 222 of the first storage capacitor 220 and the fourth capacitor plate 232 of the second storage capacitor 230 are both located on the film layer where the third metal layer 1012 is located, and the second capacitor plate 222 and the fourth capacitor plate 232 are electrically connected. Furthermore, in conjunction with... Figure 35 and Figure 36 As shown, the first storage capacitor 220 and the second storage capacitor 230 are electrically connected, which increases the overall capacitance value. The space occupied by the first storage capacitor 220 and the second storage capacitor 230 can be adaptively adjusted according to the space reserved in each film layer, reflecting the flexibility of the storage capacitor setting.

[0097] Continue to refer Figure 2 , Figures 4 to 41 As shown, the pixel circuit 200 also includes an initialization transistor T6 and a first light-emitting control transistor T5; the display panel 10 also includes a first connection portion 310, which connects the first terminal of the initialization transistor T6, the first terminal of the first light-emitting control transistor T5 and the fourth capacitor plate 232.

[0098] Among them, reference Figure 2 As shown, the pixel circuit 200 also includes an initialization transistor T6 and a first light-emitting control transistor T5. The initialization transistor T6 can also be a first-type transistor 210, so the first gate 212 of the initialization transistor T6 and one of the capacitor plates of the first storage capacitor 220 can be arranged on the same layer. Further, the output terminal of the initialization transistor T6, the output terminal of the first light-emitting control transistor T5, and one capacitor plate of the storage capacitor Cst are connected to the fourth node N4. Specifically, the display panel 10 also includes a first connection portion 310, through which the initialization transistor T6, the first light-emitting control transistor T5, and the capacitor plate of the storage capacitor Cst are electrically connected. The first connection portion 310 is electrically connected to the fourth capacitor plate 232 of the second storage capacitor 230 in the storage capacitor Cst. The first connection portion 310 ensures the electrical connection between the transistors in the pixel circuit 200 and also ensures that the electrical connection between the storage capacitor Cst and the transistors is maintained even when the storage capacitor Cst is adjusted, thus ensuring stable signal transmission in the pixel circuit 200. The adjustments to the storage capacitor Cst include adjusting the position of the film layer and the area and position of the capacitor plates in the storage capacitor Cst.

[0099] For example, refer to Figure 2 , Figures 4 to 16 As shown, in conjunction with reference Figure 12As shown, the display panel 10 includes a first connecting portion 310, which is located on the film layer where the fourth metal layer 1014 is located. The first connecting portion 310 includes a first connecting end 310a, a second connecting end 310b, and a third connecting end 310c, which are connected to... Figure 8 , Figure 9 , Figure 10 , Figure 12 and Figure 13 As shown, the first connection terminal 310a is electrically connected to the output terminal of the initialization transistor T6; combined with Figures 10 to 13 The second connection terminal 310b is electrically connected to the fourth capacitor plate 232 of the second storage capacitor 230; junction and Figure 7 , Figure 8 , Figure 12 and Figure 13 As shown, the third connection terminal 310c is electrically connected to the output terminal of the first light-emitting control transistor T5. Therefore, the first connection portion 310 connects the first terminal of the initialization transistor T6, the first terminal of the first light-emitting control transistor T5, and the fourth capacitor plate 232, ensuring the transmission of signals in the pixel circuit 200, ensuring the driving stability of the pixel circuit 200 on the light-emitting element 400, and ensuring the overall display effect of the display panel 10.

[0100] For example, refer to Figure 2 , Figure 4 , Figures 17 to 28 As shown, the display panel 10 includes a first connecting portion 310, which is located on the film layer where the fourth metal layer 1014 is located. Figure 20 , Figure 21 , Figure 22 , Figure 24 and Figure 25 As shown, one end of the first connection portion 310 is electrically connected to the output terminal of the initialization transistor T6; combined with Figures 22 to 24 One end of the first connecting part 310 is electrically connected to the fourth capacitor plate 232 of the second storage capacitor 230; Figure 19 , Figure 20 , Figure 24 and Figure 25 As shown, one end of the first connection portion 310 is electrically connected to the output terminal of the first light-emitting control transistor T5. Therefore, the first connection portion 310 connects the first terminal of the initialization transistor T6, the first terminal of the first light-emitting control transistor T5, and the fourth capacitor plate 232, ensuring signal transmission in the pixel circuit 200, ensuring the driving stability of the pixel circuit 200 on the light-emitting element 400, and ensuring the overall display effect of the display panel 10.

[0101] For example, refer to Figure 2 , Figures 29 to 41As shown, the display panel 10 includes a first connecting portion 310, which is located on the film layer where the fourth metal layer 1014 is located. Figure 33 , Figure 34 , Figure 35 , Figure 38 and Figure 39 As shown, one end of the first connection portion 310 is electrically connected to the output terminal of the initialization transistor T6; combined with Figure 35 , Figure 36 , Figure 38 and Figure 39 As shown, one end of the first connecting part 310 is electrically connected to the fourth capacitor plate 232 of the second storage capacitor 230; combined with Figure 32 , Figure 33 , Figure 38 and Figure 39 As shown, one end of the first connection portion 310 is electrically connected to the output terminal of the first light-emitting control transistor T5. Therefore, the first connection portion 310 connects the first terminal of the initialization transistor T6, the first terminal of the first light-emitting control transistor T5, and the fourth capacitor plate 232, ensuring signal transmission in the pixel circuit 200, ensuring the driving stability of the pixel circuit 200 on the light-emitting element 400, and ensuring the overall display effect of the display panel 10.

[0102] Continue to refer Figure 2 , Figures 4 to 41 As shown, the first capacitor plate 221 and the third capacitor plate 231 are connected to the capacitor plate connection portion 221a; the first type transistor 210 also includes a threshold compensation transistor T2; the display panel also includes a second connection portion 320, which connects the capacitor plate connection portion 221a and the first end of the threshold compensation transistor T2.

[0103] The display panel 10 also includes a capacitor plate connection part 221a, which is used to electrically connect the first storage capacitor 220 and the second storage capacitor 230. Specifically, the first capacitor plate 221 of the first storage capacitor 220 is electrically connected to the third capacitor plate 231 of the second storage capacitor 230 through the capacitor plate connection part 221a.

[0104] refer to Figure 2As shown, the pixel circuit 200 also includes a threshold compensation transistor T2, which can also be a first type transistor 210. That is, the first gate 212 of the threshold compensation transistor T2 is disposed on the same layer as one of the capacitor plates in the first storage capacitor 220. Furthermore, the output terminal of the threshold compensation transistor T2 is electrically connected to the storage capacitor Cst, and connected to the first node N1. Specifically, the display panel 10 also includes a second connection portion 320, through which the storage capacitor Cst and the first terminal of the threshold compensation transistor T2 are electrically connected. The second connection portion 320 is also electrically connected to the capacitor plate connection portion 221a, thus achieving the connection with the storage capacitor Cst. The second connection portion 320 ensures the electrical connection between transistors in the pixel circuit 200 and maintains the electrical connection between the storage capacitor Cst and the transistors even when the storage capacitor Cst is adjusted, ensuring stable signal transmission in the pixel circuit 200.

[0105] For example, refer to Figure 2 , Figures 4 to 16 As shown, please refer to the following for details. Figure 10 and Figure 11 As shown, the capacitor plate connection portion 221a is located between the first capacitor plate 221 and the third capacitor plate 231, and is electrically connected to both the first capacitor plate 221 and the third capacitor plate 231. The capacitor plate connection portion 221a, the first capacitor plate 221, and the third capacitor plate 231 are all located in the film layer containing the second metal layer 1010. Further, referring to the reference... Figure 12 As shown, the display panel 10 includes a second connecting portion 320, which is located on the film layer where the fourth metal layer 1014 is located. The second connecting portion 320 includes a third connecting end 320a and a fourth connecting end 320b, which are combined with... Figure 8 , Figure 9 , Figure 10 , Figure 12 and Figure 13 As shown, the third connection terminal 320a is electrically connected to the output terminal of the threshold compensation transistor T2; combined with Figures 10 to 13 As shown, the fourth connection terminal 320b is electrically connected to the capacitor plate connection portion 221a. Therefore, the second connection portion 320 connects the capacitor plate connection portion 221a and the first terminal of the threshold compensation transistor T2, ensuring signal transmission in the pixel circuit 200, ensuring the driving stability of the pixel circuit 200 on the light-emitting element 400, and ensuring the overall display effect of the display panel 10.

[0106] For example, refer to Figure 2 , Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 22 and Figure 23As shown, the capacitor plate connection portion 221a is located between the first capacitor plate 221 and the third capacitor plate 231, and is electrically connected to both the first capacitor plate 221 and the third capacitor plate 231. The capacitor plate connection portion 221a, the first capacitor plate 221, and the third capacitor plate 231 are all located in the film layer containing the second metal layer 1010. Further, referring to the reference... Figure 24 As shown, the display panel 10 includes a second connecting portion 320, which is located on the film layer where the fourth metal layer 1014 is located. (Combined) Figure 20 , Figure 21 , Figure 22 , Figure 24 and Figure 25 As shown, one end of the second connection portion 320 is electrically connected to the output terminal of the threshold compensation transistor T2; combined with Figures 22 to 25 As shown, one end of the second connection portion 320 is electrically connected to the capacitor plate connection portion 221a. Therefore, the second connection portion 320 connects the capacitor plate connection portion 221a and the first end of the threshold compensation transistor T2, ensuring signal transmission in the pixel circuit 200, ensuring the driving stability of the pixel circuit 200 on the light-emitting element 400, and ensuring the overall display effect of the display panel 10.

[0107] For example, refer to Figure 2 , Figures 29 to 41 As shown, please refer to the following for details. Figure 35 and Figure 36 As shown, the capacitor plate connection portion 221a is located between the first capacitor plate 221 and the third capacitor plate 231, and is electrically connected to both the first capacitor plate 221 and the third capacitor plate 231. The capacitor plate connection portion 221a, the first capacitor plate 221, and the third capacitor plate 231 are all located in the film layer containing the second metal layer 1010. Further, referring to the reference... Figure 29 and Figure 39 As shown, the display panel 10 includes a second connecting portion 320, which is located on the film layer where the fourth metal layer 1014 is located. (Combined) Figure 33 , Figure 34 , Figure 35 , Figure 38 and Figure 39 As shown, one end of the second connection portion 320 is electrically connected to the output terminal of the threshold compensation transistor T2; combined with Figure 35 , Figure 36 , Figure 38 and Figure 39 As shown, one end of the second connection portion 320 is electrically connected to the capacitor plate connection portion 221a. Therefore, the second connection portion 320 connects the capacitor plate connection portion 221a and the first end of the threshold compensation transistor T2, ensuring signal transmission in the pixel circuit 200, ensuring the driving stability of the pixel circuit 200 on the light-emitting element 400, and ensuring the overall display effect of the display panel 10.

[0108] Continue to refer Figure 2 , Figures 4 to 41 As shown, the display panel 10 also includes a light-emitting element 400, which includes a first electrode 410; the display panel 10 also includes a third connecting portion 330, which connects the second capacitor plate 222 and the first electrode 410.

[0109] Among them, reference Figure 2 As shown, the display panel 10 also includes a light-emitting element 400, which is electrically connected to the pixel circuit 200. The pixel circuit 200 drives the light-emitting element 400 to emit light for display. The light-emitting element 400 includes a first electrode 410, which is electrically connected to the pixel circuit 200 to ensure that the pixel circuit 200 drives the light-emitting element 400. The first electrode 410 can be understood as the anode in the light-emitting element 400.

[0110] Further reference Figure 2 As shown, the first electrode 410 is electrically connected to the storage capacitor Cst in the pixel circuit 200, and is connected to the fourth node N4. Specifically, the display panel 10 also includes a third connection part 330, through which the storage capacitor Cst and the first electrode 410 can be electrically connected. The storage capacitor Cst includes a first storage capacitor 220 and a second storage capacitor 230 connected to each other. The third connection part 330 can realize the electrical connection relationship between the first electrode 410 and the storage capacitor Cst by being electrically connected to the first storage capacitor 220. The provided third connection part 330 can ensure that the electrical connection relationship between the storage capacitor Cst and the first electrode 410 is satisfied when the storage capacitor Cst is adjusted, thus ensuring the driving effect of the pixel circuit 200 on the light-emitting element 400.

[0111] For example, refer to Figure 2 , Figures 4 to 16 As shown, in conjunction with reference Figure 12 As shown, the display panel 10 includes a third connecting portion 330, which is located on the film layer where the fourth metal layer 1014 is located. The third connecting portion 330 includes a fifth connecting end 330a and a sixth connecting end 330b, which are combined with... Figure 11 , Figure 12 and Figure 13 As shown, the fifth connection terminal 330a is electrically connected to the second capacitor plate 222; Reference Figures 12 to 16 As shown, the film layer containing the fifth metal layer 1016 also includes an anode connection via 330c, and the sixth connection end 330b is electrically connected to the first electrode 410 through the anode connection via 330c. Therefore, the third connection part 330 electrically connects the second capacitor plate 222 and the first electrode 410, ensuring the driving stability of the pixel circuit 200 on the light-emitting element 400 and ensuring the overall display effect of the display panel 10.

[0112] For example, refer to Figure 2 , Figure 4 , Figures 17 to 28 As shown, in conjunction with reference Figure 24 As shown, the display panel 10 includes a third connecting portion 330, which is located on the film layer where the fourth metal layer 1014 is located. Figure 23 , Figure 24 and Figure 25 As shown, one end of the third connecting part 330 is electrically connected to the second capacitor plate 222; Reference Figures 24 to 28 As shown, the film layer containing the fifth metal layer 1016 also includes an anode connection via 330c. One end of the third connection portion 330 is electrically connected to the first electrode 410 through the anode connection via 330c. Therefore, the third connection portion 330 electrically connects the second capacitor plate 222 and the first electrode 410, ensuring the driving stability of the pixel circuit 200 on the light-emitting element 400 and ensuring the overall display effect of the display panel 10.

[0113] For example, refer to Figure 2 , Figures 29 to 41 As shown, combined with Figure 29 As shown, the display panel 10 includes a third connecting portion 330, which is located on the film layer where the fourth metal layer 1014 is located. Figure 36 , Figure 38 and Figure 39 As shown, one end of the third connecting part 330 is electrically connected to the second capacitor plate 222; Reference Figures 38 to 41 As shown, the film layer containing the fifth metal layer 1016 also includes an anode connection via 330c. One end of the third connection portion 330 is electrically connected to the first electrode 410 through the anode connection via 330c. Therefore, the third connection portion 330 electrically connects the second capacitor plate 222 and the first electrode 410, ensuring the driving stability of the pixel circuit 200 on the light-emitting element 400 and ensuring the overall display effect of the display panel 10.

[0114] Continue to refer Figure 2 , Figures 4 to 41As shown, the pixel circuit 200 further includes an initialization transistor T6 and a first light-emitting control transistor T5; the first type transistor 210 further includes a threshold compensation transistor T2; the display panel 10 further includes a light-emitting element 400, which includes a first electrode 410; the display panel 10 further includes a first connecting portion 310, a second connecting portion 320, and a third connecting portion 330; the first connecting portion 310 connects the first terminal of the initialization transistor T6, the first terminal of the first light-emitting control transistor T5, and the fourth capacitor plate 232; the first capacitor plate 221 and the third capacitor plate 231 are connected to the capacitor plate connecting portion 221a, the second connecting portion 320 connects the capacitor plate connecting portion 221a and the first terminal of the threshold compensation transistor T2; the third connecting portion 330 connects the second capacitor plate 222 and the first electrode 410; the first connecting portion 310, the second connecting portion 320, and the third connecting portion 330 are arranged on the same layer.

[0115] Among them, reference Figure 2 As shown, the pixel circuit 200 includes an initialization transistor T6, a first emission control transistor T5, a threshold compensation transistor T2, and a driving transistor T3. The first type transistor 210 may include the initialization transistor T6, the threshold compensation transistor T2, and the driving transistor T3. Furthermore, the display panel 10 also includes a light-emitting element 400. The pixel circuit 200 provides a driving signal to the light-emitting element 400 by electrically connecting to the first electrode 410 of the light-emitting element 400, thereby driving the light-emitting element 400 to emit light for display. Specifically, the display panel 10 also includes a first connection portion 310, a second connection portion 320, and a third connection portion 330. The initialization transistor T6, the first emission control transistor T5, and the capacitor plate of the storage capacitor Cst are electrically connected through the first connection portion 310. The storage capacitor Cst and the first terminal of the threshold compensation transistor T2 are electrically connected through the second connection portion 320. The first electrode 410 and the storage capacitor Cst are electrically connected through the third connection portion 330. By combining the first connecting part 310, the second connecting part 320 and the third connecting part 330, the electrical connection between the transistor and the storage capacitor Cst in the pixel circuit 200 is realized, as well as the electrical connection between the pixel circuit 200 and the light-emitting element 400 is realized.

[0116] Furthermore, by setting the first connecting portion 310, the second connecting portion 320, and the third connecting portion 330 in the same layer, the overall film thickness of the pixel circuit 200 can be reduced, which is beneficial to realizing the thin design of the display panel 10. During the manufacturing process of the display panel 10, the first connecting portion 310, the second connecting portion 320, and the third connecting portion 330 can be manufactured simultaneously, which can further reduce the manufacturing cost of the display panel 10.

[0117] For example, refer to Figure 2 , Figures 4 to 16 As shown, please refer to the following for details. Figure 12 As shown, the first connecting portion 310, the second connecting portion 320, and the third connecting portion 330 in the display panel 10 are all located on the film layer where the fourth metal layer 1014 is located, demonstrating the same-layer arrangement of the first connecting portion 310, the second connecting portion 320, and the third connecting portion 330. (Refer to...) Figures 5 to 16 As shown, in the pixel circuit 200, the first connection portion 310 electrically connects the initialization transistor T6, the first light-emitting control transistor T5, and the fourth capacitor plate 232 (second storage capacitor 230); the second connection portion 320 electrically connects the capacitor plate connection portion 221a and the threshold compensation transistor T2, that is, the second connection portion 320 electrically connects the first storage capacitor 220, the second storage capacitor 230, and the threshold compensation transistor T2; the third connection portion 330 electrically connects the first electrode 410 (light-emitting element) and the second capacitor plate 222 (first storage capacitor 220). This ensures the electrical connection relationship between the transistors and the storage capacitor Cst in the pixel circuit 200, thereby ensuring the driving stability of the light-emitting element 400 by the pixel circuit 200 and guaranteeing the overall display effect of the display panel 10.

[0118] For example, refer to Figure 2 , Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 24 As shown, the first connecting portion 310, the second connecting portion 320, and the third connecting portion 330 in the display panel 10 are all located on the film layer where the fourth metal layer 1014 is located, demonstrating the same-layer arrangement of the first connecting portion 310, the second connecting portion 320, and the third connecting portion 330. (Refer to...) Figures 17 to 28 As shown, in the pixel circuit 200, the first connection portion 310 electrically connects the initialization transistor T6, the first light-emitting control transistor T5, and the fourth capacitor plate 232 (second storage capacitor 230); the second connection portion 320 electrically connects the capacitor plate connection portion 221a and the threshold compensation transistor T2, that is, the second connection portion 320 electrically connects the first storage capacitor 220, the second storage capacitor 230, and the threshold compensation transistor T2; the third connection portion 330 electrically connects the first electrode 410 (light-emitting element) and the second capacitor plate 222 (first storage capacitor 220). This ensures the electrical connection relationship between the transistors and the storage capacitor Cst in the pixel circuit 200, thereby ensuring the driving stability of the light-emitting element 400 by the pixel circuit 200 and guaranteeing the overall display effect of the display panel 10.

[0119] For example, refer to Figure 2 , Figures 29 to 41 As shown, please refer to the following for details. Figure 29 and Figure 38As shown, the first connecting portion 310, the second connecting portion 320, and the third connecting portion 330 in the display panel 10 are all located on the film layer where the fourth metal layer 1014 is located, demonstrating the same-layer arrangement of the first connecting portion 310, the second connecting portion 320, and the third connecting portion 330. (Refer to...) Figures 29 to 41 As shown, in the pixel circuit 200, the first connection portion 310 electrically connects the initialization transistor T6, the first light-emitting control transistor T5, and the fourth capacitor plate 232 (second storage capacitor 230); the second connection portion 320 electrically connects the capacitor plate connection portion 221a and the threshold compensation transistor T2, that is, the second connection portion 320 electrically connects the first storage capacitor 220, the second storage capacitor 230, and the threshold compensation transistor T2; the third connection portion 330 electrically connects the first electrode 410 (light-emitting element) and the second capacitor plate 222 (first storage capacitor 220). This ensures the electrical connection relationship between the transistors and the storage capacitor Cst in the pixel circuit 200, thereby ensuring the driving stability of the light-emitting element 400 by the pixel circuit 200 and guaranteeing the overall display effect of the display panel 10.

[0120] Continue to refer Figure 2 , Figures 4 to 41 As shown, the display panel 10 also includes a signal line 500, which includes a first scan signal line SN. The first scan signal line SN is electrically connected to the control terminal of the threshold supplement transistor T2. The first connection portion 310 and the second connection portion 320 are arranged along the first direction X1, and the second connection portion 320 and the third connection portion 330 are arranged along the second direction X2. The first direction X1 and the second direction X2 intersect and are both parallel to the plane where the substrate 100 is located. Along the thickness direction of the display panel 10, the first connection portion 310 and the second connection portion 320 overlap with the first scan signal line SN, and the second capacitor plate 222 covers the third connection portion 330.

[0121] Furthermore, the display panel 10 also includes a signal line 500, which is configured to provide voltage and / or current signals to the pixel circuit 200, thereby enabling the pixel circuit 200 to drive the light-emitting element 400 and realize the display function of the display panel 10. (Refer to...) Figure 2 As shown, signal line 500 includes a first scan signal line SN, which is electrically connected to the control terminal of threshold compensation transistor T2. The signal transmitted in the first scan signal line SN can control the conduction or de-conduction of threshold compensation transistor T2. Combined with... Figure 2 and Figure 3As shown, the threshold compensation transistor T2 is an oxide transistor. When the signal transmitted in the first scan signal line SN is high, the threshold compensation transistor T2 is turned on, and the high level transmitted in the first scan signal line SN is the enable level of the threshold compensation transistor T2. When the signal transmitted in the first scan signal line SN is low, the threshold compensation transistor T2 is turned off, and the low level transmitted in the first scan signal line SN is the disable level of the threshold compensation transistor T2. Furthermore, by combining the signal line 500 and the transistor's placement position, the placement positions of the first connection part 310, the second connection part 320, and the third connection part 330 can be adaptively adjusted, thereby ensuring the flexibility of the pixel circuit 200's placement.

[0122] For example, refer to Figure 2 , Figures 4 to 16 As shown, please refer to the following for details. Figure 12 As shown, the first connecting portion 310 and the second connecting portion 320 are arranged along the first direction X1, and the second connecting portion 320 and the third connecting portion 330 are arranged along the second direction X2. The first direction X1 can be understood as... Figures 5 to 16 The horizontal or vertical direction in the middle, the second direction X2 can be understood as... Figures 5 to 16 The column direction or vertical direction. Further, refer to... Figure 8 , Figure 10 , Figure 12 and Figure 13 As shown, the first scan signal line SN extends along the first direction X1; Reference Figure 12 and Figure 13 As shown, the first connecting portion 310 and the second connecting portion 320 are also arranged along the first direction X1. Furthermore, along the direction behind the display panel 10, the location of the first connecting portion 310 overlaps with the location of the first scan signal line SN. Considering the relative positions of the first connecting portion 310 and the second connecting portion 320, the location of the second connecting portion 320 also overlaps with the location of the first scan signal line SN. This demonstrates the location of the first connecting portion 310 and the second connecting portion 320 within the pixel circuit 200. Further, considering... Figures 11 to 13 As shown, the third connecting part 330 is electrically connected to the second capacitor plate 222, and the third connecting part 330 and the second capacitor plate 222 overlap along the thickness direction of the display panel 10. Specifically, the second capacitor plate 222 covers the third connecting part 330, thus showing the setting position of the third connecting part 330 in the pixel circuit 200.

[0123] For example, refer to Figure 2 , Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 24As shown, the first connecting portion 310 and the second connecting portion 320 are arranged along the first direction X1, and the second connecting portion 320 and the third connecting portion 330 are arranged along the second direction X2. The first direction X1 can be understood as... Figures 17 to 28 The horizontal or vertical direction in the middle, the second direction X2 can be understood as... Figures 17 to 28 The column direction or vertical direction. Further, refer to... Figure 20 , Figure 22 , Figure 24 and Figure 25 As shown, the first scan signal line SN extends along the first direction X1; Reference Figure 24 and Figure 25 As shown, the first connecting portion 310 and the second connecting portion 320 are also arranged along the first direction X1. Furthermore, along the direction behind the display panel 10, the location of the first connecting portion 310 overlaps with the location of the first scan signal line SN. Considering the relative positions of the first connecting portion 310 and the second connecting portion 320, the location of the second connecting portion 320 also overlaps with the location of the first scan signal line SN. This demonstrates the location of the first connecting portion 310 and the second connecting portion 320 within the pixel circuit 200. Further, considering... Figures 23 to 25 As shown, the third connecting part 330 is electrically connected to the second capacitor plate 222, and the third connecting part 330 and the second capacitor plate 222 overlap along the thickness direction of the display panel 10. Specifically, the second capacitor plate 222 covers the third connecting part 330, thus showing the setting position of the third connecting part 330 in the pixel circuit 200.

[0124] For example, refer to Figure 2 , Figures 29 to 41 As shown, please refer to the following for details. Figure 38 As shown, the first connecting portion 310 and the second connecting portion 320 are arranged along the first direction X1, and the second connecting portion 320 and the third connecting portion 330 are arranged along the second direction X2. The first direction X1 can be understood as... Figures 30 to 41 The horizontal or vertical direction in the middle, the second direction X2 can be understood as... Figures 30 to 41 The column direction or vertical direction. Further, refer to... Figure 33 , Figure 35 , Figure 38 and Figure 39 As shown, the first scan signal line SN extends along the first direction X1; Reference Figure 38 and Figure 39As shown, the first connecting portion 310 and the second connecting portion 320 are also arranged along the first direction X1. Furthermore, along the direction behind the display panel 10, the location of the first connecting portion 310 overlaps with the location of the first scan signal line SN. Considering the relative positions of the first connecting portion 310 and the second connecting portion 320, the location of the second connecting portion 320 also overlaps with the location of the first scan signal line SN. This demonstrates the location of the first connecting portion 310 and the second connecting portion 320 within the pixel circuit 200. Further, considering... Figure 36 , Figure 38 and Figure 39 As shown, the third connecting part 330 is electrically connected to the second capacitor plate 222, and the third connecting part 330 and the second capacitor plate 222 overlap along the thickness direction of the display panel 10. Specifically, the second capacitor plate 222 covers the third connecting part 330, thus showing the setting position of the third connecting part 330 in the pixel circuit 200.

[0125] Continue to refer Figures 4 to 41 As shown, the overlapping area of ​​the first capacitor plate 221 and the second capacitor plate 222 is greater than the overlapping area of ​​the third capacitor plate 231 and the fourth capacitor plate 232.

[0126] Specifically, for the first storage capacitor 220 and the second storage capacitor 230 in the pixel circuit 200, the relative area of ​​the plates of the first storage capacitor 220 and the area of ​​the plates of the second storage capacitor 230 can be adjusted to be different, thereby achieving differentiated settings for the first storage capacitor 220 and the second storage capacitor 230. This can be understood as the first storage capacitor 220 and the second storage capacitor 230 adjusting their plate areas according to the available space in the pixel circuit 200, thus making the pixel circuit 200 setup more flexible and helping to reduce the space occupied by the pixel circuit 200 in the display panel 10.

[0127] For example, refer to Figures 5 to 16 As shown, please refer to the following for details. Figure 10 The projected area of ​​the first capacitor plate 221 onto the substrate 100 is larger than the projected area of ​​the third capacitor plate 231 onto the substrate 100, for reference. Figure 11 As shown, the projected area of ​​the second capacitor plate 222 onto the substrate 100 is larger than the projected area of ​​the fourth capacitor plate 232 onto the substrate 100. Furthermore, in conjunction with the reference... Figure 10 and Figure 11As shown, the overlapping area of ​​the first capacitor plate 221 and the second capacitor plate 222 is larger than the overlapping area of ​​the third capacitor plate 231 and the fourth capacitor plate 232. Specifically, part of the structure of the first capacitor plate 221 reuses the first gate 212 of the driving transistor T3. Since the area of ​​the first gate 212 is larger, the plate area of ​​the first capacitor plate 221 is also larger, thus the plate area of ​​the first capacitor plate 221 is larger than that of the third capacitor plate 231. The first storage capacitor 220 can be understood as the main body of the storage capacitor Cst, and the second storage capacitor 230 can be understood as the supplementary part of the storage capacitor Cst. Furthermore, the second capacitor plate 222 is correspondingly arranged with the first capacitor plate 221, and the fourth capacitor plate 232 is correspondingly arranged with the third capacitor plate 231. The relative area of ​​the plates of the first storage capacitor 220 is larger than that of the second storage capacitor 230. By cooperating with the first storage capacitor 220 and the second storage capacitor 230, a larger storage capacitance or a more flexible adjustment of the capacitance value can be achieved.

[0128] For example, refer to Figures 17 to 28 As shown, please refer to the following for details. Figure 22 The projected area of ​​the first capacitor plate 221 onto the substrate 100 is larger than the projected area of ​​the third capacitor plate 231 onto the substrate 100, for reference. Figure 23 As shown, the projected area of ​​the second capacitor plate 222 onto the substrate 100 is larger than the projected area of ​​the fourth capacitor plate 232 onto the substrate 100. Furthermore, in conjunction with the reference... Figure 22 and Figure 23 As shown, the overlapping area of ​​the first capacitor plate 221 and the second capacitor plate 222 is greater than the overlapping area of ​​the third capacitor plate 231 and the fourth capacitor plate 232. Specifically, the first capacitor plate 221 partially reuses the first gate 212 of the driving transistor T3. Since the area of ​​the first gate 212 is larger, the plate area of ​​the first capacitor plate 221 is also larger, thus the plate area of ​​the first capacitor plate 221 is greater than that of the third capacitor plate 231. The first storage capacitor 220 can be understood as the main body of the storage capacitor Cst, and the second storage capacitor 230 can be understood as the supplementary part of the storage capacitor Cst. Furthermore, the second capacitor plate 222 is correspondingly arranged with the first capacitor plate 221, and the fourth capacitor plate 232 is correspondingly arranged with the third capacitor plate 231. The relative area of ​​the plates of the first storage capacitor 220 is greater than that of the plates of the second storage capacitor 230. By cooperating with the first storage capacitor 220 and the second storage capacitor 230, a larger storage capacitance or a more flexible adjustment of the capacitance value can be achieved.

[0129] For example, refer to Figures 30 to 41 As shown, please refer to the following for details. Figure 35The projected area of ​​the first capacitor plate 221 onto the substrate 100 is larger than the projected area of ​​the third capacitor plate 231 onto the substrate 100, for reference. Figure 36 As shown, the projected area of ​​the second capacitor plate 222 onto the substrate 100 is larger than the projected area of ​​the fourth capacitor plate 232 onto the substrate 100. Furthermore, in conjunction with the reference... Figure 35 and Figure 36 As shown, the overlapping area of ​​the first capacitor plate 221 and the second capacitor plate 222 is greater than the overlapping area of ​​the third capacitor plate 231 and the fourth capacitor plate 232. Specifically, the first capacitor plate 221 partially reuses the first gate 212 of the driving transistor T3. Since the area of ​​the first gate 212 is larger, the plate area of ​​the first capacitor plate 221 is also larger, thus the plate area of ​​the first capacitor plate 221 is greater than that of the third capacitor plate 231. The first storage capacitor 220 can be understood as the main body of the storage capacitor Cst, and the second storage capacitor 230 can be understood as the supplementary part of the storage capacitor Cst. Furthermore, the second capacitor plate 222 is correspondingly arranged with the first capacitor plate 221, and the fourth capacitor plate 232 is correspondingly arranged with the third capacitor plate 231. The relative area of ​​the plates of the first storage capacitor 220 is greater than that of the plates of the second storage capacitor 230. By cooperating with the first storage capacitor 220 and the second storage capacitor 230, a larger storage capacitance or a more flexible adjustment of the capacitance value can be achieved.

[0130] Continue to refer Figure 2 , Figures 4 to 41 As shown, the projection of the overlapping area of ​​the first capacitor plate 221 and the second capacitor plate 222 onto the plane of the substrate 100 is the first overlapping projection, and the projection of the overlapping area of ​​the third capacitor plate 231 and the fourth capacitor plate 232 onto the plane of the substrate 100 is the second overlapping projection; the first type transistor 210 also includes a threshold compensation transistor T2; the pixel circuit 200 also includes a first light-emitting control transistor T5; the display panel also includes a signal line 500, which includes a first scan signal line SN and a first light-emitting control signal line EM2. The first scan signal line SN is electrically connected to the control terminal of the threshold compensation transistor T2, and the first light-emitting control signal line EM2 is electrically connected to the first light-emitting control transistor T5. The control terminal of the control transistor T5 is electrically connected; the projection of the first scan signal line SN onto the plane of the substrate 100 is the first scan line projection, and the projection of the first light emission control signal line EM2 onto the plane of the substrate 100 is the second scan line projection; the first overlapping projection includes a first boundary 611 near the first scan line projection and a second boundary 621 near the second scan line projection, and the second overlapping projection includes a third boundary 631 near the first scan line projection and a fourth boundary 641 near the second scan line projection; the first boundary 611 is located on the side of the third boundary 631 away from the first scan line projection, and the second boundary 621 is located on the side of the fourth boundary 641 near the second scan line projection.

[0131] In the pixel circuit 200, the threshold compensation transistor T2 can also be a first-type transistor 210. The first gate 212 of the threshold compensation transistor T2 and the first gate 212 of the driving transistor T3 are disposed on the same layer, and are also disposed on the same layer as one of the capacitor plates in the first storage capacitor 220. (Reference) Figure 2 As shown, the signal line 500 in the display panel 10 includes a first scan signal line SN and a first light emission control signal line EM2. The first scan signal line SN is electrically connected to the control terminal of the threshold compensation transistor T2, so that the signal transmitted in the first scan signal line SN can control the conduction or de-conduction of the threshold compensation transistor T2. The first light emission control signal line EM2 is electrically connected to the control terminal of the first light emission control transistor T5, so that the signal transmitted in the first light emission control signal line EM2 can control the conduction or de-conduction of the first light emission control transistor T5. Furthermore, the positions of the first storage capacitor 220 and the second storage capacitor 230 can be adaptively adjusted according to the positions of the first scan signal line SN and the first light emission control signal line EM2, reflecting the adaptability between different film layers in the pixel circuit 200.

[0132] For example, refer to Figure 2 , Figures 5 to 16 As shown, please refer to the following for details. Figure 10 , Figure 11 and Figure 13 As shown, the projection of the overlapping area of ​​the first capacitor plate 221 and the second capacitor plate 222 onto the plane of the substrate 100 is the first overlapping projection, which can also be understood as the area of ​​the two plates facing each other in the first storage capacitor 220. Similarly, the projection of the overlapping area of ​​the third capacitor plate 231 and the fourth capacitor plate 232 onto the plane of the substrate 100 is the second overlapping projection, which can also be understood as the area of ​​the two plates facing each other in the second storage capacitor 230. Further, refer to... Figure 8 , Figure 10 , Figure 11 and Figure 13 As shown, the projection of the first scan signal line SN onto the plane of the substrate 100 is the first scan line projection, and the projection of the first light emission control signal line EM2 onto the plane of the substrate 100 is the second scan line projection. Figure 13 As shown, the first overlapping projection includes a first boundary 611 and a second boundary 621. The first boundary 611 is located on the side of the second boundary 621 closer to the first scan line projection, and the second boundary 621 is located on the side of the first boundary 611 closer to the second scan line projection. That is, the first overlapping projection of the first storage capacitor 220 is located between the first scan line projection and the second scan line projection. Figure 13As shown, the second overlapping projection includes a third boundary 631 and a fourth boundary 641. The third boundary 631 is located on the side of the fourth boundary 641 closer to the first scan line projection, and the fourth boundary 641 is located on the side of the third boundary 631 closer to the second scan line projection. In other words, the second overlapping projection of the second storage capacitor 230 is located between the first scan line projection and the second scan line projection. Further, refer to... Figure 13 As shown, the first boundary 611 is located on the side of the third boundary 631 away from the projection of the first scan line, and the second boundary 621 is located on the side of the fourth boundary 641 closer to the projection of the second scan line. In other words, the first storage capacitor 220 is positioned closer to the first light-emitting control signal line EM2 than the second storage capacitor 230. Thus, the relative positional relationship between the first storage capacitor 220 and the second storage capacitor 230 is represented by different signal lines 500.

[0133] For example, refer to Figure 2 , Figures 17 to 28 As shown, please refer to the following for details. Figure 22 , Figure 23 and Figure 25 As shown, the projection of the overlapping area of ​​the first capacitor plate 221 and the second capacitor plate 222 onto the plane of the substrate 100 is the first overlapping projection, which can also be understood as the area of ​​the two plates facing each other in the first storage capacitor 220. Similarly, the projection of the overlapping area of ​​the third capacitor plate 231 and the fourth capacitor plate 232 onto the plane of the substrate 100 is the second overlapping projection, which can also be understood as the area of ​​the two plates facing each other in the second storage capacitor 230. Further, refer to... Figure 20 , Figure 22 , Figure 23 and Figure 25 As shown, the projection of the first scan signal line SN onto the plane of the substrate 100 is the first scan line projection, and the projection of the first light emission control signal line EM2 onto the plane of the substrate 100 is the second scan line projection. Figure 25 As shown, the first overlapping projection includes a first boundary 611 and a second boundary 621. The first boundary 611 is located on the side of the second boundary 621 closer to the first scan line projection, and the second boundary 621 is located on the side of the first boundary 611 closer to the second scan line projection. That is, the first overlapping projection of the first storage capacitor 220 is located between the first scan line projection and the second scan line projection. Figure 25 As shown, the second overlapping projection includes a third boundary 631 and a fourth boundary 641. The third boundary 631 is located on the side of the fourth boundary 641 closer to the first scan line projection, and the fourth boundary 641 is located on the side of the third boundary 631 closer to the second scan line projection. In other words, the second overlapping projection of the second storage capacitor 230 is located between the first scan line projection and the second scan line projection. Further, refer to... Figure 25As shown, the first boundary 611 is located on the side of the third boundary 631 away from the projection of the first scan line, and the second boundary 621 is located on the side of the fourth boundary 641 closer to the projection of the second scan line. In other words, the first storage capacitor 220 is positioned closer to the first light-emitting control signal line EM2 than the second storage capacitor 230. Thus, the relative positional relationship between the first storage capacitor 220 and the second storage capacitor 230 is represented by different signal lines 500.

[0134] For example, refer to Figure 2 , Figures 30 to 41 As shown, please refer to the following for details. Figure 35 , Figure 36 and Figure 38 As shown, the projection of the overlapping area of ​​the first capacitor plate 221 and the second capacitor plate 222 onto the plane of the substrate 100 is the first overlapping projection, which can also be understood as the area of ​​the two plates facing each other in the first storage capacitor 220. Similarly, the projection of the overlapping area of ​​the third capacitor plate 231 and the fourth capacitor plate 232 onto the plane of the substrate 100 is the second overlapping projection, which can also be understood as the area of ​​the two plates facing each other in the second storage capacitor 230. Further, refer to... Figure 33 , Figure 35 , Figure 36 and Figure 38 As shown, the projection of the first scan signal line SN onto the plane of the substrate 100 is the first scan line projection, and the projection of the first light emission control signal line EM2 onto the plane of the substrate 100 is the second scan line projection. Figure 38 As shown, the first overlapping projection includes a first boundary 611 and a second boundary 621. The first boundary 611 is located on the side of the second boundary 621 closer to the first scan line projection, and the second boundary 621 is located on the side of the first boundary 611 closer to the second scan line projection. That is, the first overlapping projection of the first storage capacitor 220 is located between the first scan line projection and the second scan line projection. Figure 38 As shown, the second overlapping projection includes a third boundary 631 and a fourth boundary 641. The third boundary 631 is located on the side of the fourth boundary 641 closer to the first scan line projection, and the fourth boundary 641 is located on the side of the third boundary 631 closer to the second scan line projection. In other words, the second overlapping projection of the second storage capacitor 230 is located between the first scan line projection and the second scan line projection. Further, refer to... Figure 38As shown, the first boundary 611 is located on the side of the third boundary 631 away from the projection of the first scan line, and the second boundary 621 is located on the side of the fourth boundary 641 closer to the projection of the second scan line. In other words, the first storage capacitor 220 is positioned closer to the first light-emitting control signal line EM2 than the second storage capacitor 230. Thus, the relative positional relationship between the first storage capacitor 220 and the second storage capacitor 230 is represented by different signal lines 500.

[0135] Continue to refer Figure 2 , Figures 4 to 41 As shown, the first type transistor 210 also includes a second gate 213, which is located on the side of the first active layer 211 near the substrate 100; the first type transistor 210 includes a driving transistor T3; the pixel circuit 200 also includes a data writing transistor T4; the display panel 10 also includes a fourth connection portion 340, which connects the first end of the data writing transistor T4, the second end of the driving transistor T3, and the second gate 213 of the driving transistor T3.

[0136] The first type transistor 210 also includes a second gate 213, which is located on the side of the first active layer 211 closest to the substrate 100. Therefore, the second gate 213 can be understood as the bottom gate structure in the first type transistor 210. The first type transistor 210 can simultaneously have a first gate 212 and a second gate 213, meaning that the first type transistor 210 is a top-bottom dual-gate structure. This ensures that the first type transistor 210 has a better response to the control signals for turning on or off.

[0137] For further reference, Figure 2 As shown, the pixel circuit 200 includes a driving transistor T3 and a data writing transistor T4, wherein the driving transistor T3 is a first type transistor 210. One end of the driving transistor T3, the bottom gate of the driving transistor T3, and the output terminal of the data writing transistor T4 are electrically connected to the third node N3. Specifically, the display panel 10 includes a fourth connection portion 340, through which the driving transistor T3 and the data writing transistor T4 are electrically connected.

[0138] For example, refer to Figure 2 , Figures 4 to 16 As shown, in conjunction with reference Figure 12 As shown, the display panel 10 includes a fourth connection portion 340, which is located on the film layer where the fourth metal layer 1014 is located. The fourth connection portion 340 includes a seventh connection terminal 340a, an eighth connection terminal 340b, and a ninth connection terminal 340c, which are combined with... Figure 7 , Figure 8 , Figure 12 and Figure 13As shown, the seventh connection terminal 340a is electrically connected to the output terminal of the data writing transistor T4; combined with Figure 8 , Figure 9 , Figure 10 , Figure 12 and Figure 13 As shown, the eighth connection terminal 340b is electrically connected to one end of the driving transistor T3, and the ninth connection terminal 340c is electrically connected to the second gate 213 of the driving transistor T3. Therefore, the fourth connection part 310 connects the data writing transistor T4 and the driving transistor T3, ensuring the transmission of signals in the pixel circuit 200 and ensuring the overall display effect of the display panel 10.

[0139] For example, refer to Figure 2 , Figure 4 , Figures 17 to 28 As shown, in conjunction with reference Figure 24 As shown, the display panel 10 includes a fourth connecting portion 340, which is located on the film layer where the fourth metal layer 1014 is located. (Combined with...) Figure 19 , Figure 20 , Figure 24 and Figure 25 As shown, one end of the fourth connection portion 340 is electrically connected to the output terminal of the data writing transistor T4; combined with Figure 20 , Figure 21 , Figure 22 , Figure 24 and Figure 25 As shown, one end of the fourth connection portion 340 is electrically connected to one end of the driving transistor T3, and the other end of the fourth connection portion 340 is electrically connected to the second gate 213 of the driving transistor T3. Therefore, the fourth connection portion 310 connects the data writing transistor T4 and the driving transistor T3, ensuring the transmission of signals in the pixel circuit 200 and ensuring the overall display effect of the display panel 10.

[0140] For example, refer to Figure 2 , Figures 29 to 41 As shown, in conjunction with reference Figure 39 As shown, the display panel 10 includes a fourth connecting portion 340, which is located on the film layer where the fourth metal layer 1014 is located. (Combined with...) Figure 32 , Figure 33 , Figure 38 and Figure 39 As shown, one end of the fourth connection portion 340 is electrically connected to the output terminal of the data writing transistor T4; combined with Figure 33 , Figure 34 , Figure 34 , Figure 38 and Figure 39As shown, one end of the fourth connection portion 340 is electrically connected to one end of the driving transistor T3, and the other end of the fourth connection portion 340 is electrically connected to the second gate 213 of the driving transistor T3. Therefore, the fourth connection portion 310 connects the data writing transistor T4 and the driving transistor T3, ensuring the transmission of signals in the pixel circuit 200 and ensuring the overall display effect of the display panel 10.

[0141] Continue to refer Figure 2 , Figures 4 to 41 As shown, the pixel circuit 200 also includes a second type transistor 240, which includes a second active layer 241 and a third gate 242. The second active layer includes silicon, and the third gate 242 is located on the side of the second active layer 241 away from the substrate 100, or the third gate 242 is located on the side of the second active layer 241 close to the substrate 100; the second gate 213 and the third gate 242 are disposed on the same layer.

[0142] The pixel circuit 200 further includes a second type transistor 240, which includes a second active layer 241 and a third gate 242. The second active layer 241 includes silicon, and the second type transistor 240 can be a low-temperature polysilicon transistor, for example, referencing... Figure 2 The second light-emitting control transistor T1 is used. Furthermore, the third gate 242 can be located on the side of the second active layer 241 away from the substrate 100, and the third gate 242 can be understood as the top gate of the second type transistor 240; or the third gate 242 can be located on the side of the second active layer 241 close to the substrate 100, and the third gate 242 can be understood as the bottom gate of the second type transistor 240. The specific location of the third gate 242 can be adaptively adjusted according to implementation requirements. Furthermore, in the first type transistor 210, the second gate 213 is located on the side of the first active layer 211 close to the substrate 100; in the second type transistor 240, when the third gate 242 is located on the side of the second active layer 241 away from the substrate 100, the second gate 213 and the third gate 242 can be disposed on the same layer. This can reduce the overall film thickness of the pixel circuit 200, which is beneficial for achieving a thinner design of the display panel 10 and can also reduce the manufacturing cost of the display panel.

[0143] For example, refer to Figure 2 , Figures 4 to 16 As shown, please refer to the following for details. Figure 7 and Figure 8 As shown, the second type transistor 240 can be a second light-emitting control transistor T1, a data writing transistor T4, and a first light-emitting control transistor T5, etc., wherein the second active layer 241 of the second type transistor 240 is located in the film layer where the first semiconductor layer 104 is located, and the third gate 242 is located in the film layer where the first metal layer 106 is located. Therefore, Figures 4 to 16 The example is illustrated by placing the third gate 242 on the side of the second active layer 241 away from the substrate 100. Further, refer to... Figure 8 As shown, the second gate 213 of the first type transistor 210 is also located in the film layer where the first metal layer 106 is located, so the second gate 213 and the third gate 242 are disposed in the same layer.

[0144] For example, refer to Figure 2 , Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 19 and Figure 20 As shown, the second type transistor 240 can be a second light-emitting control transistor T1, a data writing transistor T4, and a first light-emitting control transistor T5, etc., wherein the second active layer 241 of the second type transistor 240 is located in the film layer where the first semiconductor layer 104 is located, and the third gate 242 is located in the film layer where the first metal layer 106 is located. Therefore, Figures 17 to 28 The example is illustrated by placing the third gate 242 on the side of the second active layer 241 away from the substrate 100. Further, refer to... Figure 20 As shown, the second gate 213 of the first type transistor 210 is also located in the film layer where the first metal layer 106 is located, so the second gate 213 and the third gate 242 are disposed in the same layer.

[0145] For example, refer to Figure 2 , Figures 29 to 41 As shown, please refer to the following for details. Figure 32 and Figure 33 As shown, the second type transistor 240 can be a second light-emitting control transistor T1, a data writing transistor T4, and a first light-emitting control transistor T5, etc., wherein the second active layer 241 of the second type transistor 240 is located in the film layer where the first semiconductor layer 104 is located, and the third gate 242 is located in the film layer where the first metal layer 106 is located. Therefore, Figures 30 to 41 The example is illustrated by placing the third gate 242 on the side of the second active layer 241 away from the substrate 100. Further, refer to... Figure 33 As shown, the second gate 213 of the first type transistor 210 is also located in the film layer where the first metal layer 106 is located, so the second gate 213 and the third gate 242 are disposed in the same layer.

[0146] Continue to refer Figure 2 , Figures 4 to 28As shown, the pixel circuit 200 further includes a driving transistor T3 and a second light-emitting control transistor T1; the display panel also includes a signal line 500, the signal line including a positive power signal line PVDD; the second light-emitting control transistor T1 is electrically connected between the positive power signal line PVDD and the driving transistor T3; the positive power signal line PVDD includes a first positive power signal line PVDDa, the first positive power signal line PVDDa extends along a first direction X1, multiple first positive power signal lines PVDDa are arranged along a second direction X2, the first direction X1 and the second direction X2 intersect; the first positive power signal line PVDDa is disposed on the same layer as the first capacitor plate 221 or the second capacitor plate 222.

[0147] Among them, reference Figure 2 As shown, the pixel circuit 200 includes a driving transistor T3 and a second light-emitting control transistor T1. The second light-emitting control transistor T1 is located between the positive power signal line PVDD and the driving transistor T3. When the second light-emitting control transistor T1 is in the on state, the signal transmitted through the positive power signal line PVDD can be transmitted to the driving transistor T3 through the second light-emitting control transistor T1. Furthermore, in order to minimize the overall number of film layers in the pixel circuit 200, a portion of the trace of the positive power signal line PVDD can be disposed on the same layer as the electrode of the first storage capacitor 220.

[0148] For example, refer to Figures 4 to 16 As shown, please refer to the following for details. Figure 11 As shown, the positive power signal line PVDD includes multiple first positive power signal lines PVDDa, which extend along a first direction X1, and are located in the film layer containing the third metal layer 1012. Further, refer to... Figure 11 As shown, the second capacitor plate 222 of the first storage capacitor 220 is located on the film layer where the third metal layer 1012 is located. Therefore, the first positive power signal line PVDDa can be set on the same layer as the second capacitor plate 222, which can reduce the overall film layer thickness of the pixel circuit 200. At the same time, the first positive power signal line PVDDa and the second capacitor plate 222 can also be prepared simultaneously, reducing the manufacturing cost of the display panel 10.

[0149] For example, refer to Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 22 As shown, the positive power signal line PVDD includes multiple first positive power signal lines PVDDa, which extend along a first direction X1, and are located in the film layer containing the second metal layer 1010. Further, refer to... Figure 22As shown, the first capacitor plate 221 of the first storage capacitor 220 is located on the film layer where the second metal layer 1010 is located. Therefore, the first positive power signal line PVDDa can be set on the same layer as the first capacitor plate 221, which can reduce the overall film layer thickness of the pixel circuit 200. At the same time, the first positive power signal line PVDDa and the second capacitor plate 222 can also be prepared simultaneously, reducing the manufacturing cost of the display panel 10.

[0150] Optional, see reference Figures 29 to 41 As shown, please refer to the following for details. Figure 37 As shown, the positive power signal line PVDD includes multiple first positive power signal lines PVDDa. The multiple first positive power signal lines PVDDa extend along the first direction X1. At the same time, the first positive power signal lines PVDDa are located in the film layer where the fifth metal layer 1016 is located. Therefore, the first positive power signal lines PVDDa can also be set in the same layer as other traces, thus reflecting the flexible setting method of the first positive power signal lines PVDDa.

[0151] Continue to refer Figure 2 , Figures 4 to 28 As shown, the positive power signal line PVDD also includes a second positive power signal line PVDDb, which extends along the second direction X2, and multiple second positive power signal lines PVDDb are arranged along the first direction X1; the second positive power signal line PVDDb and the first positive power signal line PVDDa are disposed in different layers and electrically connected.

[0152] The positive power signal line PVDD comprises an electrically connected first positive power signal line PVDDa and a second positive power signal line PVDDb. The extension directions of the first positive power signal line PVDDa and the second positive power signal line PVDDb are different. Therefore, the first positive power signal line PVDDa and the second positive power signal line PVDDb can form a grid-like distribution of positive power signal lines PVDD. This grid-like distribution of positive power signal lines PVDD ensures good signal transmission performance, improving the balance of positive power signal transmission within the positive power signal line PVDD, and also demonstrates the flexibility in setting up the positive power signal PVDD.

[0153] For example, refer to Figure 2 , Figures 4 to 16 As shown, please refer to the following for details. Figure 14 and Figure 16 As shown, the second positive power signal line PVDDb extends along the second direction X2, and the second positive power signal line PVDDb is located in the film layer containing the fifth metal layer 1016. (Reference) Figure 11 As shown, the first positive power signal line PVDDa is located in the film layer containing the third metal layer 1012. (Reference) Figure 11 , Figure 12 and Figure 14 As shown, in Figure 12 It includes a positive power signal line connection portion 350, through which a second positive power signal line PVDDb located in the fifth metal layer 1016 and a first positive power signal line PVDDa located in the third metal layer 1012 are electrically connected. (See also...) Figure 5 As shown, the first positive power signal line PVDDa and the second positive power signal line PVDDb, which are electrically connected, form a mesh-like routing pattern.

[0154] For example, refer to Figure 2 , Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 26 and Figure 28 As shown, the second positive power signal line PVDDb extends along the second direction X2, and the second positive power signal line PVDDb is located in the film layer containing the fifth metal layer 1016. (Reference) Figure 22 As shown, the first positive power signal line PVDDa is located in the film layer containing the second metal layer 1010. (Reference) Figure 22 , Figure 24 and Figure 26 As shown, in Figure 24 It includes a positive power signal line connection portion 350, through which a second positive power signal line PVDDb located in the fifth metal layer 1016 and a first positive power signal line PVDDa located in the third metal layer 1012 are electrically connected. (See also...) Figure 17 As shown, the first positive power signal line PVDDa and the second positive power signal line PVDDb, which are electrically connected, form a mesh-like routing pattern.

[0155] Optional, see reference Figure 2 , Figures 29 to 41 As shown, please refer to the following for details. Figure 40 As shown, the second positive power signal line PVDDb extends along the second direction X2, and the second positive power signal line PVDDb is located in the film layer containing the sixth metal layer 1019. (Reference) Figure 37 As shown, the first positive power signal line PVDDa is located in the film layer containing the fifth metal layer 1016. (Reference) Figure 37 , Figure 39 and Figure 40 As shown, in Figure 34 The device includes a positive power signal line connection portion 350, which is located in the film layer containing the fourth metal layer 1014. Therefore, the second positive power signal line PVDDb located in the fifth metal layer 1016 and the first positive power signal line PVDDa located in the third metal layer 1012 are electrically connected through the positive power signal line connection portion 350. (See also...) Figure 30 As shown, the first positive power signal line PVDDa and the second positive power signal line PVDDb, which are electrically connected, form a mesh-like routing pattern.

[0156] Continue to refer Figure 2 , Figures 4 to 41 As shown, the pixel circuit 200 also includes an initialization transistor T6; the display panel 10 also includes a signal line 500, which includes an initialization signal line VREF; the initialization transistor T6 is electrically connected between the initialization signal line VREF and the first storage capacitor 220; the initialization signal line VREF includes a first initialization signal line VREFa, which extends along a first direction X1, and multiple first initialization signal lines VREFa are arranged along a second direction X2, where the first direction X1 and the second direction X2 intersect; the first initialization signal line VREFa is disposed on the same layer as the first capacitor plate 221 or the second capacitor plate 222.

[0157] Among them, reference Figure 2 As shown, the pixel circuit 200 includes an initialization transistor T6, which is located between the initialization signal line VREF and the first storage capacitor 220. When the initialization signal line VREF controls the initialization transistor T6 to be turned on, the reset signal transmitted by the initialization signal line VREF can be transmitted to the first storage capacitor 220 and to the light-emitting element 400 through the initialization transistor T6. Furthermore, in order to minimize the overall number of film layers in the pixel circuit 200, a portion of the initialization signal line VREF can be disposed on the same layer as the electrode of the first storage capacitor 220.

[0158] For example, refer to Figures 4 to 16 As shown, please refer to the following for details. Figure 10 As shown, the initialization signal line VREF includes multiple first initialization signal lines VREFa, which extend along a first direction X1, and are located in the film layer containing the second metal layer 1010. Further, refer to... Figure 10 As shown, the first capacitor plate 221 of the first storage capacitor 220 is located on the film layer where the second metal layer 1010 is located. Therefore, the first initialization signal line VREFa can be set on the same layer as the first capacitor plate 221, which can reduce the overall film layer thickness of the pixel circuit 200. At the same time, the first initialization signal line VREFa and the first capacitor plate 221 can be prepared simultaneously, reducing the manufacturing cost of the display panel 10.

[0159] For example, refer to Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 23As shown, the initialization signal line VREF includes multiple first initialization signal lines VREFa, which extend along a first direction X1, and are located in the film layer containing the third metal layer 1012. Further, refer to... Figure 23 As shown, the second capacitor plate 222 of the first storage capacitor 220 is located on the film layer where the third metal layer 1012 is located. Therefore, the first initialization signal line VREFa can be set on the same layer as the second capacitor plate 222, which can reduce the overall film layer thickness of the pixel circuit 200. At the same time, the first initialization signal line VREFa and the second capacitor plate 222 can be prepared simultaneously, reducing the manufacturing cost of the display panel 10.

[0160] For example, refer to Figures 29 to 41 As shown, please refer to the following for details. Figure 35 As shown, the initialization signal line VREF includes multiple first initialization signal lines VREFa, which extend along a first direction X1, and are located in the film layer containing the second metal layer 1010. Further, refer to... Figure 35 As shown, the first capacitor plate 221 of the first storage capacitor 220 is located on the film layer where the second metal layer 1010 is located. Therefore, the first initialization signal line VREFa can be set on the same layer as the first capacitor plate 221, which can reduce the overall film layer thickness of the pixel circuit 200. At the same time, the first initialization signal line VREFa and the first capacitor plate 221 can be prepared simultaneously, reducing the manufacturing cost of the display panel 10.

[0161] Continue to refer Figure 2 , Figures 4 to 41 As shown, the display panel 10 also includes a light-emitting element 400, which includes a second electrode 420; the display panel 10 also includes a signal line 500, which includes a negative power signal line PVEE; the second electrode 420 is electrically connected to the negative power signal line PVEE; the negative power signal line PVEE includes a first negative power signal line PVEEa, which extends along a first direction X1, and multiple first negative power signal lines PVEEa are arranged along a second direction X2, and the first direction X1 and the second direction X2 intersect; the first negative power signal line PVEEa is disposed on the same layer as the first capacitor plate 221 or the second capacitor plate 222.

[0162] Among them, reference Figure 2As shown, the pixel circuit 200 includes a light-emitting element 400, which includes a second electrode 420. The second electrode 420 can be understood as the cathode in the light-emitting element 400. The second electrode 420 is electrically connected to the negative power signal line PVEE, and the first electrode 410 is electrically connected to the pixel circuit 200. Furthermore, in order to minimize the overall number of film layers in the pixel circuit 200, a portion of the traces of the negative power signal line PVEE can be disposed on the same layer as the electrode plate of the first storage capacitor 220.

[0163] For example, refer to Figures 4 to 16 As shown, please refer to the following for details. Figure 10 As shown, the negative power signal line PVEE includes multiple first negative power signal lines PVEEa, which extend along a first direction X1, and are located in the film layer containing the second metal layer 1010. Further, refer to... Figure 10 As shown, the first capacitor plate 221 of the first storage capacitor 220 is located in the film layer where the second metal layer 1010 is located. Therefore, the first negative power signal line PVEEa can be set in the same layer as the first capacitor plate 221, which can reduce the overall film layer thickness of the pixel circuit 200. At the same time, the first negative power signal line PVEEa and the first capacitor plate 221 can be fabricated simultaneously, reducing the manufacturing cost of the display panel 10.

[0164] For example, refer to Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 23 As shown, the negative power signal line PVEE includes multiple first negative power signal lines PVEEa, which extend along the first direction X1. Simultaneously, the first initialization signal line VREFa is located in the film layer containing the third metal layer 1012. Further, refer to... Figure 23 As shown, the second capacitor plate 222 of the first storage capacitor 220 is located on the film layer where the third metal layer 1012 is located. Therefore, the first negative power signal line PVEEa can be set on the same layer as the second capacitor plate 222, which can reduce the overall film layer thickness of the pixel circuit 200. At the same time, the first negative power signal line PVEEa and the second capacitor plate 222 can be prepared simultaneously, reducing the manufacturing cost of the display panel 10.

[0165] For example, refer to Figures 29 to 41 As shown, please refer to the following for details. Figure 35 As shown, the negative power signal line PVEE includes multiple first negative power signal lines PVEEa, which extend along a first direction X1, and are located in the film layer containing the third metal layer 1012. Further, refer to... Figure 36As shown, the second capacitor plate 222 of the first storage capacitor 220 is located on the film layer where the third metal layer 1012 is located. Therefore, the first negative power signal line PVEEa can be set on the same layer as the second capacitor plate 222, which can reduce the overall film layer thickness of the pixel circuit 200. At the same time, the first negative power signal line PVEEa and the second capacitor plate 222 can be prepared simultaneously, reducing the manufacturing cost of the display panel 10.

[0166] Continue to refer Figure 2 , Figures 4 to 28 As shown, the pixel circuit 200 also includes an initialization transistor T6; the display panel 10 also includes a signal line 500 and a light-emitting element 400. The signal line 500 includes an initialization signal line VREF and a negative power supply signal line PVEE. The light-emitting element 400 includes a second electrode 420. The initialization transistor T6 is electrically connected between the initialization signal line VREF and the first storage capacitor 220. The second electrode 420 is electrically connected to the negative power supply signal line PVEE. The initialization signal line VREF includes a first initialization signal line VREFa, which runs along a first direction X1. Extending, multiple first initialization signal lines VREFa are arranged along the second direction X2; the negative power signal line PVEE includes a first negative power signal line PVEEa, which extends along the first direction X1, and multiple first negative power signal lines PVEEa are arranged along the second direction X2; the first direction X1 and the second direction X2 intersect; the first initialization signal line VREFa and the first negative power signal line PVEEa are arranged on the same layer, and along the second direction X2, the first initialization signal line VREFa and the first negative power signal line PVEEa are arranged alternately.

[0167] Among them, reference Figure 2 As shown, the initialization transistor T6 is located between the initialization signal line VREF and the first storage capacitor 220. When the initialization signal line VREF controls the initialization transistor T6 to be on, the reset signal transmitted by the initialization signal line VREF can be transmitted to the first storage capacitor 220 and to the light-emitting element 400 through the initialization transistor T6. Simultaneously, the second electrode 420 of the light-emitting element 400 in the pixel circuit 200 is electrically connected to the negative power supply signal line PVEE. Furthermore, to minimize the overall number of film layers in the pixel circuit 200, a portion of the initialization signal line VREF and a portion of the negative power supply signal line PVEE can be disposed on the same layer as the electrode plate of the first storage capacitor 220.

[0168] For example, refer to Figures 4 to 16 As shown, please refer to the following for details. Figure 10As shown, the negative power signal line PVEE includes multiple first negative power signal lines PVEEa, which extend along a first direction X1. The initialization signal line VREF includes multiple first initialization signal lines VREFa, which extend along the first direction X1. Both the first negative power signal lines PVEEa and the first initialization signal lines VREFa are located in the film layer containing the second metal layer 1010. Further, refer to... Figure 10 As shown, the first capacitor plate 221 of the first storage capacitor 220 is located on the film layer where the second metal layer 1010 is located. Therefore, the first initialization signal line VREFa and the first negative power signal line PVEEa are both disposed on the same layer as the first capacitor plate 221, which can reduce the overall film layer thickness of the pixel circuit 200 and reduce the manufacturing cost of the display panel 10. Furthermore, along the second direction X2, the first initialization signal line VREFa and the first negative power signal line PVEEa are arranged alternately. By alternating the traces that are on the same layer and extend in the same direction, the balanced arrangement of the traces of the display panel 10 can be ensured, thus ensuring the regularity of the display panel 10.

[0169] For example, refer to Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 23 As shown, the negative power signal line PVEE includes multiple first negative power signal lines PVEEa, which extend along a first direction X1. The initialization signal line VREF includes multiple first initialization signal lines VREFa, which extend along the first direction X1. Both the first negative power signal lines PVEEa and the first initialization signal lines VREFa are located in the film layer containing the third metal layer 1012. Further, refer to... Figure 23 As shown, the first capacitor plate 221 of the first storage capacitor 220 is located on the film layer where the second metal layer 1010 is located. Therefore, the first initialization signal line VREFa and the first negative power signal line PVEEa are both disposed on the same layer as the first capacitor plate 221, which can reduce the overall film layer thickness of the pixel circuit 200 and reduce the manufacturing cost of the display panel 10. Furthermore, along the second direction X2, the first initialization signal line VREFa and the first negative power signal line PVEEa are arranged alternately. By alternating the traces that are on the same layer and extend in the same direction, the balanced arrangement of the traces of the display panel 10 can be ensured, thus ensuring the regularity of the display panel 10.

[0170] Continue to refer Figure 2 , Figures 4 to 28As shown, the initialization signal line VREF further includes a second initialization signal line VREFb, which extends along a second direction X2, and multiple second initialization signal lines VREFb are arranged along a first direction X1; the second initialization signal line VREFb and the first initialization signal line VREFa are disposed on different layers and electrically connected; the negative power signal line PVEE further includes a second negative power signal line PVEEb, which extends along a second direction X2, and multiple first negative power signal lines PVEEa are arranged along a first direction X1; the second negative power signal line PVEEb and the first negative power signal line PVEEa are disposed on different layers and electrically connected; the second initialization signal line VREFb and the second negative power signal line PVEEb are disposed on the same layer and along the first direction X1, and the second initialization signal line VREFb and the second negative power signal line PVEEb are arranged alternately.

[0171] The initialization signal line VREF includes a first initialization signal line VREFa and a second initialization signal line VREFb that are electrically connected. The extension direction of the first initialization signal line VREFa is different from that of the second initialization signal line VREFb. Therefore, the first initialization signal line VREFa and the second initialization signal line VREFb can form a grid-like distribution of the initialization signal line VREF. The grid-like distribution of the initialization signal line VREF can ensure the signal transmission effect, that is, improve the balance of the reset signal transmission in the initialization signal line VREF, and also reflect the flexibility of the initialization signal line VREF setting. Furthermore, the negative power signal line PVEE includes a first negative power signal line PVEEa and a second negative power signal line PVEEb that are electrically connected. The extension direction of the first negative power signal line PVEEa is different from that of the second negative power signal line PVEEb. Therefore, the first negative power signal line PVEEa and the second negative power signal line PVEEb can form a grid-like distribution of the negative power signal line PVEE. A grid-like distribution of negative power signal lines (PVEE) can ensure signal transmission quality, improving the balance of negative power signal transmission within the PVEE and demonstrating the flexibility of PVEE configuration.

[0172] For example, refer to Figure 2 , Figures 4 to 16 As shown, please refer to the following for details. Figure 10 , Figure 12 and Figure 14 As shown, the second initialization signal line VREFb extends along the second direction X2, and the second initialization signal line VREFb is located in the film layer containing the fifth metal layer 1016. (Reference) Figure 10 As shown, the first initialization signal line VREFa is located in the film layer where the second metal layer 1010 is located. (Reference) Figure 10 , Figure 12 and Figure 14 As shown, in Figure 12 It includes an initialization signal line connection portion 360, through which a second initialization signal line VREFb located in the fifth metal layer 1016 and a first initialization signal line VREFa located in the second metal layer 1010 are electrically connected. (See also...) Figure 5 As shown, the first initialization signal line VREFa and the second initialization signal line VREFb form a mesh-like routing pattern for electrical connections. Further details can be found in the reference [link / reference needed]. Figure 10 , Figure 12 and Figure 14 As shown, the second negative power signal line PVEEb extends along the second direction X2, and the second negative power signal line PVEEb is located in the film layer containing the fifth metal layer 1016. (Reference) Figure 10 As shown, the first initial negative power supply signal line PVEEa is located in the film layer where the second metal layer 1010 is located. (Reference) Figure 10 , Figure 12 and Figure 14 As shown, in Figure 12 It includes a negative power signal line connection portion 370, through which a second negative power signal line PVEEb located in the fifth metal layer 1016 and a first negative power signal line PVEEa located in the second metal layer 1010 are electrically connected. (See also...) Figure 5 As shown, the first negative power signal line PVEEa and the second negative power signal line PVEEb form a mesh-like routing pattern. (Refer to...) Figure 14 As shown, the second initialization signal line VREFb and the second negative power signal line PVEEb are located in the same film layer, and the two are arranged alternately along the first direction X1, which can ensure the balanced arrangement of the traces of the display panel 10 and ensure the regularity of the display panel 10.

[0173] For example, refer to Figure 2 , Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 23 , Figure 24 and Figure 26 As shown, the second initialization signal line VREFb extends along the second direction X2, and the second initialization signal line VREFb is located in the film layer containing the fifth metal layer 1016. (Reference) Figure 23 As shown, the first initialization signal line VREFa is located in the film layer containing the second metal layer 1010. (Reference) Figure 23 , Figure 24 and Figure 26 As shown, in Figure 24It includes an initialization signal line connection portion 360, through which a second initialization signal line VREFb located in the fifth metal layer 1016 and a first initialization signal line VREFa located in the second metal layer 1010 are electrically connected. (See also...) Figure 17 As shown, the first initialization signal line VREFa and the second initialization signal line VREFb form a mesh-like routing pattern for electrical connections. Further details can be found in the reference [link / reference needed]. Figure 23 , Figure 24 and Figure 26 As shown, the second negative power signal line PVEEb extends along the second direction X2, and the second negative power signal line PVEEb is located in the film layer containing the fifth metal layer 1016. (Reference) Figure 23 As shown, the first initial negative power supply signal line PVEEa is located in the film layer where the second metal layer 1010 is located. (Reference) Figure 23 , Figure 24 and Figure 26 As shown, in Figure 24 It includes a negative power signal line connection portion 370, through which a second negative power signal line PVEEb located in the fifth metal layer 1016 and a first negative power signal line PVEEa located in the second metal layer 1010 are electrically connected. (See also...) Figure 17 As shown, the first negative power signal line PVEEa and the second negative power signal line PVEEb form a mesh-like routing pattern. (Refer to...) Figure 26 As shown, the second initialization signal line VREFb and the second negative power signal line PVEEb are located in the same film layer, and the two are arranged alternately along the first direction X1, which can ensure the balanced arrangement of the traces of the display panel 10 and ensure the regularity of the display panel 10.

[0174] Optional, see reference Figure 2 , Figures 29 to 41 As shown, please refer to the following for details. Figure 35 , Figure 39 and Figure 40 As shown, the second initialization signal line VREFb extends along the second direction X2, and the second initialization signal line VREFb is located in the film layer containing the sixth metal layer 1019. (Reference) Figure 35 As shown, the first initialization signal line VREFa is located in the film layer where the second metal layer 1010 is located. (Reference) Figure 35 , Figure 39 and Figure 40 As shown, in Figure 39 The device includes an initialization signal line connection portion 360, through which a second initialization signal line VREFb located in the sixth metal layer 1019 and a first initialization signal line VREFa located in the second metal layer 1010 are electrically connected. (See also...) Figure 30As shown, the first initialization signal line VREFa and the second initialization signal line VREFb form a mesh-like routing pattern for electrical connections. Further details can be found in the reference [link / reference needed]. Figure 36 , Figure 39 and Figure 40 As shown, the second negative power signal line PVEEb extends along the second direction X2, and the second negative power signal line PVEEb is located in the film layer containing the sixth metal layer 1019. (Reference) Figure 36 As shown, the first initial negative power signal line PVEEa is located in the film layer containing the third metal layer 1012. (Reference) Figure 36 , Figure 39 and Figure 40 As shown, in Figure 39 It includes a negative power signal line connection portion 370, through which a second negative power signal line PVEEb located in the sixth metal layer 1019 and a first negative power signal line PVEEa located in the third metal layer 1012 are electrically connected. (See also...) Figure 30 As shown, the first negative power signal line PVEEa and the second negative power signal line PVEEb form a mesh-like routing pattern. (Refer to...) Figure 40 As shown, the second initialization signal line VREFb and the second negative power signal line PVEEb are located in the same film layer, and the two are arranged alternately along the first direction X1, which can ensure the balanced arrangement of the traces of the display panel 10 and ensure the regularity of the display panel 10.

[0175] Figure 42 This is a schematic diagram of the structure of the second type of display panel provided in an embodiment of the present invention, for reference. Figure 1 , Figure 2 and Figure 42 As shown, the display panel 10 also includes multiple signal lines 500; the signal lines 500 include data signal lines VDATA, the multiple data signal lines VDATA are arranged along a first direction X1 and extend along a second direction X2, the first direction X1 and the second direction X2 intersect; the display panel 10 also includes a display area AA and a non-display area NA that at least partially surrounds the display area AA, the display area AA includes a first display area AA1 and a second display area AA2, the second display area AA2 is located on at least one side of the first display area AA1 along the first direction X1; both the first display area AA1 and the second display area AA2 include multiple data signal lines VDATA; the non-display area NA includes a fan-out area A1 located on one side of the display area AA along the second direction X2, the fan-out area A1 includes multiple fan-out traces S0; the signal lines 500 also include multiple data auxiliary lines 510, the data signal lines VDATA located in the second display area AA2 are electrically connected to the fan-out traces S0 through the data auxiliary lines 510.

[0176] The signal line 500 includes a data signal line VDATA, which provides data signals to the pixel circuit 200. For details, refer to... Figure 42 As shown, multiple data signal lines VDATA extend along the second direction X2 and are arranged along the first direction X1, thus illustrating the overall setup and layout of the data signal lines VDATA. It should be noted that the diagram only illustrates the electrical connection between the data signal lines VDATA and the pixel circuit 200 through their overlap, but does not limit the position or area of ​​the overlap. Furthermore, in conjunction with... Figure 42 As shown, multiple pixel circuits 200 arranged along the second direction X2 are electrically connected to the same data signal line VDATA, that is, multiple pixel circuits 200 arranged along the second direction X2 receive data signals provided by the same data signal line VDATA; it can be understood that pixel circuits 200 arranged in the same column are electrically connected to the same data signal line VDATA.

[0177] Further reference Figure 42 As shown, the display panel 10 includes a display area AA and a non-display area NA. The display area AA includes a light-emitting element (not specifically shown in the figure) and a data signal line VDATA connected to the light-emitting element, etc., for realizing the display function of the display panel 10. The non-display area NA includes a display controller, such as a driver chip (not specifically shown in the figure), connected to the data signal line VDATA. The display controller provides data signals to the data signal line VDATA, thereby driving the display panel 10 to realize the display function. The non-display area NA surrounds at least a portion of the display area AA. Based on the specific locations of the display area AA and the non-display area NA, the embodiments of the present invention do not impose specific limitations.

[0178] Further reference Figure 42 As shown, the non-display area NA also includes a fan-out area A1, which includes multiple fan-out traces S0. The fan-out traces S0 are electrically connected to multiple data signal lines VDATA, meaning that the display controller can transmit data signals to the data signal lines VDATA through the fan-out traces S0, thereby ensuring stable transmission of data signals.

[0179] Specifically, the display area AA includes a first display area AA1 and a second display area AA2. The second display area AA2 is located on both sides of the first display area AA1, and is closer to the boundary of the display area AA than the first display area AA1. In the first display area AA1, the data signal line VDATA extends along the second direction X2 and is arranged along the first direction X1, and the data signal line VDATA can be directly electrically connected to the fan-out trace S0. In the second display area AA2, the data signal line VDATA also extends along the second direction X2 and is arranged along the first direction X1, but the data signal line VDATA is not directly electrically connected to the fan-out trace S0. (Reference) Figure 42 As shown, the signal line 500 also includes a data auxiliary line 510. The data auxiliary line 510 electrically connects the data signal line VDATA located in the second display area AA2 to the fan-out trace S0. The data signal is transmitted to the data signal line VDATA located in the second display area AA1 through the fan-out trace S0 and the data auxiliary line 510. This avoids the direct electrical connection between the data signal line VDATA in the second display area AA1 and the fan-out trace S0, reducing the space occupied by the fan-out trace S0, thereby reducing the area of ​​the fan-out area A1, effectively reducing the proportion of the non-display area NA, increasing the proportion of the display area AA of the display panel 10, and improving the display effect of the display panel 10. It should be noted that there are various ways to configure the data auxiliary line 510. Figure 42 This is just an example; the routing methods for all data auxiliary lines 510 are not shown one by one.

[0180] Continue to refer Figure 42 As shown, the data auxiliary line 510 includes a first auxiliary line segment 511 and a second auxiliary line segment 512. The first auxiliary line segment 511 extends along a first direction X1, and the second auxiliary line segment 512 extends along a second direction X2. The first auxiliary line segment 511 and the second auxiliary line segment 512 are electrically connected to the data signal line VDATA located in the second display area AA2, and the second auxiliary line segment 512 is electrically connected to the fan-out routing line S0.

[0181] Furthermore, the data auxiliary line 510 includes a first auxiliary line segment 511 and a second auxiliary delimiter 512, wherein the extension directions of the first auxiliary line segment 511 and the second auxiliary line segment 512 are different. Specifically, the extension direction of the second auxiliary line segment 512 is the same as the extension direction of the data signal line VDATA, and the extension direction of the first auxiliary line segment 511 intersects with the extension direction of the data signal line VDATA. Figure 42As shown, the data signal line VDATA located in the second display area AA2 can be electrically connected to the fan-out trace S0 in sequence through the first auxiliary line segment 511 and the second auxiliary line segment 512, so as to realize the transmission of the data signal provided by the fan-out trace S0 to the data signal line VDATA in the second display area AA2. The first auxiliary line segment 511 and the second auxiliary line segment 512 realize the flexible arrangement of the data auxiliary trace 510 in the display panel 10.

[0182] Figure 43 yes Figure 42 A schematic diagram of the first type of partial membrane structure. Figure 44 yes Figure 42 The second type of partial membrane structure is shown in the schematic diagram. (Refer to...) Figures 42 to 44 As shown, the display panel also includes virtual auxiliary lines 520, which include a first virtual auxiliary line segment 521 and / or a second virtual auxiliary line segment 522. The first virtual auxiliary line segment 521 extends along a first direction X1, is disposed on the same layer as the first auxiliary line segment 511, and has a first gap S1 between them. The second virtual auxiliary line segment 522 extends along a second direction X2, is disposed on the same layer as the second auxiliary line segment 522, and has a second gap between it and the second auxiliary line segment 512. The display panel 10 also includes a light-emitting element 400, which includes a first electrode 410. Along the thickness direction of the display panel 10, the first gap S1 and / or the second gap S2 overlap with the first electrode 410.

[0183] The display panel 10 also includes virtual auxiliary lines 520 located in the display area AA. The virtual auxiliary lines 520 include a first virtual auxiliary line segment 521 and a second virtual auxiliary line segment 522, or the virtual auxiliary lines 520 include either the first virtual auxiliary line segment 521 or the second virtual auxiliary line segment 522. The setting method of the virtual auxiliary lines 520 can be adaptively adjusted according to the needs of the display panel 10. Figure 42 The display panel 10 includes a first virtual auxiliary line segment 521 and a second virtual auxiliary line segment 522 for illustrative purposes.

[0184] Among them, reference Figure 43 As shown, the extension direction of the first virtual auxiliary line segment 521 is the same as that of the first auxiliary line segment 511, and both are arranged on the same layer. A first gap S1 exists between the first virtual auxiliary line segment 521 and the first auxiliary line segment 511, which can be understood as the first virtual auxiliary line segment 521 and the first auxiliary line segment 511 being insulated from each other. (Reference) Figure 44As shown, the extension direction of the second virtual auxiliary line segment 522 is the same as that of the second auxiliary line segment 512, and both are arranged on the same layer. A second gap exists between the second auxiliary line segment 522 and the second auxiliary line segment 512, which can be understood as the second virtual auxiliary line segment 522 being insulated from the second auxiliary line segment 512. In general, since the virtual auxiliary line 520 and the data auxiliary line 510 are on the same layer and insulated, the arrangement of the virtual auxiliary line 520 will not affect the signal transmission in the data auxiliary line 510. For example, refer to... Figure 42 As shown, the data signal provided by the fan-out trace S0 is transmitted through the second auxiliary segment 512 and the first auxiliary segment 511 (see reference). Figure 43 (As shown in the middle routing line C1); Reference Figure 43 As shown, the data signal provided by the fan-out trace S0 is transmitted through the second auxiliary segment 512 and the first auxiliary segment 511 (see reference). Figure 44 (As shown in the middle routing line C2).

[0185] The virtual auxiliary line 520 ensures overall wiring balance and does not affect the normal signal transmission in the data auxiliary line 510. For example, the virtual auxiliary line 520 can be placed in areas not covered by the data auxiliary line 510. In other words, by setting the virtual auxiliary line 520, the wiring in the area where the data auxiliary line 510 is set is balanced overall, ensuring uniform wiring density in different areas. This avoids uneven light reflectivity in different areas of the display panel 10 due to uneven wiring, thus preventing uneven display effects.

[0186] Further reference Figure 42 and Figure 43 As shown, along the thickness direction of the display panel 10, the first electrode 410 of the light-emitting element 400 overlaps with the first gap S1 and / or the second gap S2. This can also be understood as the first electrode 410 covering the first gap S1 and / or the second gap S2. The gap between the virtual auxiliary line 520 and the data auxiliary line 510 is blocked by the first electrode 410, which can prevent color shift in the light transmission of the display panel 10 due to the existence of the gap, thereby ensuring the overall display effect of the display panel 10. Simultaneously, the first electrode 410 covering the first gap S1 and / or the second gap S2 also helps improve the overall flatness of the display panel 10.

[0187] Continue to refer Figure 42 and Figure 43As shown, the display panel 10 also includes a virtual auxiliary line 520, which includes a first virtual auxiliary line segment 521. The first virtual auxiliary line segment 521 extends along a first direction X1, is disposed on the same layer as the first auxiliary line segment 511, and has a first gap S1 between them. The pixel circuit 200 also includes a driving transistor T3 and a second light-emitting control transistor T1. The display panel also includes a signal line 500, which includes a positive power signal line PVDD. The second light-emitting control transistor T2 is electrically connected between the positive power signal line PVDD and the driving transistor T3. The positive power signal line PVDD includes a second positive power signal line PVDDb, which extends along a second direction X2. Multiple second positive power signal lines PVDDb are arranged along the first direction X1, and the first direction X1 and the second direction X2 intersect. Along the thickness direction of the display panel 10, the first gap S1 overlaps with the second positive power signal line PVDDb.

[0188] In this design, the first virtual auxiliary line segment 521 of the virtual auxiliary line 520 extends in the same direction as the first auxiliary line segment 511. Due to the insulation between the virtual auxiliary line 520 and the data auxiliary line 510, a first gap S1 exists between the first auxiliary line segment 511 and the data auxiliary line 510, which are arranged on the same layer. Further, refer to... Figure 24 As shown, the display panel 10 also includes a positive power signal line PVDD, and the positive power signal line PVDD further includes a second positive power signal line PVDDb extending along the second direction X2. Along the thickness direction of the display panel 10, the first gap S1 overlaps with the second positive power signal line PVDDb, which can also be understood as the second positive power signal line PVDDb covering the first gap S1, thus improving the overall flatness of the display panel 10.

[0189] For example, see corresponding reference. Figure 12 , Figure 14 and Figure 43 As shown, please refer to the following for details. Figure 12 As shown, the first auxiliary line segment 511 extending along the first direction X1 is located in the film layer where the fourth metal layer 1014 is located. Since the first virtual auxiliary line segment 521 is disposed in the same layer as the first auxiliary line segment 511, the first virtual auxiliary line segment 521 is also located in the film layer where the fourth metal layer 1014 is located. (Reference) Figure 14 As shown, the second positive power signal line PVDDb is located in the film layer containing the fifth metal layer 1016. The film layer containing the second positive power signal line PVDDb is located on the side of the film layer containing the first auxiliary line segment 511 that is away from the substrate 100. Similarly, the film layer containing the second positive power signal line PVDDb is located on the side of the film layer containing the first virtual auxiliary line segment 521 that is away from the substrate 100. Further, refer to... Figure 43As shown, the second positive power signal line PVDDb covers the first gap S1, which helps to improve the overall flatness of the display panel 10.

[0190] For example, see corresponding reference. Figure 24 , Figure 26 and Figure 43 As shown, please refer to the following for details. Figure 24 As shown, the first auxiliary line segment 511 extending along the first direction X1 is located in the film layer where the fourth metal layer 1014 is located. Since the first virtual auxiliary line segment 521 is disposed in the same layer as the first auxiliary line segment 511, the first virtual auxiliary line segment 521 is also located in the film layer where the fourth metal layer 1014 is located. (Reference) Figure 26 As shown, the second positive power signal line PVDDb is located in the film layer containing the fifth metal layer 1016. The film layer containing the second positive power signal line PVDDb is located on the side of the film layer containing the first auxiliary line segment 511 that is away from the substrate 100. Similarly, the film layer containing the second positive power signal line PVDDb is located on the side of the film layer containing the first virtual auxiliary line segment 521 that is away from the substrate 100. Further, refer to... Figure 43 As shown, the second positive power signal line PVDDb covers the first gap S1, which helps to improve the overall flatness of the display panel 10.

[0191] For example, see corresponding reference. Figure 37 , Figure 40 and Figure 43 As shown, please refer to the following for details. Figure 37 As shown, the first auxiliary line segment 511 extending along the first direction X1 is located in the film layer where the fifth metal layer 1016 is located. Since the first virtual auxiliary line segment 521 is disposed in the same layer as the first auxiliary line segment 511, the first virtual auxiliary line segment 521 is also located in the film layer where the fourth metal layer 1014 is located. (Reference) Figure 40 As shown, the second positive power signal line PVDDb is located in the film layer containing the sixth metal layer 1019. The film layer containing the second positive power signal line PVDDb is located on the side of the film layer containing the first auxiliary line segment 511 that is away from the substrate 100. Similarly, the film layer containing the second positive power signal line PVDDb is located on the side of the film layer containing the first virtual auxiliary line segment 521 that is away from the substrate 100. Further, refer to... Figure 43 As shown, the second positive power signal line PVDDb covers the first gap S1, which helps to improve the overall flatness of the display panel 10.

[0192] Continue to refer Figures 42 to 44 As shown, the first virtual auxiliary line segment 521 and / or the second virtual auxiliary line segment 522 are electrically connected to the fixed potential signal line.

[0193] Furthermore, the virtual auxiliary line 520 is electrically connected to the fixed potential signal line, thereby connecting the virtual auxiliary line 520 to the fixed point signal. This avoids interference to the display caused by the virtual auxiliary line 520 floating and coupling with other signals. Additionally, the parallel connection of the virtual auxiliary line 520 and the fixed potential signal line reduces the resistance at the fixed signal terminal or on the fixed potential signal line, ensuring minimal loss of the fixed potential signal during transmission. For example, the fixed potential signal line electrically connected to the first virtual auxiliary line segment 521 and / or the second virtual auxiliary line segment 522 can be a positive power signal PVDD or a negative power signal PVEE, etc. Based on the type of fixed potential signal line, adaptive adjustments can be made according to different display panels 10.

[0194] Continue to refer Figure 2 , Figures 4 to 42 As shown, the pixel circuit 200 further includes a driving transistor T3, a second light-emitting control transistor T1, and a data writing transistor T4; the signal line 500 includes a positive power signal line PVDD and a second scan signal line SP; the second light-emitting control transistor T1 is electrically connected between the positive power signal line PVDD and the driving transistor T3; the control terminal of the data writing transistor T4 is electrically connected to the second scan signal line SP; the positive power signal line PVDD includes a first positive power signal line PVDDa, which extends along a first direction X1, and multiple first positive power signal lines PVDDa are arranged along a second direction X2, with the first direction X1 and the second direction X2 intersecting; the orthographic projection of the first positive power signal line PVDDa onto the plane of the substrate 100 is located between the orthographic projection of the first auxiliary line segment 511 onto the plane of the substrate 100 and the orthographic projection of the second scan signal line SP onto the plane of the substrate 100.

[0195] Among them, reference Figure 2 As shown, the signal line 500 of the display panel 10 also includes a positive power signal line PVDD, which is connected to the input terminal of the second light-emitting control transistor T1. When the second light-emitting control transistor T1 is turned on, the power signal in the positive power signal line PVDD is transmitted to the driving transistor T3 through the second light-emitting control transistor T1. The signal line 500 of the display panel 10 also includes a second scan signal line SP, which is electrically connected to the control terminal of the data writing transistor T4. When the second scan signal line SP controls the data writing transistor T4 to turn on, the data signal line VDATA, which is electrically connected to the input terminal of the data writing transistor T4, is transmitted to the driving transistor T3 through the data writing transistor T4. Further, refer to... Figure 2 and Figure 42As shown, the routing positions of signal lines 500 can be adjusted, such as the routing positions of data auxiliary line 510, positive power signal line PVDD, and second scan signal line SP. The first positive power signal line PVDDa isolates the mutual interference between the signal in the first auxiliary line segment 511 and the signal in the second scan signal line SP, preventing the switching scan signal line signal in the second scan signal line SP from affecting the data signal line transmitted in the first auxiliary line segment 511, ensuring the signal transmission stability of the display panel 10, and also demonstrating the flexibility of the pixel circuit 200.

[0196] For example, refer to Figure 2 , Figures 4 to 16 As shown, please refer to the following for details. Figure 11 As shown, the positive power signal line PVD includes a first positive power signal line PVDDa extending along the first direction X1, and the first positive power signal line PVDDa is located in the film layer where the third metal layer 1012 is located; see specific reference. Figure 8 As shown, the second scan signal line SP, extending along the first direction X1, is located in the film layer where the first metal layer 106 is located; see specific reference. Figure 12 As shown, the first auxiliary line segment 511 extending along the first direction X1 in the data auxiliary line 510 is located in the film layer where the fourth metal layer 1014 is located; referring to the reference Figure 11 , Figure 8 , Figure 12 and Figure 13 As shown, the first positive power signal line PVDDa, the second scan signal line SP, and the first auxiliary line segment 511 are arranged in different layers. Further, refer to... Figure 4 and Figure 13 As shown, along the thickness direction of the display panel 10, the projection of the first positive power signal line PVDDa is located between the projection of the second scan signal line SP and the projection of the first auxiliary line segment 511. In other words, without considering the layer configuration, the first positive power signal line PVDDa is located between the second scan signal line SP and the first auxiliary line segment 511.

[0197] For example, refer to Figure 2 , Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 22 As shown, the positive power signal line PVD includes a first positive power signal line PVDDa extending along the first direction X1, and the first positive power signal line PVDDa is located in the film layer where the second metal layer 1010 is located; see specific reference. Figure 20 As shown, the second scan signal line SP, extending along the first direction X1, is located in the film layer where the first metal layer 106 is located; see specific reference. Figure 24As shown, the first auxiliary line segment 511 extending along the first direction X1 in the data auxiliary line 510 is located in the film layer where the fourth metal layer 1014 is located; referring to the reference Figure 22 , Figure 20 , Figure 24 and Figure 25 As shown, the first positive power signal line PVDDa, the second scan signal line SP, and the first auxiliary line segment 511 are arranged in different layers. Further, refer to... Figure 17 and Figure 25 As shown, along the thickness direction of the display panel 10, the projection of the first positive power signal line PVDDa is located between the projection of the second scan signal line SP and the projection of the first auxiliary line segment 511. In other words, without considering the layer configuration, the first positive power signal line PVDDa is located between the second scan signal line SP and the first auxiliary line segment 511.

[0198] For example, refer to Figure 2 , Figures 29 to 41 As shown, please refer to the following for details. Figure 37 As shown, the positive power signal line PVD includes a first positive power signal line PVDDa extending along the first direction X1, and the first positive power signal line PVDDa is located in the film layer where the fifth metal layer 1016 is located; see specific reference. Figure 33 As shown, the second scan signal line SP, extending along the first direction X1, is located in the film layer where the first metal layer 106 is located; see specific reference. Figure 39 As shown, the first auxiliary line segment 511 extending along the first direction X1 in the data auxiliary line 510 is located in the film layer where the fourth metal layer 1014 is located; referring to the reference Figure 37 , Figure 33 and Figure 39 As shown, the first positive power signal line PVDDa, the second scan signal line SP, and the first auxiliary line segment 511 are arranged in different layers. Further, refer to... Figure 30 As shown, along the thickness direction of the display panel 10, the projection of the first positive power signal line PVDDa is located between the projection of the second scan signal line SP and the projection of the first auxiliary line segment 511. In other words, without considering the layer configuration, the first positive power signal line PVDDa is located between the second scan signal line SP and the first auxiliary line segment 511.

[0199] Continue to refer Figure 2 , Figures 4 to 42As shown, the pixel circuit 200 further includes an initialization transistor T6 and a second light-emitting control transistor T1; the display panel 10 further includes a signal line 500, which includes an initialization signal line VREF and a second light-emitting control signal line EM1; the initialization transistor T6 is electrically connected between the initialization signal line VREF and the first storage capacitor 220, and the control terminal of the second light-emitting control transistor T1 is electrically connected to the second light-emitting control signal line EM1; the initialization signal line VREF includes a first initialization signal line VREFa, which extends along a first direction X1, and multiple first initialization signal lines VREFa are arranged along a second direction X2, with the first direction X1 and the second direction X2 intersecting; the orthographic projection of the first initialization signal line VREFa onto the plane of the substrate 100 is located between the orthographic projection of the first auxiliary line segment 511 onto the plane of the substrate 100 and the orthographic projection of the second light-emitting control signal line EM1 onto the plane of the substrate 100.

[0200] Among them, reference Figure 2 As shown, the signal line 500 of the display panel 10 also includes an initialization signal line VREF, which is connected to the input terminal of the initialization transistor T6. When the initialization transistor T6 is turned on, the initialization signal in the initialization signal line VREF is transmitted to the first storage capacitor 220 through the initialization transistor T6. The signal line 500 of the display panel 10 also includes a second light emission control signal line EM1, which is electrically connected to the control terminal of the second light emission control transistor T1. When the second light emission control transistor T1 is turned on, the power supply signal electrically connected to the input terminal of the second light emission control transistor T1 is transmitted to the driving transistor T3 through the second light emission control transistor T1. Further, refer to... Figure 2 and Figure 42 As shown, the routing positions of signal lines 500 can be adjusted, for example, the routing positions of data auxiliary line 510, initialization signal line VREF, and second light emission control signal line EM1 can be adjusted. The first initialization signal line VREFa isolates the mutual interference between the signals in the first auxiliary line segment 511 and the signals in the second light emission control signal line EM1, preventing the switching scanning signal line signals in the second light emission control signal line EM1 from affecting the data signal lines transmitted in the first auxiliary line segment 511, ensuring the signal transmission stability of the display panel 10, and also demonstrating the flexibility of the pixel circuit 200.

[0201] For example, refer to Figure 2 , Figures 4 to 16 As shown, please refer to the following for details. Figure 10As shown, the initialization signal line VREF includes a first initialization signal line VREFa extending along the first direction X1, and the first initialization signal line VREFa is located in the film layer where the second metal layer 1010 is located; see details below. Figure 8 As shown, the second light-emitting control signal line EM1, extending along the first direction X1, is located in the film layer where the first metal layer 106 is located; see specific reference. Figure 12 As shown, the first auxiliary line segment 511 extending along the first direction X1 in the data auxiliary line 510 is located in the film layer where the fourth metal layer 1014 is located; referring to the reference Figure 10 , Figure 8 , Figure 12 and Figure 13 As shown, the first initialization signal line VREFa, the second light emission control signal line EM1, and the first auxiliary line segment 511 are configured in different layers. Further, refer to... Figure 4 and Figure 13 As shown, along the thickness direction of the display panel 10, the projection of the first initialization signal line VREFa is located between the projection of the second light emission control signal line EM1 and the projection of the first auxiliary line segment 511. In other words, without considering the layer setting, the first initialization signal line VREFa is located between the second light emission control signal line EM1 and the first auxiliary line segment 511.

[0202] For example, refer to Figure 2 , Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 23 As shown, the initialization signal line VREF includes a first initialization signal line VREFa extending along the first direction X1, and the first initialization signal line VREFa is located in the film layer where the third metal layer 1012 is located; see details below. Figure 20 As shown, the second light-emitting control signal line EM1, extending along the first direction X1, is located in the film layer where the first metal layer 106 is located; see specific reference. Figure 24 As shown, the first auxiliary line segment 511 extending along the first direction X1 in the data auxiliary line 510 is located in the film layer where the fourth metal layer 1014 is located; referring to the reference Figure 23 , Figure 20 , Figure 24 and Figure 25 As shown, the first initialization signal line VREFa, the second light emission control signal line EM1, and the first auxiliary line segment 511 are arranged in different layers. Further, refer to... Figure 17 and Figure 25 As shown, along the thickness direction of the display panel 10, the projection of the first initialization signal line VREFa is located between the projection of the second light emission control signal line EM1 and the projection of the first auxiliary line segment 511. In other words, without considering the layer setting, the first initialization signal line VREFa is located between the second light emission control signal line EM1 and the first auxiliary line segment 511.

[0203] For example, refer to Figure 2 , Figures 29 to 41 As shown, please refer to the following for details. Figure 35 As shown, the initialization signal line VREF includes a first initialization signal line VREFa extending along the first direction X1, and the first initialization signal line VREFa is located in the film layer where the second metal layer 1010 is located; see details below. Figure 33 As shown, the second light-emitting control signal line EM1, extending along the first direction X1, is located in the film layer where the first metal layer 106 is located; see specific reference. Figure 39 As shown, the first auxiliary line segment 511 extending along the first direction X1 in the data auxiliary line 510 is located in the film layer where the fourth metal layer 1014 is located; referring to the reference Figure 35 , Figure 33 and Figure 39 As shown, the first initialization signal line VREFa, the second light emission control signal line EM1, and the first auxiliary line segment 511 are arranged in different layers. Further, refer to... Figure 30 As shown, along the thickness direction of the display panel 10, the projection of the first initialization signal line VREFa is located between the projection of the second light emission control signal line EM1 and the projection of the first auxiliary line segment 511. In other words, without considering the layer setting, the first initialization signal line VREFa is located between the second light emission control signal line EM1 and the first auxiliary line segment 511.

[0204] Continue to refer to Figure 2 , Figures 4 to 28 , Figure 42 As shown, the pixel circuit 200 further includes a second light-emitting control transistor T1; the display panel 10 further includes a signal line 500 and a light-emitting element 400; the signal line 500 includes a second light-emitting control signal line EM1 and a negative power signal line PVEE; the light-emitting element 400 includes a second electrode 420; the control terminal of the second light-emitting control transistor T1 is electrically connected to the second light-emitting control signal line EM1, and the second electrode 420 is electrically connected to the negative power signal line PVEE; the negative power signal line PVEE includes a first negative power signal line PVEEa, the first negative power signal line PVEEa extends along a first direction X1, and multiple first negative power signal lines PVEEa are arranged along a second direction X2, and the first direction X1 and the second direction X2 intersect; the orthographic projection of the first negative power signal line PVEEa onto the plane of the substrate 100 is located between the orthographic projection of the first auxiliary line segment 511 onto the plane of the substrate 100 and the orthographic projection of the second light-emitting control signal line EM1 onto the plane of the substrate.

[0205] Among them, reference Figure 2As shown, the signal line 500 of the display panel 10 includes a second light-emitting control signal line EM1 and a negative power supply signal line PVEE. The second light-emitting control signal line EM1 is electrically connected to the control terminal of the second light-emitting control transistor T1, and the negative power supply signal line PVEE is electrically connected to the second electrode 420 of the light-emitting element 400. Further, in conjunction with... Figure 2 and Figure 42 As shown, the routing positions of signal lines 500 can be adjusted, for example, the routing positions of the second light emission control signal line EM1, the negative power signal line PVEE, and the data auxiliary line 510 can be adjusted. The first negative power signal line PVEEa isolates the mutual interference between the signal in the first auxiliary line segment 511 and the signal in the second light emission control signal line EM1, preventing the switching scanning signal line signal in the second light emission control signal line EM1 from affecting the data signal line transmitted in the first auxiliary line segment 511, ensuring the signal transmission stability of the display panel 10, and also demonstrating the flexibility of the pixel circuit 200.

[0206] For example, refer to Figure 2 , Figures 4 to 16 As shown, please refer to the following for details. Figure 10 As shown, the negative power signal line PVEE includes a first negative power signal line PVEEa extending along the first direction X1, and the first negative power signal line PVEEa is located in the film layer where the second metal layer 1010 is located; see specific reference. Figure 8 As shown, the second light-emitting control signal line EM1, extending along the first direction X1, is located in the film layer where the first metal layer 106 is located; see specific reference. Figure 12 As shown, the first auxiliary line segment 511 extending along the first direction X1 in the data auxiliary line 510 is located in the film layer where the fourth metal layer 1014 is located; referring to the reference Figure 10 , Figure 8 , Figure 12 and Figure 13 As shown, the first negative power supply signal line PVEEa, the second light emission control signal line EM1, and the first auxiliary line segment 511 are arranged in different layers. Further, refer to... Figure 4 and Figure 13 As shown, along the thickness direction of the display panel 10, the projection of the first negative power signal line PVEEa is located between the projection of the second light emission control signal line EM1 and the projection of the first auxiliary line segment 511. In other words, without considering the layer configuration, the first negative power signal line PVEEa is located between the second light emission control signal line EM1 and the first auxiliary line segment 511.

[0207] For example, refer to Figure 2 , Figure 4 , Figures 17 to 28 As shown, please refer to the following for details. Figure 23As shown, the negative power signal line PVEE includes a first negative power signal line PVEEa extending along the first direction X1, and the first negative power signal line PVEEa is located in the film layer where the third metal layer 1012 is located; see specific reference. Figure 20 As shown, the second light-emitting control signal line EM1, extending along the first direction X1, is located in the film layer where the first metal layer 106 is located; see specific reference. Figure 24 As shown, the first auxiliary line segment 511 extending along the first direction X1 in the data auxiliary line 510 is located in the film layer where the fourth metal layer 1014 is located; referring to the reference Figure 23 , Figure 20 , Figure 24 and Figure 25 As shown, the first negative power supply signal line PVEEa, the second light emission control signal line EM1, and the first auxiliary line segment 511 are arranged in different layers. Further, refer to... Figure 17 and Figure 25 As shown, along the thickness direction of the display panel 10, the projection of the first negative power signal line PVEEa is located between the projection of the second light emission control signal line EM1 and the projection of the first auxiliary line segment 511. In other words, without considering the layer configuration, the first negative power signal line PVEEa is located between the second light emission control signal line EM1 and the first auxiliary line segment 511.

[0208] Continue to refer to Figure 2 , Figures 29 to 42 As shown, the pixel circuit 200 also includes a data writing transistor T4; the display panel 10 also includes a signal line 500 and a light-emitting element 400; the signal line 500 includes a second scan signal line SP and a negative power signal line PVEE; the light-emitting element 400 includes a second electrode 420; the control terminal of the data writing transistor T4 is electrically connected to the second scan signal line SP, and the second electrode 420 is electrically connected to the negative power signal line PVEE; the negative power signal line PVEE includes a first negative power signal line PVEEa, the first negative power signal line PVEEa extends along a first direction X1, and multiple first negative power signal lines PVEEa are arranged along a second direction X2, and the first direction X1 and the second direction X2 intersect; the orthographic projection of the first negative power signal line PVEEa onto the plane of the substrate 100 is located between the orthographic projection of the first auxiliary line segment 511 onto the plane of the substrate 100 and the orthographic projection of the second scan signal line SP onto the plane of the substrate 100.

[0209] Among them, reference Figure 2 As shown, the signal line 500 of the display panel 10 includes a second scan signal line SP and a negative power signal line PVEE. The second scan signal line SP is electrically connected to the control terminal of the data writing transistor T4, and the negative power signal line PVEE is electrically connected to the second electrode 420 of the light-emitting element 400. Further, combined with... Figure 2 and Figure 42 As shown, the routing positions of the signal line 500 can be adjusted, for example, the routing positions of the second scan signal line SP, the negative power signal line PVEE, and the data auxiliary line 510 can be adjusted. The first negative power signal line PVEEa isolates the mutual interference between the signal in the first auxiliary line segment 511 and the signal in the second scan signal line SP, preventing the switching scan signal line signal in the second scan signal line SP from affecting the data signal line transmitted in the first auxiliary line segment 511, ensuring the signal transmission stability of the display panel 10, and also reflecting the flexibility of the pixel circuit 200.

[0210] For example, refer to Figure 2 , Figures 29 to 41 As shown, please refer to the following for details. Figure 36 As shown, the negative power signal line PVEE includes a first negative power signal line PVEEa extending along the first direction X1, and a first initialization signal line VREFa located in the film layer where the third metal layer 1012 is located. Optionally, the first initialization signal line VREFa is also located in the film layer where the second metal layer 101 is located (not specifically shown in the figure); see details. Figure 33 As shown, the second scan signal line SP, extending along the first direction X1, is located in the film layer where the first metal layer 106 is located; see specific reference. Figure 39 As shown, the first auxiliary line segment 511 extending along the first direction X1 in the data auxiliary line 510 is located in the film layer where the fourth metal layer 1014 is located; referring to the reference Figure 35 , Figure 33 and Figure 39 As shown, the first negative power supply signal line PVEEa, the second scan signal line SP, and the first auxiliary line segment 511 are arranged in different layers. Further, refer to... Figure 30 As shown, along the thickness direction of the display panel 10, the projection of the first negative power signal line PVEEa is located between the projection of the second scan signal line SP and the projection of the first auxiliary line segment 511. In other words, without considering the layer configuration, the first negative power signal line PVEEa is located between the second scan signal line SP and the first auxiliary line segment 511.

[0211] Continue to refer to Figures 4 to 41 As shown, the pixel circuit 200 also includes a second type transistor 240, which includes a second active layer 241, which includes silicon. The display panel 10 also includes a zero metal layer 102, which is located on the side of the pixel circuit 200 near the substrate 100. The zero metal layer 102 includes a plurality of light-shielding portions 610, which overlap at least partially with the channel region of the second type transistor 240 along the thickness direction of the display panel 10.

[0212] The pixel circuit 200 further includes a second type transistor 240, the second type transistor 240 including a second active layer 241 comprising silicon, and the second type transistor 240 can be a low-temperature polysilicon transistor. Specifically, the display panel 10 also includes a zero metal layer 102, the zero metal layer 102 including a plurality of light-shielding portions 610, which can block the transmission path of light. Since the light-shielding portions 610 are located on the side of the pixel circuit 200 close to the substrate 100, light transmission to the pixel circuit 200 can be prevented, avoiding light leakage in the pixel circuit 200, thereby ensuring the stability and reliability of the pixel circuit 200.

[0213] Furthermore, the light-shielding portion 610 at least partially overlaps with the channel region of the second type transistor 240. Therefore, the light-shielding portion 610 can prevent light from being transmitted to the second active layer 241 of the second type transistor 240, thereby ensuring the operational stability of the second type transistor 240. The channel region of the second type transistor 240 can be understood as the overlapping area of ​​the third gate 242 and the second active layer 241 along the thickness direction of the display panel 10.

[0214] For example, refer to Figures 4 to 8 , Figure 13 As shown, please refer to the following for details. Figure 6 As shown, the light-shielding portion 610 is located in the film layer where the zero metal layer 102 is located, combined with Figures 6 to 8 , Figure 13 As shown, along the thickness direction of the display panel 10, the light-shielding portion 610 at least partially overlaps with the channel region of the second type transistor 240. The light-shielding portion 610 can block light from interfering with the second type transistor 240, thereby ensuring the stability of the second type transistor 240.

[0215] For example, refer to Figure 4 , Figures 17 to 20 , Figure 25 As shown, please refer to the following for details. Figure 18 As shown, the light-shielding portion 610 is located in the film layer where the zero metal layer 102 is located, combined with Figures 18 to 20 , Figure 25 As shown, along the thickness direction of the display panel 10, the light-shielding portion 610 at least partially overlaps with the channel region of the second type transistor 240. The light-shielding portion 610 can block light from interfering with the second type transistor 240, thereby ensuring the stability of the second type transistor 240.

[0216] For example, refer to Figures 29 to 33 As shown, please refer to the following for details. Figure 31 As shown, the light-shielding portion 610 is located in the film layer where the zero metal layer 102 is located, combined with Figures 31 to 33As shown, along the thickness direction of the display panel 10, the light-shielding portion 610 at least partially overlaps with the channel region of the second type transistor 240. The light-shielding portion 610 can block light from interfering with the second type transistor 240, thereby ensuring the stability of the second type transistor 240.

[0217] Continue to refer to Figures 4 to 41 As shown, the zeroth metal layer 102 is electrically connected to the fixed potential signal line.

[0218] Furthermore, the zeroth metal layer 102 is electrically connected to the fixed potential signal line. The zeroth metal layer 102 can be equivalent to a shielding structure to prevent the signal from interfering with the pixel circuit 200, thereby ensuring the stability and reliability of the pixel circuit 200.

[0219] Specifically, the zero metal layer 102 and the fixed potential signal line can, on the one hand, avoid interference to the display caused by the floating coupling of other signals due to the zero metal layer 102 potential, and on the other hand, the zero metal layer 102 potential and the fixed potential signal line are connected in parallel, which can reduce the resistance of the fixed signal terminal or the fixed potential signal line and ensure that the fixed potential signal has less loss during transmission.

[0220] Continue to refer to Figure 2 , Figures 4 to 41 As shown, the display panel 10 further includes a first semiconductor layer 104, a first metal layer 106, a second semiconductor layer 108, a second metal layer 1010, and a third metal layer 1012. The second semiconductor layer 108 is located on the side of the first semiconductor layer 104 and the first metal layer 106 away from the substrate 100, the second metal layer 1010 is located on the side of the second semiconductor layer 108 away from the substrate 100, and the third metal layer 1012 is located on the side of the second metal layer 1010 away from the substrate 100. A second active layer 241 is located on the first semiconductor layer 108. A second gate 242 and a third gate 213 are located on the first metal layer 106. A first active layer 211 is located on the second semiconductor layer 108. A first capacitor plate 221 is located on the second metal layer 1010, and a second capacitor plate 222 is located on the third metal layer 1012.

[0221] For details, please refer to Figure 2 As shown, the pixel circuit 200 includes a first type of transistor 210 and a second type of transistor 240. Figure 2 The example given is a first type of transistor 210 including a driving transistor T3 and a second type of transistor 240 including a second light-emitting control transistor T1. The specific transistor configuration in the pixel circuit 200 can be adjusted according to actual needs.

[0222] For details, please refer to Figure 4 and Figure 29As shown, the display panel 10 may include, on one side of the substrate 100, a first semiconductor layer 104, a first metal layer 106, a second semiconductor layer 108, a second metal layer 1010, and a third metal layer 1012, etc. The number of film layers can be added or removed adaptively under different display panels 10, which will not be described in detail in the embodiments of the present invention.

[0223] For example, refer to Figures 4 to 41 As shown, please refer to the following for details. Figure 9 , Figure 21 and Figure 34 As shown, the first active layer 211 in the first type transistor 210 is located in the second semiconductor layer 108; see details below. Figure 10 , Figure 22 and Figure 35 As shown, in the first type transistor 210, the first gate 212 is located in the second metal layer 1010, and the first capacitor plate 221 is also located in the second metal layer 1010. Therefore, the first gate 212 and the first capacitor plate 221 are disposed in the same layer; see details below. Figure 8 , Figure 20 and Figure 33 As shown, in the first type transistor 210, the second gate 213 is located on the first metal layer 106, and in the second type transistor 240, the third gate 213 is also located on the first metal layer 106. Therefore, the second gate 213 and the third gate 213 are disposed on the same layer; see reference for details. Figure 11 , Figure 23 and Figure 36 As shown, the second capacitor plate 222 is located in the third metal layer 1012; see reference for details. Figure 7 , Figure 19 and Figure 32 As shown, the second active layer 241 of the second type transistor 240 is located in the first semiconductor layer 108. The first gate 212 and the first capacitor plate 221 are disposed in the same layer, and the second gate 213 and the third gate 213 are disposed in the same layer, which is beneficial to realizing the thin design of the display panel 10 and can also reduce the manufacturing cost of the display panel 10.

[0224] refer to Figure 15 , Figure 27 and Figure 41As shown, the display panel 10 also includes a light-emitting element 400, which is electrically connected to the pixel circuit 200. The light-emitting element 400 includes a first-color light-emitting element 400A, a second-color light-emitting element 400B, a third-color light-emitting element 400C, and a fourth-color light-emitting element 400D. The first-color light-emitting element 400A, the second-color light-emitting element 400B, the third-color light-emitting element 400C, and the fourth-color light-emitting element 400D are one or more of red, blue, green, and white light-emitting elements. Multiple first-color light-emitting elements 400A and second-color light-emitting elements 400B form a first virtual quadrilateral 411. The first-color light-emitting element 400A is located in the first... At the first vertex of the virtual quadrilateral 411, the center of the second color light-emitting element 400B is located at the second vertex of the first virtual quadrilateral 411. The first vertex and the second vertex alternate and are spaced apart. The third color light-emitting element 400C or the fourth color light-emitting element 400D is located inside the first virtual quadrilateral 411. Multiple third color light-emitting elements 400C and / or fourth color light-emitting elements 400D constitute the second virtual quadrilateral 421. The centers of multiple third color light-emitting elements 400C and / or fourth color light-emitting elements 400D are respectively located at the vertices of the second virtual quadrilateral 421. The first color light-emitting element 400A or the second color light-emitting element 400B is located inside the second virtual quadrilateral 421.

[0225] Among them, reference Figure 15 , Figure 27 and Figure 41 As shown, see details. Figure 15 The light-emitting element 400 includes a first color light-emitting element 400A, a second color light-emitting element 400B, a third color light-emitting element 400C, and a fourth color light-emitting element 400D. The first color light-emitting element 400A, the second color light-emitting element 400B, the third color light-emitting element 400C, and the fourth color light-emitting element 400D can be one or more of red, blue, green, and white light-emitting elements. By driving the light-emitting elements of different colors to emit light, the overall color display effect of the display panel 10 is achieved.

[0226] Specifically, multiple first-color light-emitting elements 400A and second-color light-emitting elements 400B form a first virtual quadrilateral 411. Two first-color light-emitting elements 400A are located at opposite corners of the first virtual quadrilateral 411, and two second-color light-emitting elements 400B are located at the other two opposite corners of the first virtual quadrilateral 411. Furthermore, a third-color light-emitting element 400C or a fourth-color light-emitting element 400D is placed at the center of the first virtual quadrilateral 411. Figure 15 The example is illustrated by placing the third color light-emitting element 400C at the center of the first virtual quadrilateral 411.

[0227] Furthermore, multiple third-color light-emitting elements 400C and / or fourth-color light-emitting elements 400D constitute a second virtual quadrilateral 421. Figure 15 The following example illustrates a second virtual quadrilateral 421 formed by multiple third-color light-emitting elements 400C. In the second virtual quadrilateral 421, either the first-color light-emitting element 400A or the second-color light-emitting element 400B can be located at the center.

[0228] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 45 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 45 As shown, the display device 1 includes the display panel 10 described in any of the above embodiments. Therefore, the display device 1 provided in this embodiment of the invention possesses the corresponding beneficial effects described in the above embodiments, which will not be repeated here. For example, the display device 1 can be an electronic device such as a mobile phone, computer, smart wearable device (e.g., smartwatch), and in-vehicle display device, and this embodiment of the invention does not limit it.

[0229] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: It includes a substrate and a plurality of pixel circuits located on one side of the substrate, wherein the pixel circuit includes a first type transistor and a first storage capacitor; The first type transistor comprises a first active layer and a first gate, the first active layer comprises oxide, and the first gate is located on a side of the first active layer away from the substrate; The first storage capacitor includes a first capacitor plate and a second capacitor plate which are stacked, and the first capacitor plate or the second capacitor plate is arranged in the same layer as the first gate.

2. The display panel according to claim 1, characterized in that: The first capacitor plate or the second capacitor plate reuses at least part of the first gate of the first type transistor.

3. The display panel according to claim 2, characterized in that: The second capacitor plate is located on a side of the first capacitor plate away from the substrate; At least part of the first gate of the first type transistor is reused in the first capacitor plate.

4. The display panel according to claim 2, characterized in that: The first type transistors include driver transistors; The first capacitor plate or the second capacitor plate reuses the first gate of the driving transistor.

5. The display panel according to claim 4, characterized in that: The pixel circuit further includes a second storage capacitor, wherein the second storage capacitor includes a third capacitor plate and a fourth capacitor plate; The third capacitor plate is disposed in the same layer as and connected to the first capacitor plate, and the fourth capacitor plate is disposed in the same layer as and connected to the second capacitor plate.

6. The display panel according to claim 5, characterized in that: The pixel circuit further includes an initialization transistor and a first light emission control transistor; The display panel further includes a first connection portion connecting a first end of the initialization transistor, a first end of the first light emission control transistor, and the fourth capacitor plate.

7. The display panel according to claim 5, characterized in that: The first capacitor plate and the third capacitor plate are connected to a capacitor plate connecting portion; The first type transistor also includes a threshold compensation transistor; The display panel further includes a second connection portion connecting the capacitor plate connection portion and a first end of the threshold compensation transistor.

8. The display panel according to claim 5, characterized in that: The display panel further includes a light emitting element, wherein the light emitting element includes a first electrode; The display panel further includes a third connecting portion, and the third connecting portion connects the second capacitor plate and the first electrode.

9. The display panel according to claim 5, characterized in that: The pixel circuit further includes an initialization transistor and a first light emission control transistor; The first type transistor also includes a threshold compensation transistor; The display panel further includes a light emitting element, wherein the light emitting element includes a first electrode; The display panel further includes a first connection portion, a second connection portion and a third connection portion; The first connecting portion connects the first end of the initialization transistor, the first end of the first light emission control transistor and the fourth capacitor plate; The first capacitor plate and the third capacitor plate are connected to a capacitor plate connecting portion, and the second connecting portion connects the capacitor plate connecting portion and a first end of the threshold compensation transistor; The third connecting portion connects the second capacitor plate and the first electrode; The first connection part, the second connection part and the third connection part are arranged in the same layer.

10. The display panel according to claim 9, characterized in that: The display panel further includes a signal line, wherein the signal line includes a first scanning signal line, and the first scanning signal line is electrically connected to the control end of the threshold supplement transistor; The first connection portion and the second connection portion are arranged along a first direction, and the second connection portion and the third connection portion are arranged along a second direction; the first direction and the second direction intersect and are both parallel to the plane where the substrate is located; Along the thickness direction of the display panel, the first connection portion and the second connection portion both overlap with the first scanning signal line, and the second capacitor plate covers the third connection portion.

11. The display panel according to claim 5, characterized in that: An overlapping area between the first capacitor plate and the second capacitor plate is greater than an overlapping area between the third capacitor plate and the fourth capacitor plate.

12. The display panel according to claim 5, characterized in that: The projection of the overlapping area of ​​the first capacitor plate and the second capacitor plate on the plane where the substrate is located is a first overlapping projection, and the projection of the overlapping area of ​​the third capacitor plate and the fourth capacitor plate on the plane where the substrate is located is a second overlapping projection; The first type transistor further includes a threshold compensation transistor; the pixel circuit further includes a first light emission control transistor; the display panel further includes a signal line, the signal line includes a first scan signal line and a first light emission control signal line, the first scan signal line is electrically connected to the control end of the threshold compensation transistor, and the first light emission control signal line is electrically connected to the control end of the first light emission control transistor; the projection of the first scan signal line on the plane where the substrate is located is a first scan line projection, and the projection of the first light emission control signal line on the plane where the substrate is located is a second scan line projection; The first overlapping projection includes a first boundary close to the first scan line projection and a second boundary close to the second scan line projection, and the second overlapping projection includes a third boundary close to the first scan line projection and a fourth boundary close to the second scan line projection; The first boundary is located at a side of the third boundary away from the projection of the first scan line, and the second boundary is located at a side of the fourth boundary close to the projection of the second scan line.

13. The display panel according to claim 1, characterized in that: The first type transistor further includes a second gate, and the second gate is located on a side of the first active layer close to the substrate; The first type transistors include driver transistors; The pixel circuit also includes a data writing transistor; The display panel further includes a fourth connection portion connecting the first end of the data writing transistor, the second end of the driving transistor, and the second gate of the driving transistor.

14. The display panel according to claim 13, characterized in that: The pixel circuit further includes a second type transistor, the second type transistor includes a second active layer and a third gate, the second active layer includes silicon, the third gate is located on a side of the second active layer away from the substrate, or the third gate is located on a side of the second active layer close to the substrate; The second gate and the third gate are arranged in the same layer.

15. The display panel according to claim 1, characterized in that: The pixel circuit also includes a driving transistor and a second light emitting control transistor; The display panel further comprises a signal line, wherein the signal line comprises a positive power signal line; The second light emission control transistor is electrically connected between the positive power signal line and the driving transistor; The positive power signal line includes a first positive power signal line, the first positive power signal line extends along a first direction, a plurality of the first positive power signal lines are arranged along a second direction, and the first direction and the second direction intersect; The first positive power signal line is arranged in the same layer as the first capacitor plate or the second capacitor plate.

16. The display panel according to claim 15, characterized in that: The positive power signal line further includes a second positive power signal line, the second positive power signal line extends along the second direction, and a plurality of the second positive power signal lines are arranged along the first direction; The second positive power signal line and the first positive power signal line are arranged in different layers and are electrically connected.

17. The display panel according to claim 1, characterized in that: The pixel circuit further includes an initialization transistor; The display panel further includes a signal line, wherein the signal line includes an initialization signal line; The initialization transistor is electrically connected between the initialization signal line and the first storage capacitor; The initialization signal line includes a first initialization signal line, the first initialization signal line extends along a first direction, a plurality of the first initialization signal lines are arranged along a second direction, and the first direction and the second direction intersect; The first initialization signal line is disposed in the same layer as the first capacitor plate or the second capacitor plate.

18. The display panel according to claim 1, characterized in that: The display panel further includes a light emitting element, wherein the light emitting element includes a second electrode; The display panel further comprises a signal line, wherein the signal line comprises a negative power signal line; The second electrode is electrically connected to the negative power signal line; The negative power signal line includes a first negative power signal line, the first negative power signal line extends along a first direction, a plurality of the first negative power signal lines are arranged along a second direction, and the first direction and the second direction intersect; The first negative power signal line is arranged in the same layer as the first capacitor plate or the second capacitor plate.

19. The display panel according to claim 1, characterized in that: The pixel circuit further includes an initialization transistor; The display panel further comprises a signal line and a light emitting element, wherein the signal line comprises an initialization signal line and a negative power signal line, and the light emitting element comprises a second electrode; The initialization transistor is electrically connected between the initialization signal line and the first storage capacitor; the second electrode is electrically connected to the negative power signal line; The initialization signal line includes a first initialization signal line, the first initialization signal line extends along a first direction, and a plurality of the first initialization signal lines are arranged along a second direction; the negative power signal line includes a first negative power signal line, the first negative power signal line extends along the first direction, and a plurality of the first negative power signal lines are arranged along the second direction; the first direction and the second direction intersect; The first initialization signal line and the first negative power signal line are arranged in the same layer, and along the second direction, the first initialization signal line and the first negative power signal line are arranged alternately.

20. The display panel according to claim 19, characterized in that: The initialization signal line further includes a second initialization signal line, the second initialization signal line extends along the second direction, and a plurality of the second initialization signal lines are arranged along the first direction; the second initialization signal line is arranged in a different layer from the first initialization signal line and is electrically connected; The negative power signal line further includes a second negative power signal line, the second negative power signal line extends along the second direction, and a plurality of the first negative power signal lines are arranged along the first direction; the second negative power signal line and the first negative power signal line are arranged in different layers and are electrically connected; The second initialization signal line and the second negative power signal line are arranged in the same layer, and along the first direction, the second initialization signal line and the second negative power signal line are arranged alternately.

21. The display panel according to claim 1, characterized in that: The display panel also includes a plurality of signal lines; The signal lines include data signal lines, a plurality of the data signal lines are arranged along a first direction and extend along a second direction, and the first direction and the second direction intersect; The display panel further comprises a display area and a non-display area at least partially surrounding the display area, the display area comprises a first display area and a second display area, the second display area is located at least on one side of the first display area along the first direction; the first display area and the second display area both comprise a plurality of the data signal lines; the non-display area comprises a fan-out area located on one side of the display area along the second direction, the fan-out area comprises a plurality of fan-out wirings; The signal lines further include a plurality of data auxiliary lines, and the data signal lines located in the second display area are electrically connected to the fan-out wiring through the data auxiliary lines.

22. The display panel according to claim 21, characterized in that: The data auxiliary line includes a first auxiliary line segment and a second auxiliary line segment, the first auxiliary line segment extends along the first direction, and the second auxiliary line segment extends along the second direction; The first auxiliary line segment is electrically connected to the second auxiliary line segment and the data signal line located in the second display area, and the second auxiliary line segment is electrically connected to the fan-out wiring.

23. The display panel according to claim 22, characterized in that: The display panel further includes a virtual auxiliary line, and the virtual auxiliary line includes a first virtual auxiliary line segment and / or a second virtual auxiliary line segment; The first virtual auxiliary line segment extends along the first direction, is disposed in the same layer as the first auxiliary line segment, and has a first gap between the first virtual auxiliary line segment and the first auxiliary line segment. The second virtual auxiliary line segment extends along the second direction, is disposed in the same layer as the second auxiliary line segment, and has a second gap therebetween; The display panel further includes a light emitting element, wherein the light emitting element includes a first electrode; Along a thickness direction of the display panel, the first gap and / or the second gap overlaps with the first electrode.

24. The display panel according to claim 22, characterized in that: The display panel further includes a virtual auxiliary line, wherein the virtual auxiliary line includes a first virtual auxiliary line segment; The first virtual auxiliary line segment extends along the first direction, is disposed in the same layer as the first auxiliary line segment, and has a first gap between the first virtual auxiliary line segment and the first auxiliary line segment. The pixel circuit also includes a driving transistor and a second light emitting control transistor; The display panel further comprises a signal line, wherein the signal line comprises a positive power signal line; The second light emission control transistor is electrically connected between the positive power signal line and the driving transistor; The positive power signal line includes a second positive power signal line, the second positive power signal line extends along a second direction, a plurality of the second positive power signal lines are arranged along a first direction, and the first direction and the second direction intersect; Along a thickness direction of the display panel, the first gap overlaps with the second positive power signal line.

25. The display panel according to claim 23, characterized in that: The first virtual auxiliary line segment and / or the second virtual auxiliary line segment are electrically connected to a fixed potential signal line.

26. The display panel according to claim 22, characterized in that: The pixel circuit further includes a driving transistor, a second light emission control transistor and a data writing transistor; The signal line includes a positive power signal line and a second scanning signal line; The second light emitting control transistor is electrically connected between the positive power supply signal line and the driving transistor; the control end of the data writing transistor is electrically connected to the second scanning signal line; The positive power signal line includes a first positive power signal line, the first positive power signal line extends along a first direction, a plurality of the first positive power signal lines are arranged along a second direction, and the first direction and the second direction intersect; The orthographic projection of the first positive power signal line on the plane where the substrate is located is located between the orthographic projection of the first auxiliary line segment on the plane where the substrate is located and the orthographic projection of the second scanning signal line on the plane where the substrate is located.

27. The display panel according to claim 22, characterized in that: The pixel circuit further includes an initialization transistor and a second light emission control transistor; The display panel further includes signal lines, wherein the signal lines include an initialization signal line and a second light emission control signal line; The initialization transistor is electrically connected between the initialization signal line and the first storage capacitor, and the control end of the second light emission control transistor is electrically connected to the second light emission control signal line; The initialization signal line includes a first initialization signal line, the first initialization signal line extends along a first direction, a plurality of the first initialization signal lines are arranged along a second direction, and the first direction and the second direction intersect; The orthographic projection of the first initialization signal line on the plane where the substrate is located is located between the orthographic projection of the first auxiliary line segment on the plane where the substrate is located and the orthographic projection of the second light-emitting control signal line on the plane where the substrate is located.

28. The display panel according to claim 22, characterized in that: The pixel circuit further includes a second light emitting control transistor; The display panel further comprises a signal line and a light emitting element; the signal line comprises a second light emitting control signal line and a negative power supply signal line; the light emitting element comprises a second electrode; The control end of the second light emitting control transistor is electrically connected to the second light emitting control signal line, and the second electrode is electrically connected to the negative power supply signal line; The negative power signal line includes a first negative power signal line, the first negative power signal line extends along a first direction, a plurality of the first negative power signal lines are arranged along a second direction, and the first direction and the second direction intersect; The orthographic projection of the first negative power signal line on the plane where the substrate is located is located between the orthographic projection of the first auxiliary line segment on the plane where the substrate is located and the orthographic projection of the second light-emitting control signal line on the plane where the substrate is located.

29. The display panel according to claim 22, characterized in that: The pixel circuit also includes a data writing transistor; The display panel further comprises a signal line and a light emitting element; the signal line comprises a second scanning signal line and a negative power signal line; the light emitting element comprises a second electrode; The control end of the data writing transistor is electrically connected to the second scanning signal line, and the second electrode is electrically connected to the negative power signal line; The negative power signal line includes a first negative power signal line, the first negative power signal line extends along a first direction, a plurality of the first negative power signal lines are arranged along a second direction, and the first direction and the second direction intersect; The orthographic projection of the first negative power signal line on the plane where the substrate is located is located between the orthographic projection of the first auxiliary line segment on the plane where the substrate is located and the orthographic projection of the second scanning signal line on the plane where the substrate is located.

30. The display panel according to claim 1, characterized in that: The pixel circuit further includes a second type transistor, the second type transistor includes a second active layer, the second active layer includes silicon; The display panel further includes a zero metal layer, and the zero metal layer is located on a side of the pixel circuit close to the substrate; The zeroth metal layer includes a plurality of light shielding sections, and along a thickness direction of the display panel, the light shielding sections at least partially overlap with the channel regions of the second type transistors.

31. The display panel according to claim 30, characterized in that: The zeroth metal layer is electrically connected to the fixed potential signal line.

32. The display panel according to claim 13, characterized in that: The display panel further comprises a first semiconductor layer, a first metal layer, a second semiconductor layer, a second metal layer and a third metal layer, wherein the second semiconductor layer is located on a side of the first semiconductor layer and the first metal layer away from the substrate, the second metal layer is located on a side of the second semiconductor layer away from the substrate, and the third metal layer is located on a side of the second metal layer away from the substrate; The second active layer is located in the first semiconductor layer; the second gate and the third gate are located in the first metal layer; The first active layer is located on the second semiconductor layer; The first capacitor plate is located in the second metal layer, and the second capacitor plate is located in the third metal layer.

33. The display panel according to claim 1, characterized in that: The display panel further comprises a light emitting element, wherein the light emitting element is electrically connected to the pixel circuit; The light-emitting elements include a first color light-emitting element, a second color light-emitting element, a third color light-emitting element and a fourth color light-emitting element, wherein the first color light-emitting element, the second color light-emitting element, the third color light-emitting element and the fourth color light-emitting element are one or more of a red light-emitting element, a blue light-emitting element, a green light-emitting element and a white light-emitting element; A plurality of the first color light emitting elements and the second color light emitting elements form a first virtual quadrilateral, the first color light emitting elements are located at first vertices of the first virtual quadrilateral, the centers of the second color light emitting elements are located at second vertices of the first virtual quadrilateral, the first vertices and the second vertices are alternately and spaced apart, and the third color light emitting element or the fourth color light emitting element is located inside the first virtual quadrilateral; The plurality of third color light emitting elements and / or the fourth color light emitting elements constitute a second virtual quadrilateral, the centers of the plurality of third color light emitting elements and / or the fourth color light emitting elements are respectively located at the vertices of the second virtual quadrilateral, and the first color light emitting element or the second color light emitting element is located inside the second virtual quadrilateral.

34. A display device, characterized in that: A display panel comprising any one of claims 1-33.

Images