A method and system for compensation of wafer backgrinding

Abstract

The present application relates to the technical field of semiconductor, in particular to a kind of wafer back grinding compensation method and system, it includes: first wafer layer is stacked on the layer to be stacked to form first stacked layer;Monitoring at least one first bending value and at least one second bending value of first stacked layer respectively in first target area and second target area;Using first discriminant model, grinding compensation index is calculated according to first bending value and second bending value;L1 is grinding compensation index, a is first weight, b is second weight, X1 is first bending degree, Y1 is second bending degree;First bending degree is the eigenvalue of at least one first bending value, and second bending degree is the eigenvalue of at least one second bending value;When grinding compensation index is greater than the set first compensation threshold, then reduce the grinding thickness of next wafer layer.The compensation method provided by the present application can be combined with actual situation to start the adjustment of wafer back grinding thickness rolling, to control edge curl problem.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically to a compensation method and system for crystal back polishing. Background Technology

[0002] Integrated circuits in semiconductor devices are typically fabricated on a single wafer, which is then diced into individual small dies. Driven by the need for mass production and cost reduction, wafer sizes have evolved from early four-inch and six-inch wafers to eight-inch, twelve-inch, and even sixteen-inch wafers. Furthermore, after the integrated circuits are completed, back-side grinding is often required before dicing into dies, reducing die thickness to meet the specifications of high-density or thin-film packaging. Wafer yield is crucial to the performance of semiconductor devices. However, wafers are prone to edge bending during the manufacturing and stacking process, leading to an increase in wafer defects.

[0003] See patent application CN108110043A for a method to optimize wafer curvature. This method discloses a method for optimizing wafer curvature, comprising: providing a wafer with a faceted SiN formed on its front side and a backed SiN formed on its back side, wherein the faceted and backed SiNs are formed in the same furnace tube process; treating the front side of the wafer to form an acid-resistant protective layer; and, under the protection of the protective layer, using acid to remove at least a portion of the backed SiN. This method aims to improve the quality of subsequent bonding and other process steps by adjusting the wafer curvature.

[0004] However, the applicant noted that although the traditional solution has optimized the wafer processing technology, with the continuous development of semiconductor technology, especially when the number of wafer layers of semiconductor devices reaches a certain number and the circuit structure on the wafer becomes more and more complex, it is still very easy to cause bending at the edge, which in turn causes defects.

[0005] Therefore, a method to reduce bending defects during the stacking process is currently being pursued. Summary of the Invention

[0006] The purpose of this invention is to provide a compensation method and system for crystal back grinding, which partially solves or alleviates the above-mentioned deficiencies in the prior art and can control the degree of bending deformation during the stacking process through gradient grinding thickness adjustment.

[0007] To solve the aforementioned technical problems, the present invention specifically adopts the following technical solution:

[0008] A first aspect of the present invention is to provide a compensation method for crystal back polishing, comprising:

[0009] S101, at least one first wafer layer is stacked on the layer to be stacked to form a first stacked layer; wherein, the wafer layer includes: multiple rows of dies spaced apart;

[0010] S102, monitor at least one first bending value and at least one second bending value of the first stacked layer in a first target area and a second target area respectively; wherein, the first target area is located in the peripheral area of ​​the wafer layer, the second target area is located in the central area of ​​the wafer layer, and an intermediate area is spaced between the first target area and the second target area, and multiple rows of dies are arranged around the intermediate area;

[0011] S103, a first discrimination model is used to calculate a grinding compensation index based on the first bending value and the second bending value; wherein, the first discrimination model includes:

[0012] L1 = aX1 + bY1; where L1 is the grinding compensation index, a is the first weight, b is the second weight, X1 is the first degree of curvature, and Y1 is the second degree of curvature; wherein the first degree of curvature is a characteristic value of the at least one first curvature value, and the second degree of curvature is a characteristic value of the at least one second curvature value, and the characteristic value includes one or more of the following types: mean, median, mode, or maximum value.

[0013] S104, when the polishing compensation index is greater than the set first compensation threshold, the polishing thickness of the next wafer layer is reduced.

[0014] In some embodiments, the steps further include:

[0015] S105, at least one second wafer layer is stacked on the first stacked layer to obtain the second stacked layer;

[0016] S106, monitor at least one third bending value and / or at least one fourth bending value of the second stacked layer in the first target area and / or the second target area respectively;

[0017] S107, a second discriminant model is used to calculate the bending trend based on at least one set of bending values; wherein, the second discriminant model includes:

[0018] L2 = α(X2 - X1) / t + β(Y2 - Y1) / t; where L2 is the bending tendency, α is the third weight, β is the fourth weight, X1 and X2 are the first bending degrees of the first wafer layer and the second wafer layer, respectively, and Y... 1、 Y2 represents the second degree of bending of the first wafer layer and the second wafer layer, respectively; t is the interval between the two monitoring sessions.

[0019] S108, when the bending tendency is greater than the set bending threshold, the grinding thickness of the next wafer layer is reduced.

[0020] In some embodiments, the steps further include:

[0021] S109, obtain an exceedance indicator that the bending trend exceeds the bending threshold within a first time period. The exceedance indicator can be the frequency of exceedance or the duration of exceedance.

[0022] S110, when the exceeded indicator is greater than a preset first exceeded threshold, the first discrimination model is corrected.

[0023] In some embodiments, the step of modifying the first discrimination model includes:

[0024] Increase the value of the first weight, and / or decrease the value of the second weight.

[0025] In some embodiments, the polishing thickness of the second wafer layer is less than or equal to the polishing thickness of the first wafer layer.

[0026] In some embodiments, the calculation model for the polishing thickness of the current wafer layer includes:

[0027] Th n =Th n-1 +λ; where Th n Th represents the polishing thickness of the current wafer layer. n-1 λ represents the grinding thickness of the wafer layer described above, and λ is a preset compensation thickness.

[0028] In some embodiments, after the step of reducing the polishing thickness of the next wafer layer, the method further includes:

[0029] S111, the second discrimination model is used to calculate the first bending trend in the first time period and the second bending trend in the second time period respectively;

[0030] S112, determine whether the difference between the second bending trend and the first bending trend belongs to the set threshold range; if not, issue a corresponding prompt signal.

[0031] The present invention also provides a compensation system for crystal back polishing, comprising:

[0032] A first stacking module is used to stack at least one first wafer layer on a layer to be stacked to form a first stacking layer; wherein, the wafer layer includes: multiple rows of dies spaced apart;

[0033] A first monitoring module is used to monitor at least one first bending value and at least one second bending value of the first stacked layer in a first target area and a second target area, respectively; wherein the first target area is located in the peripheral area of ​​the wafer layer, the second target area is located in the central area of ​​the wafer layer, and an intermediate area is spaced between the first target area and the second target area, wherein multiple rows of dies are arranged around the intermediate area;

[0034] A first discrimination module is used to calculate a grinding compensation index based on the first bending value and the second bending value using a first discrimination model; wherein, the first discrimination model includes:

[0035] L1 = aX1 + bY1; where L1 is the grinding compensation index, a is the first weight, b is the second weight, X1 is the first degree of curvature, and Y1 is the second degree of curvature; wherein the first degree of curvature is a characteristic value of the at least one first curvature value, and the second degree of curvature is a characteristic value of the at least one second curvature value, and the characteristic value includes one or more of the following types: mean, median, mode, or maximum value.

[0036] The compensation module is used to reduce the polishing thickness of the next wafer layer when the polishing compensation index is greater than a set first compensation threshold.

[0037] In some embodiments, including:

[0038] The second stacking module is used to stack at least one second wafer layer on the first stacking layer to obtain the second stacking layer;

[0039] The second monitoring module is used to monitor at least one third bending value and / or at least one fourth bending value of the second stacked layer in the first target area and / or the second target area, respectively.

[0040] The second discrimination module is used to calculate the bending trend based on at least one set of bending values ​​using a second discrimination model; wherein the second discrimination model includes:

[0041] L2 = α(X2 - X1) / t + β(Y2 - Y1) / t; where L2 represents the bending tendency, α is the third weight, β is the fourth weight, X1 and X2 are the first bending degrees of the first wafer layer and the second wafer layer, respectively, and Y... 1、 Y2 represents the second degree of bending of the first wafer layer and the second wafer layer, respectively; t is the interval between the two monitoring sessions.

[0042] The bending trend determination module is used to reduce the grinding thickness of the next wafer layer when the bending trend is greater than a set bending threshold.

[0043] In some embodiments, it also includes:

[0044] The exceeding indicator determination module is used to obtain the exceeding indicator when the bending trend exceeds the bending threshold within a first time period. The exceeding indicator can be the frequency of exceeding or the duration of exceeding.

[0045] The model correction module is used to correct the first discrimination model when the exceeded indicator is greater than a preset first exceeded threshold.

[0046] Beneficial technical effects:

[0047] To address the edge curling problem that may occur during the stacking process, this invention provides a scheme for adjusting the grain grinding thickness based on partition detection and a rolling adjustment of the bending degree (i.e., a gradient adjustment scheme based on partition detection). Specifically, this invention comprehensively analyzes the bending values ​​(i.e., the degree of deformation) of the edge region with high stress and the central region affected by edge stress and wafer layer size. This allows for a comprehensive assessment of the bending deformation degree through distributed point measurements, enabling timely determination of whether to initiate correction of the grain grinding thickness.

[0048] Furthermore, to avoid excessive lag in the gradient adjustment scheme, a collaborative evaluation will be conducted based on the bending deformation trend. This will allow for early correction of the grinding thickness during the initial stage of rapid bending deformation expansion. Moreover, this evaluation of the bending deformation trend also facilitates the assessment of the timeliness of the first discriminant model. For example, if an excessively large bending deformation trend is detected, the first discriminant model can be adjusted in reverse.

[0049] Furthermore, after correcting the grinding thickness based on the evaluation results of the first or second discrimination model, it is also possible to detect the change in bending trend after correction, so as to determine whether the correction result is reliable by the change in bending trend.

[0050] Furthermore, for this gradient adjustment scheme based on partition detection, the present invention also provides a crystal back compensation model. This crystal back compensation model combines key factors such as the thickness of the stacked layer, the grinding thickness of the previous layer of grain and the curvature (i.e., the current overall thickness of the semiconductor, the grinding thickness of the previous gradient interval and the degree of deformation, etc.), as well as the type of semiconductor device (such as grain size and stacked layer size) to comprehensively analyze the corrected grinding thickness in order to predict the grinding thickness of the next gradient.

[0051] In other words, this invention coordinates the processing of semiconductor bending based on the stacking type and current stacking state of the semiconductor devices to achieve precise gradient adjustment of the grinding thickness for specific semiconductor types. This gradient-based, limited grinding thickness adjustment improves the overall yield of the semiconductor devices. Furthermore, this limited grinding thickness adjustment reduces the difficulty of the grinding process (ensuring the grinding process is as uniform as possible) while preventing the overall grinding thickness from being too small, thus avoiding an increase in defects in individual grains due to variations in the grinding process.

[0052] Preferably, in this invention, the crystal back compensation model is activated to correct the grinding thickness only when gradient adjustment is detected as necessary. This staged correction also reduces the frequency of grinding correction, thereby simplifying the correction process. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale. Obviously, the drawings described below are some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0054] Figure 1 This is a schematic diagram of the wafer layer structure in an exemplary embodiment of the present invention;

[0055] Figure 2 This is a structural disassembly diagram of the packaging system in an exemplary embodiment of the present invention;

[0056] Figure 3 This is a top view of the packaging system in an exemplary embodiment of the present invention;

[0057] Figure 4 This is a schematic diagram of the bending data of the encapsulation system in an exemplary embodiment;

[0058] Figure 5 This is a schematic diagram of the method flow in an exemplary embodiment of the present invention;

[0059] Figure 6 This is a schematic diagram of the method flow in another exemplary embodiment of the present invention.

[0060] Reference numerals: First target area 10, middle area 20, second target area 30, grain 40; first measurement point 11, second measurement point 31; mother sheet 01, first stacked portion 02, first edge grain 021, first center grain 023, first spacer grain 022; second stacked portion 03, second edge grain 031, second center grain 033, second spacer grain 032, center point O. Detailed Implementation

[0061] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0062] In this document, suffixes such as "module," "part," or "unit" used to denote elements are used only for the purpose of illustrative purposes and have no specific meaning in themselves. Therefore, "module," "part," or "unit" may be used interchangeably.

[0063] In this document, the terms "upper," "lower," "inner," "outer," "front," "rear," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the present invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0064] In this document, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0065] In this document, "and / or" includes any and all combinations of one or more of the listed related items.

[0066] In this article, "multiple" means two or more, that is, it includes two, three, four, five, etc.

[0067] As used in this specification, the term "about" typically means + / -5% of the value, more typically + / -4% of the value, more typically + / -3% of the value, more typically + / -2% of the value, even more typically + / -1% of the value, and even more typically + / -0.5% of the value.

[0068] In this specification, certain embodiments may be disclosed in a range-bound format. It should be understood that this "range-bound" description is merely for convenience and brevity and should not be construed as a rigid limitation on the disclosed range. Therefore, the description of a range should be considered as having specifically disclosed all possible subranges and the individual numerical values ​​within those ranges. For example, a description of the range 1-6 should be considered as having specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and the individual numbers within those ranges, such as 1, 2, 3, 4, 5, and 6. This rule applies regardless of the breadth of the range.

[0069] In this article, a wafer refers to a silicon wafer used to fabricate silicon semiconductor circuits. A "die" can be a small piece cut from a wafer and is also called a "die". A "die" on which circuit structures are fabricated can also be called a "chip".

[0070] Typically, multiple dies need to be stacked to package a complete semiconductor device. This can be done on a master wafer (e.g., a substrate, or SUB) or on a substrate with multiple stacked wafer layers, where each wafer layer comprises multiple dies. As the number of stacked layers increases, the package structure may curl due to accumulated tension, leading to defects and reduced yield. Figure 4 As shown. Curve S2 and curve S3 respectively illustrate the bending values ​​of different layers in an exemplary semiconductor device.

[0071] To address this, it may be necessary to reduce the thickness of the back side of the grain (i.e., perform a back grinding operation). For example, the thickness of the grain after manufacturing is approximately 700-800 μm, and it may be necessary to perform back grinding during the stacking process to reduce its thickness to approximately 70-80 μm.

[0072] Currently, a standardized back-grinding process is commonly used, which involves uniformly processing multi-layered dies with a standardized grinding thickness. However, the applicant notes that when the number of layers in a semiconductor device is too large and the area of ​​the wafer layer is too large, this standardized process still has significant problems in terms of overall reliability and yield.

[0073] In contrast to the traditional standardized process, this application proposes a rolling differential grinding compensation scheme for multilayer packaging structures. This rolling grinding compensation scheme can compensate for the grinding thickness of the grains in different layer regions, and this differential compensation process can prevent the grinding thickness from becoming too small, which would increase the difficulty of the grinding process (it should be noted that the smaller the grain thickness, the more defects are likely to be generated during the preparation process, and the higher the technical requirements for the grinding process).

[0074] In this document, different terms are used to describe the curling of stacked structures, such as "bending degree" and "degree of bending." This is mainly to facilitate the differentiation of different compensation systems in different embodiments. In the embodiments of the present invention, the degree of bending or bending is mainly a characterization index used to describe the degree of curling deformation of the stacked structure. For example, it can be the degree of upward or downward deformation at different diameter positions, or it can be the bending angle at different positions. As long as it can characterize the degree of bending deformation, it can be applied to the present invention and should be within the protection scope of the present invention.

[0075] Example 1

[0076] See Figure 5 As shown, the present invention provides a compensation method for crystal back grinding, comprising:

[0077] S101, at least one first wafer layer is stacked on the layer to be stacked to form a first stacked layer; wherein, the wafer layer includes: multiple rows of dies spaced apart;

[0078] In some embodiments, the layers to be stacked include: a mother wafer, and a plurality of wafer layers disposed on the mother wafer.

[0079] In particular, in some embodiments, at the initial moment of stacking, the layer to be stacked refers to the master wafer.

[0080] In some embodiments, the wafer layer includes at least one layer of dies. In particular, the wafer layer includes one layer of dies, wherein data such as the current bending value can be acquired each time a new layer of dies is stacked.

[0081] S102, monitor at least one first bending value and at least one second bending value of the first stacked layer in a first target area and a second target area respectively; wherein, the first target area is located in the peripheral area of ​​the wafer layer, the second target area is located in the central area of ​​the wafer layer, and an intermediate area is spaced between the first target area and the second target area, and multiple rows of dies are arranged around the intermediate area;

[0082] See Figure 3Multiple grains are stacked sequentially on the mother wafer 01, and a first target region 10, an intermediate region 20 and a second target region 30 are arranged sequentially along the direction from the edge of the mother wafer to the center point O. Each region has multiple rows of grains 40.

[0083] In some embodiments, a row of grains refers to a ring of grains arranged around the center point O. Alternatively, in some embodiments, a row of grains refers to a row of grains arranged along the radial direction of the mother wafer, or along a direction parallel to the radial direction.

[0084] Preferably, the measurement scheme for the bending value is as follows: Figure 1 As shown, multiple first measurement points 11 are selected on the first target area 10, and multiple second measurement points 31 are selected on the second target area 30. The curvature value of each measurement point is the distance between that point and the reference line S, such as a first curvature value Z2 and a second curvature value Z1. The reference line S can be a straight line corresponding to the ideal position of multiple measurement points under the ideal state where the grains do not curl during the stacking process, or the reference line can be set by the user, which can be used to standardize the relative curvature of measurement points at different positions.

[0085] For example, the degree of curvature can be the difference between the ordinate of the measurement point and the standard line, with any straight line (or a line parallel to or approximately to it) in the plane where the master piece is located at the initial moment as the abscissa and any straight line in the direction perpendicular to it as the ordinate.

[0086] S103, a first discrimination model is used to calculate a grinding compensation index based on the first bending value and the second bending value; wherein, the first discrimination model includes:

[0087] L1 = aX1 + bY1; where L1 is the grinding compensation index, a is the first weight, b is the second weight, X1 is the first degree of curvature, and Y1 is the second degree of curvature; wherein the first degree of curvature is a characteristic value of the at least one first curvature value, and the second degree of curvature is a characteristic value of the at least one second curvature value, and the characteristic value includes one or more of the following types: mean, median, mode, or maximum value.

[0088] Preferably, the average value of multiple bending values ​​corresponding to multiple first measurement points 11 can be calculated. Preferably, the bending value can be an absolute value.

[0089] In particular, when there is only one bending value, the degree of bending can be directly characterized by the bending value.

[0090] S104, when the polishing compensation index is greater than the set first compensation threshold, the polishing thickness of the next wafer layer is reduced.

[0091] In other words, in this embodiment, when the polishing compensation index measured by the first target area and the second target area is large, it is preferable to reduce the polishing thickness of the next wafer layer in order to control the overall degree of bending deformation.

[0092] In some embodiments, the steps further include:

[0093] S105, at least one second wafer layer is stacked on the first stacked layer to obtain a second stacked layer; similarly, the second wafer layer includes a plurality of dies;

[0094] S106, monitor at least one third bending value and / or at least one fourth bending value of the second stacked layer in the first target area and / or the second target area respectively;

[0095] S107, a second discriminant model is used to calculate the bending trend based on at least one set of bending values; wherein, the second discriminant model includes:

[0096] L2 = α(X2 - X1) / t + β(Y2 - Y1) / t; where L2 represents the bending tendency, α is the third weight, β is the fourth weight, X1 and X2 are the first bending degrees of the first wafer layer and the second wafer layer, respectively, and Y... 1、 Y2 represents the second degree of bending of the first wafer layer and the second wafer layer, respectively; t is the interval between the two monitoring sessions.

[0097] S108, when the bending tendency is greater than the set bending threshold, the grinding thickness of the next wafer layer is reduced.

[0098] Preferably, in some embodiments, the bending values ​​of the first target area and the second target area at multiple times are used simultaneously to calculate their changing trend over a period of time.

[0099] For example, in some embodiments, the degree of curvature is taken as a positive value for easy comparison. When the wafer layer includes a single die, a first degree of curvature X1 and a first degree of curvature X2 of the second wafer layer are calculated, and a second degree of curvature Y of the first wafer layer and the second wafer layer are calculated accordingly. 1、 Y2. The third and fourth weights can be set by the user, and t is the difference between the measurement times of the first and second wafer layers. In this embodiment, when the bending difference between the two measurements is large, a new compensation correction will be performed on the next wafer layer, i.e., the grinding thickness of the next wafer layer will be further reduced.

[0100] In other words, in this embodiment, the second discrimination model can actually be used to calculate the first degree of bending of the first wafer layer at the first time and the first degree of bending of the second wafer layer at the second time, so as to compare the changes in the degree of bending.

[0101] In some embodiments, at least one set of bending values ​​includes: a first degree of bending of the first wafer layer and the second wafer layer; and / or, a second degree of bending of the first wafer layer and the second wafer layer.

[0102] For example, in some embodiments, the degree of bending is also taken as a positive number. When the wafer layer includes multiple grains, the bending value of the multiple grains will be obtained when measuring the first wafer layer, and the degree of bending can be a characteristic value of the degree of bending at multiple times.

[0103] Preferably, the characteristic value of the degree of bending can be the average, median, mean, or maximum of multiple bending values; alternatively, the characteristic value of the degree of bending can also be the difference between the initial measurement time and the final measurement time in a measurement process. That is, the degree of bending further incorporates a time factor, which can describe the bending trend of the wafer layer over a period of time. Correspondingly, when the difference in the bending trends of the first and second wafer layers is small, the corrected polishing thickness is considered more reliable; conversely, when the difference is large, a new compensation correction will be performed on the next wafer layer, i.e., the polishing thickness of the next wafer layer will continue to decrease.

[0104] For example, in some embodiments, the first wafer layer and the second wafer layer can be two adjacent wafer layers. Alternatively, at least one third wafer layer can be disposed between them at intervals.

[0105] For example, in some embodiments, a first discriminant model or a second discriminant model may be used to independently determine whether to initiate the step of correcting the grinding thickness.

[0106] In some embodiments, the steps further include:

[0107] S109, obtain an exceedance indicator that the bending trend exceeds the bending threshold within a first time period. The exceedance indicator can be the frequency of exceedance or the duration of exceedance. For example, a corresponding exceedance signal can be issued to prompt the user to pay attention to whether the current compensation process is reliable.

[0108] S110, when the exceeded indicator is greater than a preset first exceeded threshold, the first discrimination model is corrected.

[0109] In some embodiments, the step of modifying the first discrimination model includes:

[0110] Increase the value of the first weight, and / or decrease the value of the second weight.

[0111] Preferably, the first weight and the second weight can have an initial value set by the user or by default, and can be adjusted in response to the correction effect as the stacking process gradually changes.

[0112] Preferably, when an excess signal indicating a bending trend exceeding the bending threshold is frequently detected over a relatively long period of time, such as when the number of excess signals exceeds a set number or the duration of the excess signal exceeds a set duration, the weight relationship of the first discrimination model will be adjusted.

[0113] In this embodiment, by evaluating the bending trend, the applicability of the first discriminant model can be adjusted before compensation correction. For example, if the bending degree increases rapidly and the first discriminant model has not yet responded, its weight settings will be adjusted to increase the sensitivity of the first discriminant model. Thus, by adjusting the sensitivity in the early stage, excessive delays in compensation adjustment can be avoided.

[0114] In some embodiments, the polishing thickness of the second wafer layer is less than or equal to the polishing thickness of the first wafer layer.

[0115] In some embodiments, the calculation model for the polishing thickness of the current wafer layer includes:

[0116] Th n =Th n-1 +λ; where Th n Th represents the polishing thickness of the current wafer layer. n-1 λ represents the grinding thickness of the wafer layer described above, and λ is a preset compensation thickness.

[0117] For example, Th n-1 If Th is the grinding thickness of the first wafer layer, then Th n The grinding thickness of the second wafer layer.

[0118] For example, in some embodiments, the compensation thickness may have a preset default reference value. For instance, for semiconductor devices of different thicknesses and sizes, a corresponding default compensation thickness can be set based on the user's engineering experience or historical stacking data. Alternatively, the compensation thickness can also be calculated using AI based on a compensation model.

[0119] In some embodiments, after the step of reducing the polishing thickness of the next wafer layer, the method further includes:

[0120] S111, the second discrimination model is used to calculate the first bending trend in the first time period and the second bending trend in the second time period respectively;

[0121] S112, determine whether the difference between the second bending trend and the first bending trend belongs to the set threshold range; if not, issue a corresponding prompt signal.

[0122] Preferably, in this embodiment, when the model is corrected by combining the discrimination result of the first discrimination model, the reliability of the correction can also be verified by the continuous change in the bending trend.

[0123] Correspondingly, the present invention also provides a compensation system for crystal back polishing, comprising:

[0124] A first stacking module is used to stack at least one first wafer layer on a layer to be stacked to form a first stacking layer; wherein, the wafer layer includes: multiple rows of dies spaced apart;

[0125] A first monitoring module is used to monitor at least one first bending value and at least one second bending value of the first stacked layer in a first target area and a second target area, respectively; wherein the first target area is located in the peripheral area of ​​the wafer layer, the second target area is located in the central area of ​​the wafer layer, and an intermediate area is spaced between the first target area and the second target area, wherein multiple rows of dies are arranged around the intermediate area;

[0126] A first discrimination module is used to calculate a grinding compensation index based on the first bending value and the second bending value using a first discrimination model; wherein, the first discrimination model includes:

[0127] L1 = aX1 + bY1; where L1 is the grinding compensation index, a is the first weight, b is the second weight, X1 is the first degree of curvature, and Y1 is the second degree of curvature; wherein the first degree of curvature is a characteristic value of the at least one first curvature value, and the second degree of curvature is a characteristic value of the at least one second curvature value, and the characteristic value includes one or more of the following types: mean, median, mode, or maximum value.

[0128] The compensation module is used to reduce the polishing thickness of the next wafer layer when the polishing compensation index is greater than a set first compensation threshold.

[0129] In some embodiments, it also includes:

[0130] The second stacking module is used to stack at least one second wafer layer on the first stacking layer to obtain the second stacking layer;

[0131] The second monitoring module is used to monitor at least one third bending value and / or at least one fourth bending value of the second stacked layer in the first target area and / or the second target area, respectively.

[0132] The second discrimination module is used to calculate the bending trend based on at least one set of bending values ​​using a second discrimination model; wherein the second discrimination model includes:

[0133] L2 = α(X2 - X1) / t + β(Y2 - Y1) / t; where L2 represents the bending tendency, α is the third weight, β is the fourth weight, X1 and X2 are the first bending degrees of the first wafer layer and the second wafer layer, respectively, and Y... 1、 Y2 represents the second degree of bending of the first wafer layer and the second wafer layer, respectively; t is the interval between the two monitoring sessions.

[0134] The bending trend determination module is used to reduce the grinding thickness of the next wafer layer when the bending trend is greater than a set bending threshold.

[0135] In some embodiments, it also includes:

[0136] The exceeding indicator determination module is used to obtain the exceeding indicator when the bending trend exceeds the bending threshold within a first time period. The exceeding indicator can be the frequency of exceeding or the duration of exceeding.

[0137] The model correction module is used to correct the first discrimination model when the exceeded indicator is greater than a preset first exceeded threshold.

[0138] Example 2

[0139] See Figure 6 As shown, the present invention also provides a compensation method based on a crystal back compensation model, comprising:

[0140] S201, Obtain the stacking parameter combination of the first stacking layer, the first stacking layer comprising: a mother wafer, and at least one wafer layer disposed on the mother wafer, wherein the wafer layer has a plurality of grains, and correspondingly, the stacking parameter combination comprises:

[0141] The first data type includes: the thickness of the first stacked layer (e.g., the thickness of the first stacked layer is the overall thickness of the mother wafer and the wafer layers thereon), the size of the first stacked layer (e.g., the radius, diameter, etc. of the mother wafer), and the size of the grain (e.g., the radius, diameter, etc. of the grain).

[0142] The second data type includes: the first polishing thickness (e.g., the thickness of a grain) of the uppermost wafer layer of the first stacked layer, and the first curvature of the first stacked layer;

[0143] S202, the stacking parameter combination is input into the pre-built crystal back compensation model to obtain the second grinding thickness of the next wafer layer; wherein, the step of constructing the crystal back compensation model includes:

[0144] S21, Obtain a training sample set, the training sample set including: multiple sample points, the sample points being associated with a first historical stacking parameter combination and a second historical stacking parameter combination collected based on historical stacking layers, wherein the historical stacking layer includes: a first historical stacking layer; and a second historical stacking layer obtained by stacking at least one historical wafer layer on the first historical stacking layer; correspondingly, the first historical stacking parameter combination includes:

[0145] The first historical data type includes: the thickness of the first historical stack layer, the size of the historical stack layer, and the size of the grain;

[0146] The second historical data type includes: the first historical polishing thickness of the uppermost wafer layer of the first historical stack layer, and the first historical curvature of the first historical stack layer;

[0147] The second combination of historical stacking parameters includes:

[0148] The second polishing thickness of the at least one historical wafer layer, and the second historical curvature of the second historical stacked layer;

[0149] In this embodiment, the difference between the first historical curvature and the second historical curvature can be used to evaluate the impact of the second historical stacking layer on subsequent events.

[0150] In other words, one sample point in this embodiment corresponds to a semiconductor device at a packaging time.

[0151] S22, the training sample set is input to obtain a neural network model, and the corresponding crystal back compensation model is obtained; wherein, the input layer of the neural network model includes: the first historical stacking parameter combination and the second historical curvature, and the output layer includes: the second grinding thickness.

[0152] In some embodiments, different neural network models can be used for model training depending on the type of semiconductor device (e.g., different functional types or different size scales of semiconductor devices). For example, the neural network models that can be selected include: BP neural network, fully connected neural network (FCN), deep feedforward neural network (DNN), etc.

[0153] In some embodiments, the backplane compensation model can output a second polishing thickness at a specific degree of bend adjustment. The degree of bend adjustment (also equivalent to the bend adjustment speed) is the difference between the first bend at the current moment and the predicted bend (or target bend) at the next moment. At least one modified wafer layer with the second polishing thickness is stacked on the first stack layer to obtain a second stack layer, and the predicted bend of the second stack layer is the second bend.

[0154] Understandably, the specific degree of bending adjustment set in the model can be set by the user and can be used as the initial velocity of the crystal back compensation model.

[0155] For example, in some embodiments, the crystal back compensation model can also output multiple second grinding thicknesses corresponding to multiple bending adjustment conditions, which the user can freely select according to the multiple second grinding thicknesses.

[0156] In some embodiments, the curvature can be a first degree of curvature measured within a first target area.

[0157] Alternatively, the curvature can also be the second degree of curvature measured within the second target area.

[0158] Alternatively, the curvature can be a grinding compensation index obtained by combining the first and second target areas.

[0159] Alternatively, the curvature can also be multiple curvature values ​​at multiple measurement points in the first and second target regions. That is, the input combination of the crystal back compensation model also includes the curvature values ​​at multiple measurement points.

[0160] In some embodiments, including:

[0161] The grinding thickness of the next wafer layer is corrected to the second grinding thickness (i.e., this wafer layer is also called the corrected wafer layer).

[0162] The next wafer layer is stacked onto the first stacking layer to obtain the second stacking layer.

[0163] Monitor the second curvature of one or more of the second stacked layers;

[0164] The bending change trend is calculated based on the first curvature and the second curvature;

[0165] If the bending trend is less than the set bending trend, then the current second grinding thickness is considered to meet the compensation requirements.

[0166] For example, in some embodiments, the curvature is taken as an absolute value for ease of calculation. In actual stacking correction, due to the relatively limited compensation amount, there may be a certain delay in adjusting the curvature; that is, even after the grinding thickness of the next wafer layer is reduced, the curvature may still continue to increase. To address this, the difference in curvature before and after stacking (equivalent to the curvature trend) is calculated. When the difference between the curvature after stacking and the curvature at the previous moment is relatively small, the curvature trend is considered to be decreasing, and the correction feedback is relatively effective. Otherwise, if the correction speed is considered too slow or the correction is considered ineffective, a prompt signal can be issued to the user for manual verification.

[0167] Preferably, in some embodiments, the bending trend can be the actual trend of change in the curvature before correction.

[0168] Alternatively, in other embodiments, the bending tendency can be set by the user.

[0169] In some embodiments, the bending trend of the ice flower can be calculated by the curvature of the edge region between two moments.

[0170] In some embodiments, a central grain, spacer grains, and edge grains are sequentially disposed along the region from the center to the edge of the wafer layer. The first historical stacking parameter combination further includes a third historical data type, which includes the historical aperture of the edge grains, the historical aperture of the spacer grains, and the historical aperture of the edge grains. That is, the historical aperture can also be used as data for the input layer of the model training. Correspondingly, the stacking parameter combination may also include the historical aperture of the edge grains, the historical aperture of the spacer grains, and the historical aperture of the edge grains. In other words, the back-end compensation model in this embodiment can combine the grinding thickness of the stacked grains and the via size of the grains in different regions to comprehensively predict the optimized grinding thickness of the next layer of grains.

[0171] In some embodiments, the first historical stacking parameter combination further includes: the historical column number of the edge grains, the historical column number of the spacer grains, and the historical column number of the edge grains. That is, in some embodiments, the above column number can also be used as data for the input layer of the model training.

[0172] The present invention also provides a corresponding compensation system based on a crystal back compensation model, comprising:

[0173] A stacking parameter acquisition module is used to acquire a stacking parameter combination of a first stacking layer, the first stacking layer comprising: a mother wafer, and at least one wafer layer disposed on the mother wafer, wherein the wafer layer has multiple grains, and correspondingly, the stacking parameter combination includes:

[0174] The first data type includes: the thickness of the first stacked layer, the size of the first stacked layer, and the size of the grain;

[0175] The second data type includes: the first polishing thickness of the uppermost wafer layer of the first stacked layer, and the first curvature of the first stacked layer;

[0176] An input module is used to input the stacking parameter combination into a pre-built crystal back compensation model, and correspondingly obtain the second grinding thickness of the next wafer layer; wherein, the crystal back compensation model is constructed by training using a model training module; wherein, the model training module includes:

[0177] A sample set acquisition unit is used to acquire a training sample set, which includes: multiple sample points, each sample point being associated with a first historical stacking parameter combination and a second historical stacking parameter combination acquired based on historical stacking layers, wherein the historical stacking layers include: a first historical stacking layer; and a second historical stacking layer obtained by stacking at least one historical wafer layer on the first historical stacking layer; correspondingly,

[0178] The first historical stacking parameter combination includes: a first historical data type, which includes: the thickness of the first historical stacking layer, the size of the historical stacking layer, and the size of the die; and a second historical data type, which includes: the first historical polishing thickness of the uppermost wafer layer of the first historical stacking layer, and the first historical curvature of the first historical stacking layer.

[0179] The second combination of historical stacking parameters includes: the second polishing thickness of the current at least one historical wafer layer, and the second historical curvature of the second historical stacking layer;

[0180] The training unit is used to input the training sample set into the neural network model for training, and obtain the crystal back compensation model accordingly; wherein, the input layer of the neural network model includes: the first historical stacking parameter combination and the second historical curvature, and the output layer includes: the second grinding thickness.

[0181] In some embodiments, the system further includes: a monitoring module, the monitoring module comprising:

[0182] A correction unit is used to correct the grinding thickness of the next wafer layer to the second grinding thickness.

[0183] A stacking unit is used to stack the next wafer layer onto the first stacking layer, thereby obtaining a second stacking layer.

[0184] A monitoring unit is used to monitor the second curvature of one or more of the second stacked layers;

[0185] A trend calculation unit is used to calculate the bending change trend based on (one or more) first curvatures and (one or more) second curvatures;

[0186] An evaluation unit is used to determine that the current second grinding thickness meets the compensation requirements when the bending change trend is less than the set bending trend.

[0187] In some embodiments, a central grain, a spacer grain, and an edge grain are sequentially disposed on the wafer layer along its center to edge. The first historical stacking parameter combination further includes a third historical data type, which includes the historical aperture of the edge grain, the historical aperture of the spacer grain, and the historical aperture of the edge grain.

[0188] In some embodiments, the first historical stacking parameter combination further includes: the historical column number of the edge grains, the historical column number of the spacer grains, and the historical column number of the edge grains.

[0189] In some embodiments, the aperture of different regions can be set differently.

[0190] See Figure 2 As shown, the semiconductor device includes:

[0191] Mother chip 01, on which multiple transmission interfaces (such as I / O interfaces) are spaced apart, the transmission interfaces are used to electrically connect with the vias (such as TSVs, i.e., through-silicon vias) of the dies stacked thereon, and adjacent dies are electrically connected through the vias.

[0192] A first stacked portion 02 is disposed on the mother wafer, wherein the first stacked portion 02 includes: multiple first grain layers, and each grain layer includes: a plurality of spaced grains; the first grain layer includes: a first edge region arranged along the edge of the mother wafer, and a first central region arranged along the center region of the mother wafer, wherein the first edge region is provided with at least one column of first edge grains 021, the first central region is provided with at least one column of first central grains 023, and the first edge region and the first central region are arranged with a plurality of columns of first spacer grains 022 spaced apart;

[0193] A second stacking portion 03 is disposed on the first stacking portion, wherein the second stacking portion includes: a multilayer second grain layer, the second grain layer including: a second edge region arranged along the edge of the mother sheet, and a second center region arranged along the center region, wherein the second edge region is provided with at least one column of second edge grains 031, the second center region is provided with at least one column of second center grains 033, and the second edge region and the second center region are arranged with multiple columns of second spacer grains 032 at intervals;

[0194] In this article, different terms are used for the structural layer formed by a single grain, such as "grain layer" and "wafer layer". This is mainly to facilitate the distinction between different stacked structures or semiconductor devices in different embodiments.

[0195] The present invention also provides a computer-readable storage medium storing a program or instructions that, when executed, implement the method as described in any of the embodiments.

[0196] The present invention also provides a computer program product storing a program or instructions that, when executed, implement the method as described in any of the embodiments.

[0197] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0198] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a computer terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0199] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.

Claims

1. A compensation method for crystal back grinding, characterized in that, include: S101, at least one first wafer layer is stacked on the layer to be stacked to form a first stacked layer; wherein, the wafer layer includes: multiple rows of dies spaced apart; S102, monitor at least one first bending value and at least one second bending value of the first stacked layer in a first target area and a second target area respectively; wherein, the first target area is located in the peripheral area of ​​the wafer layer, the second target area is located in the central area of ​​the wafer layer, and an intermediate area is spaced between the first target area and the second target area, and multiple rows of dies are arranged around the intermediate area; S103, a first discrimination model is used to calculate a grinding compensation index based on the first bending value and the second bending value; wherein, the first discrimination model includes: L1 = aX1 + bY1; where L1 is the grinding compensation index, a is the first weight, b is the second weight, X1 is the first degree of curvature, and Y1 is the second degree of curvature; wherein the first degree of curvature is a characteristic value of the at least one first curvature value, and the second degree of curvature is a characteristic value of the at least one second curvature value, and the characteristic value includes one or more of the following types: mean, median, mode, or maximum value. S104, when the polishing compensation index is greater than the set first compensation threshold, the polishing thickness of the next wafer layer is reduced.

2. The compensation method according to claim 1, characterized in that, It also includes the following steps: S105, at least one second wafer layer is stacked on the first stacked layer to obtain the second stacked layer; S106, monitor at least one third bending value and / or at least one fourth bending value of the second stacked layer in the first target area and / or the second target area respectively; S107, a second discriminant model is used to calculate the bending trend based on at least one set of bending values; wherein, the second discriminant model includes: L2 = α(X2 - X1) / t + β(Y2 - Y1) / t; where L2 is the bending tendency, α is the third weight, β is the fourth weight, X1 and X2 are the first bending degrees of the first wafer layer and the second wafer layer, respectively, and Y... 1、 Y2 represents the second degree of bending of the first wafer layer and the second wafer layer, respectively; t is the interval between the two monitoring sessions. S108, when the bending tendency is greater than the set bending threshold, the grinding thickness of the next wafer layer is reduced.

3. The compensation method according to claim 2, characterized in that, It also includes the following steps: S109, obtain an exceedance indicator that the bending trend exceeds the bending threshold within a first time period. The exceedance indicator can be the frequency of exceedance or the duration of exceedance. S110, when the exceeded indicator is greater than a preset first exceeded threshold, the first discrimination model is corrected.

4. The compensation method according to claim 3, characterized in that, The steps for correcting the first discrimination model include: Increase the value of the first weight, and / or decrease the value of the second weight.

5. The compensation method according to claim 2, characterized in that, The polishing thickness of the second wafer layer is less than or equal to the polishing thickness of the first wafer layer.

6. The compensation method according to claim 2, characterized in that, The calculation model for the polishing thickness of the wafer layer currently mentioned includes: Th n =Th n-1 +λ; where Th n Th represents the polishing thickness of the current wafer layer. n-1 λ represents the grinding thickness of the wafer layer described above, and λ is the preset compensation thickness.

7. The compensation method according to claim 2, characterized in that, After the step of reducing the polishing thickness of the next wafer layer, the method further includes: S111, the second discrimination model is used to calculate the first bending trend in the first time period and the second bending trend in the second time period respectively; S112, determine whether the difference between the second bending trend and the first bending trend belongs to the set threshold range; if not, issue a corresponding prompt signal.

8. A compensation system for crystal back grinding, characterized in that, include: A first stacking module is configured to stack at least one first wafer layer on a layer to be stacked to form a first stacking layer; wherein the wafer layer comprises: multiple rows of dies spaced apart; A first monitoring module is used to monitor at least one first bending value and at least one second bending value of the first stacked layer in a first target area and a second target area, respectively; wherein the first target area is located in the peripheral area of ​​the wafer layer, the second target area is located in the central area of ​​the wafer layer, and an intermediate area is spaced between the first target area and the second target area, wherein multiple rows of dies are arranged around the intermediate area; A first discrimination module is used to calculate a grinding compensation index based on the first bending value and the second bending value using a first discrimination model; wherein, the first discrimination model includes: L1 = aX1 + bY1; where L1 is the grinding compensation index, a is the first weight, b is the second weight, X1 is the first degree of curvature, and Y1 is the second degree of curvature; wherein the first degree of curvature is a characteristic value of the at least one first curvature value, and the second degree of curvature is a characteristic value of the at least one second curvature value, and the characteristic value includes one or more of the following types: mean, median, mode, or maximum value. The compensation module is used to reduce the polishing thickness of the next wafer layer when the polishing compensation index is greater than a set first compensation threshold.

9. The compensation system according to claim 8, characterized in that, Also includes: The second stacking module is used to stack at least one second wafer layer on the first stacking layer to obtain the second stacking layer; The second monitoring module is used to monitor at least one third bending value and / or at least one fourth bending value of the second stacked layer in the first target area and / or the second target area, respectively. The second discrimination module is used to calculate the bending trend based on at least one set of bending values ​​using a second discrimination model; wherein the second discrimination model includes: L2 = α(X2 - X1) / t + β(Y2 - Y1) / t; where L2 represents the bending tendency, α is the third weight, β is the fourth weight, X1 and X2 are the first bending degrees of the first wafer layer and the second wafer layer, respectively, and Y... 1、 Y2 represents the second degree of bending of the first wafer layer and the second wafer layer, respectively; t is the interval between the two monitoring sessions. The bending trend determination module is used to reduce the grinding thickness of the next wafer layer when the bending trend is greater than a set bending threshold.

10. The compensation system according to claim 9, characterized in that, Also includes: The exceeding indicator determination module is used to obtain the exceeding indicator when the bending trend exceeds the bending threshold within a first time period. The exceeding indicator can be the frequency of exceeding or the duration of exceeding. The model correction module is used to correct the first discrimination model when the exceeded indicator is greater than a preset first exceeded threshold.

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