Epitaxial growth method and epitaxial growth device
By conducting stress testing on the edge of the epitaxial silicon wafer and adjusting relevant process parameters according to the test results, the problem of high fragmentation rate caused by excessive stress of the epitaxial silicon wafer is solved, and manufacturing quality and circuit performance are improved.
Patent Information
- Application Number
- CN202411731276.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-03-18
AI Technical Summary
Excessive stress on epitaxial silicon wafers leads to high debris ratio, affecting manufacturing quality and circuit performance.
By conducting stress testing on multiple preset test points at the edge of the epitaxial silicon wafer, edge stress is calculated based on the obtained stress value, and the power proportion of the edge heating module in the epitaxial reaction chamber, process temperature, position of the silicon wafer on the base and starting temperature when entering the reaction chamber are adjusted according to the stress value.
It reduces thermal stress during epitaxial growth, reduces the incidence of back-end fragmentation, improves the manufacturing quality and service life of epitaxial silicon wafers, and ensures circuit performance.
Smart Images
Figure CN119640396A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to an epitaxial growth method and an epitaxial growth device. Background Art
[0002] Epitaxial growth refers to the process of growing a single crystal thin film (the crystal direction is consistent with the substrate crystal direction) on a single crystal silicon substrate through epitaxy technology. The entire production process of epitaxial wafers includes five major processes: crystal growth (pulling silicon crystal rods from polysilicon materials) → molding (slicing and grinding) → polishing (double-sided polishing) → cleaning (removing surface particles, metal ions and organic matter) → epitaxy (vapor deposition). Epitaxy is the last important process, which can improve the crystal properties, native defects, stress and flatness of the polished wafer.
[0003] like Figure 1 As shown, the epitaxial growth equipment generally includes: an upper quartz bell jar 1, a lower quartz bell jar 2, an air inlet, an exhaust port, a halogen lamp 3, a mounting component 4, a top thermometer 9, and a bottom thermometer 10. In the reaction chamber enclosed by the upper quartz bell jar 1 and the lower quartz bell jar 2, a base 6 for placing a silicon wafer, a base support rod 7, and a silicon wafer support rod are provided. After the silicon wafer 8 is input into the reaction chamber and placed on the base 6 in the reaction chamber, the upper heating module arranged on the upper side of the base 6 and the lower heating module arranged on the lower side of the base 6 heat the silicon wafer 8, and the raw material gas 5 is supplied to the surface of the silicon wafer 8, thereby performing vapor phase epitaxial growth, and the epitaxial wafer obtained by vapor phase epitaxial growth is output to the outside of the reaction chamber. During the growth process, the base support rod 7 plays the role of fixing the base 6 and driving the base 6 to rotate, so that the epitaxial growth can be carried out evenly on the substrate 6.
[0004] The fragmentation rate of epitaxial silicon wafers is one of the important quality parameters of epitaxial silicon wafers, and the excessive stress of epitaxial silicon wafers is the main cause of epitaxial silicon wafer fragmentation. If the stress of epitaxial silicon wafers is too high, epitaxial silicon wafers are very likely to be fragmented during the back-end processing, resulting in loss of yield and reduced production efficiency. In addition, cracks or fragmentation on the surface of epitaxial silicon wafers will also cause damage to the devices on the epitaxial silicon wafers, affecting the performance of the entire circuit. Summary of the invention
[0005] In order to solve the above technical problems, the present invention provides an epitaxial growth method and an epitaxial growth device, which can reduce the occurrence of epitaxial silicon wafer fragments.
[0006] In order to achieve the above object, the technical solution adopted by the embodiment of the present invention is:
[0007] An epitaxial growth method comprising:
[0008] The first silicon wafer is sent into the epitaxial reaction chamber and placed on a susceptor in the epitaxial reaction chamber for epitaxial growth to obtain an epitaxial silicon wafer;
[0009] Performing stress tests on a plurality of preset test points at the edge of the epitaxial silicon wafer, and calculating the edge stress of the epitaxial silicon wafer according to the obtained stress values;
[0010] According to the edge stress, at least one of the following parameters is adjusted: the power proportion of the edge heating module in the epitaxial reaction chamber; the process temperature during the epitaxial growth process; the position of the second silicon wafer to be epitaxially grown on the base; the starting temperature of the second silicon wafer to be epitaxially grown when entering the epitaxial reaction chamber.
[0011] In some embodiments, the method specifically includes:
[0012] When the edge stress is greater than or equal to a preset threshold, the power proportion of the edge heating module in the epitaxial reaction chamber is reduced according to a preset first step length, and the preset first step length is 3-4%.
[0013] In some embodiments, the method specifically comprises:
[0014] When the edge stress is greater than or equal to a preset threshold, the process temperature during the epitaxial growth process is reduced according to a preset second step length, and the preset second step length is 8-10°C.
[0015] In some embodiments, the method specifically includes:
[0016] When the edge stress is greater than or equal to a preset threshold, the second silicon wafer is moved toward the center of the base.
[0017] In some embodiments, the method specifically includes:
[0018] When the edge stress is greater than or equal to a preset threshold, the starting temperature of the second silicon wafer to be subjected to epitaxial growth when entering the epitaxial reaction chamber is reduced according to a preset third step length, and the preset third step length is 8-10°C.
[0019] In some embodiments, performing stress testing on a plurality of preset test points at the edge of the epitaxial silicon wafer and calculating the edge stress of the epitaxial silicon wafer according to the obtained stress values comprises:
[0020] The maximum stress value of all test points is recorded as Y_max, and the minimum stress value is recorded as Y_min;
[0021] The edge stress Y is calculated using the following formula:
[0022] Y=(Y_max-Y_min) / (Y_max+Y_min)*100%.
[0023] In some embodiments, 9-45 test points are evenly arranged in the circumferential direction at the edge region of the epitaxial silicon wafer.
[0024] The embodiment of the present invention further provides an epitaxial growth device, comprising:
[0025] A conveying mechanism, used for conveying the first silicon wafer into the epitaxial reaction chamber, placing the first silicon wafer on a susceptor in the epitaxial reaction chamber for epitaxial growth, and obtaining an epitaxial silicon wafer;
[0026] A testing module, used to perform stress testing on a plurality of preset test points at the edge of the epitaxial silicon wafer, and calculate the edge stress of the epitaxial silicon wafer according to the obtained stress values;
[0027] An adjustment module is used to adjust at least one of the following parameters according to the edge stress: the power proportion of the edge heating module in the epitaxial reaction chamber; the process temperature during the epitaxial growth process; the position of the second silicon wafer to be epitaxially grown on the base; the starting temperature of the second silicon wafer to be epitaxially grown when entering the epitaxial reaction chamber.
[0028] An embodiment of the present invention further provides an epitaxial growth device, which includes: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the above-mentioned epitaxial growth method.
[0029] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores at least one instruction, and the at least one instruction is used to be executed by a processor to implement the above-mentioned epitaxial growth method.
[0030] The beneficial effects of the present invention are:
[0031] In this embodiment, stress tests are performed on multiple preset test points on the edge of the epitaxial silicon wafer, and the edge stress of the epitaxial silicon wafer is calculated based on the obtained stress value; based on the edge stress of the epitaxial silicon wafer, process parameters such as the power ratio of the edge heating module in the epitaxial reaction chamber, the process temperature during the epitaxial growth process, the position of the second silicon wafer to be epitaxially grown on the base, and the starting temperature of the second silicon wafer to be epitaxially grown when entering the epitaxial reaction chamber are adjusted, which can reduce the thermal stress during the epitaxial growth process, reduce the incidence of back-end fragments, and is beneficial to improving the manufacturing quality and service life of the epitaxial silicon wafer, and ensuring circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 A schematic diagram showing the structure of an existing epitaxial growth device;
[0033] Figure 2 A schematic diagram showing a flow chart of an epitaxial growth method according to an embodiment of the present invention;
[0034] Figure 3-Figure 6 A schematic diagram showing stress test data;
[0035] Figure 7 A schematic diagram showing the structure of an epitaxial growth device according to an embodiment of the present invention.
[0036] Reference numerals
[0037] 1Upper quartz bell jar
[0038] 2 Lower quartz bell jar
[0039] 3 Halogen lamps
[0040] 4. Install the components
[0041] 5. Process Gas
[0042] 6 Base
[0043] 7 Base support rod
[0044] 8 Silicon Wafer
[0045] 9 Top Thermometer
[0046] 10 Bottom thermometer DETAILED DESCRIPTION
[0047] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.
[0048] The invention provides an epitaxial growth method and an epitaxial growth device, which can reduce the occurrence of epitaxial silicon wafer fragments.
[0049] The embodiment of the present invention provides an epitaxial growth method, such as Figure 2 As shown, including:
[0050] Step 101: sending a first silicon wafer into an epitaxial reaction chamber, placing it on a susceptor in the epitaxial reaction chamber for epitaxial growth, and obtaining an epitaxial silicon wafer;
[0051] Step 102: performing stress tests on a plurality of preset test points at the edge of the epitaxial silicon wafer, and calculating the edge stress of the epitaxial silicon wafer according to the obtained stress values;
[0052] Step 103: According to the edge stress, at least one of the following parameters is adjusted: the power proportion of the edge heating module in the epitaxial reaction chamber; the process temperature during the epitaxial growth process; the position of the second silicon wafer to be epitaxially grown on the base; the starting temperature of the second silicon wafer to be epitaxially grown when entering the epitaxial reaction chamber.
[0053] In this embodiment, stress tests are performed on multiple preset test points on the edge of the epitaxial silicon wafer, and the edge stress of the epitaxial silicon wafer is calculated based on the obtained stress value; based on the edge stress of the epitaxial silicon wafer, process parameters such as the power ratio of the edge heating module in the epitaxial reaction chamber, the process temperature during the epitaxial growth process, the position of the second silicon wafer to be epitaxially grown on the base, and the starting temperature of the second silicon wafer to be epitaxially grown when entering the epitaxial reaction chamber are adjusted, which can reduce the thermal stress during the epitaxial growth process, reduce the incidence of back-end fragments, and is beneficial to improving the manufacturing quality and service life of the epitaxial silicon wafer, and ensuring circuit performance.
[0054] Experiments have found that the edge stress of epitaxial silicon wafers is related to the power proportion of the edge heating module during epitaxial growth. The greater the power proportion of the edge heating module, the greater the edge stress. The total heating module in the epitaxial reaction chamber includes an upper heating module and a lower heating module. The upper heating module and the lower heating module respectively include a central heating module close to the base and an edge heating module far from the base. The power proportion of the edge heating module is the ratio of the power of the edge heating module to the power of the total heating module.
[0055] like Figure 3The data shown are the data obtained by testing the edge stress of epitaxial silicon wafers under different power ratios of the edge heating module. Among them, when the power ratio of the edge heating module is 34%, the edge stress of the two epitaxial silicon wafers (including silicon wafer 1 and silicon wafer 2) is 7.97% and 9.03% respectively; when the power ratio of the edge heating module is 30%, the edge stress of the two epitaxial silicon wafers (including silicon wafer 1 and silicon wafer 2) is 6.85% and 5.78% respectively; when the power ratio of the edge heating module is 26%, the edge stress of the two epitaxial silicon wafers (including silicon wafer 1 and silicon wafer 2) is 6.35% and 5.17% respectively. It can be seen that the greater the power ratio of the edge heating module, the greater the edge stress. For every 4% reduction in the power ratio of the edge heating module, the edge stress can be reduced by 2% to 5%. Therefore, in some embodiments, when the edge stress is greater than or equal to the preset threshold, the power ratio of the edge heating module in the epitaxial reaction chamber can be reduced according to the preset first step length, the preset first step length is 3-4%, and the above preset threshold can be 5%. For example, when the edge stress is greater than or equal to a preset threshold, the power share of the edge heating module can be reduced by 4%, the second silicon wafer is placed in the epitaxial reaction chamber, epitaxial growth is performed on the second silicon wafer, and then the edge stress of the second silicon wafer is tested again. If the edge stress of the second silicon wafer is still greater than or equal to the preset threshold, the power share of the edge heating module continues to be reduced; if the edge stress of the second silicon wafer is less than the preset threshold, the power share of the edge heating module is no longer reduced.
[0056] It has been found through experiments that the edge stress of epitaxial silicon wafers is related to the process temperature during the epitaxial growth process. The higher the process temperature during the epitaxial growth process, the greater the edge stress.
[0057] like Figure 4The data shown are obtained by testing the edge stress of epitaxial silicon wafers at different process temperatures during the epitaxial growth process. When the process temperature during the epitaxial growth process is 1090 degrees Celsius, the edge stress of the two epitaxial silicon wafers (including silicon wafer 1 and silicon wafer 2) is 0% and 0.276% respectively; when the process temperature during the epitaxial growth process is 1110 degrees Celsius, the edge stress of the two epitaxial silicon wafers (including silicon wafer 1 and silicon wafer 2) is 0.552% and 0.331% respectively; when the process temperature during the epitaxial growth process is 1120 degrees Celsius, the edge stress of the two epitaxial silicon wafers (including silicon wafer 1 and silicon wafer 2) is 0.554% and 0.555% respectively; when the process temperature during the epitaxial growth process is 1130 degrees Celsius, the edge stress of the two epitaxial silicon wafers (including silicon wafer 1 and silicon wafer 2) is 1.780% and 1.050% respectively. It can be seen that the higher the process temperature during the epitaxial growth process, the greater the edge stress. For every 10°C decrease in the process temperature during the epitaxial growth process, the edge stress of the epitaxial silicon wafer can be reduced by 1% to 5%. Therefore, in some embodiments, when the edge stress is greater than or equal to the preset threshold, the process temperature during the epitaxial growth process is reduced according to the preset second step length, and the preset second step length is 8-10°C. The above preset threshold can be 5%. For example, when the edge stress is greater than or equal to the preset threshold, the process temperature during the epitaxial growth process can be reduced by 10°C, the second silicon wafer is placed in the epitaxial reaction chamber, and epitaxial growth is performed on the second silicon wafer. After that, the edge stress of the second silicon wafer is tested again. If the edge stress of the second silicon wafer is still greater than or equal to the preset threshold, the process temperature during the epitaxial growth process continues to be reduced; if the edge stress of the second silicon wafer is less than the preset threshold, the process temperature during the epitaxial growth process is no longer reduced.
[0058] Experiments have found that the edge stress of epitaxial silicon wafers is related to the position of the silicon wafer on the base. The closer the silicon wafer is to the center of the base, the less the base can scratch the edge of the silicon wafer, thereby reducing the edge stress.
[0059] like Figure 5The data shown are the data obtained by testing the edge stress of the epitaxial silicon wafer when the silicon wafer is placed at different positions on the base. Among them, when the position of silicon wafer 1 is close to the center of the base, the edge stress of the epitaxial silicon wafer obtained by silicon wafer 1 is 2.57%, and when the position of silicon wafer 2 is far from the center of the base, the edge stress of the epitaxial silicon wafer obtained by silicon wafer 2 is 7.35%; by adjusting the position of the silicon wafer on the base and reducing the scratching of the base on the edge of the silicon wafer, the edge stress of the epitaxial silicon wafer can be reduced by 5% to 10%. Therefore, in some embodiments, when the edge stress is greater than or equal to the preset threshold, the second silicon wafer is moved in the direction close to the center of the base. After that, the edge stress of the second silicon wafer is tested again. If the edge stress of the second silicon wafer is still greater than or equal to the preset threshold, the position of the silicon wafer on the base continues to be moved; if the edge stress of the second silicon wafer is less than the preset threshold, the position of the silicon wafer on the base is no longer moved.
[0060] It is found through experiments that the edge stress of the epitaxial silicon wafer is related to the starting temperature of the silicon wafer when it enters the epitaxial reaction chamber. The higher the starting temperature of the silicon wafer when it enters the epitaxial reaction chamber, the greater the edge stress.
[0061] like Figure 6 The data shown are obtained by testing the edge stress of the epitaxial silicon wafer at different starting temperatures when the silicon wafer enters the epitaxial reaction chamber. Among them, when the starting temperature of silicon wafer 1 entering the epitaxial reaction chamber is 575 degrees Celsius, the edge stress of the epitaxial silicon wafer obtained by silicon wafer 1 is 4.55%; when the starting temperature of silicon wafer 2 entering the epitaxial reaction chamber is 650 degrees Celsius, the edge stress of the epitaxial silicon wafer obtained by silicon wafer 2 is 5.45%; when the starting temperature of silicon wafer 3 entering the epitaxial reaction chamber is 750 degrees Celsius, the edge stress of the epitaxial silicon wafer obtained by silicon wafer 3 is 5.62%; by reducing the starting temperature when the silicon wafer enters the epitaxial reaction chamber, the edge stress of the epitaxial silicon wafer can be reduced by 1% to 5%. Therefore, in some embodiments, when the edge stress is greater than or equal to the preset threshold value, the starting temperature of the second silicon wafer to be subjected to epitaxial growth when entering the epitaxial reaction chamber is reduced according to the preset third step length, and the preset third step length is 8-10°C.
[0062] The preset threshold value may be 5%. For example, when the edge stress is greater than or equal to the preset threshold value, the starting temperature of the silicon wafer when entering the epitaxial reaction chamber may be reduced by 10°C, a second silicon wafer may be placed in the epitaxial reaction chamber, epitaxial growth may be performed on the second silicon wafer, and then the edge stress of the second silicon wafer may be tested again, and if the edge stress of the second silicon wafer is still greater than or equal to the preset threshold value, the starting temperature of the silicon wafer when entering the epitaxial reaction chamber may continue to be reduced; if the edge stress of the second silicon wafer is less than the preset threshold value, the starting temperature of the silicon wafer when entering the epitaxial reaction chamber may no longer be reduced.
[0063] In some embodiments, performing stress testing on a plurality of preset test points at the edge of the epitaxial silicon wafer and calculating the edge stress of the epitaxial silicon wafer according to the obtained stress values comprises:
[0064] The maximum stress value of all test points is recorded as Y_max, and the minimum stress value is recorded as Y_min;
[0065] The edge stress Y is calculated using the following formula:
[0066] Y=(Y_max-Y_min) / (Y_max+Y_min)*100%.
[0067] In some embodiments, 9-45 test points are evenly arranged in the circumferential direction at the edge region of the epitaxial silicon wafer.
[0068] In this embodiment, the edge stress of the epitaxial silicon wafer is improved to reduce the occurrence of fragments. In this embodiment, the edge stress of the epitaxial silicon wafer can be measured by a wafer residual stress measurement system (SIRD).
[0069] The embodiment of the present invention also provides an epitaxial growth device, such as Figure 7 As shown, including:
[0070] The conveying mechanism 21 is used to convey the first silicon wafer into the epitaxial reaction chamber, place it on the susceptor in the epitaxial reaction chamber for epitaxial growth, and obtain an epitaxial silicon wafer;
[0071] A testing module 22, configured to perform stress testing on a plurality of preset test points at the edge of the epitaxial silicon wafer, and calculate the edge stress of the epitaxial silicon wafer according to the obtained stress values;
[0072] The adjustment module 23 is used to adjust at least one of the following parameters according to the edge stress: the power proportion of the edge heating module in the epitaxial reaction chamber; the process temperature during the epitaxial growth process; the position of the second silicon wafer to be epitaxially grown on the base; the starting temperature of the second silicon wafer to be epitaxially grown when entering the epitaxial reaction chamber.
[0073] In this embodiment, stress tests are performed on multiple preset test points on the edge of the epitaxial silicon wafer, and the edge stress of the epitaxial silicon wafer is calculated based on the obtained stress value; based on the edge stress of the epitaxial silicon wafer, process parameters such as the power ratio of the edge heating module in the epitaxial reaction chamber, the process temperature during the epitaxial growth process, the position of the second silicon wafer to be epitaxially grown on the base, and the starting temperature of the second silicon wafer to be epitaxially grown when entering the epitaxial reaction chamber are adjusted, which can reduce the thermal stress during the epitaxial growth process, reduce the incidence of back-end fragments, and is beneficial to improving the manufacturing quality and service life of the epitaxial silicon wafer, and ensuring circuit performance.
[0074] In some embodiments, the adjustment module 23 is specifically used to reduce the power share of the edge heating module in the epitaxial reaction chamber according to a preset first step length when the edge stress is greater than or equal to a preset threshold, and the preset first step length is 3-4%.
[0075] In some embodiments, the adjustment module 23 is specifically used to reduce the process temperature in the epitaxial growth process according to a preset second step length when the edge stress is greater than or equal to a preset threshold, and the preset second step length is 8-10°C.
[0076] In some embodiments, the adjustment module 23 is specifically configured to move the second silicon wafer toward the center of the base when the edge stress is greater than or equal to a preset threshold.
[0077] In some embodiments, the adjustment module 23 is specifically used to reduce the starting temperature of the second silicon wafer to be epitaxially grown when entering the epitaxial reaction chamber according to a preset third step when the edge stress is greater than or equal to a preset threshold, and the preset third step is 8-10°C.
[0078] In some embodiments, the test module 22 is specifically used to record the maximum stress value of all test points as Y_max and the minimum stress value as Y_min;
[0079] The edge stress Y is calculated using the following formula:
[0080] Y=(Y_max-Y_min) / (Y_max+Y_min)*100%.
[0081] In some embodiments, 9-45 test points are evenly arranged in the circumferential direction at the edge region of the epitaxial silicon wafer.
[0082] An embodiment of the present invention further provides an epitaxial growth device, which includes: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the above-mentioned epitaxial growth method.
[0083] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores at least one instruction, and the at least one instruction is used to be executed by a processor to implement the above-mentioned epitaxial growth method.
[0084] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented with hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein the communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a general or special-purpose computer can access.
[0085] An embodiment of the present invention further provides an epitaxial device, which includes the above-mentioned epitaxial growth device.
[0086] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiments.
[0087] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0088] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.
[0089] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.
[0090] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.
Claims
1. An epitaxial growth method, characterized in that: include: The first silicon wafer is sent into the epitaxial reaction chamber and placed on a susceptor in the epitaxial reaction chamber for epitaxial growth to obtain an epitaxial silicon wafer; Performing stress tests on a plurality of preset test points at the edge of the epitaxial silicon wafer, and calculating the edge stress of the epitaxial silicon wafer according to the obtained stress values; According to the edge stress, at least one of the following parameters is adjusted: the power proportion of the edge heating module in the epitaxial reaction chamber; the process temperature during the epitaxial growth process; the position of the second silicon wafer to be epitaxially grown on the base; the starting temperature of the second silicon wafer to be epitaxially grown when entering the epitaxial reaction chamber.
2. The epitaxial growth method according to claim 1, characterized in that: The method specifically comprises: When the edge stress is greater than or equal to a preset threshold, the power proportion of the edge heating module in the epitaxial reaction chamber is reduced according to a preset first step length, and the preset first step length is 3-4%.
3. The epitaxial growth method according to claim 1, characterized in that: The method specifically comprises: When the edge stress is greater than or equal to a preset threshold, the process temperature during the epitaxial growth process is reduced according to a preset second step length, and the preset second step length is 8-10°C.
4. The epitaxial growth method according to claim 1, characterized in that: The method specifically comprises: When the edge stress is greater than or equal to a preset threshold, the second silicon wafer is moved toward the center of the base.
5. The epitaxial growth method according to claim 1, characterized in that: The method specifically comprises: When the edge stress is greater than or equal to a preset threshold, the starting temperature of the second silicon wafer to be subjected to epitaxial growth when entering the epitaxial reaction chamber is reduced according to a preset third step length, and the preset third step length is 8-10°C.
6. The epitaxial growth method according to claim 1, characterized in that: The step of performing stress testing on a plurality of preset test points at the edge of the epitaxial silicon wafer and calculating the edge stress of the epitaxial silicon wafer according to the obtained stress values comprises: The maximum stress value of all test points is recorded as Y_max, and the minimum stress value is recorded as Y_min; The edge stress Y is calculated using the following formula: Y=(Y_max-Y_min) / (Y_max+Y_min)*100%.
7. The epitaxial growth method according to claim 1, characterized in that: 9-45 test points are evenly arranged in the circumferential direction at the edge area of the epitaxial silicon wafer.
8. An epitaxial growth device, characterized in that: include: A conveying mechanism, used for conveying the first silicon wafer into the epitaxial reaction chamber, placing the first silicon wafer on a susceptor in the epitaxial reaction chamber for epitaxial growth, and obtaining an epitaxial silicon wafer; A testing module, used to perform stress testing on a plurality of preset test points at the edge of the epitaxial silicon wafer, and calculate the edge stress of the epitaxial silicon wafer according to the obtained stress values; An adjustment module is used to adjust at least one of the following parameters according to the edge stress: the power proportion of the edge heating module in the epitaxial reaction chamber; the process temperature during the epitaxial growth process; the position of the second silicon wafer to be epitaxially grown on the base; the starting temperature of the second silicon wafer to be epitaxially grown when entering the epitaxial reaction chamber.
9. An epitaxial growth device, characterized in that: The device comprises: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the epitaxial growth method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one instruction, and the at least one instruction is used to be executed by a processor to implement the epitaxial growth method according to any one of claims 1 to 7.