Low-noise infrared detector readout circuit

Abstract

This invention provides a low-noise infrared detector readout circuit, comprising: an integrating input module, a sample-and-hold module, a source follower module, a column-level switched capacitor module, and an analog-to-digital converter module connected in sequence. The sample-and-hold module samples two voltage signals output from the integrating input module twice based on the time difference of the sampling pulses; one sampling is of the voltage value before integration, and the other is of the voltage value at the end of integration; the time difference between the two sampling pulses is controlled to ensure that the noise at the two points is the same; the voltages obtained from the two samplings are then processed by the column-level switched capacitor module through a difference calculation, and finally output through the analog-to-digital converter module. This invention can solve the technical problems of insufficient noise and insufficient dynamic range in existing infrared detector readout circuits.

Description

Technical Field

[0001] This invention relates to the field of infrared detector readout circuit technology, and specifically to a low-noise infrared detector readout circuit. Background Technology

[0002] Infrared detection technology utilizes the difference in infrared radiation energy between the target and the imaging background to obtain information that is not directly visible to the naked eye. Infrared detectors can be used in temperature control, fire prevention and machine vision systems, body temperature monitoring and disease diagnosis, and monitoring greenhouse gas emissions, among other applications. As the performance requirements for infrared detectors increase, the dynamic range requirements for the detector's readout circuit also increase. However, the dynamic range is greatly affected by circuit noise; reducing circuit noise can effectively improve the dynamic range.

[0003] Therefore, there is an urgent need for a circuit structure that can reduce noise and be used in the readout circuit of an infrared detector to increase the dynamic range of the readout circuit. Summary of the Invention

[0004] In view of the shortcomings of the existing technology, the present invention proposes a low-noise infrared detector readout circuit to solve the technical problems of insufficient noise and insufficient dynamic range of the infrared detector readout circuit in the existing technology.

[0005] The technical solution adopted in this invention is as follows:

[0006] In a first aspect, a low-noise infrared detector readout circuit is provided, comprising: an integral input module, a sample and hold module, a source follower module, a column-level switched capacitor module, and an analog-to-digital converter module connected in sequence;

[0007] The integration input module is used to integrate and reset the input photocurrent to obtain two voltage signals;

[0008] The sample-and-hold module is used to sample the two voltage signals output by the integration input module twice according to the time difference of the sampling pulses; one sampling is of the voltage value before integration, and the other sampling is of the voltage value at the end of integration; the time difference between the two sampling pulses is controlled so that the noise at the two points is the same; the voltages obtained from the two samplings are then processed by the column-level switched capacitor module to calculate the difference, and finally output through the analog-to-digital converter module.

[0009] Furthermore, the integral input module includes a photodiode, an operational transconductance amplifier, two transmission gate switches S1 and S2, and two capacitors C1 and C2.

[0010] Furthermore, the sample-and-hold module includes a transmission gate switch S3 and a capacitor C3.

[0011] Furthermore, the source follower module includes NMOS transistors M1 and M2.

[0012] Furthermore, the column-level switched capacitor module includes capacitors C4 and C5, NMOS transistor switches S5 and S6, transmission gate switch S4, and a second operational amplifier.

[0013] Furthermore, the column-level switched capacitor module operates as follows: When Vpix samples the reset voltage, switches S4 and S5 are first turned on to obtain the charge Q4 stored on capacitor C4 and the charge Q5 stored on capacitor C5; when Vpix samples the integral voltage, switches S4 and S5 are turned off and switch S6 is turned on, the charge Q4' stored on capacitor C4 and the charge Q5' stored on capacitor C5 are obtained, the sum of Q4 and Q5 is equal to the sum of Q4' and Q5', and the output voltage is the difference between the two voltages; the noise voltage and the offset voltage cancel each other out, eliminating noise and voltage offset.

[0014] Furthermore, the analog-to-digital conversion module is a 10-bit, 20MHz SAR ADC.

[0015] Furthermore, the low-noise infrared detector readout circuit is array-type, and the control signals include row selection signals and column selection signals.

[0016] Secondly, a low-noise infrared detector is provided. Using the low-noise infrared detector readout circuit described in the first aspect, the input photocurrent signal is read, integrated to obtain a voltage signal, and then sequentially read out as a digital signal.

[0017] As can be seen from the above technical solution, the beneficial technical effects of the present invention are as follows:

[0018] 1. The circuit structure uses a single switched capacitor for pixel-level sampling, followed by a source follower, and then a column-level switched capacitor circuit as a subtractor. This saves more area, which can be used for a larger sampling capacitor to suppress KT / C noise. At the same time, placing the column-level subtractor after the source follower can eliminate the fixed-mode noise introduced by the source follower when using the existing circuit structure, further reducing circuit noise, improving the signal-to-noise ratio, and increasing the dynamic range of the readout circuit.

[0019] 2. Two samplings are performed based on the time difference of the sampling pulses; one sampling is of the voltage value before integration, and the other is of the voltage value at the end of integration; the time difference between the two sampling pulses is controlled to make the noise at the two points the same, and then the voltages obtained from the two samplings are processed by subtraction calculation through the column-level switched capacitor module, which can eliminate reset noise and suppress low-frequency noise, and can significantly improve the signal-to-noise ratio of the circuit.

[0020] 3. The offset voltage Vos of the second operational amplifier and the circuit noise Vnoise remain unchanged in both samplings. The noise voltage and offset voltage cancel each other out, eliminating noise and voltage offset. Attached Figure Description

[0021] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0022] Figure 1 This is a schematic diagram of the low-noise infrared detector readout circuit structure according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the structure of the two-stage operational amplifier used in the embodiments of the present invention;

[0024] Figure 3 This is a schematic diagram of the structure of the improved switched capacitor module according to an embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the operating timing of each switch in an embodiment of the present invention;

[0026] Figure 5 This is a schematic diagram showing the voltage / time relationship when the readout circuit is working according to an embodiment of the present invention. Detailed Implementation

[0027] The embodiments of the technical solution of the present invention will now be described in detail with reference to the accompanying drawings. These embodiments are merely illustrative of the technical solution of the present invention and are therefore intended to limit the scope of protection of the present invention.

[0028] It should be noted that, unless otherwise specified, the technical or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0029] Example

[0030] This embodiment provides a low-noise infrared detector readout circuit, such as Figure 1 As shown, it includes an integral input module, a sample-and-hold module, a source follower module, a column-level switched capacitor module, and an analog-to-digital converter (ADC) module connected in sequence. Details are as follows:

[0031] 1. Integral Input Module

[0032] The integration input module is used to integrate the input photocurrent and reset it after integration, resulting in two voltage signals; it includes a photodiode, an operational transconductance amplifier (OTA), two transmission gate switches S1 and S2, and two capacitors C1 and C2. In a specific implementation:

[0033] The positive input of the operational transconductance amplifier is connected to a bandgap reference voltage source Vref, and the negative input is connected to the cathode of a photodiode, providing the photodiode with a constant reverse bias voltage.

[0034] The transmission gate switch S2 is connected between the input and output terminals of the operational transconductance amplifier as a reset switch. After integration, S2 is opened to reset the voltage at the output terminal of the operational transconductance amplifier to the Vref value.

[0035] C1 is used as an integrating capacitor. The upper stage of the capacitor is connected to the output terminal of the operational amplifier, and the lower stage is connected to the negative input terminal of the operational transconductance amplifier. The capacitance value of C1 is smaller than that of C2, which is suitable for passive illumination. At this time, the light signal is weak and the generated photocurrent is smaller. Using a small capacitor to integrate it increases the dynamic range.

[0036] The transmission gate switch S1 and capacitor C2 are connected in series. The upper stage board of capacitor C2 is connected to the output of the operational amplifier, and the lower stage board is connected to the output of switch S1. The input of switch S1 is connected to the negative input of the operational transconductance amplifier. Switch S1 and capacitor C2 are suitable for active illumination. When switch S1 is turned on, C1 and C2 are connected in parallel, resulting in a larger equivalent integrating capacitance. At this time, the optical signal is strong and the photocurrent is larger. Using a large capacitor for integration prevents charge saturation and increases the dynamic range.

[0037] The circuit structure of the integral input module is used in the input stage of the readout circuit of a low-noise infrared detector, offering advantages such as high injection efficiency, high linearity, stable bias, and a wide dynamic range. Experimental data shows that when the operational amplifier gain is greater than 80dB, the injection efficiency and linearity can reach 99%. The operational transconductance amplifier's positive input is connected to a bandgap reference voltage, providing the infrared detector with a stable bias that is virtually unaffected by temperature. The high output swing of the operational transconductance amplifier provides a wide dynamic range for the readout circuit.

[0038] 2. Sample and hold module

[0039] The sample-and-hold module is used to sample the two voltage signals output by the integral input module.

[0040] In a specific implementation: the sample-and-hold module includes a transmission gate switch S3 and a capacitor C3. The input terminal of switch S3 is connected to the output terminal of the operational transconductance amplifier; the upper plate of capacitor C3 is connected to the output terminal of switch S3 and the gate of the source follower NMOS transistor M1, and the lower plate is grounded. The Vint voltage is sampled by closing or opening switch S3. Specifically, S3 is closed just before the reset switch S2 is about to close, at which time the voltage at the end of integration is sampled; after the reset is opened and then opened again, the voltage at a short time point after integration has just begun is sampled. The difference between the two voltage values ​​is then calculated to obtain the integrated voltage value.

[0041] 3. Source Follower Module

[0042] In a specific implementation, the source follower module includes NMOS transistors M1 and M2;

[0043] The gate of NMOS transistor M1 is connected to the upper stage of capacitor C3, the drain is connected to the working voltage VDD, and the source is connected to the source of NMOS transistor M2.

[0044] The gate of NMOS transistor M2 is connected to the row control signal ROW, and the drain is connected to the column bus and the upper plate of capacitor C4.

[0045] ROW acts as a row selection switch, controlling the voltage input on the sampling capacitor C3 to the subtractor.

[0046] 4. Column-level switched capacitor module

[0047] In a specific implementation, the column-level switched capacitor module includes capacitors C4 and C5, NMOS transistor switches S5 and S6, transmission gate switch S4, and a second operational amplifier.

[0048] The upper plate of capacitor C4 is connected to the column bus, and the lower plate is connected to the negative input terminal of the second operational amplifier.

[0049] The positive input terminal of the second operational amplifier is grounded, and the output terminal is connected to the analog-to-digital converter module.

[0050] The transmission gate switch S4 is connected between the input and output terminals of the second operational amplifier.

[0051] The lower plate of capacitor C5 is connected to the negative input terminal of the second operational amplifier, and the upper plate is connected to the source of NMOS transistor switches S5 and S6.

[0052] The drain of NMOS transistor switch S5 is grounded, and the gate is connected to the control signal.

[0053] The gate of NMOS transistor switch S6 is connected to the control signal, and the drain is connected to the output of transmission gate switch S4 and the output of the second operational amplifier.

[0054] In a specific implementation, the control signal connected to the gates of switches S5 and S6 is a voltage signal applied to the gate of the NMOS transistor. When the gate voltage is high (i.e., VDD), the switch is open, and when the gate voltage is low (i.e., GND), the switch is closed.

[0055] 5. Analog-to-Digital Conversion Module

[0056] In a specific implementation, the analog-to-digital converter (ADC) module consists of a 10-bit, 20MHz SAR ADC that sequentially reads the Vcds signal into digital signals, which are then processed by a DSP to obtain the image signal. As a chip-level ADC, the SAR ADC must meet the speed and accuracy requirements of the readout circuit. 20MHz corresponds to the readout circuit speed requirement, meaning the readout time for each pixel is no more than 50ns, and 10-bit corresponds to the readout circuit accuracy requirement, meaning the minimum resolvable voltage value is 1mV.

[0057] Figure 1 The dashed box in the image indicates that the entire infrared detector readout circuit is column-level, meaning that the circuit structure within the dashed box is a circuit module present in each pixel.

[0058] The synergistic effects of the above-mentioned modules are as follows: The integral input module can reduce readout circuit noise because the subtractor of the column-level switched capacitor module is located at the column level, and there is only one sampling capacitor per pixel. The integral capacitor of the integral input module can be set to be larger, and the KT / C noise of the switched capacitor can be reduced. At the same time, the integral capacitor of the integral input module is equivalent to Miller, and the equivalent capacitance at the input terminal is (1+Av)Cint, which can suppress input noise. The input stage operational transconductance amplifier of the integral input module has a large gain and an injection efficiency of up to 99%, which can also suppress the fluctuation noise of the current signal.

[0059] Compared with the existing infrared detector readout circuit structures, the circuit structure of this embodiment uses a single switched capacitor for pixel-level sampling, followed by a source follower, and then a column-level switched capacitor circuit as a subtractor. This saves more area, which can be used for a larger sampling capacitor to suppress KT / C noise. At the same time, the column-level subtractor is placed after the source follower, which can eliminate the fixed-mode noise introduced by the source follower when using the existing circuit structure, further reducing circuit noise, improving the signal-to-noise ratio, and increasing the dynamic range of the readout circuit.

[0060] The low-noise infrared detector readout circuit provided in this embodiment can eliminate reset noise and suppress low-frequency noise, significantly improving the circuit's signal-to-noise ratio. Within the same circuit, noise exhibits a certain temporal correlation. Its working principle is as follows: During one signal output cycle, two short pulses are applied to the readout circuit. By controlling these two pulses, the output signal is sampled twice. One pulse is located at the beginning of the output signal, sampling the voltage value before integration; the other pulse samples the voltage value at the end of integration. If the time difference between the two sampling pulses is properly controlled, the noise at the two sampling points can be made the same or nearly the same. Then, by subtracting the voltages obtained from the two samples, most of the 1 / f noise can be suppressed, the actual effective amplitude of the signal level can be obtained, and the dynamic range of the circuit can be further improved.

[0061] In some embodiments, reference Figure 2 This is the operational transconductance amplifier in the integrating input module, and its circuit structure is similar to that of the second operational amplifier in the column-stage switched capacitor module, hereinafter referred to as the second-stage op-amp. The left side of the second-stage op-amp is the bias circuit. M9 and M11 are cascode structures, effectively suppressing channel length modulation effects. M7, M8, M10, and M12 are self-biased current mirrors. Resistor R is added to provide a stable operating point for the current mirrors. The bias circuit provides a stable current source for the second-stage op-amp. The middle section is a five-transistor OTA structure. M19 and M20 are the differential input transistors of the op-amp, M3 and M4 are the first-stage load transistors, M0 is the tail current source transistor, and the drain of M2 is the first-stage output terminal. M5 and M6 form the second stage of the op-amp. M6 is the second-stage input transistor, M5 is the second-stage load transistor, and the drain of M6 is the second-stage output terminal. M13 and capacitor Cc form a Miller compensation structure, separating the major and minor poles of the op-amp, increasing the phase margin of the op-amp, and improving the stability of the op-amp. By incorporating a two-stage operational amplifier into the circuit, high gain and high bandwidth can be provided to meet the readout circuit design requirements.

[0062] In some embodiments, reference Figure 3 The working principle of the column-level switched capacitor module is as follows: When Vpix samples the reset voltage, switches S4 and S5 are first turned on, and the charge stored on capacitor C4 is Q4 = C4(Vrst + Vnoise - Vos - Vref), and the charge stored on capacitor C5 is Q5 = C5(Vos). When Vpix samples the integral voltage, switches S4 and S5 are turned off, and switch S6 is turned on. The charge stored on capacitor C4 is Q4' = C4(Vsig + Vnoise - Vos - Vref), and the charge stored on capacitor C5 is Q5' = C5(Vcds - Vos - Vref). According to the principle of charge conservation, Q4 + Q5 = Q4' + Q5', and the output voltage is the difference between the two sampled voltages, i.e., Vcds = Vref - (Vsig - Vrst), thus achieving the subtraction effect. Meanwhile, the offset voltage Vos of the second operational amplifier and the circuit noise Vnoise remain unchanged in both samplings. According to the principle of charge conservation, the noise voltage Vnoise and the offset voltage Vos cancel each other out, eliminating noise and voltage offset.

[0063] To facilitate understanding of the timing sequence of the low-noise infrared detector readout circuit in this embodiment, an example is provided: (Refer to...) Figure 4The diagram shows the timing control of each switch. Sampling switch S3 turns off a short time after reset switch S2 turns off. At this time, capacitor C3 stores the reset voltage Vrst and enters the integration state. ROW switch turns on before sampling switch S3 turns off, and switches S4 and S5 also turn on. At this time, the voltage Vpix is ​​the reset voltage Vrst sampled on capacitor C3. Sampling switch S3 turns off a short time before reset switch S2 turns off. At this time, the voltage sampled on capacitor C3 is the integrated voltage value Vsig. At the same time, switch ROW remains closed. Switch S6 also turns off after sampling switch S3 turns off. At this time, the voltage Vpix is ​​the integrated voltage value Vsig. Through the action of the subtractor, Vcds is the voltage value obtained by subtracting Vsig from Vrst. This value is transmitted to the SAR ADC for analog-to-digital conversion, converting the input current signal into a digital signal.

[0064] In some embodiments, the low-noise infrared detector readout circuit of this embodiment can be an array, and the control signals include row selection signals and column selection signals.

[0065] The voltage / time relationship of the low-noise infrared detector readout circuit in this embodiment during operation is as follows: Figure 5 As shown.

[0066] This embodiment also provides a low-noise infrared detector, which uses the low-noise infrared detector readout circuit described above to read the input photocurrent signal, integrate it to obtain a voltage signal, and then read it out sequentially as a digital signal.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and specification of the present invention.

Claims

1. A low-noise infrared detector readout circuit, characterized in that, include: The integral input module, sample and hold module, source follower module, column-level switched capacitor module, and analog-to-digital converter module are connected in sequence. The integration input module is used to integrate and reset the input photocurrent to obtain two voltage signals; The sample-and-hold module is used to sample the two voltage signals output by the integration input module twice according to the time difference of the sampling pulses; one sampling is of the voltage value before integration, and the other sampling is of the voltage value at the end of integration; the time difference between the two sampling pulses is controlled so that the noise at the two sampling points is the same; the voltages obtained from the two samplings are then processed by the column-level switched capacitor module to calculate the difference, and finally output through the analog-to-digital converter module; The integral input module includes a photodiode, an operational transconductance amplifier, two transmission gate switches S1 and S2, and two capacitors C1 and C2; the sample-and-hold module includes a transmission gate switch S3 and a capacitor C3; the source follower module includes NMOS transistors M1 and M2; the column-level switched capacitor module includes capacitors C4 and C5, NMOS transistor switches S5 and S6, a transmission gate switch S4, and a second operational amplifier. The integration input module, sample-and-hold module, and source follower module are considered as one pixel. The low-noise infrared detector readout circuit is an array type, containing multiple pixels and a column-level switched capacitor module. The control signals include row selection signals and column selection signals. The gate of NMOS transistor M2 is connected to the row control signal ROW, and the drain is connected to the column-level bus COL. When the low-noise infrared detector readout circuit is working, switch S3 is turned off a period of time after switch S2 is turned off. At this time, capacitor C3 stores the reset voltage Vrst and enters the integration state. The ROW switch is turned on before switch S3 is closed, and switches S4 and S5 are turned on at the same time. At this time, the Vpix voltage is the reset voltage Vrst sampled on capacitor C3. The sampling switch S3 is closed a period of time before the reset switch S2 is closed. At this time, the voltage sampled on capacitor C3 is the integrated voltage value Vsig. At the same time, switch ROW is kept closed. Switch S6 is also closed after the sampling switch S3 is closed. At this time, the Vpix voltage is the integrated voltage value Vsig. The offset voltage Vos of the second operational amplifier and the circuit noise Vnoise remain unchanged in both sampling and cancel each other out through the subtractor.

2. The low-noise infrared detector readout circuit according to claim 1, characterized in that, The column-level switched capacitor module operates as follows: When Vpix samples the reset voltage, switches S4 and S5 are first turned on to obtain the amount of charge stored on capacitor C4. The capacitor C5 stores charge. ; When Vpix samples the integral voltage, switches S4 and S5 are turned off, and switch S6 is turned on. The charge stored on capacitor C4 is... The charge stored in capacitor C5 is The sum of Q4 and Q5 is equal to the sum of Q4' and Q5', resulting in the output voltage being the difference between the two voltages; the noise voltage and the offset voltage cancel each other out, eliminating noise and voltage offset.

3. The low-noise infrared detector readout circuit according to claim 1, characterized in that, The analog-to-digital conversion module is a 10-bit, 20MHz SAR ADC.

4. A low-noise infrared detector, characterized in that, Using the low-noise infrared detector readout circuit according to any one of claims 1-3, the input photocurrent signal is read, integrated to obtain a voltage signal, and then sequentially read out as a digital signal.

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