An internal cavity defect detection method for MOSFET

Abstract

The present invention relates to the technical field of defect detection, and provides an internal cavity defect detection method for a MOSFET, comprising the following steps: acquiring an X-ray image of the MOSFET; detecting the vertex positions of the transistors in the X-ray image, and determining the transistor regions based on the vertex positions; dividing the transistor regions into a plurality of partitions, calculating the similarity between the partition gray-scale distribution and the fitted Gaussian distribution for each partition, and determining whether the similarity is less than a preset similarity threshold. If so, it is considered that the partition corresponding to the similarity contains a cavity defect; otherwise, based on the calculation of the pixel gray-scale values, the pixel with the largest gray-scale value in the partition corresponding to the similarity is found; determining whether the pixel with the largest gray-scale value is a cavity defect pixel. If so, it is considered that the partition contains a cavity defect, otherwise it is considered that the partition does not contain a cavity defect; positioning the cavity defect in the partition containing the cavity defect; The result accuracy and calculation robustness of this defect detection method are relatively good.

Description

Technical Field

[0001] The present invention relates to the technical field of defect detection, and more specifically, to a method for detecting internal cavity defects of a MOSFET. Background Art

[0002] Internal cavity defects may be caused by various factors such as material purity problems and process errors during the manufacturing process. These cavity defects will lead to an increase in resistance in the electron channel, an increase in leakage current, and a shortening of the device life, thereby affecting the performance and reliability of the device. Moreover, the higher the proportion of cavity defects, the worse the performance of the device and the shorter its life. When using the X-ray technology to manually detect cavities, it is easy to miss detections and make false detections. Therefore, for the design of electronic components such as MOSFETs, the importance of an automatic cavity defect detection algorithm is self-evident. Timely discovery and resolution of internal cavity defects can improve the reliability and performance of the device and ensure its stable operation in various applications.

[0003] Different from other electronic components, a MOSFET is attached to a substrate through a welding material. To obtain the proportion of cavity defects, it is necessary to calculate the areas of the transistor and the cavity defects in sequence, and finally obtain the proportion of cavity defects. The X-ray image of a MOSFET has the problem of uneven gray-scale distribution, and some cavity defects present weak edges, which makes it difficult for global threshold or edge detection algorithms to accurately locate the cavity defects at the pixel level. If a deep learning method is used, a large number of manually labeled samples are required, which will greatly increase the cost. In addition, if new samples appear, the model needs to be retrained, which is time-consuming and laborious.

[0004] In order to overcome the defects of the defect detection method based on deep learning, the prior art proposes a method for detecting MOSFET etching defects based on machine vision. Based on the gray-scale image of the MOSFET etching defects, the significant change trend of each pixel can be deduced according to the gray-scale information of the pixels in the eight neighborhoods around each pixel. Subsequently, by analyzing the change trend of the pixels in the neighborhood window of each pixel, it can be inferred whether the pixel is in the notch area, and the suspicion degree of its notch area can be calculated. Considering the suspicion degree of the notch area of each pixel comprehensively, the suspicion degree of the notch defect of each pixel is obtained. Further, the severity of the MOSFET etching defects is evaluated according to the suspicion degree of the notch defect. Finally, combined with a preset defect threshold, the detection task of the MOSFET etching defects is completed.

[0005] However, the object detected by the methods of the prior art is the etching defects of MOSFETs. The defect detection problem is transformed into the problem of analyzing the change trend of pixel gray levels. However, the images of MOSFETs may be interfered by noise, and the method of deriving using gray level information will lead to unstable detection results. Moreover, it is necessary to preset a defect threshold for separating the transistor region from the void defects, and the selection of the threshold will be affected by subjective factors of people, resulting in insufficient accuracy and robustness of defect detection. Summary of the Invention

[0006] To overcome the defect of insufficient accuracy and robustness of defect detection caused by the need to preset a defect threshold in the above-mentioned prior art, the present invention provides an internal void defect detection method for MOSFETs that can adaptively locate void defects.

[0007] To solve the above technical problems, the technical solution of the present invention is as follows:

[0008] Obtain the X-ray image of the MOSFET;

[0009] Detect the vertex positions of the transistors in the X-ray image, and determine the transistor region based on the vertex positions;

[0010] Divide the transistor region into several partitions. For each partition, calculate the similarity between the partition gray level distribution and the fitted Gaussian distribution, and determine whether the similarity is less than a preset similarity threshold. If so, it is considered that the partition corresponding to the similarity contains void defects; otherwise, based on the calculation of pixel gray level values, find the pixel with the largest gray level value in the partition corresponding to the similarity; determine whether the pixel with the largest gray level value is a void defect pixel. If so, it is considered that this partition contains void defects, otherwise it is considered that this partition does not contain void defects;

[0011] Locate the void defects in the partitions containing void defects.

[0012] The present invention also proposes an internal void defect detection system for MOSFETs to implement the above-mentioned internal void defect detection method for MOSFETs. The system includes:

[0013] An image acquisition module that acquires the X-ray image of the MOSFET;

[0014] A vertex detection module for detecting the vertex positions of the transistors in the X-ray image and determining the transistor region based on the vertex positions;

[0015] The cavity defect partition detection module is used to divide the transistor region into several partitions. For each partition, calculate the similarity between the partition gray distribution and the fitted Gaussian distribution, and determine whether the similarity is less than a preset similarity threshold. If so, it is considered that the partition corresponding to the similarity contains cavity defects; otherwise, based on the calculation of pixel gray values, find the pixel with the largest gray value within the partition corresponding to the similarity; determine whether the pixel with the largest gray value is a cavity defect pixel. If so, it is considered that this partition contains cavity defects, otherwise it is considered that this partition does not contain cavity defects;

[0016] The cavity defect location module locates the cavity defects in the partitions containing cavity defects.

[0017] The present invention also proposes a computer device, including a memory and a processor. Computer-readable instructions are stored in the memory. When the computer-readable instructions are executed by the processor, the processor executes the steps of the internal cavity defect detection method of the above MOSFET.

[0018] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0019] The present invention determines the transistor region based on the vertex positions of the transistors, can accurately locate the vertices, and overcomes the disadvantages that the edge detection algorithm cannot recognize the transistor boundary because it is a weak edge, or the recognition is incomplete. The transistor region is divided into several partitions. Through the characteristic that the gray distribution of the partition without cavity defects approaches the fitted Gaussian distribution, the partitions with obvious cavity defects are initially screened out. For the partitions with a large similarity between the partition gray distribution and the fitted Gaussian distribution, by determining whether the pixel with the largest gray value within the partition is a cavity defect pixel, it is determined whether there are cavity defects in this partition; it overcomes the defect that the global threshold segmentation algorithm is prone to misjudging non-cavity defect pixels as cavity defect pixels. After determining the partitions with cavity defects, the cavity defects in all partitions with cavity defects are located, improving the efficiency of cavity defect detection and achieving a high pixel-level location accuracy. Description of the Drawings

[0020] Figure 1 It is the first flow schematic diagram of the internal cavity defect detection method of the MOSFET proposed in Embodiment 1;

[0021] Figure 2 It is the second flow schematic diagram of the internal cavity defect detection method of the MOSFET proposed in Embodiment 2;

[0022] Figure 3 It is the vertex detection algorithm schematic diagram proposed in Embodiment 2;

[0023] Figure 4 It is the flow schematic diagram of the partition and preprocessing proposed in Embodiment 2. Detailed implementation manners

[0024] The attached drawings are only for illustrative purposes and should not be construed as a limitation to this embodiment;

[0025] For better illustration of this embodiment, some components in the attached drawings will be omitted, enlarged or reduced, which do not represent the dimensions of the actual product;

[0026] For those skilled in the art, it is understandable that some well-known structures and their descriptions in the attached drawings may be omitted.

[0027] The technical solutions of the present invention will be further described below in conjunction with the attached drawings and embodiments.

[0028] Embodiment 1

[0029] This embodiment proposes a method for detecting internal cavity defects of a MOSFET, Figure 1 which is the first flow schematic diagram of the method for detecting internal cavity defects of the MOSFET in this embodiment;

[0030] A method for detecting internal cavity defects of a MOSFET proposed in this embodiment includes the following steps:

[0031] S1: Obtain the X-ray image of the MOSFET;

[0032] S2: Detect the vertex positions of the transistors in the X-ray image, and determine the transistor regions based on the vertex positions;

[0033] S3: Divide the transistor regions into several partitions. For each partition, calculate the similarity between the partition gray distribution and the fitted Gaussian distribution, and determine whether the similarity is less than a preset similarity threshold. If so, it is considered that the partition corresponding to the similarity contains cavity defects; otherwise, based on the calculation of pixel gray values, find the pixel with the largest gray value in the partition corresponding to the similarity; determine whether the pixel with the largest gray value is a cavity defect pixel. If so, it is considered that this partition contains cavity defects; otherwise, it is considered that this partition does not contain cavity defects;

[0034] S4: Locate the cavity defects in the partitions containing cavity defects.

[0035] In the specific implementation process, determining the transistor region based on the vertex position of the transistor can accurately locate the vertex, overcome the disadvantages that the edge detection algorithm cannot recognize the boundary of the transistor because it is a weak edge, or the recognition is incomplete; and divide the transistor region into several partitions. Based on the characteristic that the gray-scale distribution of the partition without hole defects approaches the fitted Gaussian distribution, the partitions with obvious hole defects are preliminarily screened out. For the partitions with a large similarity between the gray-scale distribution and the fitted Gaussian distribution, it is determined whether there are hole defects in the partition by judging whether the pixel with the largest gray-scale value in the partition is a hole-defect pixel; overcome the defect that the global threshold segmentation algorithm is prone to misjudging non-hole-defect pixels as hole-defect pixels; after determining the partitions with hole defects, perform hole-defect positioning on all partitions with hole defects, improve the efficiency of hole-defect detection, and can achieve a high pixel-level positioning accuracy.

[0036] In an alternative embodiment, the step of detecting the vertex position of the transistor in the X-ray image includes:

[0037] Using the sliding window technique to find the vertex of the transistor from the X-ray image, and obtaining the rough positioning coordinates (x y c1 ) of the upper left vertex of the transistor, the rough positioning coordinates (x c， y c2 ) of the lower left vertex, the rough positioning coordinates (x c3 , y c3 ) of the upper right vertex, and the rough positioning coordinates (x c4， y c4 ) of the lower right vertex;

[0038] Divide the sliding window w ci , y ci ) centered on the rough positioning coordinates of the vertex of the transistor into two parts, one part is w i , and the other part is w 1i , where i = 1, 2, 3, 4. When i = 1, w 2i is the lower right 1 / 4 part of the sliding window w 1i , when i = 2, w i is the upper right 1 / 4 part of the sliding window w 1i , when i = 3, w i is the lower left 1 / 4 part of the sliding window w 1i , when i = 4, w i is the upper left 1 / 4 part of the sliding window w 1i ; i

[0039] Based on w 1i , w 2i for the rough positioning coordinates (x ci ​, y ci ) perform iterative optimization to obtain the vertex position coordinates (x vi , y vi ) of the transistor, where i = 1, 2, 3, 4. When i = 1, (x vi , y vi ) represents the upper left vertex position coordinates of the transistor. When i = 2, (x vi , y vi ) represents the lower left vertex position coordinates of the transistor. When i = 3, (x vi , y vi ) represents the upper right vertex position coordinates of the transistor. When i = 4, (x vi , y vi ) represents the lower right vertex position coordinates of the transistor;

[0040] The calculation expression of the vertex position coordinates (x vi , y vi ) of the transistor includes:

[0041] (x vi , y vi ) = argminJ(x ci , y ci )

[0042]

[0043] In the formula, and respectively represent the variances of w 1i , w 2i and w i . and respectively represent the means of w 1i and w 2i . α represents the balance coefficient;

[0044] The area enclosed by the vertex position coordinates (x vi , y vi ) of the transistor is the transistor area.

[0045] As an exemplary illustration, the vertex position coordinates (x ci , y vi ) of the transistor are subject to the constraints, and the expression of the constraints includes:

[0046]

[0047] In the formula, N I represents the width size of the X-ray image, and N w represents the window width size of the sliding window w i .

[0048] In an alternative embodiment, before dividing the transistor region into a plurality of partitions, preprocessing of the image within the transistor region is performed by mean filtering and adaptive histogram equalization to obtain a preprocessed transistor region image;

[0049] Based on the preprocessed transistor region image, the transistor region is divided into a plurality of partitions by linear spatial transformation based on gray values, wherein the difference between the minimum gray value and the maximum gray value of the pixels within the same partition does not exceed a preset difference.

[0050] In an alternative embodiment, the calculation expression for calculating the similarity between the partition gray distribution and the fitted Gaussian distribution for each partition includes:

[0051] G Coarse (P1) = k co × D KL (R P ||Q P ) + b co

[0052]

[0053] In the formula, P1 represents any partition, G Coarse (P1) represents the similarity between partition P1 and the fitted Gaussian distribution, R P represents the gray distribution of partition P1, Q P represents the maximum likelihood fitted distribution of the gray distribution R P , ρ represents a proportionality coefficient, τ represents a smoothing factor, p Hf represents the gray value corresponding to the maximum gray frequency of partition P1, μ represents the gray mean of partition P1, and |·| represents the absolute value operation.

[0054] In an alternative embodiment, when determining whether the pixel with the maximum gray value is a void defect pixel, the maximum gray difference G Fine (P2) of the gray values of two adjacent pixel value neighborhoods corresponding to the pixel with the maximum gray value is calculated. If the maximum gray difference G Fine (P2) exceeds a preset gray difference threshold, then the pixel with the maximum gray value is regarded as a void defect pixel; otherwise, it is considered that there is no void defect within the partition corresponding to the pixel with the maximum gray value;

[0055] Assume that the size of the first pixel value neighborhood corresponding to the pixel with the maximum gray value is (N×l + 1)×(N×l + 1), and the size of the second pixel value neighborhood is ((N - 1)×l + 1)×((N - 1)×l + 1). Then the expression for the maximum gray difference G Fine (P2) includes:

[0056]

[0057] Δ(D P (N)) = D P (N) - D P (N - 1)

[0058]

[0059] m = [M P (N), -M P (N - 1)] T

[0060] n = [(N × l + 1) 2 , ((N - 1) × l + 1) 2 T

[0061] In the formula, P2 represents the partition where the pixel with the maximum gray value is located, G Fine (P2) represents the maximum gray difference value within the partition P2, N represents the neighborhood expansion coefficient, l represents the step size of neighborhood expansion, N d represents the maximum neighborhood expansion coefficient, |·| represents the absolute value operation, T represents the transpose symbol, M P (N) represents the mean function of the neighborhood of the first pixel value, M P (N - 1) represents the mean function of the neighborhood of the second pixel value.

[0062] In an optional embodiment, after locating the hole defect in the partition containing the hole defect, a hole defect pixel - level location map P seg (x, y) is obtained. The expression of the location map P seg (x, y) includes:

[0063]

[0064] (u opt , v opt ) = arg minθ(u, V)

[0065] s.t. (k ref - δ) ≤ u, v ≤ (k ref + δ)

[0066]

[0067] s.t. k peak < k < L

[0068] k peak = arg max F(k) ​

[0069]

[0070] In the formula, P represents the partition where the void defect pixel is located, P n represents the per-pixel neighborhood mean of partition P, P(x, y) and P n (x, y) respectively represent the gray values of P and P n at the coordinate (x, y), u opt represents the abscissa of the segmentation threshold coordinate of partition P, v opt represents the ordinate of the segmentation threshold coordinate of partition P, u represents the abscissa of the boundary threshold coordinate of partition P, v represents the ordinate of the boundary threshold coordinate of partition P, and δ represents the size of the window for traversal. represents the set of positive integers, L represents the maximum gray value that can be obtained within the partition, f(i, j) represents the joint probability density distribution of partition P, both i and j represent the random variables of f(i, j), λ represents the stop condition for the search, and γ represents the correction factor; G r represents a preset gray value; θ(u, v) represents the void defect threshold discrimination vector.

[0071] As an exemplary illustration, the larger the value of G r , the more obvious the void defect is in the void defect pixel-level localization map P seg (x, y). In order to highlight the void defect as much as possible, in this alternative embodiment, the maximum gray value 255 is selected as the value of G r .

[0072] In an alternative embodiment, the expression of the void defect threshold discrimination vector θ(u, v) includes:

[0073]

[0074] In the formula, AMD intra (u, v) represents the intra-class aggregation coefficient of the void defect and the transistor region-like pixels, AMD intra (u, v) is smaller, indicating that the intra-class aggregation of the void defect and the transistor region-like pixels is better; AMD inter (u, v) represents the inter-class difference coefficient between the void defect and the transistor region-like pixels, AMD inter (u, v) is larger, indicating a greater difference between the void defect and the transistor region-like pixels; ω void (u, v) represents the weight of the void defect region, ω tran (u, v) represents the weight of the transistor region, and |·| represents the absolute value operation.

[0075] In an alternative embodiment, the intra-class aggregation coefficient AMD of the void defect and the transistor region-like pixels intra(u, v) and the between-class difference coefficient AMD inter The expression of (u, v) includes:

[0076] AMD intra (u, v) = ω tran (u, v) × d tran (u, v) + ω void (u, v) × d void (u, v)

[0077]

[0078] In the formula, AMD intra The smaller (u, v) is, the better the intra-class aggregation of the pixels in the void defect and transistor region classes; AMD inter The larger (u, v) is, the greater the difference between the void defect and the pixels in the transistor region class; d tran (u, v) represents the intra-class average absolute difference of the pixels in the transistor region class; d void (u, v) represents the intra-class average absolute difference of the pixels in the void defect region class; μ(u, v)1 and μ(u, v)2 respectively represent the first and second elements of μ(u, v).

[0079] Example 2

[0080] Based on the internal void defect detection method of the MOSFET proposed in Example 1, the following specific implementation examples are proposed:

[0081] Figure 2 For the second flow schematic diagram of the internal void defect detection method of the MOSFET in this embodiment, as Figure 2 shown, this method mainly includes three stages: transistor region detection, void defect detection, and void defect ratio calculation. In the transistor region detection stage, the vertex positions of the transistors are obtained using a custom position-aware algorithm, and the area of the transistor region is obtained. In the void defect detection stage, a custom coarse-to-fine patch-level void defect discrimination framework is used to screen out the patches containing void defects, and pixel-level localization of the void defects is performed on the patches containing void defects. In the void defect ratio calculation stage, the void defect ratio is calculated using the areas of the transistors and void defect regions obtained, realizing the void defect detection of the MOSFET.

[0082] The steps of transistor region detection are as follows:

[0083] Since the boundary of the transistor region is a weak edge with an unclear gray-scale gradient, if an edge detection algorithm is used, it is easy to have the problem of not finding a suitable boundary, and the internal hole defects are likely to cause interference, resulting in incomplete edge extraction. Therefore, we propose a vertex localization algorithm based on position awareness, which constructs an optimization function through the data features of the window and obtains the vertices of the transistor region through iterative optimization. Then, the obtained vertices are connected in sequence to calculate the area of the transistor region.

[0084] The steps for detecting hole defects are as follows:

[0085] Partitioning and preprocessing: Since there is noise interference in the MOSFET image, the image is first subjected to mean filtering to complete preliminary denoising. To solve the problem that the contrast between some defects and the background is not strong, the image is subjected to adaptive histogram equalization. To solve the problem of uneven gray-scale distribution in the transistor region, the transistor region is divided into several different patches. Finally, a linear spatial transformation is performed on each patch to further enhance the contrast.

[0086] Coarse discrimination: For the divided patches, a patch-level discrimination algorithm for hole defects is used to screen out the patches containing hole defects. The gray-scale distribution of each patch is fitted, and the similarity between the fitted distribution and the original distribution is evaluated. Finally, a discrimination function combining weights and bias terms is used to determine whether a patch contains hole defects.

[0087] Fine discrimination: Since tiny hole defects do not have much impact on the gray-scale distribution within a patch, patches containing only a small number of tiny hole defects are likely to be misjudged as patches without hole defects by the coarse discrimination module. Therefore, we propose a fine discrimination module to perform secondary discrimination on the patches. This method uses a set function to evaluate the difference in gray-scale distributions in different neighborhoods, thereby determining whether there are tiny hole defects within a patch.

[0088] Since there is noise interference in the MOSFET image itself and noise is introduced during the adaptive histogram equalization stage. And ordinary threshold algorithms rely too much on gray-scale features and fail to fully exploit the gray-scale distribution information, easily resulting in pixel-level discrimination errors. To reduce the detection time and make full use of the gray-scale distribution information, we propose an adaptive threshold algorithm for pixel-level localization of hole defects. This algorithm first narrows the range of selectable thresholds and finally determines the segmentation threshold using the proposed threshold decision function to complete the pixel-level localization of hole defects.

[0089] The steps for calculating the proportion of hole defects are as follows:

[0090] After obtaining the areas of the transistor and the cavity defect region through the above steps, the proportion of cavity defects can be calculated to complete the final MOSFET cavity defect detection.

[0091] Specifically, the MOSFET transistor part is similar to a quadrilateral in shape, so the area of this part can be obtained by locating the vertices of the transistor region. We propose a vertex detection algorithm based on position awareness. Taking the solution of the upper left vertex of the transistor region as an example, the algorithm is outlined as follows.

[0092] Let the point coordinates be (x c , y c ). Figure 3 This is the schematic diagram of the vertex detection algorithm proposed in this embodiment.

[0093] As Figure 3 shown, (x c , y c ) is at a certain distance from the vertex. Let the lower right 1 / 4 (dashed box) part of the window w centered on (x c , y c ) be w1, and the other part be w2. When (x c , y c ) is the vertex, the gray value of w1 is lower, the gray value of w2 is higher, and the gray difference in each part is not large. The coordinates of the vertex can be obtained by iteratively optimizing (x c , y c ). The vertex coordinates (x v , y v ) are:

[0094] (x v , y v ) = arg min J(x c , y c )

[0095]

[0096] where N I represents the width and height of the image, and N w represents the width and height of the window. Based on the gray feature of the vertex neighborhood window described above, the function J(x c , y c ) can be expressed as:

[0097]

[0098] where and represent the variances of w1, w2, and w respectively, and represent the means of w1 and w2 respectively, and α is a balance coefficient.

[0099] The other three vertices can also be located in the same way. After all the vertices are located, the transistor region can be detected and its area can be calculated.

[0100] For the convenience of subsequent void defect detection, the detected transistor region is first partitioned and preprocessed. Figure 4 This is a schematic flowchart of the partitioning and preprocessing proposed in this embodiment.

[0101] As Figure 4 shown, since the X-ray image of the MOSFET is affected by noise, mean filtering is first performed to suppress the noise and smooth the image at the same time. In order to enhance the contrast of void defects, the Contrast Limited Adaptive Histogram Equalization (CLAHE) algorithm is used to process the image. Since the gray level of the transistor region is uneven, which is not conducive to subsequent void defect detection, the transistor region is divided into several different patches. Finally, for the divided patches, linear spatial transformation is performed on them to further enhance the contrast.

[0102] To screen out the patches containing void defects, we propose a coarse-fine patch-level void defect discrimination framework. First, the preliminary discrimination is completed through the coarse discrimination module. However, patches that only contain small-sized void defects are easily misjudged as patches without void defects. Therefore, for the patches judged as without void defects by the coarse discrimination module, the fine discrimination module is used for secondary discrimination.

[0103] Since the gray level distribution of patches without void defects approaches a Gaussian distribution, the distribution R P of each image patch (P) is subjected to maximum likelihood estimation, the mean and standard deviation within P are calculated, distribution fitting is performed to obtain the fitted distribution QP, and the KL divergence between R P and QP is calculated to measure the similarity between the two distributions. The formula is as follows:

[0104]

[0105] The smaller the value of the KL divergence, the closer Rp is to the Gaussian distribution, and the more likely P is to be without void defects. However, if P has large-area void defects, the KL divergence is prone to a cancellation effect and its value will be relatively low. Therefore, the discrimination function of the coarse discrimination module is defined as:

[0106] G coarse (P) = k co ×D KL (R P ||Q P ) + b co

[0107]

[0108] where p Hf is the gray value corresponding to the maximum gray frequency of P, and p max is the maximum gray value of the pixels of P, μ is the gray mean value of P, and L is the upper limit of the gray value, i.e., 255. After obtaining the discriminant function value, if the discriminant function value is greater than or equal to the preset threshold, it is judged as a patch with a hole defect; otherwise, it is judged as a patch without a hole defect. Specifically:

[0109]

[0110] After the patch-level rough discrimination of the hole defect, the patches with hole defects have been preliminarily screened. However, for the patches with only tiny hole defects, the rough discrimination module is likely to misjudge them as patches without hole defects, resulting in accuracy loss. Therefore, we propose a patch-level fine discrimination algorithm for hole defects to perform secondary discrimination on the patches that have been judged as patches without hole defects by the rough discrimination module.

[0111] If P contains a hole defect, then the pixels with the maximum gray value are probably hole defect pixels. Let (N×l + 1)×(N×l + 1) be the size of the neighborhood of the pixel value, and the mean function of this neighborhood is M P (N), where N is the expansion factor of the neighborhood and l is the expansion step. To measure the gray difference between two adjacent neighborhoods, the weighted difference function can be defined as:

[0112]

[0113] m = [M P (N), -M P (N - 1)] T

[0114] n = [(N×l + 1) 2 , ((N - 1)×l + 1) 2 T

[0115] where T represents the transpose, and the difference function of D P (N) can be expressed as:

[0116] Δ(D P (N)) = D P (N) - D P (N - 1)

[0117] After that, the discriminant function of the fine discrimination module is defined as:

[0118] ​

[0119] Where |·| represents absolute value calculation, and Nd represents the maximum expansion coefficient. If the discriminant function value is greater than or equal to the set threshold, it is judged as a patch with void defects; otherwise, it is judged as a patch without void defects. Specifically:

[0120]

[0121] Where th fi represents the threshold of the fine discrimination module.

[0122] After passing through the coarse-fine patch-level void defect discrimination module, patches with void defects are obtained. Now, the pixel-level localization of the void defects in these patches is carried out. The traditional adaptive threshold algorithm fails to fully explore the gray distribution and has a long traversal time. Therefore, we propose an adaptive threshold algorithm to complete the pixel-level localization of void defects.

[0123] First, the per-pixel neighborhood mean of the image patch P to be detected is solved to obtain P n , and then the joint probability density distribution f(i, j) can be solved. The pixels of P are concentrated on the diagonal of the probability distribution map, and the other parts are mainly noise and edges. The weights of the void defect and transistor regions can be expressed as:

[0124]

[0125] Where (u, v) is the threshold of the patch to be segmented, and the specific value needs to be solved in an adaptive manner. Generally, the proportion of noise and edges is small, so it can be considered that ω void (u, V) + ω tran (u, v) approaches 1. After obtaining the total pixel proportion occupied by the void defect and transistor regions, the mean vectors of the two types can be obtained respectively:

[0126]

[0127] The overall mean vector within the region is:

[0128]

[0129] In order for the threshold segmentation to fully consider the aggregation of void defect and transistor-like pixels, it is necessary to reduce the intra-class absolute difference between pixels of the same type. The intra-class average absolute difference of pixels in the void defect and transistor regions can be expressed as:

[0130]

[0131] According to the obtained weights of the void defect and transistor-like pixels, the overall intra-class average absolute difference can be obtained as:

[0132] AMD intra (u, v) = ω tran (u, v) × d tran (u, v) + ω void (u, v) × d void (u, v)

[0133] And AMD intra The smaller (u, v) is, the better the intra-class aggregation of hole defects and transistor region pixels is.

[0134] To distinguish hole defects from transistor pixels, the method of solving the inter-class mean absolute difference is adopted:

[0135]

[0136] When AMD inter (u, v) is larger, the difference between hole defects and transistor region pixels is greater.

[0137] To fully consider the intra-class aggregation and inter-class difference between hole defects and transistor region pixels, and ensure that the sum of the two parts approaches 1, the threshold discrimination vector is set as:

[0138]

[0139] To narrow the range of (u, V) traversal and thus reduce the processing time, we propose a scheme to narrow the optional threshold. First, find the center of the maximum value of the cumulative frequency within the interval of f(i, j), specifically:

[0140] kpeak = argmaxF(k)

[0141]

[0142] where δ is the size of the window. After solving kpeak, it can be used for subsequent optimization by solving the reference point, and the reference point can be expressed as:

[0143]

[0144] s.t. k peak < k < L

[0145] where λ represents the search stop condition and γ represents the correction factor. After that, the optimal threshold can be obtained according to the interval where the reference point k ref is located, and the segmentation threshold (u opt , v opt ) can be solved through the decision function, specifically:

[0146] (uopt , v opt ) = arg minθ(u, v)

[0147] s.t. (k ref - δ) ≤ u, v ≤ (k ref + δ)

[0148] Through the calculation of the threshold, the final pixel-level localization map of void defects can be expressed as:

[0149]

[0150] where P(x, y) and P n (x, y) represent the gray values of P and P n at (x, y) respectively.

[0151] After detecting the transistor region and the void defect region, the proportion of void defects can be calculated, specifically as follows:

[0152]

[0153] where S void and S tran represent the areas of the transistor region and the void defect region respectively.

[0154] This application first proposes an integrated algorithm framework for calculating the proportion of void defects inside MOSFETs, which is divided into three stages: transistor region detection, void defect detection, and calculation of the proportion of void defects. First, the four vertices of the transistor region are obtained through the vertex detection algorithm to detect the transistor region. Then, the transistor region is divided into different patches, and the patches containing void defects are screened out through a coarse-fine patch-level void defect discrimination framework. Finally, the void defects are located at the pixel level, and the proportion of void defects is calculated.

[0155] This application utilizes the neighborhood gray feature of the vertices of MOSFET transistors, designs an optimization function, and locates the vertices of the transistor region through iterative optimization to complete the detection of the transistor region.

[0156] This application also proposes a coarse-fine patch-level void defect discrimination framework. For the coarse / fine discrimination modules, discrimination functions are defined respectively to screen out the patches containing void defects for subsequent pixel-level localization of void defects.

[0157] This application also proposes an adaptive threshold algorithm for pixel-level localization of void defects. The interval cumulative frequency is used to narrow the threshold range, reduce the processing time, and fully exploit the gray feature to complete accurate pixel-level localization.

[0158] The MOSFET cavity defect detection framework proposed in this application avoids the problems of the deep learning algorithm that requires a large amount of manual pixel-level annotation and long training time, and greatly reduces the development cost of the cavity defect detection algorithm.

[0159] In summary, to improve the detection accuracy, we propose a vertex detection algorithm based on position perception to locate the vertices of the transistor region and thereby determine the area of this region. First, we propose an optimization function to obtain the positions of the vertices of the transistor region through iterative optimization. Since the gray-scale distribution of the transistor region in the X-ray image of the MOSFET is uneven, it is difficult for the global threshold algorithm to find a suitable threshold for pixel-level localization of cavity defects. We divide the transistor region into patches and screen out the patches containing cavity defects through a coarse-to-fine cavity defect discrimination module. Since the traditional threshold algorithm overly relies on gray-scale features, for the patches containing cavity defects, we propose an adaptive threshold segmentation algorithm to perform pixel-level localization of cavity defects. Finally, we calculate the proportion of cavity defects by using the areas of the obtained transistor region and cavity defect region.

[0160] Embodiment 3

[0161] This embodiment proposes an internal cavity defect detection system for a MOSFET to implement an internal cavity defect detection method for a MOSFET proposed in Embodiment 1.

[0162] The internal cavity defect detection system for the MOSFET includes:

[0163] An image acquisition module to acquire the X-ray image of the MOSFET;

[0164] A vertex detection module for detecting the vertex positions of the transistors in the X-ray image and determining the transistor region based on the vertex positions;

[0165] A cavity defect partition detection module for dividing the transistor region into several partitions, calculating the similarity between the partition gray-scale distribution and the fitted Gaussian distribution for each partition, and determining whether the similarity is less than a preset similarity threshold. If so, it is considered that the partition corresponding to the similarity contains cavity defects; otherwise, based on pixel gray-scale value calculation, find the pixel with the largest gray-scale value in the partition corresponding to the similarity; determine whether the pixel with the largest gray-scale value is a cavity defect pixel. If so, it is considered that this partition contains cavity defects, otherwise it is considered that this partition does not contain cavity defects;

[0166] A cavity defect localization module for localizing the cavity defects in the partitions containing cavity defects.

[0167] This embodiment provides a computer device, including a memory and a processor. Computer-readable instructions are stored in the memory. When the computer-readable instructions are executed by the processor, the processor is caused to execute the steps of the method for detecting internal cavity defects of the MOSFET described in Embodiment 1.

[0168] It can be understood that the internal cavity defect detection system and computer device of the MOSFET in this embodiment make improvements to the method of Embodiment 1. The optional items in Embodiment 1 above are equally applicable to this embodiment, so they will not be described repeatedly here.

[0169] Identical or similar reference numerals correspond to identical or similar components;

[0170] The terms used to describe the positional relationship in the drawings are for illustrative purposes only and should not be construed as a limitation on this embodiment;

[0171] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A method for detecting internal cavity defects of a MOSFET, characterized in that, It includes the following steps: Obtain the X-ray image of the MOSFET; Detect the vertex positions of the transistors in the X-ray image, and determine the transistor regions based on the vertex positions; Divide the transistor regions into several partitions. For each partition, calculate the similarity between the partition gray-scale distribution and the fitted Gaussian distribution, and determine whether the similarity is less than a preset similarity threshold. If so, it is considered that the partition corresponding to the similarity contains void defects; otherwise, based on the calculation of pixel gray-scale values, find the pixel with the largest gray-scale value within the partition corresponding to the similarity; determine whether the pixel with the largest gray-scale value is a void defect pixel. If so, it is considered that the partition contains void defects, otherwise it is considered that the partition does not contain void defects; Locate the void defects in the partitions containing void defects; Among them, when determining whether the pixel with the largest gray value is a hole defect pixel, calculate the maximum gray value difference in the neighborhood of two adjacent pixel values corresponding to the pixel with the largest gray value , if the maximum gray value difference exceeds a preset gray value difference threshold, then regard the pixel with the largest gray value as a hole defect pixel; otherwise, it is considered that there is no hole defect in the partition corresponding to the pixel with the largest gray value; Let the size of the first pixel value neighborhood of the two adjacent pixel value neighborhoods corresponding to the pixel with the maximum gray value be , and the size of the second pixel value neighborhood be . Then the expression of the maximum gray difference includes: In the formula, represents the partition where the pixel with the largest grayscale value is located, represents the partition the maximum grayscale difference value within, represents the neighborhood expansion coefficient, represents the step size of neighborhood expansion, represents the maximum neighborhood expansion coefficient, represents the absolute value operation, represents the transpose symbol, represents the mean function of the neighborhood of the first pixel value, represents the mean function of the neighborhood of the second pixel value.

2. The internal cavity defect detection method of the MOSFET according to claim 1, wherein The step of detecting the vertex positions of the transistors in the X-ray image includes: Use the sliding window technique to find the vertices of the transistor from the X-ray image, and obtain the rough positioning coordinates of the upper left vertex of the transistor , the rough positioning coordinates of the lower left vertex , the rough positioning coordinates of the upper right and the rough positioning coordinates of the lower right ; The sliding window centered on the rough positioning coordinates of the vertex of the transistor is divided into two parts. One part is , and the other part is . Among them, , when , , is the lower right 1 / 4 part of the sliding window . When , , is the upper right 1 / 4 part of the sliding window . When , , is the lower left 1 / 4 part of the sliding window . When , , is the upper left 1 / 4 part of the sliding window ; Based on and iteratively optimize the rough positioning coordinates of the vertices of the transistor to obtain the vertex position coordinates of the transistor , where , when , represents the position coordinates of the upper left vertex of the transistor, when , represents the position coordinates of the lower left vertex of the transistor, when , represents the position coordinates of the upper right vertex of the transistor, when , represents the position coordinates of the lower right vertex of the transistor; Vertex position coordinates of the transistor The calculation expression includes: In the formula, , and respectively represent , and 's variances, and respectively represent and 's means, represents the balance coefficient; Vertex position coordinates of the transistor The enclosed area is the transistor area mentioned above.

3. The internal cavity defect detection method of the MOSFET according to claim 1, wherein Before dividing the transistor regions into several partitions, perform preprocessing of mean filtering and adaptive histogram equalization on the image within the transistor regions to obtain the preprocessed transistor region image; Based on the preprocessed transistor region image, use linear space transformation to divide the transistor regions into several partitions based on gray-scale values, where the difference between the minimum gray-scale value and the maximum gray-scale value of the pixels within the same partition does not exceed a preset difference.

4. The internal cavity defect detection method of the MOSFET according to claim 1, characterized in that The calculation expression for calculating the similarity between the partition gray-scale distribution and the fitted Gaussian distribution for each partition includes: In the formula, represents any partition, represents the partition and the similarity to the fitted Gaussian distribution, represents the partition gray-scale distribution, represents the gray-scale distribution maximum likelihood fitting distribution, represents the proportionality coefficient, represents the smoothing factor, represents the partition gray-scale value corresponding to the maximum gray-scale frequency of the partition, represents the partition gray-scale mean of the partition, represents the absolute value operation.

5. The method for detecting internal cavity defects of a MOSFET according to any one of claims 1 to 4, characterized in that After locating the void defects in the partition with void defects, a pixel-level location map of the void defects is obtained , the location map The expression of includes: In the formula, represents the partition where the void defect pixel is located, represents the per-pixel neighborhood mean of partition , and respectively represent and 's gray values at coordinate , represents the abscissa of the segmentation threshold coordinate of partition , represents the ordinate of the segmentation threshold coordinate of partition , represents the abscissa of the boundary threshold coordinate of partition , represents the ordinate of the boundary threshold coordinate of partition , represents the size of the window for traversal, represents the set of positive integers, represents the maximum gray value that can be obtained within the partition, represents the joint probability density distribution of partition , and both represent 's random variables, represents the stop condition for the search, represents the correction factor; represents the preset gray value; represents the void defect threshold discrimination vector.

6. The internal cavity defect detection method of the MOSFET according to claim 5, characterized in that, The void defect threshold discrimination vector has an expression including: In the formula, represents the intra-class aggregation coefficient of the void defect and transistor region pixels, The smaller it is, the better the intra-class aggregation of the void defect and transistor region pixels; represents the inter-class difference coefficient between the void defect and transistor region pixels, The larger it is, the greater the difference between the void defect and transistor region pixels; represents the weight of the void defect region, represents the weight of the transistor region, represents the absolute value operation.

7. The internal cavity defect detection method of the MOSFET according to claim 6, wherein The intra-class aggregation coefficient of the hole defect and the transistor region-like pixels and the inter-class difference coefficient are expressed as follows: In the formula, The smaller it is, the better the intra-class aggregation of the void defect and the pixels in the transistor region; The larger it is, the greater the difference between the void defect and the pixels in the transistor region; Represents the average absolute difference within the class of pixels in the transistor region; Represents the average absolute difference within the class of pixels in the void defect region; and respectively represent The first and second elements of 8. An internal cavity defect detection system for a MOSFET, which is used to implement the internal cavity defect detection method for the MOSFET described in any one of claims 1 to 7, characterized in that, It includes: An image acquisition module that obtains the X-ray image of the MOSFET; A vertex detection module for detecting the vertex positions of the transistors in the X-ray image and determining the transistor regions based on the vertex positions; A void defect partition detection module for dividing the transistor regions into several partitions, calculating the similarity between the partition gray-scale distribution and the fitted Gaussian distribution for each partition, and determining whether the similarity is less than a preset similarity threshold. If so, it is considered that the partition corresponding to the similarity contains void defects; otherwise, based on the calculation of pixel gray-scale values, find the pixel with the largest gray-scale value within the partition corresponding to the similarity; determine whether the pixel with the largest gray-scale value is a void defect pixel. If so, it is considered that the partition contains void defects, otherwise it is considered that the partition does not contain void defects; A void defect location module that locates the void defects in the partitions containing void defects.

9. A computer device, comprising a memory and a processor, wherein computer-readable instructions are stored in the memory, characterized in that, When the computer-readable instructions are executed by the processor, the processor is caused to execute the steps of the method for detecting internal void defects of the MOSFET according to any one of claims 1 to 7.

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