IGBT (Insulated Gate Bipolar Translator) defect detection method and device based on gate voltage signal in opening process

Abstract

The invention provides an IGBT defect detection method and device based on a gate voltage signal in an opening process, and the method comprises the steps: obtaining a voltage waveform of a target stage during the actual work of an IGBT based on the gate voltage signal in the opening process of the IGBT; according to the voltage waveform of the target stage when the IGBT actually works, calculating to obtain the gate loop discharge time of the target stage when the IGBT actually works; and analyzing and judging whether the IGBT to be detected has gate and emitter loop defects or not according to the gate loop discharge time of the target stage during the actual work of the IGBT. According to the invention, the change of the discharge time of the gate loop is analyzed through the gate voltage waveform in the opening process of the IGBT, so that whether the IGBT has gate emitter loop defects is judged, and the detection efficiency is improved. When gate emitter loop defects exist in the IGBT, the number of packaging chips, specifically having the gate emitter loop defects, of the IGBT can be known by adopting the technical scheme of the invention, and quantitative detection can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to an IGBT defect detection method and device based on a gate voltage signal during a turn-on process. Background Art

[0002] Insulate-Gate Bipolar Transistor (IGBT) devices have the advantages of fast switching speed of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices and low conduction loss of bipolar devices. They are widely used in new energy converters, flexible DC transmission equipment, dynamic reactive power compensation equipment, etc. IGBT is a three-terminal device, including: gate, collector and emitter. However, in practical applications, it is difficult to detect the internal defect state of IGBT. Summary of the invention

[0003] The main purpose of the embodiments of the present invention is to provide an IGBT defect detection method and device based on the gate voltage signal of the turn-on process. By analyzing the gate current waveform of the IGBT turn-on process, the change of the gate circuit discharge time is analyzed to determine whether the IGBT has a gate-emitter circuit defect. The present invention has certain guiding significance for IGBT status detection.

[0004] In order to achieve the above object, an embodiment of the present invention provides an IGBT defect state detection method, comprising:

[0005] Collecting gate voltage signals of the IGBT turn-on process in the commutation circuit to be tested; the commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor; in the commutation circuit, the IGBT and the freewheeling diode are connected in series, the freewheeling diode and the load inductor are connected in parallel, the DC bus capacitor is connected in parallel with the IGBT and the freewheeling diode, the gate turn-on resistor and the gate turn-on resistor are connected in parallel, and the gate turn-on resistor and the gate turn-on resistor are connected in series with the IGBT respectively; a plurality of chips are packaged inside the IGBT, and each chip includes a gate-emitter capacitor, a Miller capacitor, a collector-emitter capacitor, a collector-side parasitic inductance, an emitter-side parasitic inductance, and a gate-side parasitic inductance; the second end of the collector-side parasitic inductance of each chip is connected to the collector of the IGBT, the first end of the emitter-side parasitic inductance of each chip is connected to the emitter of the IGBT, and the first end of the gate-side parasitic inductance of each chip is connected to the gate of the IGBT;

[0006] According to the gate voltage signal of the IGBT turn-on process, drawing a voltage waveform of a target stage when the IGBT is actually working;

[0007] Based on the voltage waveform of the target stage when the IGBT is actually working, the gate circuit discharge time of the target stage when the IGBT is actually working is calculated;

[0008] By analyzing the gate circuit discharge time of the target phase when the IGBT is actually working, it is determined whether there is a gate-emitter circuit defect in the IGBT in the current circuit to be tested.

[0009] In one embodiment, the calculating of the gate circuit discharge time in the target stage when the IGBT is actually working based on the voltage waveform in the target stage when the IGBT is actually working includes:

[0010] According to the voltage waveform of the target stage when the IGBT is actually working, obtaining the gate voltage at each moment of the target stage when the IGBT is actually working;

[0011] Based on the gate voltage at each moment of the target stage when the IGBT is actually working, the gate loop discharge time of the target stage when the IGBT is actually working is obtained.

[0012] In one embodiment, the gate circuit discharge time in the target phase when the IGBT is actually working is calculated by the following formula:

[0013]

[0014] Among them, t A is the gate circuit discharge time of the target stage when the IGBT is actually working, n is the total number of IGBT packaged chips, τ0 is the gate emitter circuit time of a single chip, U G,on To turn on the control voltage for the drive power supply, U T is the IGBT gate threshold voltage, U G,off Shuts down the control voltage for the driver power supply.

[0015] In one embodiment, the single chip gate-emitter loop time τ0 is calculated by the following formula:

[0016] τ0=R G,on C GE ;

[0017] Among them, R G,on is the gate turn-on resistance, C GE is the gate-emitter capacitance.

[0018] In one embodiment, the step of analyzing and judging whether the IGBT to be tested has a gate-emitter loop defect by the gate loop discharge time in the target phase when the IGBT is actually working includes:

[0019] When the gate loop discharge time in the target phase when the IGBT is actually working is less than a threshold value, the IGBT to be tested has a gate-emitter loop defect.

[0020] In one embodiment, the threshold is the gate circuit discharge time in the target phase when the IGBT to be tested is working normally.

[0021] In one embodiment, the method further includes: if the IGBT to be tested has a gate-emitter loop defect, the number of chips with gate-emitter loop defects in the IGBT is calculated based on the gate loop discharge time of the target stage when the IGBT is actually working.

[0022] In one embodiment, the number m of chips with gate-emitter loop defects in the IGBT is calculated by the following formula:

[0023]

[0024] Where n is the total number of IGBT packaged chips, t A is the gate circuit discharge time in the target phase when the IGBT is actually working, t′ A It is the gate circuit discharge time in the target phase when the IGBT is working normally.

[0025] The embodiment of the present invention further provides an IGBT defect detection device based on a gate voltage signal during a turn-on process, comprising:

[0026] The acquisition module is used to acquire the gate voltage signal of the IGBT turn-on process in the commutation circuit to be tested; the commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor; in the commutation circuit, the IGBT and the freewheeling diode are connected in series, the freewheeling diode and the load inductor are connected in parallel, the DC bus capacitor is connected in parallel with the IGBT and the freewheeling diode, the gate turn-on resistor and the gate turn-on resistor are connected in parallel, and the gate turn-on resistor and the gate turn-on resistor are respectively connected in series with the IGBT; a plurality of chips are packaged inside the IGBT, and each chip includes a gate-emitter capacitor, a Miller capacitor, a collector-emitter capacitor, a collector-side parasitic inductance, an emitter-side parasitic inductance, and a gate-side parasitic inductance; the second end of the collector-side parasitic inductance of each chip is connected to the collector of the IGBT, the first end of the emitter-side parasitic inductance of each chip is connected to the emitter of the IGBT, and the first end of the gate-side parasitic inductance of each chip is connected to the gate of the IGBT;

[0027] A drawing module, used for drawing a voltage waveform of a target stage when the IGBT is actually working according to a gate voltage signal of the IGBT turn-on process;

[0028] A calculation module, configured to calculate a gate circuit discharge time in a target stage when the IGBT is actually working, based on a voltage waveform in a target stage when the IGBT is actually working;

[0029] The judgment module is used to judge whether there is a gate-emitter loop defect of the IGBT in the current loop to be tested by analyzing the gate loop discharge time of the target stage when the IGBT is actually working.

[0030] An embodiment of the present invention further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor implements the steps of any of the above methods when executing the computer program.

[0031] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of any of the above methods when executed by a processor.

[0032] An embodiment of the present invention further provides a computer program product, wherein the computer program product includes a computer program, and when the computer program is executed by a processor, any of the above methods is implemented.

[0033] The embodiment of the present invention provides an IGBT defect detection method and device based on the gate voltage signal of the turn-on process. Based on the gate voltage signal of the IGBT turn-on process, the voltage waveform of the target stage when the IGBT is actually working is obtained; according to the voltage waveform of the target stage when the IGBT is actually working, the gate circuit discharge time of the target stage when the IGBT is actually working is calculated; according to the gate circuit discharge time of the target stage when the IGBT is actually working, it is analyzed and determined whether the IGBT to be tested has a gate-emitter circuit defect. Compared with the prior art, the present invention analyzes the change of the gate circuit discharge time through the gate voltage waveform of the IGBT turn-on process, and then determines whether the IGBT has a gate-emitter circuit defect, which can easily detect the defect state of the IGBT and improve the detection efficiency. When the IGBT has a gate-emitter circuit defect, the technical solution of the present invention can also know the number of packaged chips with gate-emitter circuit defects in the IGBT, and quantitative detection can be achieved, which has certain guiding significance for IGBT state detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1is a schematic diagram of a commutation circuit structure provided by an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of the internal structure of an IGBT provided by an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of an IGBT turn-on transient process provided by an embodiment of the present invention;

[0038] Figure 4 It is a flow chart of an IGBT defect detection method based on a gate voltage signal during a turn-on process provided by an embodiment of the present invention;

[0039] Figure 5 It is a structural schematic diagram of an IGBT defect detection device based on a gate voltage signal during a turn-on process provided by an embodiment of the present invention;

[0040] Figure 6 It is a structural block diagram of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] Those skilled in the art will appreciate that the embodiments of the present invention may be implemented as a system, device, apparatus, method or computer program product. Therefore, the present disclosure may be specifically implemented in the following forms, namely: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0043] IGBT has been widely used in new energy converters, flexible direct current transmission equipment, dynamic reactive power compensation equipment and other occasions. However, in practical applications, it is difficult to detect the internal defect state of IGBT. In order to solve the problems in the prior art, the present invention analyzes the change of gate loop discharge time through the gate voltage waveform of the IGBT turn-on process, and then determines whether the IGBT has a gate-emitter loop defect, which can easily detect the defect state of the IGBT and improve the detection efficiency. When there is a gate-emitter loop defect in the IGBT, the technical solution of the present invention can also be used to know the specific number of packaged chips with gate-emitter loop defects in the IGBT, which has certain guiding significance for IGBT state detection.

[0044] In order to facilitate understanding of the technical solution provided by this application, the research background of the technical solution of this application is briefly described below.

[0045] Figure 1 It is a schematic diagram of a commutation circuit structure provided by an embodiment of the present invention. Figure 1 It is the circuit structure model of power electronic commutation device. Most commutation devices (such as dynamic reactive power compensation equipment, flexible DC equipment, wind power converter, traction converter, etc.) can be used. Figure 1 The topology shown is analyzed. Figure 1 The commutation circuit shown mainly includes the DC bus capacitor C0, the insulated gate bipolar transistor IGBT (gate-emitter capacitor C GE 、Miller capacitance C GC , Collector-emitter capacitance C CE , G is the gate, C is the collector, E is the emitter), freewheeling diode FWD and other structures, the reference direction of voltage and current is already in Figure 1 Winning bid. Figure 1 Medium load is the load inductance, L s,1 is the parasitic inductance of the IGBT circuit, L s,2 is the parasitic inductance of the FWD loop; u chip,F is the voltage of the chip inside the freewheeling diode, u s,F is the parasitic inductance voltage inside the freewheeling diode package, u F is the voltage across the freewheeling diode, u s,2 is the parasitic inductance of the FWD loop L s,2 Voltage; u GE is the gate voltage of IGBT, u CE is the collector-emitter voltage of the IGBT, u chip,CE is the collector-emitter voltage of the IGBT internal chip, and the collector-emitter voltage u during the turn-off delay process CE =u chip,CE ,u CG is the collector-gate voltage of the IGBT; i C is the collector current, i G is the gate current, i GE For flow through C GE The current, i GC For flow through C GC The current, I L is the current flowing through the load inductor L load The current. L s,F and L s,CE They represent the parasitic parameters of the FWD and IGBT internal packaging main circuits, respectively. s,F Including the parasitic inductance of the FWD anode and cathode sides, L s,CE Including L s,C , L s,ETwo parts, L s,C is the parasitic inductance on the collector side of the IGBT, L s,E is the parasitic inductance on the emitter side of the IGBT; in addition, R G,on is the gate turn-on resistance, R G,off is the gate turn-off resistance, U G,on To turn on the control voltage for the drive power supply, U G,off The present invention is mainly used to detect Figure 1 Whether there are defects in the gate-emitter loop (GE) in the device, wherein the gate-emitter loop defects include gate defects and emitter defects.

[0046] Figure 2 Schematic diagram of the internal structure of an IGBT provided by an embodiment of the present invention. The insulated gate bipolar transistor IGBT includes a gate-emitter capacitor C GE 、Miller capacitance C GC , Collector-emitter capacitance C CE , G is the gate, C is the collector, E is the emitter, L s,C is the collector side parasitic inductance, L s,E is the parasitic inductance on the emitter side, L s,G is the parasitic inductance on the gate side. In the figure, n is the total number of IGBT internal package chips, and each IGBT internal package chip includes a gate-emitter capacitor C GE 、Miller capacitance C GC , Collector-emitter capacitance C CE , G is the gate, C is the collector, E is the emitter, and the collector side parasitic inductance L s,C , emitter side parasitic inductance L s,E , gate side parasitic inductance L s,G , the collector side parasitic inductance L of each IGBT internal package chip s,C The second end is connected to the IGBT collector C. The emitter side parasitic inductance L of each IGBT internal package chip s,E The first end is connected to the IGBT emitter E, and the gate side parasitic inductance L of each IGBT internal package chip s,G The first end is connected to the IGBT gate G. IGBT packaging defects can be divided into three categories: gate defects ( Figure 2 Marking ①), collector defect ( Figure 2 Marking②), emitter defect ( Figure 2 The present invention is mainly used to detect whether ① and ③ have gate-emitter loop defects, that is, whether the IGBT has gate-emitter loop defects.

[0047] Figure 3 The figure is a schematic diagram of an IGBT turn-on transient process provided by an embodiment of the present invention. The stage t0 to t1 in the figure is the target stage of the present invention.

[0048] In order to achieve the above object, an embodiment of the present invention provides an IGBT defect detection method based on a gate voltage signal during a turn-on process. Figure 4 This is a flow chart of an IGBT defect detection method based on a gate voltage signal during a turn-on process provided by an embodiment of the present invention, and the main steps include:

[0049] S1. Collect the gate voltage signal of the IGBT turn-on process in the commutation circuit to be tested; the commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor; in the commutation circuit, the IGBT and the freewheeling diode are connected in series, the freewheeling diode and the load inductor are connected in parallel, the DC bus capacitor is connected in parallel with the IGBT and the freewheeling diode, the gate turn-on resistor and the gate turn-on resistor are connected in parallel, and the gate turn-on resistor and the gate turn-on resistor are respectively connected in series with the IGBT; a plurality of chips are packaged inside the IGBT, and each chip includes a gate-emitter capacitor, a Miller capacitor, a collector-emitter capacitor, a collector-side parasitic inductance, an emitter-side parasitic inductance, and a gate-side parasitic inductance; the second end of the collector-side parasitic inductance of each chip is connected to the collector of the IGBT, the first end of the emitter-side parasitic inductance of each chip is connected to the emitter of the IGBT, and the first end of the gate-side parasitic inductance of each chip is connected to the gate of the IGBT.

[0050] Specifically, the present invention can collect the gate voltage signal of the IGBT turn-on process to be tested through the voltage signal detector. In the commutation circuit, the insulated gate bipolar transistor IGBT and the freewheeling diode FWD are connected in series, and the freewheeling diode FWD and the load inductor L load The DC bus capacitor C0 is connected in parallel with the insulated gate bipolar transistor IGBT and the freewheeling diode FWD, the gate turn-on resistor and the gate turn-on resistor are connected in parallel, and the gate turn-on resistor and the gate turn-on resistor are connected in series with the IGBT respectively. The collector of the insulated gate bipolar transistor IGBT is connected to the parasitic inductance L on the collector side of the IGBT s,C First terminal (positive pole), parasitic inductance L on the collector side of IGBT s,C The second end (negative pole) is connected to the FWD loop parasitic inductance L s,2 The first terminal (positive electrode), load inductance L load The second end (negative pole), FWD loop parasitic inductance L s,2 The second end (negative pole) is connected to the FWD parasitic inductance L s,F First terminal (positive), FWD parasitic inductance L s,F The second end (negative pole) is connected to the first end (positive pole) of FWD, and the second end (negative pole) of FWD is connected to the load inductor L load The first terminal (positive pole) and the IGBT loop parasitic inductance L s,1 First terminal (positive pole), IGBT loop parasitic inductance L s,1The second end (negative pole) is connected to the first end (positive pole) of the DC bus capacitor C0, and the second end (negative pole) of the DC bus capacitor C0 is connected to the parasitic inductance L on the emitter side of the IGBT. s,E The first terminal (positive electrode), the gate turn-on resistor R G,on The second terminal (negative electrode), the gate turn-off resistor R G,off The second end (negative pole), IGBT emitter side parasitic inductance L s,E The second end (negative electrode) is connected to the IGBT emitter, and the IGBT gate is connected to the gate turn-on resistor R G,on The first terminal (positive electrode), the gate turn-off resistor R G,off First terminal (positive terminal).

[0051] S2. Draw the target stage voltage waveform when the IGBT is actually working according to the gate voltage signal of the IGBT turn-on process;

[0052] Specifically, the present invention can collect the gate voltage signal of the IGBT turn-on process to be tested through a voltage signal detector, and then transmit the voltage signal to the waveform drawing software, or directly capture the voltage signal and display the voltage waveform through an oscilloscope or other electronic measuring instrument.

[0053] S3. Based on the voltage waveform of the target stage when the IGBT is actually working, the gate circuit discharge time of the target stage when the IGBT is actually working is calculated;

[0054] In one embodiment, the calculating of the gate circuit discharge time in the target stage when the IGBT is actually working according to the voltage waveform in the target stage when the IGBT is actually working comprises:

[0055] S301. Obtaining the gate voltage at each moment of the target phase when the IGBT is actually working from the voltage waveform of the target phase when the IGBT is actually working;

[0056] S302. Calculate the gate circuit discharge time of the target stage when the IGBT is actually working by using the gate voltage at each moment of the target stage when the IGBT is actually working.

[0057] In one embodiment, the gate circuit discharge time of the target stage when the IGBT is actually working can be obtained by calculating the gate voltage at each moment of the target stage when the IGBT is actually working in the voltage waveform diagram of the target stage when the IGBT is actually working. The gate circuit discharge time of the target stage when the IGBT is actually working is calculated by the following formula:

[0058]

[0059] Among them, t Ais the gate circuit discharge time of the target stage when the IGBT is actually working, n is the total number of IGBT packaged chips, τ0 is the gate emitter circuit time of a single chip, U G,on To turn on the control voltage for the drive power supply, U T is the IGBT gate threshold voltage, U G,off Shuts down the control voltage for the driver power supply.

[0060] Specifically, during the IGBT turn-on transient, the gate-emitter capacitance (C GE ) and Miller capacitance (C GC ) The direction of current is Figure 1 shown.

[0061] 1) For C GE , if the voltage reference direction is G→E, then the process C GE Charging, gate-emitter voltage u GE rise.

[0062] 2) For C CG , if the voltage reference direction is C→G, then the process C CG Discharge, u CG and u CE reduce.

[0063] Gate current i G There is the following relationship between Q G Discharge amount for gate of a single chip):

[0064]

[0065] If the collector-gate voltage u is taken into account CG ≈gate-emitter voltage u CE ,exist:

[0066]

[0067] C GE is a constant (not changing with u GE changes with changes), and C CG is a variable (with u CG Or u CE Considering the period from t0 to t1, u GE changes, and u CG Or u CE does not change, so C CG No changes occur during the process.

[0068] Before the collector current starts to rise (t0-t1), the voltage and capacitance change as shown in Table 1:

[0069] Table 1

[0070] <![CDATA[u GE ]]> <![CDATA[C GE ]]> <![CDATA[u CG ]]> <![CDATA[C CG ]]> <![CDATA[t0 to t1 stage]]> change No change No change No change

[0071] Considering the changes in voltage and capacitance at different stages, i G It can be expressed as:

[0072]

[0073] In summary, the gate voltage u in the t0~t1 period GE The waveform can be used to analyze gate emitter (GE) loop defects, including gate defects ( Figure 2 Marking ①), emitter defect ( Figure 2 In another embodiment, the gate voltage u in the period t0 to t1 can also be GE The gate current i in the period t0 to t1 is calculated. G , and then through the gate current i G By calculating, the amount of charge charged on the gate capacitance during the target phase when the IGBT is actually working can be obtained.

[0074] The gate-emitter loop time τ0 of a single chip can be calculated by the following formula:

[0075] τ0=R G,on C GE .

[0076] In the formula, R G,on is the gate turn-on resistance, C GE is the gate-emitter capacitance.

[0077] The overall gate loop time constant τ can be calculated using the following formula:

[0078] τ=n×τ0=R G,on ×nC GE .

[0079] In the formula, R G,on is the gate turn-on resistance, C GE is the gate-emitter capacitance, and n is the total number of IGBT packaged chips.

[0080] During the process of t0~t, the gate discharges and satisfies the following relationship:

[0081]

[0082] Where n is the total number of IGBT packaged chips, u GE is the gate voltage at each moment of the target phase when the IGBT is actually working, U G,on To turn on the control voltage for the drive power supply, U G,off Shuts down the control voltage for the driver power supply.

[0083] If the gate (G) or emitter (E) contact defect occurs in the gate-emitter loop, the gate loop discharge time constant will become smaller.

[0084] In one embodiment, the gate voltage u GE From U G,on Raised to U T The gate circuit discharge time during the process (i.e. t0~t1) is calculated by the following formula:

[0085]

[0086] Among them, t A is the gate circuit discharge time of the target stage when the IGBT is actually working, n is the total number of IGBT packaged chips, τ0 is the gate emitter circuit time of a single chip, U G,on is the driving power supply opening control voltage, that is, the gate voltage corresponding to the starting time t0 of the target phase, U T is the IGBT gate threshold voltage, that is, the gate voltage corresponding to the end time t1 of the target phase, U G,off Shuts down the control voltage for the driver power supply.

[0087] S4. Determine whether there is a gate-emitter loop defect in the IGBT in the commutation loop to be tested by analyzing the gate loop discharge time in the target phase when the IGBT is actually working.

[0088] In one embodiment, the step of analyzing and judging whether the IGBT to be tested has a gate-emitter loop defect by the gate loop discharge time in the target phase when the IGBT is actually working includes:

[0089] When the gate loop discharge time in the target phase when the IGBT is actually working is less than a threshold value, the IGBT to be tested has a gate-emitter loop defect.

[0090] In one embodiment, the threshold is the gate circuit discharge time of the target phase when the IGBT under test is working normally. The gate circuit discharge time of the target phase when the IGBT is working normally can also be calculated by referring to the above method, which will not be repeated here.

[0091] In one embodiment, the method further includes: S5. If the IGBT to be tested has a gate-emitter loop defect, the number of chips with gate-emitter loop defects in the IGBT is calculated based on the gate loop discharge time of the target stage when the IGBT is actually working.

[0092] In one embodiment, the number m of chips with gate-emitter loop defects in the IGBT is calculated by the following formula:

[0093]

[0094] Where n is the total number of IGBT packaged chips, tA is the gate circuit discharge time in the target phase when the IGBT is actually working, and t′ A It is the gate circuit discharge time in the target phase when the IGBT is working normally.

[0095] Specifically, at a known gate voltage u GE From U G,on (the gate voltage corresponding to the starting time t0 of the target phase) increases to U T When the gate circuit discharge time of the process (gate voltage corresponding to the end time t1 of the target stage) changes, the number of chips with gate-emitter circuit defects in the IGBT can be calculated by the above formula.

[0096] Specifically, when there are m IGBT chip packaging structures with abnormal gate or emitter contacts, the gate loop time T′ is calculated by the following formula:

[0097] T′=(nm)×τ0=R G，on ×(nm)C GE .

[0098] In the above case, the gate voltage u GE From U G,on Raised to U T The process time (i.e. the process time from t0 to t1) t A,fault Calculated by the following formula:

[0099]

[0100] Where n is the total number of IGBT packaged chips, τ0 is the gate-emitter loop time of a single chip, and U G,on is the driving power supply opening control voltage, that is, the gate voltage corresponding to the starting time t0 of the target phase, U T is the IGBT gate threshold voltage, that is, the gate voltage corresponding to the end time t1 of the target phase, U G,off Shuts down the control voltage for the driver power supply.

[0101] From the above formula, we can see that Δt A =t A,fault —t A <0;

[0102] Gate voltage u GE From U G,on Raised to U T The process time (i.e., the time from t0 to t1) is reduced, indicating that a gate-emitter (GE) loop defect occurs in the IGBT.

[0103] In a specific embodiment, taking a traction converter as an example, an IGBT defect detection method based on a gate voltage signal of a turn-on process provided by the present invention is used to detect whether there is a defect in the gate-emitter loop (GE) inside the IGBT of the traction converter. First, an oscilloscope is used to collect the gate voltage signal of the IGBT turn-on process and display the voltage waveform of the target stage when the IGBT is actually working. Then, the voltage waveform of the target stage when the IGBT is actually working is transmitted to an analyzer for analysis and processing. The analyzer obtains the gate voltage of the target stage when the IGBT is actually working from the voltage waveform of the target stage when the IGBT is actually working. The gate circuit discharge time of the target stage when the IGBT is actually working is calculated by the gate voltage of the target stage when the IGBT is actually working. When the gate circuit discharge time of the target stage when the IGBT is actually working is less than the gate circuit discharge time of the target stage when the current IGBT is working normally, the current IGBT has a gate-emitter loop defect. The present application can improve the defect detection efficiency of the IGBT. Furthermore, if the current IGBT has a gate-emitter loop defect, the number of defective chips in the IGBT can also be calculated based on the gate circuit discharge time of the target stage. The analyzer can detect whether the current IGBT has gate-emitter loop defects in real time based on the voltage waveform of the target phase when the IGBT is actually working, and issue an early warning to remind the operation and maintenance personnel to perform maintenance, thereby improving the efficiency of later maintenance and reducing the operation and maintenance costs. At the same time, it can also display how many packaged chips in the IGBT are faulty, which can further improve the operation and maintenance efficiency.

[0104] Compared with the prior art, the present invention analyzes the change of gate circuit discharge time through the gate voltage waveform of the IGBT turn-on process, and then determines whether the IGBT has a gate-emitter circuit defect, which can easily detect the defect state of the IGBT and improve the detection efficiency. In particular, when the IGBT has a gate-emitter circuit defect, the technical solution of the present invention can also know the number of packaged chips with gate-emitter circuit defects in the IGBT, and quantitative detection can be achieved, which has certain guiding significance for IGBT state detection.

[0105] Based on the same inventive concept, an embodiment of the present invention further provides an IGBT defect state detection device. Figure 5 1 is a schematic diagram of a structure of an IGBT defect state detection device provided by an embodiment of the present invention, comprising:

[0106] The acquisition module is used to acquire the gate voltage signal of the IGBT turn-on process in the commutation circuit to be tested; the commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor; in the commutation circuit, the IGBT and the freewheeling diode are connected in series, the freewheeling diode and the load inductor are connected in parallel, the DC bus capacitor is connected in parallel with the IGBT and the freewheeling diode, the gate turn-on resistor and the gate turn-on resistor are connected in parallel, and the gate turn-on resistor and the gate turn-on resistor are respectively connected in series with the IGBT; a plurality of chips are packaged inside the IGBT, and each chip includes a gate-emitter capacitor, a Miller capacitor, a collector-emitter capacitor, a collector-side parasitic inductance, an emitter-side parasitic inductance, and a gate-side parasitic inductance; the second end of the collector-side parasitic inductance of each chip is connected to the collector of the IGBT, the first end of the emitter-side parasitic inductance of each chip is connected to the emitter of the IGBT, and the first end of the gate-side parasitic inductance of each chip is connected to the gate of the IGBT;

[0107] A drawing module, used for drawing a voltage waveform of a target stage when the IGBT is actually working according to a gate voltage signal of the IGBT turn-on process;

[0108] A calculation module, configured to calculate a gate circuit discharge time in a target stage when the IGBT is actually working, based on a voltage waveform in a target stage when the IGBT is actually working;

[0109] The computing module includes a first unit and a second unit;

[0110] The first unit is used to obtain the gate voltage at each moment of the target stage when the IGBT is actually working from the voltage waveform of the target stage when the IGBT is actually working;

[0111] The second unit is used to calculate the gate circuit discharge time of the target stage when the IGBT is actually working according to the gate voltage at each moment of the target stage when the IGBT is actually working.

[0112] In one embodiment, the gate circuit discharge time t A Calculated by the following formula:

[0113]

[0114] Where n is the total number of IGBT packaged chips, τ0 is the gate-emitter loop time of a single chip, and U G,on To turn on the control voltage for the drive power supply, U T is the IGBT gate threshold voltage, U G,off Shuts down the control voltage for the driver power supply.

[0115] The judgment module is used to judge whether there is a gate-emitter loop defect of the IGBT in the current loop to be tested by analyzing the gate loop discharge time of the target stage when the IGBT is actually working.

[0116] The judgment module includes a third unit and a fourth unit;

[0117] The third unit is used to obtain a threshold value; the threshold value is the gate circuit discharge time in the target stage when the IGBT to be tested works normally.

[0118] The fourth unit is used to compare the gate loop discharge time of the target stage when the IGBT is actually working with the threshold value obtained by the third unit. When the gate loop discharge time of the target stage when the IGBT is actually working is less than the threshold value, it is considered that the IGBT to be tested has a gate-emitter loop defect.

[0119] The quantitative detection module is used to calculate the number of chips with gate-emitter loop defects in the IGBT according to the gate loop discharge time of the target stage when the judgment result sent by the judgment module is that the IGBT to be tested has a gate-emitter loop defect.

[0120] In one embodiment, the number m of chips with gate-emitter loop defects in the IGBT is calculated by the following formula:

[0121]

[0122] Where n is the total number of IGBT packaged chips, t A is the gate circuit discharge time in the target phase when the IGBT is actually working, t′ A It is the gate circuit discharge time in the target phase when the IGBT is working normally.

[0123] The remaining embodiments of the device can be implemented in one-to-one correspondence with the aforementioned method embodiments, and will not be described in detail here.

[0124] The embodiment of the present invention also provides a computer device, such as Figure 6 The figure is a structural block diagram of a computer device provided by an embodiment of the present invention, including a memory, a processor, and a computer program stored in the memory and running on the processor, and the processor implements any of the above methods when executing the computer program.

[0125] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements any of the above methods when executed by a processor.

[0126] An embodiment of the present invention further provides a computer program product, wherein the computer program product includes a computer program, and when the computer program is executed by a processor, any of the above methods is implemented.

[0127] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0128] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0129] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0130] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0131] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An IGBT defect detection method based on a gate voltage signal during a turn-on process, characterized in that: include: Collecting gate voltage signals of the IGBT turn-on process in the commutation circuit to be tested; the commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor; in the commutation circuit, the IGBT and the freewheeling diode are connected in series, the freewheeling diode and the load inductor are connected in parallel, the DC bus capacitor is connected in parallel with the IGBT and the freewheeling diode, the gate turn-on resistor and the gate turn-on resistor are connected in parallel, and the gate turn-on resistor and the gate turn-on resistor are connected in series with the IGBT respectively; a plurality of chips are packaged inside the IGBT, and each chip includes a gate-emitter capacitor, a Miller capacitor, a collector-emitter capacitor, a collector-side parasitic inductance, an emitter-side parasitic inductance, and a gate-side parasitic inductance; the second end of the collector-side parasitic inductance of each chip is connected to the collector of the IGBT, the first end of the emitter-side parasitic inductance of each chip is connected to the emitter of the IGBT, and the first end of the gate-side parasitic inductance of each chip is connected to the gate of the IGBT; According to the gate voltage signal of the IGBT turn-on process, drawing a voltage waveform of a target stage when the IGBT is actually working; Based on the voltage waveform of the target stage when the IGBT is actually working, the gate circuit discharge time of the target stage when the IGBT is actually working is calculated; By analyzing the gate circuit discharge time of the target phase when the IGBT is actually working, it is determined whether the IGBT in the commutation circuit to be tested has a gate-emitter circuit defect.

2. The method according to claim 1, characterized in that: The calculating of the gate circuit discharge time of the target stage when the IGBT is actually working based on the voltage waveform of the target stage when the IGBT is actually working includes: According to the voltage waveform of the target stage when the IGBT is actually working, obtaining the gate voltage at each moment of the target stage when the IGBT is actually working; Based on the gate voltage at each moment of the target stage when the IGBT is actually working, the gate loop discharge time of the target stage when the IGBT is actually working is obtained.

3. The method according to claim 2, characterized in that: The gate circuit discharge time of the target phase when the IGBT is actually working is calculated by the following formula: Among them, t A is the gate circuit discharge time of the target stage when the IGBT is actually working, n is the total number of IGBT packaged chips, τ0 is the gate emitter circuit time of a single chip, U G,on To turn on the control voltage for the drive power supply, U T is the IGBT gate threshold voltage, U G,off Shuts down the control voltage for the driver power supply.

4. The method according to claim 3, characterized in that: The single chip gate emitter loop time τ0 is calculated by the following formula: τ0=R G,on C GE ; Among them, R G,on is the gate turn-on resistance, C GE is the gate-emitter capacitance.

5. The method according to any one of claims 1 to 4, characterized in that: The step of analyzing and judging whether the IGBT to be tested has a gate-emitter loop defect by the gate loop discharge time in the target phase when the IGBT is actually working includes: When the gate loop discharge time in the target phase when the IGBT is actually working is less than a threshold value, the IGBT to be tested has a gate-emitter loop defect.

6. The method according to claim 5, characterized in that: The threshold value is the gate circuit discharge time in the target phase when the IGBT to be tested is working normally.

7. The method according to claim 5, characterized in that: The method also includes: if the IGBT to be tested has a gate-emitter loop defect, then according to the gate loop discharge time of the target stage when the IGBT is actually working, the number of chips with gate-emitter loop defects in the IGBT is calculated.

8. The method according to claim 7, characterized in that: The number of chips with gate-emitter loop defects in the IGBT is calculated by the following formula: Where m is the number of IGBT chips with gate-emitter loop defects, n is the total number of IGBT packaged chips, and t A is the gate circuit discharge time in the target phase when the IGBT is actually working, t′ A It is the gate circuit discharge time in the target phase when the IGBT is working normally.

9. An IGBT defect detection device based on a gate voltage signal during a turn-on process, characterized in that: include: The acquisition module is used to acquire the gate voltage signal of the IGBT turn-on process in the commutation circuit to be tested; the commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor; in the commutation circuit, the IGBT and the freewheeling diode are connected in series, the freewheeling diode and the load inductor are connected in parallel, the DC bus capacitor is connected in parallel with the IGBT and the freewheeling diode, the gate turn-on resistor and the gate turn-on resistor are connected in parallel, and the gate turn-on resistor and the gate turn-on resistor are respectively connected in series with the IGBT; a plurality of chips are packaged inside the IGBT, and each chip includes a gate-emitter capacitor, a Miller capacitor, a collector-emitter capacitor, a collector-side parasitic inductance, an emitter-side parasitic inductance, and a gate-side parasitic inductance; the second end of the collector-side parasitic inductance of each chip is connected to the collector of the IGBT, the first end of the emitter-side parasitic inductance of each chip is connected to the emitter of the IGBT, and the first end of the gate-side parasitic inductance of each chip is connected to the gate of the IGBT; A drawing module, used for drawing a voltage waveform of a target stage when the IGBT is actually working according to a gate voltage signal of the IGBT turn-on process; A calculation module, configured to calculate a gate circuit discharge time in a target stage when the IGBT is actually working, based on a voltage waveform in a target stage when the IGBT is actually working; The judgment module is used to judge whether there is a gate-emitter loop defect of the IGBT in the commutation loop to be tested by analyzing the gate loop discharge time of the target stage when the IGBT is actually working.

10. A computer device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 8 are implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

12. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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