Control chip of underwater sonar system and underwater sonar device

Abstract

The invention discloses a control chip of an underwater sonar system and underwater sonar equipment, the sonar system comprises a plurality of receiving array elements, the control chip comprises a processor system core and a programmable logic core, and the processor system core is used for controlling the programmable logic core to operate; the programmable logic core comprises a plurality of intellectual property cores, and each intellectual property core comprises a digital down-conversion module, an FFT (Fast Fourier Transform) module and a beam forming module; wherein the digital down-conversion module is used for obtaining a first frequency conversion signal based on an echo signal received by a receiving array element in response to a first instruction; the FFT module is used for responding to a second instruction and obtaining sub-band data based on the first frequency conversion signal; the beam forming module is used for responding to a third instruction and obtaining total output in a preset direction based on the sub-band data; and the detection module is used for obtaining target object information based on the total output in the preset direction.

Description

Technical Field

[0001] The present application relates to the field of sonar positioning, and in particular to a control chip of an underwater sonar system and an underwater sonar device. Background Art

[0002] With the development of marine resources, the accuracy of sonar needs to be higher and higher, and the complexity of the corresponding algorithms continues to increase.

[0003] In the existing sonar detection technology, a multi-core digital signal processor (DSP) is used as the core main control chip. However, as the difficulty of the algorithm continues to increase, the use of DSP will cause insufficient computing power and serious delay problems.

[0004] Accordingly, the art needs a new sonar system positioning chip to solve the above problems. Summary of the invention

[0005] In order to overcome the above-mentioned defects, the present invention is proposed to solve or at least partially solve the technical problem of low sonar positioning accuracy in the prior art.

[0006] In a first aspect, the present invention provides a positioning method for an underwater sonar system, wherein the sonar system comprises a plurality of receiving array elements, and the control chip comprises: a processor system core and a programmable logic core, wherein the processor system core is used to control the operation of the programmable logic core; the programmable logic core comprises a plurality of intellectual property cores, wherein the intellectual property core comprises: a digital down-conversion module, an FFT module and a beamforming module; wherein the digital down-conversion module: in response to a first instruction, obtains the echo signal received by the receiving array element, and performs a frequency reduction operation on the echo signal to obtain a first frequency conversion signal, wherein the frequency of the first frequency conversion signal is lower than the frequency of the echo signal, and the echo signal is obtained by reflecting the emitted sound wave signal of the target object, and the sound wave signal is emitted at a preset frequency; T module: in response to the second instruction, obtains the first frequency-converted signal, and performs frequency domain conversion on the first frequency-converted signal to obtain sub-band data, wherein the sub-band data is used to characterize the energy of the echo signal at different frequency components; beamforming module: in response to the third instruction, obtains the sub-band data, and weights all the sub-band data according to the position of the receiving array element and a preset direction set to obtain a total output in a preset direction; detection module: detects the target object according to the total output in the preset direction to obtain target object information, wherein the target object information includes at least the position information of the target object and the speed information of the target object; wherein the first instruction, the second instruction and the third instruction are all sent by the processor system core to the corresponding intellectual property core.

[0007] As an alternative or supplement to the above solution, in a method according to an embodiment of the present invention, the intellectual property core also includes: a direct memory access module, wherein the direct memory access module is used to obtain the output of other intellectual property cores and store the output of the intellectual property core in the memory of the programmable logic core.

[0008] As an alternative or supplement to the above scheme, in a method according to an embodiment of the present invention, the control chip includes: a first bus, a second bus and a third bus, wherein the first bus is used to connect the processor system core and the programmable logic core, and transmit instructions from the processor system core to the programmable logic core; the second bus connects the intellectual property cores and is used for data transmission between the intellectual property cores; the third bus is used to exchange data between the intellectual property core and the programmable logic core.

[0009] As an alternative or supplement to the above scheme, in a method according to an embodiment of the present invention, the number of at least one intellectual property core in the digital down-conversion module, FFT module or detection module is greater than or equal to 2, and each of the intellectual property cores is used to receive data corresponding to different receiving array elements.

[0010] As an alternative or supplement to the above scheme, in a method according to an embodiment of the present invention, the digital down-conversion module includes: a streaming first-in-first-out buffer module, a direct digital synthesis module, a multiplier and a filtering module; the streaming first-in-first-out buffer module is used to perform parallel-to-serial conversion on echo signals received by different receiving array elements to obtain first data; the direct digital synthesis module is used to generate a local oscillation signal, wherein the local oscillation signal includes two orthogonal signals; the multiplier is used to mix the first data with the two orthogonal signals respectively to obtain a first echo signal; the filtering module is used to filter and downsample the first echo signal to obtain a first frequency conversion signal.

[0011] As an alternative or supplement to the above scheme, in a method according to an embodiment of the present invention, the programmable logic core also includes a data transposition module; the data transposition module is used to obtain a first frequency-converted signal from the memory of the programmable logic core, and transpose the first frequency-converted signal and send it to the FFT module to obtain sub-band data.

[0012] As an alternative or supplement to the above scheme, in a method according to an embodiment of the present invention, the beamforming module includes: a data transposition module, a bit width conversion module, a complex floating-point multiplier module and a complex floating-point adder module; the data transposition module is used to transpose the sub-band data, and take out the frequency domain data in the sub-band and perform an interleaving operation with the corresponding weighting coefficient to make them interleaved, wherein the weighting coefficient is determined based on the position of the receiving array element and a preset direction set; the bit width conversion module is used to output the interleaved sub-band data and the weighting coefficient in parallel; the complex floating-point multiplier module is used to multiply the frequency domain data with the weight parameter to obtain a weighted result; the complex floating-point adder module is used to add the weighted results in parallel through an addition tree to obtain sub-outputs in B preset directions.

[0013] As an alternative or supplement to the above scheme, in a method according to an embodiment of the present invention, the detection module further includes: performing a first processing on the total output in the preset direction to obtain target object information, wherein the first processing includes: amplitude calculation, background normalization, constant false alarm processing and target detection

[0014] As an alternative or supplement to the above solution, in a method according to an embodiment of the present invention, the FFT module includes:

[0015] Acquire preset Fourier parameters, and perform Fourier transform on the echo signal based on the Fourier parameters to obtain sub-band data, wherein the mathematical expression of the sub-band data corresponding to the nth receiving array element is as follows:

[0016]

[0017] Among them, r n (l) is the sampling value of the nth receiving array element at time l, k is the subband number in the frequency domain, and L is the preset Fourier parameter.

[0018] An underwater sonar device, characterized by comprising: a plurality of receiving array elements, wherein the receiving array elements are used to receive echo signals; and a control chip as described in any one of the embodiments of the first aspect.

[0019] The above one or more technical solutions of the present invention have at least one or more of the following beneficial effects:

[0020] In the technical solution of the present invention, by combining the processor system core with the programmable logic core, the technology realizes efficient sonar signal processing. By setting the digital down-conversion module, FFT module and beamforming module in the programmable logic core, it can realize more efficient processing when facing complex data and complex algorithms, and improve the real-time performance of sonar recognition. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0023] Figure 1 is a schematic diagram of the structure of a control chip of an underwater sonar system according to an embodiment of the present invention;

[0024] Figure 2 is a schematic flow chart of main steps of a positioning method of an underwater sonar system according to an embodiment of the present invention;

[0025] Figure 3 is a schematic flow chart of the steps for converting the received echo into a discrete signal;

[0026] Figure 4 It is a structural diagram of a digital down-conversion module;

[0027] Figure 5 is a schematic diagram of a double buffer module;

[0028] Figure 6 It is a structural diagram of the modules involved in frequency conversion;

[0029] Figure 7a is a schematic diagram of bit width conversion in beamforming;

[0030] Figure 7b is a schematic diagram of a multiplier in beamforming;

[0031] Figure 7c is a schematic diagram of the adder tree in beamforming;

[0032] Figure 8 It is a flowchart of a three-thread operation of a processor system;

[0033] Figure 9a It is a schematic diagram of the sonar system data processing results;

[0034] Figure 9b It is another schematic diagram of the sonar system data processing results;

[0035] Fig.10 This is a schematic diagram of the processing time comparison under different processing window lengths. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] See attached Figure 2 , Figure 2 FIG. 1 is a schematic flow chart of the main steps of a positioning method of an underwater sonar system according to an embodiment of the present invention. Figure 2 As shown, the positioning method of the underwater sonar system in the embodiment of the present invention mainly includes the following steps S10 to S50.

[0039] Step S10: transmitting a sound wave signal.

[0040] In this embodiment, the sound wave signal is emitted at a preset frequency.

[0041] In one embodiment, the main purpose of transmitting the sound wave is to send a sonar pulse signal to the detection area to detect the echo response of the target object.

[0042] Further, the characteristics of the sound wave signal to be transmitted are determined according to the pre-configured transmission signal parameters. In some embodiments, the transmission signal is a high-frequency single pulse signal, wherein the frequency is a pre-set frequency.

[0043] In order to better process the transmitted signal, the mathematical expression of the transmitted signal is given here as follows:

[0044]

[0045] Where f0 is the carrier frequency, which is used to characterize the center frequency of the transmitted signal. T is the pulse width, which is used to characterize the duration of the transmitted signal during one transmission. c (t) is the complex envelope of the signal, which is used to characterize the amplitude and phase envelope of the transmitted signal.

[0046] Furthermore, when the transmitted signal reaches the water, it will produce strong reverberation at close range. To avoid reverberation interfering with the received signal, the sonar system usually delays the transmission pulse width before starting to receive the signal.

[0047] In one embodiment, the delay time is equal to the pulse width of the transmitted pulse, that is, waiting for T seconds after the pulse ends. For example, if the pulse width is 1 millisecond, the system will delay 1 millisecond after the end of the transmission before starting to receive the signal.

[0048] Strong reverberations can return immediately after transmission, creating interfering signals at close range. Delayed reception allows these reverberations time to decay and avoid masking the return of targets at greater distances.

[0049] After delay control, the system enters the receiving stage, waiting for the arrival of the target echo signal. The speed of sound waves in water is c, so the target distance and the return time τ of the echo have the following relationship:

[0050]

[0051] Where R is the target distance. The system estimates the possible echo arrival time based on the round-trip time τ0 after the sonar pulse is transmitted, and prepares for receiving the echo signal.

[0052] Step S20: Acquire the echo signal received by each receiving array element.

[0053] In this embodiment, the sonar system includes N receiving array elements, wherein the receiving array elements are used to receive echoes, and the echo signals are discrete signals.

[0054] After the sonar system transmits the sound wave signal, it will propagate toward the target object and be reflected back by the target object to form an echo signal. Each receiving element of the system is responsible for independently receiving this reflected signal and recording various information of the signal for subsequent analysis.

[0055] In this embodiment, first, each receiving array element receives the echo signal reflected from the target object. Then, the echo signal received by each array element is preprocessed and discretely sampled to generate a two-dimensional data matrix X. The data matrix X is used for subsequent frequency domain conversion, beamforming and target detection operations. Figure 3 As shown, Figure 3 The following is a flow chart of the steps for converting the received echo into a discrete signal:

[0056] 1) Receive echo signal:

[0057] Assume that the target is a single-point scatterer, that is, the target reflects the signal only at one point, and the underwater acoustic channel is uniform and non-directional, and the reflected wave propagates in all directions. At this time, the mathematical expression of the received signal is as follows:

[0058] r(t)=Ks(t-τ(t))=Ksη(t-τ0)

[0059] Where K is a constant, which is related to the scattering cross section of the target and is used to characterize the target's reflection ability. s(t) is the transmitted sound wave signal. τ0 is the round-trip time of the signal, that is, the time required for the signal to be transmitted from the sonar system to the target object and back. The mathematical expression of τ0 is R is the distance between the sonar system and the target, c is the speed of sound. η is the Doppler compression factor, which is used to characterize the compression of the representative signal due to the relative motion of the target (Doppler effect), where the mathematical expression of η is: β is the Doppler coefficient, and the expression of β is: Where v represents the radial velocity of the target object relative to the sonar system.

[0060] From the above mathematical expression of the received signal, we can know that the influence of the Doppler effect is taken into account when constructing the mathematical expression of the received signal. That is, due to the relative motion of the target object and the sonar system, the echo signal will undergo a Doppler shift in frequency, that is, the frequency of the echo signal will change due to the motion of the target. The frequency of the echo signal after shift can be expressed as:

[0061] f d =βf0

[0062] where f d It is the Doppler frequency shift. This frequency shift makes the frequency of the echo signal slightly higher or lower than the transmission frequency. Due to the Doppler effect, when there is an angle deviation between the wave source (sonar system) and the observer (target object), the calculated velocity will only reflect the radial velocity component and cannot provide complete velocity information. Therefore, in the present invention, it is not that only one device is used to receive the echo signal. Instead, the echo signal is received by multiple receiving array elements set in an array, thereby overcoming the limitations of the Doppler effect and finally obtaining the complete velocity information of the target object.

[0063] In this embodiment, the receiving plane array of the sonar system includes n receiving array elements, where n≥2. The receiving array elements are located at different spatial positions and receive echo signals reflected by the target object at the same time.

[0064] 2) Simplify processing

[0065] The simplified processing mainly involves making assumptions and obtaining time delays, as follows:

[0066] Assuming that the bandwidth B of the transmitted sound wave signal is very small relative to its carrier frequency, that is, when B≤f0, the envelope change in the echo signal can be ignored. This is because the frequency variation range of the transmitted sound wave signal is almost negligible relative to the center frequency. Therefore, the echo signal will not experience significant envelope shape changes during propagation and can maintain its original envelope characteristics. At this time, s c (η(t-τ0))≈s c (t-τ0), since the target object is in the water, the speed of the target object changes slowly, which can be approximated as The mathematical expression of the echo signal received by the nth receiving element is obtained as follows:

[0067]

[0068] Among them, T n is the time delay of the nth receiving element relative to the reference element. Due to the different positions of the receiving elements, the time when the echo signal reaches different receiving elements is slightly different, so one of the receiving elements is arbitrarily selected as the reference element to make it easier to express the time delay between receiving elements. c (t-τ0-τ n ) is the envelope of the echo signal, which includes the round-trip time τ0 of the signal and the relative time delay τ between the receiving array elements n .

[0069] Time delay τ n The calculation of depends on the position of the receiving array element and the arrival direction of the echo signal. Since the position of the receiving array element is pre-set, it can be assumed that the position of the nth receiving array element is p n =(p x , p v , pz), and the echo direction vector is k(θ, φ), where θ is the horizontal azimuth angle of the incident direction of the echo signal, and φ is the elevation angle of the incident direction of the echo signal, then:

[0070]

[0071] This time delay is caused by the different directions of propagation of the echo signal and the layout of the receiving array.

[0072] 3) Discrete sampling:

[0073] After preprocessing, the received echo signal is sampled and discretized, and the continuous signal is represented as discrete data points to facilitate subsequent digital signal processing. Assume that the sampling interval is where fs is the sampling rate of the sonar system during processing, then the discrete sampling signal obtained at the nth receiving element is:

[0074]

[0075] Wherein m = 0, 1, ..., M-1. M is the number of sampling points in a sampling window (time domain), and Ts is the duration of the acquisition signal of a sampling window.

[0076] The discretized sampling signals then form a matrix X, which contains the received data from different receiving array elements and different time sampling points. All the collected receiving array element echo signals can be organized into a two-dimensional matrix:

[0077] X=[r0,r1,...,r N-1 ] T

[0078] Among them, r n =[r n (0), r n (1), ..., r n (M-1)] T , represents the snapshot data received by the nth receiving element. The matrix here will be used as the data of the echo signal in subsequent processing.

[0079] Furthermore, the data will be down-converted to convert the high-frequency echo signal into a low-frequency complex baseband signal, thereby reducing the amount and complexity of subsequent processing.

[0080] In one embodiment, the steps of frequency conversion of data include: 1. performing parallel-to-serial conversion on the echo signal; 2. generating a local oscillation signal and mixing it with the received signal; 3. using an FIR filter to remove high-frequency components; 4. downsampling to reduce the amount of data, and finally obtaining a complex baseband signal. The details are as follows:

[0081] 1. Parallel to serial conversion

[0082] Sonar arrays are usually composed of multiple receiving elements, each of which receives independent echo signals. In this case, the echo data is input in parallel, that is, the signals of each element are collected in parallel.

[0083] In this embodiment, the parallel input snapshot data is converted into serial data in real time to facilitate subsequent step-by-step processing.

[0084] 2. Generate LO signal (local oscillation signal)

[0085] The LO signal is generated by a Direct Digital Synthesizer (DDS) IP core.

[0086] The LO signal is orthogonal, that is, it contains two signals: a sine signal and a cosine signal, which are 90 degrees out of phase. The frequency f0 of the LO signal is usually the same as the carrier frequency of the transmitted signal to achieve accurate frequency down conversion.

[0087] 3. Mixing

[0088] The received echo signal is mixed with the LO signal, that is, multiplied with the sine and cosine signals in the LO signal respectively. The mixing operation can reduce the frequency of the high-frequency signal.

[0089] The mixing operation is implemented by the multiplier IP core.

[0090] 4. Low-pass filtering (FIR filtering)

[0091] After mixing, the signal contains the original signal frequency and lower baseband components, as well as high-frequency components. In order to retain the baseband signal and remove the high-frequency components, the signal is filtered using a low-pass filter (a finite impulse response (FIR) low-pass filter can be used).

[0092] Low-pass filtering retains the baseband components of the received target echo signal and filters out the high-frequency components generated during the mixing process to obtain a clean low-frequency signal.

[0093] 5. Downsampling

[0094] Since the baseband signal frequency is reduced after down-conversion, the signal can be downsampled to further reduce the amount of data. The downsampling process is to discard certain data points in the original signal at fixed intervals, thereby reducing the sampling rate. For example, reducing the sampling rate to 1 / 4 of the original will reduce the pressure on data storage and processing.

[0095] The downsampling ratio is determined by the specific bandwidth requirements and system configuration parameters.

[0096] 6. Generate complex baseband signal

[0097] The resulting in-phase component I(t) and quadrature component Q(t) are combined to form a complex baseband signal r c (t) = I (t) + jQ (t).

[0098] This complex baseband signal contains the amplitude and phase information of the echo signal and is a low-frequency representation of the received signal, which facilitates subsequent FFT processing, beamforming and other operations.

[0099] By converting high-frequency echo signals into low-frequency complex baseband signals, the amplitude and phase of the echo information are retained, while the high-frequency components are removed and the sampling rate is reduced, thereby significantly reducing the amount of data and computational complexity, providing efficient and easy-to-process baseband signals for subsequent signal processing (such as FFT and beamforming).

[0100] Step S30: performing frequency domain conversion on the echo signal received by the nth receiving array element to obtain sub-band data.

[0101] In this embodiment, the sub-band data is used to characterize the energy of the echo signal at different frequency components.

[0102] The time domain signal (echo signal) received by each receiving array element is converted to the frequency domain to provide necessary data for subsequent frequency domain beamforming. Specifically, the data matrix X mentioned above is processed, and an L-point FFT operation is performed on the time domain data of each receiving array element therein to convert the time domain data into frequency domain data.

[0103] In one implementation, the echo signal is transformed into the frequency domain by Fourier transform. Specifically, the echo signal is transformed into the frequency domain by pre-set fast Fourier transform (FFT) parameters. Specifically, as follows:

[0104] 1) Get the preset FFT parameters

[0105] Before the FFT operation, the pre-set FFT parameters are first obtained, including the number of FFT points L.

[0106] The number of points L must be an integer power of 2 and must be greater than or equal to M (the actual number of sampling points). For example, if M=1024, then L may be 1024, 2048, etc.

[0107] If L is greater than M, the data is usually padded with zeros, that is, zeros are added after the original data. By padding with zeros, the data length reaches L, which can improve the frequency resolution.

[0108] 2) Perform FFT operation on the echo signal received by each receiving element to obtain sub-band data:

[0109] For each receiving element, the snapshot data r n , perform L-point FFT operation to convert time domain data into frequency domain data.

[0110] The frequency domain data after FFT processing is recorded as X n (f k ), indicating that the nth array element is at frequency f k The signal value at .

[0111] The mathematical expression of subband data is: Among them, r n (1) is the sampling value of the nth receiving array element at time l, k is the subband number in the frequency domain, representing different frequency components in the frequency domain.

[0112] 3) Frequency domain sampling

[0113] Subband data X n (f k ), k = 0, 1, ..., L-1 represents different frequency domain components. Each k corresponds to a frequency point, which is called a frequency domain subband.

[0114] The center frequency of each sub-band data is: where f s is the system sampling rate. In this way, the frequency characteristics of the signal can be observed at different frequency components. Among them, the frequency distribution of the FFT result is symmetrical, including positive and negative frequency components. Therefore, there are two formulas in the expression of the center frequency above.

[0115] 41 Aggregate data to form a multi-channel frequency domain data matrix

[0116] After performing FFT operation on the data of all receiving array elements, the frequency domain data of each array element can be arranged in columns to form a new matrix X′: X′=[X0(f k ), X1(f k ), ..., X N-1 (f k )] T The dimension of this matrix is ​​N×L, which represents the data of N array elements in the array on L frequency domain subbands.

[0117] By converting the original time domain matrix into a frequency domain matrix, the spectral characteristics of the echo signal are further revealed, which helps to identify the direction information of the signal and the target motion state, etc. And by converting the time domain signal into the frequency domain signal, the amount of calculation can be greatly reduced.

[0118] Step S40: weighting all sub-band data according to the position of the receiving array element and a preset direction set to obtain a total output of the corresponding sub-band data in multiple directions.

[0119] First, define a preset direction set Ω. Then calculate the weighting coefficient w according to each direction and subband data. n (Ω i , f k ) is used for phase and amplitude adjustment. For each direction and frequency component, the frequency domain data of each array element is weighted and summed to obtain the beamforming output Y(Ω i , f k). The beam output matrix Y containing all directions and frequency components is constructed. Then the above beamforming results are IFFT (inverse FFT transform) and converted to the time domain to obtain the time domain result y of broadband beamforming i (m).

[0120] In this embodiment, by weighting and accumulating the signals from different receiving array elements, the signal in a certain direction is enhanced, while the signal in other directions is suppressed. Thus, signals in multiple directions are obtained, and the signals in these directions can be regarded as the projections of the signals in the corresponding directions. Thus, the accuracy of target detection is finally improved. The details are as follows:

[0121] 1. Preset direction set

[0122] First, you need to define a set of preset directions, that is, the directions that the system wants to detect. For example:

[0123]

[0124] Among them, Ωi represents the i-th preset direction, N B is the number of beams. Each direction is determined by a horizontal angle (azimuth) and a vertical angle (elevation), usually expressed as Ω i =(θ i ,φ i ).

[0125] 2. Weight the echo signal received by each receiving array element

[0126] The echo signal received by each receiving element is weighted according to the beam direction to ensure that the signal is added in phase in that direction. k The weighting coefficient w on n (Ω i , f k ) is calculated as follows:

[0127]

[0128] Where N is the total number of array elements, which is used for normalization. k is the frequency, and beamforming is performed separately on each frequency component. k(Ω i ) is the beam direction vector, where k(Ω i ) is expressed as: k(Ω i )=-[sin θ i cos φ i , cos θ i cos φ i , sin φ i ] TThe negative sign indicates that the beam direction is opposite to the echo propagation direction. n is the position vector of the nth array element.

[0129] This weighting factor w n (Ω i , f k ) is used to receive the signal of the nth array element in Ω i The phase and amplitude are adjusted in a certain direction so that the signal from that direction is enhanced.

[0130] 3. Perform complex weighted summation on frequency domain data

[0131] For each beam direction Ω i And each frequency component f k , perform weighted summation on the received data of each array element to obtain the beamforming output in that direction. The specific calculation is as follows:

[0132] Y(Ω i , f k )=w H (Ω i , f k )X(f k )

[0133] Among them, Y(Ω i , f k ) is the beam direction Ω i and frequency f k The beamforming output on w H (Ω i , f k ) is the conjugate transpose of the weight vector, indicating that each array element is in Ω i Direction and f k A set of weighting coefficients over frequency.

[0134] Through this weighted summation operation, the signals of all array elements are summed in the beam direction Ω i The signals are added in phase in the direction above, thereby enhancing the signal in that direction.

[0135] 4. Obtain beamforming results for all beam directions and subband data

[0136] Repeat the above weighted summation operation for all preset beam directions and sub-band data (frequency components) to form a beam output matrix:

[0137]

[0138] Among them, each element of the matrix Y(Ω i , f k ) indicates that in the direction Ω i and frequency fk The beamforming output on .

[0139] This matrix provides beam responses in all preset directions and on all sub-band data, which can be used for subsequent target detection and parameter estimation.

[0140] 5. Perform inverse Fourier transform (IFFT) on the beamforming result

[0141] Since the beamforming result is frequency domain data, further analysis usually needs to restore it to the time domain. Therefore, for each beam direction Ω i The frequency domain result Y(Ω i , f k ) performs an inverse Fourier transform (IFFT) to obtain the time domain signal of broadband beamforming:

[0142]

[0143] where y i (m) is the time domain signal. L is the number of FFT points, and m is the time domain sampling point index.

[0144] Through frequency domain beamforming, the system can enhance the signal in multiple preset directions, thereby suppressing interference in other directions, and ultimately be used for azimuth detection and characteristic analysis of the target object.

[0145] Step S50: Detect the target object according to the total output in the preset direction to obtain target object information.

[0146] In this embodiment, the target object information at least includes position information of the target object and speed information of the target object.

[0147] In one implementation, a first processing is performed on the total output in the preset direction to obtain target object information, wherein the first processing includes: amplitude calculation, background normalization, constant false alarm processing and target detection.

[0148] Specifically, the first process comprises the following steps:

[0149] First, the amplitude of the total output signal in the preset direction is calculated. Then, the amplitude of the total output signal is normalized with the background noise to eliminate the influence of environmental noise. Through normalization, the characteristics of the target signal can be more clearly highlighted and the accuracy of target detection can be improved. Then, based on the constant false alarm algorithm, dynamic threshold detection is performed on the normalized signal. The constant false alarm algorithm can adaptively adjust the detection threshold according to the noise level to ensure a constant false alarm rate under different noise conditions, thereby improving the reliability of detection.

[0150] Furthermore, the total output in each preset direction is square-law detected, and each target object information obtained in different directions is compared with each other. If the position information and speed information of the target object are within the resolution index range, these target object information are combined into one detection result. The parameter value of the combined target detection result takes the average value of these target object information, or through interpolation processing, the distance, speed and direction information of the target object are obtained.

[0151] Finally, by processing the total output signal through the above steps, the information of the target object can be effectively extracted, including its position, intensity, and orientation, etc., providing key data for subsequent analysis and tracking.

[0152] Further, such as Figure 1 As shown, Figure 1 It is a schematic diagram of the structure of the control chip of the underwater sonar system.

[0153] The present invention also provides a control chip for an underwater sonar system. The chip includes: a processor system core and a programmable logic core, wherein the programmable logic core includes: a digital down-conversion module, an FFT module, and a beamforming module, the processor system core includes a detection module, and the processor system core is used to control the programmable logic core.

[0154] A digital down-conversion module: in response to a first instruction, obtains the echo signal received by the receiving array element, and performs a frequency reduction operation on the echo signal to obtain a first frequency conversion signal, wherein the frequency of the first frequency conversion signal is lower than the frequency of the echo signal, the echo signal is obtained by reflecting the transmitted sound wave signal of the target object, and the sound wave signal is transmitted at a preset frequency;

[0155] The FFT module: in response to the second instruction, acquires the first frequency conversion signal, and performs frequency domain conversion on the first frequency conversion signal to obtain sub-band data, wherein the sub-band data is used to characterize the energy of the echo signal at different frequency components;

[0156] A beamforming module: in response to a third instruction, obtains the sub-band data, and weights all the sub-band data according to the position of the receiving array element and a preset direction set to obtain a total output in a preset direction;

[0157] Detection module: detects the target object according to the total output in a preset direction to obtain target object information, wherein the target object information at least includes position information of the target object and speed information of the target object;

[0158] The digital down-conversion module, FFT module and beamforming module are all intellectual property cores (IP cores). Compared with ordinary processing units, intellectual property cores have high efficiency and flexibility. Since intellectual property cores are usually optimized, their energy efficiency ratio and processing speed are higher when executing specific algorithms. There are also some IP cores in the programmable logic core, such as direct memory access module (Direct Memory Access, DMA), wherein the direct memory access module is used to obtain the output of other intellectual property cores and store the output of the intellectual property core in the memory of the programmable logic core. Information is transmitted between IP cores in the programmable logic core through the AXI-Stream bus (second bus). Among them, the processor system core and the programmable logic core transmit high-level function instructions through the AXI-Lite bus (first bus), and the processor system core and the programmable logic core transmit data through the AXI-Full bus (third bus).

[0159] In this embodiment, by setting the digital down-conversion module, FFT module and beamforming module in the programmable logic core, the advantages of the IP core are fully utilized when facing complex data and complex algorithms, so that a large amount of data can be quickly processed, and the real-time performance during sonar recognition is increased. In addition, by setting the detection module in the processor system core, the difficulty of the overall chip design is reduced. The above design scheme takes into account the timeliness problem when the complex algorithm is running and the difficulty of chip design, thereby reducing the overall chip design cost.

[0160] Furthermore, the number of at least one intellectual property core in the digital down-conversion module, FFT module or detection module is greater than or equal to 2, and each of the intellectual property cores is used to receive data corresponding to different receiving array elements. This design allows each core to process data from multiple array elements in parallel, thereby improving the data processing capability of the system. Through the collaborative work of multiple intellectual property cores, the system can process a large number of signals more efficiently, improve the processing speed and accuracy of the signal, and enhance the real-time response capability of the sonar system.

[0161] like Figure 4 As shown, Figure 4 The digital down-conversion module includes a streaming first-in-first-out buffer module, a direct digital synthesis module, a multiplier and a filter module.

[0162] The processor system core sends the acquired echo signal to the programmable logic core, and obtains a first frequency conversion signal by controlling the operation of a digital down-conversion module in the programmable logic core;

[0163] The digital down-conversion module sends the first frequency conversion signal to the memory of the processor system core; wherein,

[0164] The streaming first-in-first-out buffer module is used to convert the echo signal into parallel-to-serial data to obtain the first data; the direct digital synthesis module is used to generate a local oscillation signal, wherein the local oscillation signal includes two orthogonal signals; the multiplier is used to mix the first data with the two orthogonal signals respectively to obtain the first echo signal; the filtering module is used to filter and downsample the first echo signal to obtain a first frequency-converted signal.

[0165] The digital down-conversion module can reduce the amount of collected data and reduce the pressure of subsequent data storage, transmission and signal processing. In one implementation, the design of the digital down-conversion module adopts a zero intermediate frequency architecture.

[0166] The first frequency conversion signal finally obtained is transmitted to the DDR memory of the processor system core through the direct memory access module for buffering.

[0167] Further, such as Figure 5 As shown, Figure 5 is a schematic diagram of the double buffer module.

[0168] The dual cache module is set up in the processor system core, in which two continuous memory spaces are opened up in the DDR memory of the processor system core, so that data collection and reading are staggered, thereby reducing the latency of the system data flow and improving the data throughput efficiency of the chip during processing, thereby increasing bandwidth utilization.

[0169] Furthermore, the processor system core sends the first frequency conversion signal to the memory of the programmable logic core, and obtains the sub-band data by controlling the operation of the programmable logic core.

[0170] like Figure 6 As shown, Figure 6 The schematic diagram of the structure of the modules involved in the frequency conversion is as follows: the programmable logic core sends the sub-band data to the memory of the processor system core; the programmable logic core also includes a data transposition module; the data transposition module is used to obtain the first frequency conversion signal from the memory of the programmable logic core, and transpose the first frequency conversion signal and send it to the FFT module.

[0171] First, the processor system core configures the working mode register of the FFT module through the AXI-lite bus, where 0 indicates that the input data is subjected to FFT operation, and 1 indicates that the IFFT operation is performed; then the FFT point register of the IP core is configured, and the value range is an integer power of 2, which can be 64, 128, 256, ..., 8192, 16384. Then, the direct memory access module parameters are configured to indicate the amount of data transmitted by the direct memory access module at one time, the data source address, and the destination address, and then a transmission operation is initiated to transfer a snapshot acquisition data stored in the memory of the processor system core to the FFT module of the programmable logic core. It should be noted that the FFT module requires that the input data is continuous in the time domain, but the storage address of the acquired data in the array element domain is continuous, but discontinuous in the time domain, so the data transposition module needs to solve the problem of discontinuous addresses in the time domain direction. Through the above, the time overhead of data transposition is minimized, and the data cache and transposition are realized by cooperating with the memory of the programmable logic core through state machine control. The transposed data is input into the FFT module for processing and then transmitted to the memory of the processor system core through the data transmission module. At this time, a multi-channel FFT or IFFT operation is completed.

[0172] like Figure 7a-7c As shown, the Figure 7a-7c It is a schematic diagram of the three parts of the beamforming module. Figure 7a A schematic diagram showing the operation of the data transposition module and the bit width conversion module in the beamforming module. Figure 7b It is a schematic diagram of the operation of the complex floating-point multiplier module in the beamforming module. Figure 7c It is a schematic diagram of the operation of the complex floating-point adder module in the beamforming module.

[0173] The beamforming module includes: a data transposition module, a bit width conversion module, a complex floating point multiplier module and a complex floating point adder module;

[0174] The data transposition module is used to transpose the sub-band data, and take out the frequency domain data in the sub-band and perform an interleaving operation with the corresponding weighting coefficient to make them arranged in an interleaved manner, wherein the weighting coefficient is determined based on the position of the receiving array element and a preset direction set; the bit width conversion module is used to output the interleaved sub-band data and the weighting coefficient in parallel; the complex floating-point multiplier module is used to multiply the sub-band data with the weight parameter to obtain a weighted result; the complex floating-point adder module is used to add the weighted results in parallel through an addition tree to obtain sub-outputs in B preset directions.

[0175] The frequency domain sampling signal (sub-band data) obtained by the FFT module is first traversed through each frequency point and preset beam direction through the state machine control module.

[0176] The data transposition module then performs a transposition operation on the sub-band data. The data transposition module interleaves the sub-band data and the pre-calculated weighting coefficients so that the sub-band data and the weighting coefficients are interleaved when output. The weighting coefficient here is w in the above text. n , I will not go into details here.

[0177] The transposed and interleaved data enters the bit width conversion module, which is used to adjust the bit width of the data to ensure that the sub-band data and the weighting coefficients can be output in parallel.

[0178] The parallel output sub-band data and corresponding weighting coefficients then enter the complex floating-point multiplier module. The complex floating-point multiplier module multiplies each pair of sub-band data and weighting coefficients to obtain a weighted result. The weighting operation adjusts the received data on each frequency to a phase and amplitude consistent with the current beam direction.

[0179] Furthermore, in order to improve the system throughput, the output of the complex floating-point multiplier module enters a six-stage cascaded complex floating-point adder adder tree. The adder tree structure can add multiple weighted results in parallel and accumulate the output results corresponding to a certain beam direction and subband within 6 clock cycles.

[0180] The weighted results are accumulated in parallel in different beam directions through the complex floating-point adder module, and finally sub-outputs in B preset directions are obtained.

[0181] Through the above-mentioned beamforming module, by configuring the number of frequency points and the number of beam directions, the beamforming module can realize the beamforming operation in the frequency domain and provide efficient and parallel output for each sub-band and direction. This design ensures the high throughput and real-time processing capability of the system in multiple directions and multiple frequency points.

[0182] In this embodiment, other tasks including the detection module are all executed in the processor system core.

[0183] Furthermore, in order to improve the processing capability, the processor system core adopts the Linux multi-threaded programming method, dividing the program into three threads: the main thread, the sonar task thread and the data processing thread. Figure 8 As shown, Figure 8 It is a flowchart of a three-thread operation of a processor system.

[0184] Before the active sonar system starts working, the application running on the processor system core initializes and configures each module in the programmable logic core (including the digital down-conversion module, FFT module, and beamforming module). Specifically, the registers of each module are configured through the AXI-lite bus.

[0185] After initialization is completed, the main thread creates and starts the sonar task thread and data processing thread in sequence.

[0186] The sonar task thread is responsible for transmitting sound wave signals and collecting echo signals reflected by the target object, performing digital down-conversion and data storage operations. The data processing thread receives the echo data collected by the sonar task thread and performs Fourier transform, beam forming, target detection and other processing operations on it.

[0187] After that, the sonar task thread first configures the frequency, sampling frame number, and point number of the transmitted signal through the digital down-conversion module, and then triggers the sonar transmitting module to transmit a pulse. After the transmission is completed, the transmission pulse width is delayed to avoid reverberation interference, and then the echo signal is collected. The collected echo signal undergoes parallel-to-serial conversion, mixing, filtering, and downsampling in the digital down-conversion module to obtain the first frequency conversion signal, which is then transmitted to the memory of the processor system core through the direct memory access module, recorded as cache A.

[0188] When the sonar task thread collects a complete echo data frame, it saves the data to the hard disk, releases the semaphore, and wakes up the data processing thread. The data processing thread reads data from cache A.

[0189] The data processing thread first specifies the frequency domain conversion points by configuring the point register of the FFT module. The first frequency conversion signal is transmitted to the FFT module through the direct memory access module, and the frequency domain conversion is performed on it to obtain sub-band data, and the result is transmitted back to the cache B of the processor system core. Then, the FFT result data is transposed and the frequency band is filtered in the processor system core to obtain sub-band data, which is stored in the cache C.

[0190] The subband data in buffer C is transferred to the beamforming module, which transposes the subband data and interleaves the frequency domain data in the subband with the weighting coefficients determined based on the array element position and the preset direction. The bit width conversion module ensures that the interleaved data and weighting coefficients are output in parallel, and multiplied by the complex floating point multiplier module to obtain the weighted result. The weighted results are then added in parallel in the addition tree in the complex floating point adder module to obtain the output result in the preset direction. The beamforming result is stored in buffer D.

[0191] Then, the beamforming data in cache D is transposed and padded with zeros in the processor system core, and transmitted to the FFT module through AXIDMA for inverse frequency domain transformation (IFFT) to obtain the beamforming data in the time domain, which is stored in cache E.

[0192] Finally, the detection module reads the time domain beam data from the buffer E, performs amplitude calculation, background normalization and constant false alarm processing in sequence, detects the target object and extracts the target object information.

[0193] When the collected multi-window data reaches a certain amount, the detection results are fused and parameter estimation is performed, and finally the target detection results and parameter information are saved to the hard disk. The above process will be repeated in multiple detection cycles until the detection task is completed. After the detection task is completed, the system destroys the data processing thread and sonar task thread, waiting for the next detection task to start.

[0194] To verify the correctness of the signal processing system, the results of the processing algorithm program running on the MPSoC and desktop platforms were compared under the same input data and parameter configuration to compare the consistency of the output results. The test results are shown in Table 1.

[0195]

[0196] Table 1

[0197] When verifying the algorithm function of the signal processing system, the target parameter configuration is shown in Table 2, and the generated signal time-frequency diagram is shown in Figure 9 ( Figure 9a and Figure 9b ). In the design of the present invention, the detection direction of the unmanned aerial vehicle covers ±28° in the horizontal direction, and the preset beam direction set is Ω={±28°,±24°,…,±4°,0°}, a total of 15 directions, and the vertical direction only forms a beam in the 0° direction. According to the transmission parameters and the motion platform and target parameters, it is calculated that the target echo appears at the 4th second position of the echo signal, and the Doppler frequency is 414Hz.

[0198] Target parameters Parameter Value Platform running speed / (m / s) 5 Target distance / m 2900 Target speed / (m / s) -5 Target direction / (°) 4 Signal-to-noise ratio / dB -15

[0199] Table 2

[0200] The multi-channel FFT and beamforming results of MPSoC are exported as shown in Figure 9. Due to the large number of channels, only the FFT results of channels 1 to 4 are selected. Figure 9a It can be seen that after the system performs multi-channel FFT on the echo signal, the estimated Doppler frequency of channels 1-3 is 418.0Hz, while that of channel 4 is 421.9Hz, and the theoretical value is 414Hz. This is because the input data type of the FFT module is a single-precision floating-point number, which introduces errors in the calculation. Figure 9bIt can be seen that after the system performs frequency domain beamforming on the echo signal, the maximum output is obtained at the direction of 4.000° and the frequency of 416.2 Hz, which is basically consistent with the theoretical results.

[0201] The target detection results under the CPU and MPSoC computing environments are shown in Table 3. The target parameter estimation results under the two computing environments are basically consistent and not much different from the true values, which proves good consistency.

[0202]

[0203] Table 3

[0204] In order to test the real-time performance of the signal processing system, the time of the entire signal processing process is set to be within 80% of the sampling data update cycle, which is considered to meet the real-time requirements. The pulse width of the system transmission signal is 128ms, the sampling rate after digital down-conversion is 8000Hz, the number of channels of input data is 64, and the number of beamforming directions is 15; the data processing window width is set to 256ms, corresponding to 2048 sampling points, and the data overlap rate is 50%, then the data update cycle is 128ms, corresponding to 1024 sampling points. Under this condition, data reception and processing must be completed within 103ms.

[0205] The real-time performance of the CPU and MPSoC computing environments was evaluated through Monte Carlo experiments. The imported target echo data file was read and processed continuously for 500 times, and the average value was taken. The results are shown in Table 4. The results show that the CPU running time exceeds the real-time upper limit, while the receiving and processing time of the MPSoC only accounts for half of the data update process, which meets the real-time requirements.

[0206]

[0207] Table 4

[0208] Comparing the time consumption of each signal processing stage between CPU and MPSoC, MPSoC has significant acceleration effect in digital down-conversion, FFT and beamforming stages. The algorithm operation efficiency of the signal post-processing stage is not as good as that of the CPU. This is because the pre-processing algorithm uses the programmable logic core of MPSoC for acceleration, and the pipeline and double buffer operations are used to significantly shorten the data processing time. The signal post-processing algorithm is implemented in the processor system core, and its main frequency is lower than that of the desktop platform processor. The processing time is slightly longer, but it still meets the real-time requirements and leaves sufficient margin to provide space for the application of more complex algorithms in the future, showing the advantages of heterogeneous platforms integrating software and hardware resources.

[0209] The real-time performance of the system was also tested under different processing window lengths. Fig.10As shown, under different processing window lengths, the signal processing time always meets the real-time requirements, and the proportion is stable at around 41%, which can meet the real-time detection needs under different transmission pulse widths and sampling lengths.

[0210] The active sonar signal processing system of the present invention is based on the Xilinx XCZU 15EG MPSoC heterogeneous platform, and reasonable task allocation, digital down-conversion, beamforming, matched filtering and signal post-processing schemes are designed. Computational intensive algorithms such as FFT operations and complex floating-point multiplication and addition operations are deployed to the programmable logic core, making full use of on-chip DSP resources for hardware acceleration; signal post-processing algorithms with complex logic judgments but small data volume such as background normalization, peak search, multi-beam target detection and information fusion are deployed in the processor system core, and the system is globally controlled by running the Linux system. It has high reconfigurability and realizes real-time detection of moving targets. The system only needs a single chip to replace the traditional multi-DSP or FPGA+DSP / FPGA+CPU architecture, greatly simplifies the system structure, and realizes miniaturization, lightweight and low power consumption. The actual flight test results show that the system can realize real-time detection of moving targets by underwater unmanned vehicles, and has important application value in the fields of active and passive sonar detection of underwater unmanned vehicles.

[0211] It should be pointed out that although the various steps in the above embodiments are described in a specific order, those skilled in the art can understand that in order to achieve the effects of the present invention, different steps do not have to be performed in such an order. They can be performed simultaneously (in parallel) or in other orders. These changes are within the scope of protection of the present invention.

[0212] It is understood by those skilled in the art that the present invention implements all or part of the processes in the method of the above embodiment, and can also be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes a computer program, and the computer program can be in source code form, object code form, executable file or some intermediate form. The computer-readable storage medium may include: any entity or device, medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory, random access memory, electric carrier signal, telecommunication signal and software distribution medium that can carry the computer program. It should be noted that the content contained in the computer-readable storage medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable storage media do not include electric carrier signals and telecommunication signals.

[0213] Furthermore, the present invention also provides an underwater sonar device, characterized in that it comprises: a plurality of receiving array elements, wherein the receiving array elements are used to receive echo signals;

[0214] A control chip, wherein the control chip is as shown in the control chip of the underwater sonar system in any of the above embodiments.

[0215] Those skilled in the art will appreciate that the modules in the device can be adaptively split or merged. Such splitting or merging of specific modules will not cause the technical solution to deviate from the principle of the present invention, and therefore, the technical solutions after splitting or merging will fall within the protection scope of the present invention.

[0216] It should be noted that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications should also be regarded as the scope of protection of this application.

Claims

1. A control chip for an underwater sonar system, characterized in that: The sonar system includes a plurality of receiving array elements, and the control chip includes: a processor system core and a programmable logic core, wherein the processor system core is used to control the operation of the programmable logic core; The programmable logic core includes a plurality of intellectual property cores, and the intellectual property cores include: a digital down-conversion module, an FFT module and a beamforming module; wherein, A digital down-conversion module: in response to a first instruction, obtains an echo signal received by a receiving array element, and performs a frequency reduction operation on the echo signal to obtain a first frequency conversion signal, wherein the frequency of the first frequency conversion signal is lower than the frequency of the echo signal, the echo signal is obtained by reflecting the transmitted sound wave signal of the target object, and the sound wave signal is transmitted at a preset frequency; The FFT module: in response to the second instruction, acquires the first frequency conversion signal, and performs frequency domain conversion on the first frequency conversion signal to obtain sub-band data, wherein the sub-band data is used to characterize the energy of the echo signal at different frequency components; A beamforming module: in response to a third instruction, obtains the sub-band data, and weights all the sub-band data according to the position of the receiving array element and a preset direction set to obtain a total output in a preset direction; Detection module: detects the target object according to the total output in a preset direction to obtain target object information, wherein the target object information at least includes position information of the target object and speed information of the target object; The first instruction, the second instruction and the third instruction are all sent by the processor system core to the corresponding intellectual property core.

2. The control chip according to claim 1, characterized in that: The detection module is located in the processor system core.

3. The control chip according to claim 1 or 2, characterized in that: The intellectual property core further comprises: a direct memory access module, wherein the direct memory access module is used to obtain outputs of other intellectual property cores and store the outputs of the intellectual property cores in the memory of the programmable logic core.

4. The control chip according to claim 1, characterized in that: The control chip includes: a first bus, a second bus and a third bus, wherein the first bus is used to connect the processor system core and the programmable logic core, and transmit the instructions of the processor system core to the programmable logic core; the second bus connects the intellectual property cores and is used for data transmission between the intellectual property cores; the third bus is used to exchange data between the intellectual property core and the programmable logic core.

5. The control chip according to any one of claims 1 to 4, characterized in that: The number of at least one intellectual property core in the digital down-conversion module, the FFT module or the detection module is greater than or equal to 2, and each of the intellectual property cores is used to receive data corresponding to different receiving array elements.

6. The control chip according to any one of claims 1 or 5, characterized in that: The digital down-conversion module includes: a streaming first-in-first-out buffer module, a direct digital synthesis module, a multiplier and a filtering module; The streaming FIFO buffer module is used to perform parallel-to-serial conversion on the echo signals received by different receiving array elements to obtain first data; The direct digital synthesis module is used to generate a local oscillation signal, wherein the local oscillation signal includes two orthogonal signals; The multiplier is used for mixing the first data with the two orthogonal signals respectively to obtain a first echo signal; The filtering module is configured to filter and downsample the first echo signal to obtain a first frequency conversion signal.

7. The control chip according to any one of claim 1, characterized in that: The programmable logic core also includes a data transposition module; The data transposition module is used to obtain a first frequency conversion signal from the memory of the programmable logic core, and to transpose the first frequency conversion signal and send it to the FFT module to obtain sub-band data.

8. The control chip according to any one of claim 1, characterized in that: The beamforming module includes: a data transposition module, a bit width conversion module, a complex floating point multiplier module and a complex floating point adder module; The data transposition module is used to transpose the sub-band data, and extract the frequency domain data in the sub-band and perform an interleaving operation with the corresponding weighting coefficients to make them interleaved, wherein the weighting coefficients are determined based on the position of the receiving array element and a preset direction set; The bit width conversion module is used to output the interleaved sub-band data and weighting coefficients in parallel; The complex floating-point multiplier module is used to multiply the frequency domain data by the weight parameter to obtain a weighted result; The complex floating-point adder module is used to add the weighted results in parallel through an addition tree to obtain sub-outputs in B preset directions.

9. The control chip according to claim 7 or 8, characterized in that: The detection module further comprises: performing a first processing on the total output in the preset direction to obtain target object information, wherein the first processing comprises: amplitude calculation, background normalization, constant false alarm processing and target detection.

10. An underwater sonar device, characterized in that include: A plurality of receiving array elements, wherein the receiving array elements are used to receive echo signals; A control chip, wherein the control chip is as shown in any one of claims 1-9.

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