Spatial light modulator device and method of forming same

Abstract

The embodiment of the invention provides a spatial light modulator device and a forming method thereof. A spatial light modulator device includes an array of spatial light modulator cells on a substrate. Each spatial light modulator unit comprises: a layer stack comprising a phase change material plate, a spacer dielectric material plate underlying the phase change material plate, and a metal heater plate underlying the spacer dielectric material plate and comprising an outer sidewall; and pairs of bottom electrode via structures contacting respective surface sections of the bottom surface of the metal heater plate. Each outer sidewall of the metal heater plate is vertically coincident with a corresponding sidewall of the spacer dielectric material plate and a corresponding sidewall of the phase change material plate.

Description

Technical Field

[0001] Embodiments of the present application relate to spatial light modulator devices and methods of forming the same. Background Art

[0002] A spatial light modulator (SLM) is an optical device that applies some form of spatially varying modulation to a light beam. An SLM modulates the intensity and / or phase of a light beam. SLMs can be used for holographic data storage. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a method for forming a spatial light modulator device is provided, the method comprising: providing a semiconductor substrate having a metal interconnect structure thereon; depositing a via-level dielectric layer above the metal interconnect structure; forming a bottom electrode via structure within the via-level dielectric layer; depositing a group of material layers including a metal heater material layer, a spacer dielectric material layer, and a phase change material layer; and patterning the group of material layers into an array of layer stacks by performing at least one anisotropic etching process, the anisotropic etching process transferring a pattern in the patterned etching mask to each layer in the group of material layers.

[0004] According to one aspect of an embodiment of the present application, a method for forming a spatial light modulator device is provided, the method comprising: depositing a through-hole level dielectric layer above a semiconductor substrate; forming a bottom electrode through-hole structure passing through the through-hole level dielectric layer; depositing a metal heater material layer above the bottom electrode through-hole structure; forming an opening in the metal heater material layer; depositing a group of material layers including a spacer dielectric material layer, a phase change material layer and a cover dielectric material layer on the metal heater material layer; and patterning the group of material layers and the metal heater material layer into an array of layer stacks by performing at least one anisotropic etching process, wherein each of the layer stacks includes a metal heater plate, a spacer dielectric material plate, a phase change material plate and a cover dielectric material plate.

[0005] According to another aspect of an embodiment of the present application, a spatial light modulator device is provided, comprising: a field effect transistor located on a semiconductor substrate; a metal interconnect structure formed in a dielectric material layer overlying the field effect transistor and electrically connected to the field effect transistor; and an array of spatial light modulator units located above the dielectric material layer, wherein: each of the spatial light modulator units includes a layer stack, the layer stack includes a phase change material plate, a spacer dielectric material plate located below the phase change material plate, and a metal heater plate located below the spacer dielectric material plate and including an outer side wall; and each outer side wall of the metal heater plate vertically coincides with a corresponding side wall of the spacer dielectric material plate and a corresponding side wall of the phase change material plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a vertical cross-sectional view of an embodiment structure after forming a field effect transistor and a metal interconnect structure in a dielectric material layer according to an embodiment of the present disclosure.

[0008] Figure 2 is a vertical cross-sectional view of an embodiment structure after forming a via level dielectric layer and an array of via cavities passing through the via level dielectric layer according to an embodiment of the present disclosure.

[0009] Figure 3A is a vertical cross-sectional view of an embodiment structure after forming a bottom electrode via structure array according to an embodiment of the present disclosure.

[0010] Figure 3B , Figure 3C and Figure 3D yes Figure 3A Top views of various configurations of example structures. Figure 3B and Figure 3C The vertical plane A-A' corresponds to Figure 3A The cross section in .

[0011] Figure 4 is a vertical cross-sectional view of an embodiment structure after forming a metal heater material layer, a hard mask layer, and a patterned etch mask layer according to an embodiment of the present disclosure.

[0012] Figure 5A is a vertical cross-sectional view of an embodiment structure after forming an opening through a hard mask layer, a metal heater material layer, and a via-level dielectric layer according to an embodiment of the present disclosure.

[0013] Figure 5B-5J yes Figure 5A Top views of various configurations of example structures. Figure 5B , Figure 5C , Figure 5E , Fig. 5F and Fig.5I The vertical plane A-A' corresponds to Figure 5A The cross section in .

[0014] Figure 6 is a vertical cross-sectional view of an example structure after forming a dielectric filling material layer according to an embodiment of the present disclosure.

[0015] Figure 7is a vertical cross-sectional view of an embodiment structure after forming a dielectric pillar structure according to an embodiment of the present disclosure.

[0016] Figure 8 is a vertical cross-sectional view of an embodiment structure after vertically recessing the dielectric pillar structure and removing the hard mask layer according to an embodiment of the present disclosure.

[0017] Fig. 9 is a vertical cross-sectional view of an embodiment structure after forming a spacer dielectric material layer, a phase change material layer, and a cap dielectric material layer according to an embodiment of the present disclosure.

[0018] Fig.10 is a vertical cross-sectional view of an embodiment structure according to an embodiment of the present disclosure after a group of layers including a cover dielectric material layer, a phase change material layer, a spacer dielectric material layer and a metal heater material layer are patterned into a layer stack of a metal heater plate, a spacer dielectric material plate, a phase change material plate and a cover dielectric material plate.

[0019] Fig.11A is a vertical cross-sectional view of an embodiment structure after removing the patterned photoresist layer according to an embodiment of the present disclosure.

[0020] Figure 11B-11J yes Fig.11A Top views of various configurations of example structures. Fig. 11B , Fig. 11C , Fig.11E , Fig.11F and Fig.11I The vertical plane A-A' corresponds to Fig.11A The cross section in .

[0021] Fig.12 is a vertical cross-sectional view of an example structure after forming a dielectric liner according to an example of the present disclosure.

[0022] Fig.13 is a vertical cross-sectional view of an embodiment structure after forming a dielectric cap layer and a first passivation dielectric layer according to an embodiment of the present disclosure.

[0023] Fig.14 is a vertical cross-sectional view of an embodiment structure after forming a metal contact structure and a second passivation dielectric layer according to an embodiment of the present disclosure.

[0024] Fig.15 is a vertical cross-sectional view of the first alternative embodiment structure after forming an opening through the hard mask layer and the metal heater material layer according to an embodiment of the present disclosure.

[0025] Fig.16 is a vertical cross-sectional view of the first alternative embodiment structure after forming a dielectric pillar structure according to an embodiment of the present disclosure.

[0026] Fig.17 is a vertical cross-sectional view of the first alternative embodiment structure after forming a metal contact structure and a second passivation dielectric layer according to an embodiment of the present disclosure.

[0027] Fig.18 is a vertical cross-sectional view of a second alternative embodiment structure after patterning the array of spatial light modulator elements according to an embodiment of the present disclosure.

[0028] Fig.19 is a vertical cross-sectional view of a second alternative embodiment structure after forming a metal contact structure and a second passivation dielectric layer according to an embodiment of the present disclosure.

[0029] Fig. 20 is a first flow chart illustrating general processing steps for fabricating a device structure according to an embodiment of the present disclosure.

[0030] Fig.21 is a second flow chart illustrating general processing steps for fabricating a device structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0032] In addition, for ease of description, spacing relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spacing relationship terms are intended to include different orientations of the device in use or operating processes. The device can be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relationship descriptors used in this article can be interpreted accordingly. Elements with the same reference number represent the same element and are assumed to have the same material composition and the same thickness range unless otherwise explicitly indicated.

[0033] Various embodiments of the present disclosure relate to spatial light modulators using phase change memory materials. An optimized mask layout design can be used to pattern an array of spatial light modulator cells with enhanced device performance. A metal heater material layer can be patterned in a manner that forms openings only within the region of the spatial light modulator cell array, thereby minimizing recesses in the dielectric fill material that fills the openings during a subsequent planarization process. The ratio of the area of ​​the metal heater material layer to the area of ​​the opening can be greater than 9, thereby enabling precise control of the polishing rate in a chemical mechanical polishing process for a planarization process. A dielectric pillar structure is formed in an opening in the metal heater material layer and can extend vertically through a via-level dielectric layer below, or can be formed entirely within the level of the metal heater material layer.

[0034] The same etching mask (such as a patterned photoresist layer) can then be used to pattern the phase change storage material layer and the metal heater material layer. Using the same etching mask causes the outer side wall of the metal heater plate to be aligned with the phase change material plate, thereby ensuring that the area between the metal heater plate and the phase change material plate overlaps. The dielectric pillar structure can be completely located within the area of ​​the metal heater plate. A dielectric cover layer can be formed above the spatial light modulator unit array to provide thermal insulation for the spatial light modulator unit. Various configurations of the present disclosure can provide an enhanced thermal distribution profile in the spatial light modulator unit array, and can improve the performance and reliability of the spatial light modulator unit array.

[0035] Phase change material plate is used as a reflector with adjustable phase modulation. Phase change material plate can be programmed to be crystalline or amorphous to provide different phase shifts in incident light. When subjected to specific heating and cooling conditions, the phase change material in the phase change material plate provides a transition between amorphous and crystalline states. Generally, rapid quenching from a molten state results in an amorphous phase (i.e., amorphous state), while slow cooling from a molten state results in a crystalline phase (i.e., crystalline state). Amorphous and crystalline states can provide two different refractive indices, so modulation of the crystalline phase of the phase change material can cause an optional light beam with a fixed wavelength, which produces different phase shifts when reflected on the phase change material. Phase change material can be used as a programmable optical phase modulator, which can be repeatedly programmed to provide two optical states with different phase shifts. In an illustrative example, the thickness of the phase change material can be selected so that the two reflected light beam components generated on the top and bottom surfaces of the phase change material interfere constructively in one of the two crystalline phases of the phase change material and destructively in the other of the two crystalline phases of the phase change material. By measuring the intensity of the reflected light beam from the phase change material, the optical state of the phase change material can be determined, thereby determining its crystalline state. Therefore, by controllably changing the distribution of the crystalline state on the phase change crystal plate array, optical data can be stored in the phase change material portion. Various embodiments of the present disclosure are now described with reference to the accompanying drawings.

[0036] Reference Figure 1 , showing an embodiment structure of the present disclosure. The embodiment structure includes a semiconductor substrate 8, which may be a commercially available silicon substrate. The semiconductor substrate 8 may include a semiconductor material layer 9 at least on its upper portion. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate, or may be a top semiconductor layer of a semiconductor on insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single crystal semiconductor material, such as single crystal silicon. In one embodiment, the semiconductor substrate 8 may include a single crystal silicon substrate, which includes a single crystal silicon material.

[0037] A shallow trench isolation structure 720 including a dielectric material such as silicon oxide may be formed on the upper portion of the semiconductor material layer 9. Suitable doped semiconductor wells, such as a p-type well and an n-type well, may be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 720. Semiconductor devices such as field effect transistors 701 may be formed on the top surface of the semiconductor material layer 9. For example, each field effect transistor may include a source 732, a drain 738, a semiconductor channel 735, and a gate structure 750, wherein the semiconductor channel 735 includes a surface portion of the semiconductor substrate 8 extending between the source 732 and the drain 738. The semiconductor channel 735 may include a single crystalline semiconductor material. Each gate structure 750 may include a gate dielectric layer 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal semiconductor alloy region 742 may be formed on each source 732, and a drain-side metal semiconductor alloy region 748 may be formed on each drain 738. Devices formed on the top surface of the semiconductor material layer 9 may include complementary metal oxide semiconductor (CMOS) transistors and optional additional semiconductor devices (eg, resistors, diodes, capacitor circuits, etc.), collectively referred to as CMOS circuits 700 .

[0038] One or more field effect transistors in the CMOS circuit 700 may include a semiconductor channel 735 that includes a portion of a semiconductor material layer 9 in the semiconductor substrate 8. In embodiments where the semiconductor material layer 9 includes a single crystalline semiconductor material such as single crystalline silicon, the semiconductor channel 735 of each field effect transistor in the CMOS circuit 700 may include a single crystalline semiconductor channel such as a single crystalline silicon channel. In one embodiment, a subset of the field effect transistors in the CMOS circuit 700 may include a corresponding node that is subsequently electrically connected to a node of an energy harvesting device and / or a subsequently formed cell structure.

[0039] In one embodiment, the semiconductor substrate 8 may include a single crystal silicon substrate, and the field effect transistor 701 may include a corresponding portion of the single crystal silicon substrate as a semiconductor channel. As used herein, a "semiconductor" element refers to an element with an electrical conductivity of 1.0 x 10 -6S / cm to 1.0x 10 5 S / cm. As used herein, a "semiconductor material" refers to an element in which the electrical conductivity in the absence of electrical dopants is within 1.0×10 -6 S / cm to 1.0x 10 5 S / cm range and can produce conductivity between 1.0 S / cm and 1.0 x 10 5 Doping materials in the S / cm range.

[0040] Various metal interconnect structures formed in the dielectric material layer may then be formed over the semiconductor substrate 8 and the semiconductor devices (e.g., field effect transistors) thereon. In one illustrative example, the dielectric material layer may include, for example, a first dielectric material layer 601 (sometimes referred to as a contact-level dielectric material layer 601) surrounding a contact structure connected to a source and a drain, a first interconnect-level dielectric layer 610, a second interconnect-level dielectric material layer 620, a third interconnect-level dielectric material layer 630, and a fourth interconnect-level dielectric material layer 640.

[0041] The metal interconnect structure may include a device contact via structure 612 formed in the first dielectric material layer 601 and contacting various components of the CMOS circuit 700, a first conductive line structure 618 formed in the first interconnect level dielectric material segment 610, a first conductive via structure 622 formed in a lower portion of the second interconnect level dielectric material layer 620, a second conductive line structure 628 formed in an upper portion of the second interconnect level dielectric material layer 620, a second conductive via structure 632 formed in a lower portion of the third interconnect level dielectric material layer 630, a third conductive line structure 638 formed in an upper portion of the third interconnect level dielectric material layer 630, a third conductive via structure 642 formed in a lower portion of the fourth interconnect level dielectric material layer 640, and a fourth conductive line structure 648 formed in an upper portion of the fourth interconnect level dielectric material layer 640. Although the present disclosure is described using an embodiment in which four levels of conductive line structures are formed in the dielectric material layers, it is expressly contemplated herein that fewer or more levels of conductive line structures are formed in the dielectric material layers.

[0042] Each dielectric material layer (601, 610, 620, 630, 640) may include a dielectric material, such as an undoped silicate, a doped silicate, a silicon oxynitride, a carbon-doped silicon oxide, an organic silicate, a silicon oxynitride, a silicon nitride, a silicon carbonitride, a porous variant thereof, or a combination thereof. Each metal interconnect structure (612, 618, 622, 628, 631, 638, 642, 648) may include at least one conductive material, which may be a combination of a metal liner (such as a metal nitride or a metal carbide) and a metal filler material. Each metal liner may include TiN, TaN, WN, MoN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, Au, Pt, an alloy thereof, and / or a combination thereof. Other suitable metal liners and metal filler materials may also be used within the intended disclosure. In one embodiment, the first conductive via structure 622 and the second conductive line structure 628 can be formed as an integrated line and via structure by a dual damascene process. In general, any continuous set of conductive line structures (628, 638, 648) and at least one underlying conductive via structure (622, 632, 642) can be formed as an integrated line and via structure.

[0043] Generally, a semiconductor device may be formed on a semiconductor substrate 8, and a metal interconnect structure (612, 618, 622, 628, 631, 638, 642, 648) and a dielectric material layer (601, 610, 620, 630, 640) may be formed over the semiconductor device. The metal interconnect structure (612, 618, 622, 628, 631, 638, 642, 648) may be formed in the dielectric material layer (601, 610, 620, 630, 640) and may be electrically connected to a semiconductor device such as a field effect transistor 701. The embodiment structure may include an array region 100 and a peripheral region 200, in which a spatial light modulator unit array is subsequently formed, and in which a metal contact structure is subsequently formed.

[0044] According to one aspect of the present invention, the field effect transistor 701 includes a heater drive transistor for driving a subsequently formed spatial light modulator unit. Each spatial modulator unit includes a metal heater plate and a phase change material plate. Each field heater drive transistor can be configured to apply a programming pulse selected from a first programming pulse, the first duration of the first programming pulse can melt the phase change material plate and quickly quench the melted phase change material so that the phase change material re-solidifies in an amorphous state, and the second duration of the second programming pulse can melt the phase change material plate and slowly cool the phase change material so that the phase change material re-solidifies in a crystalline state. The first duration can be in the range of 1ns to 10ns. The second duration can be in the range of 100 microseconds to 1 millisecond. In an embodiment, each spatial light modulator unit can include a pair of bottom electrode through-hole structures (formed subsequently). In this embodiment, each heater drive transistor can be configured to drive current through the structure of the metal heater plate and a pair of bottom electrodes in the corresponding spatial light modulator unit.

[0045] Reference Figure 2 A via level dielectric layer 650 may be formed over the underlying dielectric material layers (601, 610, 620, 630, 640). The via level dielectric layer 650 includes an interlayer dielectric (ILD) material such as an undoped silicate, a doped silicate, or an organic silicate. The via level dielectric layer 650 may have a thickness in the range of 200 nm to 800 nm, although lesser or greater thicknesses may also be used.

[0046] The photoresist layer 17 may be applied to the through-hole level dielectric layer 650 and may be photolithographically patterned to form an array of opening groups. Each opening group includes at least one pair of openings and is formed in a corresponding unit area UA within each opening group array. In this embodiment, the pattern of the opening group may be repeated periodically along two horizontal directions, which may or may not be perpendicular to each other. In an embodiment where the opening group array is a rectangular array, the two horizontal directions may be perpendicular to each other.

[0047] An anisotropic etching process may be performed to transfer the pattern in the photoresist layer 17 to the via-level dielectric layer 650. A via cavity 651 is formed through the via-level dielectric layer 650 below the opening in the photoresist layer 17. The top surface of the underlying metal interconnect structure (e.g., the top surface of the fourth conductive line structure 648) may be physically exposed below each via cavity 651. The photoresist layer 17 may then be removed, for example, by ashing.

[0048] Figure 3A is a vertical cross-sectional view of an embodiment structure after forming an array of bottom electrode via structures 652 according to an embodiment of the present disclosure. Figure 3B , Figure 3C and Figure 3D yes Figure 3A Top views of various configurations of example structures. Figure 3B and Figure 3C The vertical plane A-A' corresponds to Figure 3A The cross section in .

[0049] Reference Figure 3A-3D , at least one conductive material, which may be at least one metallic material, may be deposited in the via cavity 651. Excess portions of the at least one conductive material may be removed from above a horizontal plane including a top surface of the via-level dielectric layer 650. Each remaining portion of the at least one conductive material filling a corresponding via opening constitutes a conductive via structure that serves as a bottom electrode of the metal heater plate (formed subsequently, referred to herein as a bottom electrode via structure 652).

[0050] Each bottom electrode via structure 652 can contact the top surface of the metal interconnect structure below, which can be the fourth wire structure 648. In one embodiment, each bottom electrode via structure 652 can include a metal barrier liner and a metal filling material portion. The metal barrier liner can include a metal barrier material, such as TiN, TaN, WN, MoN, TiC, TaC, WC, or a combination thereof. The metal filling material portion can include Cu, Al, Ru, W, Mo, Co, or a combination thereof. In an embodiment, the metal filling material can include Cu or Al. The top surface of the bottom electrode via structure 652 can be formed in a horizontal plane including the top surface of the via level dielectric layer 650.

[0051] At least one pair of bottom electrode via structures 652 may be formed in each unit area UA of the spatial light modulator unit array. Figure 3B A configuration is shown in which two pairs of bottom electrode via structures 652 are formed in each unit area UA. In this embodiment, two bottom electrode via structures 652 can be electrically connected to the first output node of the heater driving transistor, and the other two bottom electrode via structures 652 can be electrically connected to the second output node of the heater driving transistor.

[0052] Figure 3C A configuration is shown in which a pair of bottom electrode via structures 652 are formed in each unit area UA. In this configuration, the bottom electrode via structures 652 in each unit area UA may be laterally elongated along a horizontal direction perpendicular to a lateral separation direction of the bottom electrode via structures 652.

[0053] Figure 3DA configuration is shown in which a pair of bottom electrode via structures 652 are formed in each unit area UA. In this configuration, the bottom electrode via structures 652 in each unit area UA may be diagonally spaced from each other. The lateral separation direction between the bottom electrode via structures 652 may be neither parallel nor perpendicular to the repeating direction of the subsequently formed spatial light modulator unit array.

[0054] In one embodiment, the unit area UA may be repeated periodically along the first horizontal direction hd1 and along the second horizontal direction hd2. In one embodiment, the second horizontal direction hd2 may be perpendicular to the first horizontal direction. In one embodiment, instances of the unit area UA may be repeated in a periodic rectangular two-dimensional array.

[0055] Reference Figure 4 , a metal heater material layer 20L, a hard mask layer 21L, and a patterned etch mask layer 27 may be formed over the via level dielectric layer 650. The metal heater material layer 20L includes a metal material having a melting point greater than 1500 degrees Celsius. For example, the metal heater material layer 20L may include a refractory metal such as tungsten, tantalum, rhenium, molybdenum, or niobium, or may include a metal nitride material such as TiN, TaN, WN, or MoN. The thickness of the metal heater material layer 20L may be in the range of 10 nm to 100 nm, but smaller or larger thicknesses may also be used.

[0056] A hard mask layer 21L may be deposited over the metal heater material layer 20L. The hard mask layer 21L may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, or a dielectric metal oxide material. The thickness of the hard mask layer 21L may be in the range of 20 nm to 100 nm, although lesser or greater thicknesses may also be used.

[0057] The patterned etching mask layer 27 may include a patterned photoresist layer. The patterned etching mask layer includes discrete openings whose size is smaller than each area where the metal heater plate is subsequently formed. In one embodiment, a group of at least one opening may be formed in the patterned etching mask layer 27 within each unit area UA. The group of at least one opening may be completely formed in the corresponding unit area UA for forming the spatial light modulator unit. Specifically, the group of at least one opening may be completely formed in the area of ​​the metal heater plate that is subsequently formed.

[0058] Figure 5A is a vertical cross-sectional view of the embodiment structure after forming an opening through the hard mask layer 21L, the metal heater material layer 20L, and the via-level dielectric layer 650 according to an embodiment of the present disclosure. Figure 5B-5J yes Figure 5A Top views of various configurations of example structures. Figure 5B , Figure 5C , Figure 5E , Fig. 5F and Fig.5I The vertical plane A-A' corresponds to Figure 5A The cross section in .

[0059] Reference Figure 5A-5J , an anisotropic etching process may be performed to transfer the opening pattern in the patterned etching mask layer 27 to the hard mask layer 21L and the metal heater material layer 20L. Discrete openings 29 are formed through the hard mask layer 21L, the metal heater material layer 20L, and the via-level dielectric layer 650. In one embodiment, a top surface portion of the underlying dielectric material layer (such as the fourth interconnect-level dielectric material layer 640) may be physically exposed at the bottom of each opening through the hard mask layer 21L, the metal heater material layer 20L, and the via-level dielectric layer 650. Typically, a group of at least one discrete opening 29 may be formed within each unit area UA, corresponding to the area of ​​a single spatial light modulator unit to be subsequently formed. In the array area 100, an array of a group of at least one opening may be formed through the hard mask layer 21L and the metal heater material layer 20L.

[0060] In the array region 100, an array of discrete openings 29 may be formed through the hard mask layer 21L and the metal heater material layer 20L. As described above, the array region 100 is a region where an array of spatial light modulator units is subsequently formed. According to one aspect of the present disclosure, no openings are formed through the metal heater material layer 20L in the peripheral region 200. Therefore, after forming an array of openings through the metal heater material layer 20L, the metal heater material layer 20L does not have any openings in the peripheral region 200.

[0061] Figure 5B , Figure 5E and Figure 5H Corresponding to the bottom electrode through hole structure 652 having a reference Figure 3B An embodiment of a configuration is described. Figure 5C , Fig. 5F and Fig.5I Corresponding to the bottom electrode through hole structure 652 having a reference Figure 3C An embodiment of a configuration is described. Figure 5D , Figure 5G and Figure 5J Corresponding to the bottom electrode through hole structure 652 having a reference Figure 3D An embodiment of a configuration is described. Figure 5B , Figure 5C and Figure 5D This corresponds to an embodiment in which a set of four openings are formed through the hard mask layer 21L and the metal heater material layer 20L per unit area UA. Figure 5E , Fig. 5F and Figure 5G This corresponds to an embodiment in which a set of two openings are formed through the hard mask layer 21L and the metal heater material layer 20L in each unit area UA. Figure 5H , Fig.5I and Figure 5J Corresponding to an embodiment in which a single opening is formed through the hard mask layer 21L and the metal heater material layer 20L in each unit area UA. In general, the opening in each unit area UA can form at least one conductive path provided between a first group of at least one bottom electrode via structure 652 used as a first electrode of the metal heater plate of the spatial light modulator unit and a second group of at least another bottom electrode via structure 652 used as a second electrode of the metal heater plate of the spatial light modulator unit. The total number of conductive paths per unit area can be 1, 2, 3, 4, 5, etc.

[0062] Reference Figure 6 , a dielectric filling material may be deposited in the openings through the hard mask layer 21L, the metal heater material layer 20L, and the via-level dielectric layer 650, and a dielectric filling material layer 22L is formed on the hard mask 21L. The dielectric filling material may include undoped silicate glass or doped silicate glass. The dielectric filling material may be conformally deposited to fill the volume of the opening. Typically, the thickness of the dielectric filling material layer 22L is greater than half of the width of each opening in the hard mask layer 21L to form the dielectric filling material layer 22L, thereby ensuring that the opening is filled with the dielectric filling material layer 22L.

[0063] Reference Figure 7 , a planarization process may be performed to remove a portion of the dielectric fill material layer 22L that is located above a horizontal plane including the top surface of the hard mask layer 21L. The planarization process may include a chemical mechanical polishing process and / or a groove etching process. According to one aspect of the present disclosure, the absence of any openings through the metal heater material layer 20L in the peripheral region 200 may improve the uniformity of the planarization process. For example, the pattern factor of the opening (defined as the ratio of the opening area through the hard mask layer 21L and the metal heater material layer 20L to the total area) may be less than 0.1 in the array region 100 and may be zero in the peripheral region 200. Such a low value of the pattern factor enhances the uniformity of a planarization process (such as a chemical mechanical polishing process) and avoids recessing of the remaining dielectric fill material portion.

[0064] The remaining portion of the dielectric filling material that fills the openings through the hard mask layer 21L, the metal heater material layer 20L, and the via-level dielectric layer 650 includes a dielectric material portion, referred to herein as a dielectric pillar structure 22. Each dielectric pillar structure 22 is located within a corresponding opening through the hard mask layer 21L, the metal heater material layer 20L, and the via-level dielectric layer 650, and has a straight sidewall extending vertically from the bottom surface to the top surface. The top surface of each dielectric pillar structure 22 can be formed at or near a horizontal plane including the top surface of the hard mask layer 21L. An array of dielectric pillar structures 22 can be formed in an array of openings through the hard mask layer 21L, the metal heater material layer 20L, and the via-level dielectric layer 650.

[0065] In summary, the dielectric pillar structure 22 may be formed in the opening of the metal heater material layer 20L by depositing the dielectric filling material layer 22L in the opening in the metal heater material layer 20L and by removing a portion of the dielectric filling material layer 22L from above a horizontal plane including the top surface of the metal heater material layer 20L. In one embodiment, the opening in the metal heater material layer 20L may extend vertically to the bottom surface of the via-level dielectric layer 650, and the dielectric pillar structure 650 may have a sidewall extending vertically from the top surface of the metal heater material layer 20L to the bottom surface of the via-level dielectric layer 650.

[0066] Reference Figure 8 By performing a recess etching process, the dielectric pillar structure 22 can be vertically recessed. The recess etching process can include an isotropic etching process, such as a wet etching process. For example, in an embodiment where the dielectric pillar structure 22 includes undoped silicate glass, a wet etching process using dilute hydrofluoric acid can be used to vertically recess the top surface of the dielectric pillar structure 22. In one embodiment, the top surface of the dielectric pillar structure can be formed in or near a horizontal plane including the top surface of the metal heater material layer 20L.

[0067] The hard mask layer 21L may then be removed by performing an etching process that selectively etches the material of the hard mask layer 21L to form dielectric pillar structures 22. In an illustrative example, in an embodiment where the hard mask layer 21L includes silicon nitride, the hard mask layer 21L may be removed using a wet etching process using hot phosphoric acid.

[0068] Reference Fig. 9, a spacer dielectric material layer 30L, a phase change material layer 40L, and a cap dielectric material layer 50L may be sequentially deposited over the metal heater material layer 20L. The spacer dielectric material layer 30L includes a dielectric material, such as aluminum nitride, undoped silicate glass, doped silicate glass, silicon nitride, silicon carbonitride, silicon oxynitride, or a dielectric metal oxide. In one embodiment, the spacer dielectric material layer 30L includes aluminum nitride, which exhibits high thermal conductivity and low electrical conductivity. The thickness of the spacer dielectric material layer 30L may be in the range of 5 nm to 50 nm, such as 10 nm to 30 nm, but smaller or larger thicknesses may also be used.

[0069] A phase change material layer 40L including a phase change material may be deposited on the spacer dielectric material layer 30L. As used herein, a "phase change material" refers to a material having at least two different phases and providing different resistivities. Phase change materials (PCMs) may be used to store information as resistivity states of a material, which may be in different resistivity states corresponding to different phases of the material. Different phases may include an amorphous state having a high resistivity and a crystalline state having a low resistivity (i.e., a resistivity lower than that of the amorphous state). The transition between the amorphous state and the crystalline state may be induced by controlling the cooling rate after applying an electrical pulse that causes the phase change material to become amorphous in the first part of the programming process. The second part of the programming process includes controlling the cooling rate of the phase change material. In an embodiment where rapid quenching occurs, the phase change material may be cooled to an amorphous high resistivity state and have a first refractive index. In an embodiment where slow cooling occurs, the phase change material may be cooled to a crystalline low resistivity state and have a second refractive index. According to one aspect of the present disclosure, the phase change material in the phase change material layer 40L is selected so that the second refractive index is different from the first refractive index.

[0070] Exemplary phase change materials include, but are not limited to, germanium antimony telluride (GST) compounds (such as Ge2Sb2Te5 or GeSb2Te4), antimony sulfide (Sb2S3), germanium antimony indium telluride compounds, germanium telluride compounds, germanium antimony compounds, indium germanium telluride compounds, aluminum selenium telluride compounds, indium selenium telluride compounds, and aluminum indium selenium telluride compounds. The phase change material may be doped (e.g., nitrogen doped GST) or undoped to enhance the resistance switching characteristics. The thickness of the phase change material layer 40L (also referred to as the PCM material layer 40L) may be in the range of 30 nm to 600 nm, for example, 60 nm to 300 nm, but smaller or larger thicknesses may also be used.

[0071] Typically, the thickness of the phase change material layer 40L can be selected so that the first reflected light reflected from the top surface of the phase change material layer and the interface between the phase change material layer 40G and the spacer dielectric material layer 30L undergoes constructive interference in one of the amorphous state and the crystalline state of the phase change material, and undergoes destructive interference in the other of the amorphous state and the crystalline state at the wavelength of the light beam used for sensing data in the subsequently formed spatial light modulation unit array.

[0072] The capping dielectric material layer 50L includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or a dielectric metal oxide. The capping dielectric material layer 50L may have a thickness in the range of 50nm to 600nm, such as 100nm to 300nm, but lesser or greater thicknesses may also be used.

[0073] Reference Fig.10 , a patterned etch mask layer 57 may be formed over the layer group including the cap dielectric material layer 50L, the phase change material layer 40L, the spacer dielectric material layer 30L, and the metal heater material layer 20L. For example, a photoresist layer may be applied over the layer group including the cap dielectric material layer 50L, the phase change material layer 40L, the spacer dielectric material layer 30L, and the metal heater material layer 20L, and may be photolithographically patterned into the patterned etch mask layer 57. In this embodiment, the patterned etch mask layer 57 may include a two-dimensional array of patterned photoresist material portions, each portion having a corresponding area corresponding to an area of ​​the phase change material layer 40L to be patterned out of the phase change material layer 40.

[0074] In one embodiment, the pattern of the two-dimensional array of patterned photoresist material portions may include a pattern of a two-dimensional periodic array of unit shapes. Each unit shape may be completely formed within a corresponding unit area UA. The unit shape may be a rectangle, a rounded rectangle, a circle, or any other two-dimensional shape with a closed boundary. In an illustrative example, each unit shape may be a rectangular shape with a length in the range of 200nm to 500nm and a width in the range of 200nm to 500nm, and each gap between adjacent unit shape pairs may be in the range of 50nm to 100nm, but the length, width, and gap may also use smaller or larger sizes.

[0075] The pattern in the patterned etch mask layer 57 may be transferred through a group of layers including the cap dielectric material layer 50L, the phase change material layer 40L, the spacer dielectric material layer 30L, and the metal heater material layer 20L by performing at least one anisotropic etching process, which may include a series of anisotropic etching processes that sequentially etches the unmasked cap dielectric material layer 50L, the phase change material layer 40L, the spacer dielectric material layer 30L, and the metal heater material layer 20L. In general, the group of material layers (20L, 30L, 40L, 50L) may be patterned into an array of layer stacks (20, 30, 40, 50) by performing at least one anisotropic etching process that transfers the pattern in the patterned etch mask layer 57 through each layer within the group of material layers (20L, 30L, 40L, 50L).

[0076] Each patterned portion of the cover dielectric material layer 50L, the phase change material layer 40L, the spacer dielectric material layer 30L, and the metal heater material layer 20L includes a layer stack (20, 30, 40, 50) of the metal heater plate 20, the spacer dielectric material layer 30, the phase change material layer 40, and the cover dielectric material layer segment 50. Each cover dielectric material plate 50 is a patterned portion of the cover dielectric material layer 50L. Each phase change material plate 40 is a patterned portion of the phase change material layer 40L. Each spacer dielectric material plate 30 is a patterned portion of the spacer dielectric material layer 30L. Each metal heater plate 20 is a patterned portion of the metal heater material layer 20L. After at least one anisotropic etching process, the top surface of the via level dielectric layer 650 is exposed. The terminal anisotropic etch process selected from the at least one anisotropic etch process may have an etch chemistry that selectively etches the spacer dielectric material layer 30L without etching the material of the via level dielectric layer 650. In this embodiment, incidental recessing of the top surface of the via level dielectric layer 650 may be minimal or zero.

[0077] The physically exposed sidewalls of each element within each layer stack (20, 30, 40, 50) of the metal heater plate 20, the spacer dielectric material plate 30, the phase change material plate 40, and the cover dielectric material plate 50 can be vertically coincident with each other. As used herein, when two or more surfaces overlap or are located below each other, and when there is a vertical plane containing each of the two or more surfaces, it is referred to as vertical coincidence. In this embodiment, within each layer stack (20, 30, 40, 50), each outer sidewall of the metal heater plate 20 can be vertically coincident with the overlying sidewall of the spacer dielectric material plate 30, the overlying sidewall of the phase change material plate 40, and the overlying sidewall of the cover dielectric material plate 50.

[0078] Typically, a patterned etch mask layer 57 including an array of etch mask material portions can be formed on a group of material layers (30L, 40L, 50L) including a cover dielectric material layer 50L, a phase change material layer 40L and a spacer dielectric material layer 30L, and on a metal heater material layer 20L, and at least one anisotropic etching process can be performed to transfer the pattern in the patterned etch mask layer 57 to each layer of the group of material layers (30L, 40L, 50L) and the metal heater material layer 20L.

[0079] Reference Figures 11A-11J , the patterned etching mask layer 57 may be removed, for example, by ashing. Fig.11A is a vertical cross-sectional view of an embodiment structure after removing the patterned photoresist layer according to an embodiment of the present disclosure. Figure 11B-11J yes Fig.11A Top views of various configurations of example structures. Fig. 11B , Fig. 11C , Fig.11E , Fig.11F and Fig.11I The vertical plane A-A' corresponds to Fig.11A The cross section in .

[0080] An array of spatial light modulator cells 10 may be formed on a via-level dielectric layer 650. Each spatial light modulator cell 10 includes a layer stack (20, 30, 40, 50) including a phase change material plate 40, a spacer dielectric material plate 30 located below the phase change material plate 40, and a metal heater plate 20 located below the spacer dielectric material plate 30 and including an outer sidewall. In addition, each spatial light modulator cell includes a pair of bottom electrode via structures 652 that contact corresponding surface segments of the bottom surface of the metal heater plate 20. In addition, each spatial light modulator cell 10 includes at least one dielectric post structure 22 located in a corresponding opening through the metal heater plate 20 and a lower portion of the via-level dielectric layer 650. In one embodiment, each of the at least one dielectric post structure 22 is completely located within an area defined by the outer sidewall of the metal heater plate 20.

[0081] In each layer stack (20, 30, 40, 50), each outer sidewall of the metal heater plate 20 is vertically coincident with a corresponding sidewall of the spacer dielectric material plate 30 and a corresponding sidewall of the phase change material plate 40. In one embodiment, each layer stack (20, 30, 40, 50) includes a cover dielectric material plate 50 covering the phase change material plate 40. In one embodiment, each sidewall of the cover dielectric material plate 50 is vertically coincident with a corresponding outer sidewall of the outer sidewalls of the metal heater plate 20.

[0082] In one embodiment, each of the at least one dielectric pillar structure 22 includes a top surface in contact with a bottom surface of the spacer dielectric material plate 30. In one embodiment, a pair of bottom electrode via structures 652 below each layer stack (20, 30, 40, 50) is formed within the via level dielectric layer 650, and at least one dielectric pillar structure 22 below each layer stack (20, 30, 40, 50) includes a bottom surface in contact with a top surface of a dielectric material layer (e.g., fourth interconnect level dielectric material layer 640) that is located below the via level dielectric layer 650.

[0083] Typically, each of the at least one dielectric pillar structure 22 includes a top surface in contact with the bottom surface of the spacer dielectric material plate 30 and has a thickness no less than the thickness of the metal heater plate 20. In one embodiment, the thickness of the at least one dielectric pillar structure 22 may be the same as the sum of the thickness of the metal heater plate 20 and the thickness of the via level dielectric layer 650.

[0084] Fig. 11B , Fig.11E and Fig.11H Corresponding to the bottom electrode through hole structure 652 having a reference Figure 3B An embodiment of a configuration is described. Fig. 11C , Fig.11F and Fig.11I Corresponding to the bottom electrode through hole structure 652 having a reference Figure 3C An embodiment of a configuration is described. Fig.11D , Fig.11G and Fig.11J Corresponding to the bottom electrode through hole structure 652 having a reference Figure 3D An embodiment of a configuration is described. Fig. 11B , Fig. 11C and Fig.11D Corresponding to Figure 5B , Figure 5C and Figure 5D Within the volume of the metal heater plate 20 shown, four embodiments of dielectric pillar structures 22 are formed through a set of four openings in each unit area UA. Fig.11E , Fig.11F and Fig.11G Corresponding to Figure 5E , Fig. 5F and Figure 5G Within the volume of the metal heater plate 20 shown, a set of two openings through each unit area UA form an embodiment of two dielectric pillar structures 22 . Fig.11H , Fig.11I and Fig.11J Corresponding to Figure 5H , Fig.5I and Figure 5JAn embodiment of a single dielectric pillar structure 22 is formed through a single opening in each unit area UA within the volume of the metal heater plate 20 shown. In general, a group of at least one dielectric pillar structure 22 in each unit area UA is configured to provide at least one conductance path between a first group of at least one bottom electrode via structure 652 used as a first electrode of the metal heater plate 20 of the spatial light modulator unit 10 and a group of at least one other bottom electrode via structure 652 used as a second electrode of the metal heater plate 20 of the spatial light modulator unit 10. The total number of conductance paths within each metal heater plate 20 can be 1, 2, 3, 4, 5, etc.

[0085] Field effect transistors 701 comprise heater drive transistors. Each heater drive transistor is configured to drive current through a metal heater plate 20 and a pair of bottom electrode via structures 652 within an array of spatial light modulator cells 10.

[0086] Typically, the metal heater material layer 20L can be patterned so that each metal heater plate 20 includes a corresponding set of at least one opening in the metal heater material layer 20L. Each metal heater plate 20 can contact at least one pair of bottom electrode via structures 652 in a corresponding set of bottom electrode via structures 652 present in the via level dielectric layer 650. In one embodiment, each pair of bottom electrode via structures 650 contacting a corresponding overlying metal heater plate 20L can be laterally spaced from each other by at least one opening in the corresponding overlying metal heater plate 20L. In one embodiment, each pair of bottom electrode via structures 650 contacting a corresponding overlying metal heater plate 20L can be laterally spaced from each other along the first horizontal direction hd1. In one embodiment, the corresponding set of at least one opening includes a plurality of openings.

[0087] Reference Fig.12 , a dielectric liner 60 may be conformally deposited over the array of spatial light modulator cells 10. The dielectric liner 60 comprises a dielectric material, such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxide, dielectric metal oxide, etc. In an embodiment, the dielectric liner 60 comprises an insulating dielectric material and / or is mainly composed of an insulating dielectric material, such as silicon nitride, silicon oxynitride, or silicon carbonitride. The dielectric liner 60 may be deposited by a conformal deposition process. The thickness of the dielectric liner 60 may be in the range of 5 nm to 40 nm, such as 8 nm to 20 nm, but smaller or larger thicknesses may also be used. The dielectric liner 60 covers the top surface and sidewalls of each layer stack (20, 30, 40, 50) within the array of spatial light modulator cells 10, and contacts the top surface of a via-level dielectric layer 650, which laterally surrounds the bottom electrode via structure 652 in the array of spatial light modulator cells 10.

[0088] Reference Fig.13 , a dielectric cover layer 660 may be formed over the dielectric liner 60. The dielectric cover layer 660 includes a dielectric material, such as undoped silicate glass, doped silicate glass, silicon nitride, silicon oxynitride, silicon carbonitride, organic silicate glass, a polymer material, or a combination thereof. The thickness of the dielectric cover layer 660 may be in the range of 300 nm to 2000 nm, such as 600 nm to 1000 nm, but lesser or greater thicknesses may also be used. In some embodiments, a sealed cavity 69 may be formed in the dielectric cover layer 660. The sealed cavity 69 is free of any solid material and is formed in the dielectric cover layer 660 in the gap region between adjacent pairs of layer stacks (20, 30, 40, 50) within the array of the spatial light modulator unit 10.

[0089] A first passivation dielectric layer 672 may be formed over the dielectric cap layer 660. The first passivation dielectric layer 672 includes a passivation dielectric material such as silicon nitride, silicon carbonitride, or silicon oxynitride. The thickness of the first passivation dielectric layer 672 may be in the range of 100 nm to 300 nm, although lesser or greater thicknesses may also be used.

[0090] Reference Fig.14 , through a combination of a photolithography patterning step and an anisotropic etching process, a through-hole cavity can be formed in the peripheral region 200 through the first passivation dielectric layer 672 and the dielectric cap layer 660. The top surface of the lower metal interconnect structure (e.g., a fourth wire structure 648 having a metal pad configuration) can be physically exposed below each through-hole cavity. A metal contact structure 668 can be formed in a through-hole cavity on the physically exposed top surface of the metal interconnect structure. The metal contact structure 668 can include copper, aluminum, and / or an aluminum-copper alloy. As required, a suitable metal barrier liner and / or under-bump metallization layer can be used. A second passivation dielectric layer 674 can be formed above the first passivation dielectric layer 672 and above the metal contact structure 668, and can be patterned to physically expose the surface of the metal contact structure 668. The metal contact structure 668 can be any type of metal contact structure known in the art, and can be, but is not limited to, a solder bonding pad, a metal-to-metal bonding pad (for metal-to-metal bonding, such as copper-to-copper bonding), a micro-bump structure, and the like.

[0091] Reference Fig.15 , by performing an anisotropic etching process, Figure 4A first alternative embodiment structure is derived from the illustrated embodiment structure, and the process selectively etches the material of the hard mask layer 21L and the metal heater material layer 20L without etching the material of the via-level dielectric layer 650. In the first alternative embodiment structure, the discrete openings 29 do not extend into the via-level dielectric layer 650. Therefore, although the pattern of the discrete openings 29 of the first alternative embodiment structure is the same as the pattern of the discrete openings 29 in the above-described embodiment structure, the discrete openings 29 do not extend into the dielectric layer below the via-level dielectric layer 650. In one embodiment, the discrete openings 29 do not extend into the via-level dielectric layer 650. In one embodiment, the physically exposed section of the via-level dielectric layer 650 below the discrete openings 29 may be located in the same horizontal plane as the interface between the via-level dielectric layer 650 and the metal heater material layer 20L.

[0092] Reference Fig.16 , you can execute the reference Figure 6 , Figure 7 and Figure 8 The processing steps described above are performed to form dielectric pillar structures 22 in discrete openings 29 in the metal heater material layer 20L. In this embodiment, each dielectric pillar structure 22 includes a bottom surface that contacts the top surface of the via-level dielectric layer 650. In one embodiment, the bottom surface of the dielectric pillar structure 22 can be formed in a horizontal plane that includes the interface between the via-level dielectric layer 650 and the metal heater material layer 20L.

[0093] In summary, by depositing a dielectric filling material layer 22L in an opening in the metal heater material layer 20L and removing a portion of the dielectric filling material layer 22L from above a horizontal plane including the top surface of the metal heater material layer 20L, a dielectric pillar structure 22 may be formed in the opening of the metal heater material layer 20L. In one embodiment, when the opening is formed in the metal heater material layer 20L, the top surface of the via-level dielectric layer 650 may be exposed below the opening of the metal heater material layer 20L, and the dielectric pillar structure 20 may be formed directly on a section of the top surface of the via-level dielectric layer 650.

[0094] refer to Fig.17 , you can execute reference Figure 9-Figure 14 The processing steps are described to form an array of spatial light modulator cells 10, dielectric liner 60, dielectric cap layer 660, passivation dielectric layers (672, 674) and metal contact structures 668.

[0095] refer to Fig.18 By continuing at least one anisotropic etching process and selectively changing the etching chemistry to vertically recess the physically exposed portion of the via-level dielectric layer 650, the via-level dielectric layer 650 can be removed from the substrate. Fig.10A second alternative embodiment structure is derived from the illustrated embodiment structure. The patterned etching mask layer 57 can then be removed. In this embodiment, the via-level dielectric layer 650 can have a topmost planar segment and a recessed planar segment. The topmost planar segment contacts the bottom surface of the layer stack (20, 30, 40, 50). The recessed planar segment does not contact the layer stack (20, 30, 40, 50) and is vertically recessed from the topmost planar segment by a vertical recess distance, which can be, for example, in the range of 1 nm to 100 nm, such as 5 nm to 50 nm, but smaller or larger vertical recess distances can also be used. Each outer sidewall of the metal heater plate 20 vertically coincides with a corresponding sidewall segment of the via-level dielectric layer 650, which connects the topmost planar segment and the recessed planar segment.

[0096] refer to Fig.19 , you can execute reference Figure 12-14 The processing steps are described to form an array of spatial light modulator cells 10, dielectric liner 60, dielectric cap layer 660, passivation dielectric layers (672, 674) and metal contact structures 668.

[0097] Fig. 20 is a first flow chart illustrating general processing steps for fabricating a device structure that can be used to form a spatial light modulator device.

[0098] Refer to Step 2010 and Figure 1 , a semiconductor substrate 8 having a metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) thereon may be provided.

[0099] Reference steps 2020 and Figure 2 , a via level dielectric layer 650 may be deposited on the metal interconnect structures ( 612 , 618 , 622 , 628 , 632 , 638 , 642 , 648 ).

[0100] Refer to steps 2030 and Figure 2-Figure 3D , a bottom electrode via structure 652 may be formed within the via level dielectric layer 650 .

[0101] Refer to step 2040 and Figure 4-Figure 9 and Figure 15-19 , a set of material layers ( 20L, 30L, 40L, 50L) may be deposited, including a metal heater material layer 20L, a spacer dielectric material layer 30L, and a phase change material layer 40L.

[0102] Refer to step 2050 and Figure 10-Figure 14 , Fig.17 and Fig. 20The material layer group (20L, 30L, 40L, 50L) can be patterned into a layer stack array (20, 30, 40, 50) by performing at least one anisotropic etching process, which transfers the pattern in the patterned etching mask layer 57 to each layer within the material layer group.

[0103] Fig.21 is a second flow chart illustrating general processing steps for fabricating a device structure that can be used to form a spatial light modulator device.

[0104] Refer to step 2110 and Figure 1 and Figure 2 , a via level dielectric layer 650 may be deposited over the semiconductor substrate 8 .

[0105] Refer to step 2120 and Figure 2-Figure 3D , a bottom electrode via structure 652 may be formed through the via level dielectric layer 650 .

[0106] Refer to step 2130 and Figure 4 , a metal heater material layer 20L may be deposited over the bottom electrode via structure 652 .

[0107] Refer to step 2140 and Figure 5A-5J , an opening may be formed in the metal heater material layer 20L.

[0108] Refer to step 2150 and Figure 6-Figure 9 and Figure 15-19 , a material layer group ( 30L, 40L, 50L) including a spacer dielectric material layer 30L and a phase change material layer 40L may be sequentially deposited on the metal heater material layer 20L.

[0109] Refer to step 2160 and Figure 10-Figure 14 , Fig.17 and Fig. 20 By performing at least one anisotropic etching process, the material layer group (30L, 40L, 50L) and the metal heater material layer 20L can be patterned into a layer stack array (20, 30, 40, 50). Each layer stack (20, 30, 40, 50) includes a metal heater plate 20, a spacer dielectric material plate 30, a phase change material plate 40 and a cover dielectric material plate 50.

[0110] With reference to all the drawings, according to various embodiments of the present disclosure, there is provided a spatial light modulator device, which includes an array of spatial light modulator units 10 located above a substrate. Each spatial light modulator unit 10 includes: a layer stack (20, 30, 40, 50), which includes a phase change material plate 40, a spacer dielectric material plate 30 located below the phase change material plate 40, and a metal heater plate 20 located below the spacer dielectric material plate 30 and including an outer sidewall; and a pair of bottom electrode through-hole structures 652, which contact corresponding surface sections of the bottom surface of the metal heater plate 20, wherein each outer sidewall of the metal heater plate 20 vertically coincides with a corresponding sidewall of the spacer dielectric material plate 30 and a corresponding sidewall of the phase change material plate 40.

[0111] In one embodiment, each spatial light modulator unit 10 includes at least one dielectric pillar structure 22 located in a corresponding opening through the metal heater plate 20. In one embodiment, each of the at least one dielectric pillar structure 22 includes a top surface in contact with a bottom surface of the spacer dielectric material plate 30. In one embodiment, the pair of bottom electrode via structures 652 can be formed within the via level dielectric layer 650; and the pair of bottom electrode via structures 652 include a bottom surface in contact with a top surface of a dielectric material layer below the via level dielectric layer 650.

[0112] In one embodiment, a pair of bottom electrode via structures 652 may be formed within the via level dielectric layer 650; and the pair of bottom electrode via structures 652 include bottom surfaces contacting the top surface of the via level dielectric layer 650. In one embodiment, each of the at least one dielectric pillar structure 22 is completely located within the area defined by the outer sidewall of the metal heater plate 20.

[0113] In one embodiment, the layer stack (20, 30, 40, 50) includes a cover dielectric material plate 50 covering the phase change material plate 40; and each sidewall of the cover dielectric material plate 50 is vertically coincident with a corresponding outer sidewall selected from the outer sidewalls of the metal heater plate 20. In one embodiment, a pair of bottom electrode via structures 652 can be formed in a via-level dielectric layer 650 having a topmost planar section and a recessed planar section; and each outer sidewall of the metal heater plate 20 is vertically coincident with a corresponding sidewall section of the via-level dielectric layer 650, the outer sidewall connecting a corresponding one of the topmost planar sections and a corresponding one of the recessed planar sections.

[0114] In one embodiment, the spatial light modulator device further includes a dielectric liner 60 covering the top surface and sidewalls of each layer stack (20, 30, 40, 50) within the array of spatial light modulator cells 10 and contacting the top surface of the via-level dielectric layer 650, which laterally surrounds the bottom electrode via structure 652 within the array of spatial light modulator cells 10. In one embodiment, the spatial light modulator device further includes a dielectric cover layer 660 covering the dielectric liner 60, wherein a sealed cavity free of any solid material is formed within the dielectric cover layer 660 in the gap region between adjacent pairs of layer stacks (20, 30, 40, 50) within the array of spatial light modulator cells 10.

[0115] According to another aspect of the present invention, a device structure is provided, which includes: a field effect transistor 701 located on a semiconductor substrate 8; a metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) formed in a dielectric material layer, which covers the field effect transistor 701 and is electrically connected to the field effect transistor 701; and an array of spatial light modulator units 10 located above the dielectric material layer, wherein: each spatial light modulator unit 10 includes a layer stack (20, 30, 40, 50), the layer stack includes a phase change material plate 40, a spacer dielectric material plate 30 located below the phase change material plate 40, and a metal heater plate 20 located below the spacer dielectric plate 30 and including an outer side wall; and each outer side wall of the metal heater plate 20 vertically coincides with the corresponding side wall of the spacer dielectric material plate 30 and the corresponding side wall of the phase change material plate 40.

[0116] In one embodiment, each spatial light modulator cell 10 includes a pair of bottom electrode via structures 652 that contact corresponding surface segments of the bottom surface of the metal heater plate 20. In one embodiment, the field effect transistor 701 includes a heater drive transistor; and each heater drive transistor is configured to drive current through the metal heater plate 20 and the pair of bottom electrode via structures 652 within a corresponding spatial light modulator cell in the array of spatial light modulator cells 10.

[0117] In one embodiment, each spatial light modulator cell 10 includes at least one dielectric post structure 22 located in a corresponding opening through the metal heater plate 20. In one embodiment, each of the at least one dielectric post structure 22 includes a top surface in contact with a bottom surface of the spacer dielectric material plate 30 and has a thickness no less than the thickness of the metal heater plate 20.

[0118] Referring to all the drawings, according to various embodiments of the present disclosure, there is provided a method of forming a spatial light modulator device. The method may include the following steps: providing a metal interconnect structure (612, 618, 622, 628, 632, 638, 642, 648) on a semiconductor substrate 8; depositing a via-level dielectric layer 650 above the metal interconnect structure; forming a bottom electrode via structure 652 within the via-level dielectric layer 650; depositing a group of material layers (20L, 30L, 40L, 50L), including a metal heater material layer 20L, a spacer dielectric material layer 30L and a phase change material layer 40L; and patterning the group of material layers (20L, 30L, 40L, 50L) into an array of layer stacks (20, 30, 40, 50) by performing at least one anisotropic etching process, the anisotropic etching process transferring the pattern in the patterned etching mask layer 57 to each layer within the group of material layers (20L, 30L, 40L, 50L).

[0119] In one embodiment, the top surface of the via level dielectric layer 650 may be exposed after at least one anisotropic etching process; and each layer stack (20, 30, 40, 50) may include a phase change material plate 40, a spacer dielectric material plate 30, and a metal heater plate 20, the phase change material plate 40 may be a patterned portion of the phase change material layer 40L, the spacer dielectric material plate 30 may be a patterned portion of the spacer dielectric material layer 30L, and the metal heater plate 20 may be a patterned portion of the metal heater material layer 20L. In one embodiment, the method may further include the steps of: forming an array of openings through the metal heater material layer 20; and forming an array of dielectric pillar structures 22 in the array of openings before forming the spacer dielectric material layer 30. In one embodiment, the method may further include the steps of: depositing a hard mask layer 21L over the metal heater material layer 20; forming a patterned etch mask layer 21 over the hard mask layer 21L; and removing portions of the hard mask layer 21L and the metal heater material layer 20 that are not covered by the patterned etch mask layer 21, so that an array of openings may be formed through the metal heater material layer 20. In one embodiment, the method may further include the steps of: depositing a dielectric filling material 22 in the array of openings through the metal heater material layer 20; and removing portions of the dielectric filling material 22 from over the hard mask layer 21L, so that an array of dielectric pillar structures 22 may be formed. In one embodiment, the method may further include the step of forming a dielectric capping layer 660 over the array of spatial light modulator cells 10 and the array of dielectric pillar structures 22. In one embodiment, after forming the array of openings and before patterning the set of material layers (20L, 30L, 40L, 50L), the metal heater material layer 20 may not have any openings in the peripheral region; and the method may further include the step of forming a metal contact structure through the dielectric capping layer 660 in the peripheral region.

[0120] According to another aspect of the present invention, a method for forming a spatial light modulator device may be provided, the method may include the following steps: depositing a via-level dielectric layer 650 above a semiconductor substrate 8; forming a bottom electrode via structure 652 through the via-level dielectric layer 650; depositing a metal heater material layer 20L above the bottom electrode via structure 652; forming an opening in the metal heater material layer 20L; depositing a set of material layers (20L, 30L, 40L) on the metal heater material layer 20L; 0L, 50L), which includes a spacer dielectric material layer 30L, a phase change material layer 40L and a cover dielectric material layer 50L; and patterning the group of material layers (20L, 30L, 40L, 50L) and the metal heater material layer 20L into an array of layer stacks (20L, 30L, 40L, 50L) by performing at least one anisotropic etching process, wherein each layer stack includes a metal heater plate 20, a spacer dielectric material plate 30, a phase change material plate 40 and a cover dielectric material plate 50.

[0121] In one embodiment, the method may further include the following steps: forming a patterned etch mask layer 57 including an array of etch mask material portions over the set of material layers (20L, 30L, 40L, 50L); and at least one anisotropic etching process may transfer the pattern in the patterned etch mask layer 57 to each layer within the set of material layers and the metal heater material layer 20L. In one embodiment, the method may further include the following steps: forming a dielectric pillar structure 22 in the opening in the metal heater material layer 20L by depositing a dielectric fill material layer 22 in the opening of the metal heater material layer 20L and removing a portion of the dielectric fill material layer 22 from above a horizontal plane including the top surface of the metal heater material layer 20L. In one embodiment, the opening in the metal heater material layer 20L extends vertically to the bottom surface of the via-level dielectric layer 650; and the dielectric pillar structure 22 may have a sidewall extending vertically from the top surface of the metal heater material layer 20L to the bottom surface of the via-level dielectric layer 650. In one embodiment, when the opening is formed in the metal heater material layer 20L, the top surface of the via-level dielectric layer 650 may be exposed below the opening of the metal heater material layer 20L; and the dielectric pillar structure 22 may be formed directly on a section of the top surface of the via-level dielectric layer 650. In one embodiment, the metal heater material layer 20L may be patterned so that each metal heater plate 20 may include a corresponding set of at least one opening in the openings in the metal heater material layer 20L and contact a corresponding set of at least one pair of bottom electrode via structures 652 in the bottom electrode via structures 652 present in the via-level dielectric layer 650. In one embodiment, the corresponding set of at least one opening may include a plurality of openings. In one embodiment, the method may further include the steps of: depositing a dielectric liner 60 on the top surface and sidewalls of the layer stack array and on the top surface of the via-level dielectric layer 650; and depositing a dielectric cap layer 660 over the dielectric liner 60, wherein a sealed cavity free of any solid material is formed in the dielectric cap layer in the gap region between adjacent layer stack pairs in the layer stack array.

[0122] Various embodiments of the present disclosure may be used to provide a spatial light modulator device in which each phase change material plate 40 is self-aligned with the underlying metal heater plate 20. Each metal heater plate 20 may include a corresponding set of at least one opening filled with a corresponding dielectric pillar structure 22. The small pattern factor used in the planarization process of the dielectric filling material forming the dielectric pillar structure 22 enhances the coplanarity of the top surface of the dielectric pillar structure 22 with the metal heater plate 20. By forming the top surface of the dielectric pillar structure 22 within a horizontal plane including the top surface of the metal heater plate 20, the planarity of the phase change material plate 40 may be improved. The various self-alignment features of the spatial light modulator unit 10 of the present disclosure may enhance the device performance uniformity and reliability of the spatial light modulator device of the present disclosure.

[0123] According to one aspect of an embodiment of the present application, a method for forming a spatial light modulator device is provided, the method comprising: providing a semiconductor substrate having a metal interconnect structure thereon; depositing a via-level dielectric layer above the metal interconnect structure; forming a bottom electrode via structure within the via-level dielectric layer; depositing a group of material layers including a metal heater material layer, a spacer dielectric material layer, and a phase change material layer; and patterning the group of material layers into an array of layer stacks by performing at least one anisotropic etching process, the anisotropic etching process transferring a pattern in the patterned etching mask to each layer in the group of material layers.

[0124] In some embodiments, after at least one anisotropic etching process, the top surface of the through-hole level dielectric layer is exposed; and each of the layer stacks includes a phase change material plate that is a patterned portion of the phase change material layer, a spacer dielectric material plate that is a patterned portion of the spacer dielectric material layer, and a metal heater plate that is a patterned portion of the metal heater material layer.

[0125] In some embodiments, the method further includes: forming an array of openings through the layer of metallic heater material; and forming an array of dielectric post structures in the array of openings before forming the layer of spacer dielectric material.

[0126] In some embodiments, the method also includes: depositing a hard mask layer over the metal heater material layer; forming a patterned etch mask layer over the hard mask layer; and removing portions of the hard mask layer and the metal heater material layer that are not covered by the patterned etch mask layer, thereby forming an array of openings through the metal heater material layer.

[0127] In some embodiments, the method further includes depositing a dielectric fill material in the array of openings through the layer of metallic heater material; and removing portions of the dielectric fill material from over the hard mask layer to form an array of dielectric pillar structures.

[0128] In some embodiments, the method further comprises forming a dielectric cap layer over the array of spatial light modulator cells and the array of dielectric pillar structures.

[0129] In some embodiments, after forming the array of openings and before patterning the group of material layers, the metal heater material layer is free of any openings in the peripheral region; and the method includes forming a metal contact structure through the dielectric cover layer in the peripheral region.

[0130] According to another aspect of an embodiment of the present application, a method for forming a spatial light modulator device is provided, the method comprising: depositing a through-hole level dielectric layer above a semiconductor substrate; forming a bottom electrode through-hole structure passing through the through-hole level dielectric layer; depositing a metal heater material layer above the bottom electrode through-hole structure; forming an opening in the metal heater material layer; depositing a group of material layers including a spacer dielectric material layer, a phase change material layer and a cover dielectric material layer on the metal heater material layer; and patterning the group of material layers and the metal heater material layer into an array of layer stacks by performing at least one anisotropic etching process, wherein each of the layer stacks includes a metal heater plate, a spacer dielectric material plate, a phase change material plate and a cover dielectric material plate.

[0131] In some embodiments, the method includes forming a patterned etch mask layer including an array of etch mask material portions over the group of material layers; and at least one anisotropic etching process transferring a pattern in the patterned etch mask layer to each of the group of material layers and the metal heater material layer.

[0132] In some embodiments, the method further includes forming a dielectric pillar structure in the opening of the metallic heater material layer by depositing a dielectric fill material layer in the opening of the metallic heater material layer and removing a portion of the dielectric fill material layer from above a level including a top surface of the metallic heater material layer.

[0133] In some embodiments, the opening in the metal heater material layer extends vertically to the bottom surface of the via level dielectric layer; and the dielectric pillar structure has sidewalls extending vertically from the top surface of the metal heater material layer to the bottom surface of the via level dielectric layer.

[0134] In some embodiments, when forming the opening in the metal heater material layer, the top surface of the via level dielectric layer is exposed below the opening in the metal heater material layer; and the dielectric pillar structure is formed directly on a section of the top surface of the via level dielectric layer.

[0135] In some embodiments, the metal heater material layer is patterned such that each metal heater plate includes a corresponding group of at least one of the openings in the metal heater material layer and contacts at least one pair of bottom electrode via structures of a corresponding group present in the via level dielectric layer.

[0136] In some embodiments, the respective set of at least one opening comprises a plurality of openings.

[0137] In some embodiments, the method also includes: depositing a dielectric liner over the top surface and side walls of the array of layer stacks and over the top surface of the through-hole level dielectric layer; and depositing a dielectric cover layer over the dielectric liner, wherein a sealed cavity free of any solid material is formed within the dielectric cover layer in the gap region between adjacent pairs of layer stacks within the array of layer stacks.

[0138] According to another aspect of an embodiment of the present application, a spatial light modulator device is provided, comprising: a field effect transistor located on a semiconductor substrate; a metal interconnect structure formed in a dielectric material layer overlying the field effect transistor and electrically connected to the field effect transistor; and an array of spatial light modulator units located above the dielectric material layer, wherein: each of the spatial light modulator units includes a layer stack, the layer stack includes a phase change material plate, a spacer dielectric material plate located below the phase change material plate, and a metal heater plate located below the spacer dielectric material plate and including an outer side wall; and each outer side wall of the metal heater plate vertically coincides with a corresponding side wall of the spacer dielectric material plate and a corresponding side wall of the phase change material plate.

[0139] In some embodiments, each of the spatial light modulator cells includes a pair of bottom electrode via structures contacting corresponding surface segments of the bottom surface of the metal heater plate.

[0140] In some embodiments, the field effect transistors include heater drive transistors; and each of the heater drive transistors is configured to drive a current through a pair of metal heater plates and bottom electrode via structures within a corresponding spatial light modulator cell within the array of spatial light modulator cells.

[0141] In some embodiments, each spatial light modulator cell includes at least one dielectric post structure positioned in a corresponding opening through the metallic heater plate.

[0142] In some embodiments, each of the at least one dielectric pillar structure includes a top surface contacting a bottom surface of the spacer dielectric material plate and has a thickness no less than a thickness of the metallic heater plate.

[0143] The foregoing summarizes the features of various embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Each embodiment described using the word "comprising" is also inherently disclosed, and in some embodiments, the word "comprising" can be replaced by the word "consisting essentially of..." or "consisting of...", unless otherwise explicitly disclosed herein. Whenever two or more elements are listed as alternatives in the same paragraph or in different paragraphs, the Markush group of the list including these two or more elements can also be implicitly disclosed in some embodiments. Whenever the auxiliary verb "may" is used in this disclosure to describe the formation of an element or the execution of a process step, embodiments in which such an element or such a process step is not performed are also explicitly considered, as long as the resulting device or apparatus can provide equivalent results. Therefore, the auxiliary verb "may" applied to the formation of an element or the execution of a process step should also be interpreted as "may" or "may, or may not", as long as the omission of such an element or such a process step can provide the same result or an equivalent result, and equivalent results include slightly superior results and slightly inferior results. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or obtaining the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not deviate from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications here without departing from the spirit and scope of this disclosure.

Claims

1. A method of forming a spatial light modulator device, the method comprising: Providing a semiconductor substrate having a metal interconnect structure thereon; depositing a via level dielectric layer over the metal interconnect structure; forming a bottom electrode via structure in the via level dielectric layer; depositing a group of material layers including a metal heater material layer, a spacer dielectric material layer, and a phase change material layer; as well as The set of material layers is patterned into an array of layer stacks by performing at least one anisotropic etching process that transfers a pattern in a patterned etch mask to each layer in the set of material layers.

2. The method according to claim 1, wherein: After the at least one anisotropic etching process, exposing a top surface of the via level dielectric layer; and Each of the layer stacks includes a phase change material plate that is a patterned portion of the phase change material layer, a spacer dielectric material plate that is a patterned portion of the spacer dielectric material layer, and a metal heater plate that is a patterned portion of the metal heater material layer.

3. The method according to claim 1, further comprising: forming an array of openings through the layer of metallic heater material; as well as Prior to forming the spacer dielectric material layer, an array of dielectric pillar structures is formed in the array of openings.

4. The method according to claim 3, further comprising: depositing a hard mask layer over the metal heater material layer; forming a patterned etch mask layer over the hard mask layer; as well as Portions of the hard mask layer and the metallic heater material layer not covered by the patterned etch mask layer are removed to form an array of openings through the metallic heater material layer.

5. The method according to claim 4, further comprising: depositing a dielectric fill material in the array of openings through the layer of metallic heater material; as well as Portions of the dielectric fill material are removed from over the hard mask layer to form an array of dielectric pillar structures.

6. A method of forming a spatial light modulator device, the method comprising: depositing a via level dielectric layer over the semiconductor substrate; forming a bottom electrode via structure through the via level dielectric layer; depositing a layer of metal heater material over the bottom electrode via structure; forming an opening in the layer of metallic heater material; depositing a group of material layers including a spacer dielectric material layer, a phase change material layer, and a cap dielectric material layer on the metal heater material layer; as well as The group of material layers and the metal heater material layer are patterned into an array of layer stacks by performing at least one anisotropic etching process, wherein each of the layer stacks includes a metal heater plate, a spacer dielectric material plate, a phase change material plate, and a cover dielectric material plate.

7. The method according to claim 6 also includes forming a dielectric pillar structure in the opening of the metal heater material layer by depositing a dielectric filling material layer in the opening of the metal heater material layer and removing a portion of the dielectric filling material layer from above a horizontal plane including a top surface of the metal heater material layer.

8. The method according to claim 7, wherein: the openings in the metal heater material layer extending vertically to the bottom surface of the via-level dielectric layer; and The dielectric pillar structure has sidewalls extending vertically from a top surface of the metal heater material layer to a bottom surface of the via-level dielectric layer.

9. The method according to claim 6, further comprising: depositing a dielectric liner over a top surface and sidewalls of the array of layer stacks and a top surface of the via-level dielectric layer; as well as A dielectric cap layer is deposited over the dielectric liner, wherein a sealed cavity free of any solid state material is formed within the dielectric cap layer in gap regions between adjacent pairs of layer stacks within the array of layer stacks.

10. A spatial light modulator device, comprising: Field effect transistor, located on a semiconductor substrate; a metal interconnect structure formed in a dielectric material layer overlying the field effect transistor and electrically connected to the field effect transistor; as well as an array of spatial light modulator cells located above the layer of dielectric material, wherein: Each of the spatial light modulator cells comprises a layer stack including a phase change material plate, a spacer dielectric material plate located below the phase change material plate, and a metal heater plate located below the spacer dielectric material plate and including an outer sidewall; and Each outer sidewall of the metal heater plate is vertically coincident with a corresponding sidewall of the spacer dielectric material plate and a corresponding sidewall of the phase change material plate.

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