Low quiescent current loop adaptive regulation linear voltage regulator

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a low quiescent current loop adaptive regulation linear voltage regulator which comprises a power detection comparator, an adaptive current source, a loop regulation module, a PMOS (P-channel Metal Oxide Semiconductor) tube Mp, an NMOS (N-channel Metal Oxide Semiconductor) tube Mc, a grid discharge module, a capacitor Cm, an error operational amplifier, a band-gap reference and three resistors R1, R2 and Rm, all the devices are connected in sequence to form the low quiescent current loop self-adaptive regulation linear voltage regulator; by designing the low quiescent current loop adaptive adjustment linear voltage regulator circuit, the low quiescent current loop adaptive adjustment linear voltage regulator circuit can have the characteristics of low quiescent current and quick response at the same time, adaptive adjustment is carried out when load current and input and output voltage difference change, and high response speed is ensured while static power consumption is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a low quiescent current loop adaptive regulation linear regulator. Background Art

[0002] Low Dropout Regulator (LDO) is widely used in portable electronic devices, wearable applications and system on chip (SOC) due to its good voltage stability and small size. Traditional LDO consumes static current when working, while low static current LDO chip is energy-saving and efficient, consuming less power when the whole device is in standby or quiescent state, and can be widely used in long-time standby devices such as batteries, communications, radars, etc.

[0003] Existing low quiescent current linear regulators are mainly achieved by using high-square-value resistors in the branches to reduce the current in each internal branch; Figure 1 As shown, it is composed of a bandgap reference, an error op amp, a current source, a power tube Mp and a control tube Mc, as well as feedback resistors R1 and R2. Since the bias provided by the current source is fixed, if the current setting is large, the static power consumption increases; if the current setting is small, when the load changes, the loop response speed will slow down, and even feedback adjustment cannot be performed. However, the main defect of this low quiescent current LDO is that due to the relatively small static current inside the loop, the loop feedback speed is slow and the response time is long. At the same time, under heavy load working conditions, there is also the risk of abnormal loop function due to weak response capability. Therefore, many low quiescent current LDOs cannot further reduce static power consumption or cannot operate under heavy load current. This also limits the scope of application of low quiescent current LDOs. Summary of the invention

[0004] In order to solve the problems existing in the above prior art, the present invention proposes a low static current loop adaptive regulation linear regulator, including: a power detection comparator, an adaptive current source, a loop regulation module, a PMOS tube Mp, an NMOS tube Mc, a gate discharge module, a capacitor Cm, an error amplifier, a bandgap reference and three resistors R1, R2, and Rm;

[0005] The connection relationship of each device includes: the output end of the bandgap reference is connected to the positive input end of the error amplifier; the negative input end of the error amplifier is respectively connected to one end of the resistors R1 and R2, and the output end of the error amplifier is respectively connected to the output end of the gate discharge module, one end of the resistor Rm and the gate of Mc; the other end of the resistor R2 is grounded; the other end of the resistor R1 is respectively connected to the drain of Mp and the negative input end of the power detection comparator; the positive input end of the power detection comparator is connected to the input end of the adaptive current source and the source of Mp, the first output end of the power detection comparator is connected to the first input end of the loop regulation module, and the second output end of the power detection comparator is connected to the input end of the gate discharge module; the output end of the adaptive current source is connected to the second input end of the loop regulation module; the third input end of the loop regulation module is connected to the gate of Mp, and the output end of the loop regulation module is connected to one end of Cm and the drain of Mc; the other end of Cm is connected to the other end of Rm; the source of Mc is grounded; and the other end of the resistor R2 is grounded.

[0006] Beneficial effects of the present invention:

[0007] The present invention designs a low quiescent current loop adaptive regulation linear regulator circuit, which can have the characteristics of low quiescent current and fast response at the same time, and performs adaptive adjustment when the load current and the input-output voltage difference change, thereby reducing the quiescent power consumption and ensuring a faster response speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of the structure of a traditional linear regulator;

[0009] Figure 2 The circuit structure diagram of the low quiescent current loop adaptive regulation linear voltage regulator of the present invention;

[0010] Figure 3 is a structural diagram of an adaptive current source circuit of the present invention;

[0011] Figure 4 is a circuit structure diagram of a power detection comparator of the present invention;

[0012] Figure 5 is a circuit structure diagram of the loop regulation module of the present invention;

[0013] Figure 6 is a circuit structure diagram of the gate discharge module of the present invention;

[0014] Figure 7 This is a simulation diagram comparing the power-on speed of the circuit of the present invention and the traditional LDO;

[0015] Figure 8 It is a simulation diagram comparing transient load responses of the circuit of the present invention and traditional LDO. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] The present invention aims to solve the above-mentioned problem of the low quiescent current LDO chip, and provides a low quiescent current loop adaptive regulation linear regulator circuit, which can have lower quiescent power consumption and faster loop response speed.

[0018] A low quiescent current loop adaptive regulation linear regulator, such as Figure 2 As shown, it includes: a power detection comparator, an adaptive current source, a loop adjustment module, a PMOS tube Mp, an NMOS tube Mc, a gate discharge module, a capacitor Cm, an error amplifier, a bandgap reference and three resistors R1, R2, and Rm; wherein the output end of the bandgap reference is connected to the positive input end of the error amplifier; the negative input end of the error amplifier is respectively connected to one end of the resistors R1 and R2, and the output end of the error amplifier is respectively connected to the output end of the gate discharge module, one end of the resistor Rm and the gate of Mc; the other end of the resistor R2 is grounded; the other end of the resistor R1 is respectively connected to the drain of Mp and the power detection The negative input terminal of the power detection comparator is connected to the input terminal of the adaptive current source and the source of Mp; the first output terminal of the power detection comparator is connected to the first input terminal of the loop regulation module, and the second output terminal of the power detection comparator is connected to the input terminal of the gate discharge module; the output terminal of the adaptive current source is connected to the second input terminal of the loop regulation module; the third input terminal of the loop regulation module is connected to the gate of Mp, and the output terminal of the loop regulation module is connected to one terminal of Cm and the drain of Mc; the other terminal of Cm is connected to the other terminal of Rm; the source of Mc is grounded; and the other terminal of the resistor R2 is grounded.

[0019] In this embodiment, the adaptive current source detects the difference between the input voltage and the gate voltage of the power tube, that is, the V GS When the voltage difference is small, the adaptive current source uses a small current channel and only provides a small static current to maintain the operation of the loop. When the voltage difference exceeds the threshold, the current source will open a large current channel to provide sufficient current for the loop response. The power detection comparator can detect the voltage difference between the input and output. Depending on the voltage difference, the control loop adjustment module and the gate discharge module control the control tube M c The loop regulation module receives the output voltage of the power detection comparator, selects and regulates M cThe current channel at the drain end ensures the matching of the loop response capability; the gate discharge module receives another output voltage of the power detection comparator, controls the output voltage of the error amplifier EA, and quickly discharges the voltage when necessary to improve the loop response speed. The error amplifier and the bandgap reference can be selected from the existing ordinary amplifier structure and the reference structure as the corresponding functional module in the present invention. In the linear regulator, the positive input end of the power detection comparator is used as the input end of the entire circuit, and the Vin signal is input into the device; the drain of Mp is used as the output end of the device.

[0020] like Figure 4 As shown, the power detection comparator includes: 5 NMOS tubes M6-M10, 8 PMOS tubes M4, M5, M11-M16 and 6 resistors R6-R11; one end of the resistor R6 is connected to the source of M11, the source of M12, the source of M13 and the source of M14, and the signal Vin is input; the other end of the resistor R6 is connected to the source of M4, and the gate of M4 is respectively connected to the drain of M4 and one end of R8; the other end of R8 is respectively connected to the gate of M8 and one end of R9; the other end of R9 is connected to the drain of M6; the gate of M6 is connected to the gate of M7 and the gate of M10, and the source of M6 is grounded; the source of M7 is grounded, and the drain of M7 is respectively connected to the drain of M5, the gate of M5 and the gate of M9; the source of M5 is connected to One end of resistor R7 is connected; the other end of R7 inputs Vout signal; the source of M10 is grounded, and the drain of M10 is respectively connected to the source of M9 and the source of M8; the drain of M8 is connected to one end of resistor R10; the other end of R10 is respectively connected to the drain of M11, the gate of M11 and the gate of M13; the drain of M9 is connected to one end of resistor R11; the other end of R11 is respectively connected to the drain of M12, the gate of M12 and the gate of M14; the drain of M13 is connected to the source of M15; the gate of M15 is connected to the gate of M16 and connected to Vb2 signal, and the drain of M15 serves as the first output end of the power detection comparator; the source of M16 is connected to the drain of M14, and the drain of M16 serves as the second output end of the power detection comparator.

[0021] like Figure 3 As shown, the adaptive current source includes a PMOS tube M1, two diodes D1-D2 and three resistors R1-R3; the source of M1 is respectively connected to one end of R3 and the positive electrode of D1 and then connected to the signal Vin, the gate of M1 is respectively connected to one end of the resistor R5 and the negative electrode of D2 and then connected to the signal Ic, the drain of M1 is respectively connected to the other end of the resistor R3 and one end of the resistor R4; the other end of the resistor R4 is respectively connected to the other end of the resistor R5, the positive electrode of D2 and the negative electrode of D1; the gate of M1 is used as the signal output end of the adaptive current source.

[0022] like Figure 5As shown, the loop regulation module includes: a transistor Q1, three resistors R12~R14, two capacitors C1~C2 and three NMOS tubes M17~M19; the collector of Q1 is respectively connected to the base of Q1, the gate of M17, one end of the resistor R13 and one end of the capacitor C2, and the emitter of Q1 is respectively connected to one end of the resistor R12 and one end of the capacitor C1; the other end of the resistor R12, the other end of the capacitor C1 and the other end of the capacitor C2 are all grounded; the other end of the resistor R13 is respectively connected to the source of M17 and the gate of M18; the drain of M17 is connected to the gate of M19; the drain of M18 is connected to one end of the resistor R14, the source of M18 is connected to the source of M19, and serves as the output end of the loop regulation module; the other end of the resistor R14 is connected to the drain of M19.

[0023] In this embodiment, the collector of transistor Q1 in the loop regulation module is used as the first input terminal of the loop regulation module, the drain of M18 is used as the second input terminal of the loop regulation module, and the drain of M17 is used as the third input terminal of the loop regulation module.

[0024] like Figure 6 As shown, the gate discharge module includes: 9 NMOS tubes M20-M28, 2 triodes Q2-Q3 and 1 resistor R15; the source of M20, the source of M21, the source of M22, the emitter of Q2, the source of M23 and the emitter of Q3 are all grounded; the drain of M20 is respectively connected to the gate of M20, the gate of M21, the gate of M22 and the gate of M23; the drain of M21 is respectively connected to the collector of Q2, the gate of M24, the gate of M25, the collector of M2 The gate of M26, the gate of M27 and the gate of M28 are connected; the drain of M22 is connected to the base of Q2, the source of M24, the source of M25, the source of M26 and the source of M27 respectively; the drain of M24 is connected to the drain of M23, the drain of M26, the drain of M27 and the drain of M28 respectively; the source of M28 is connected to one end of the resistor R15 and the drain of M23 respectively; the other end of R15 is connected to the base of Q3; the collector of Q3 serves as the output end of the gate discharge module.

[0025] The adaptive current source, power detection comparator, loop adjustment module, and gate discharge module specifically implemented by the present invention are shown in the attached Figure 3 , Figure 4 , Figure 5 , Figure 6 shown. Figure 3 The adaptive current source of the present invention has an input terminal connected to the Vin voltage and an output terminal connected to the power tube gate. The function is to detect the difference between the input voltage and the power tube gate voltage to adjust the current source current I cThe module is mainly composed of M1 PMOS tube and D1 diode to form a current control channel, resistors R3, R4, R5 as current distribution resistors, and diode D2 as a clamping diode. Among them, the resistance of R3 and R4 is much larger than R5. When the load current I D When it is small, the power tube has:

[0026]

[0027] Among them, V GS is the gate-source voltage of the power tube, I D is the load current flowing through the power tube, μ n is the electron migration rate, C ox is the gate oxide capacitance per unit area, W is the channel width, L is the channel length, V TH The threshold for turning on the power tube.

[0028] Because I D is smaller, the pressure difference V GS It is also relatively small. At this time, the M1 tube is turned on, and the current flows from Vin through M1, R3, R4, and R5 to output the current I c , which is approximately

[0029]

[0030] Among them, I c The bias current provided by the current source at this time, R on1 is the on-resistance of tube M1, R3 is the resistance value of resistor R3, R4 is the resistance value of resistor R4, and R5 is the resistance value of resistor R5.

[0031] As the load current increases, due to the negative feedback regulation of the LDO loop, the gate voltage of the power tube decreases, V GS At this time, the M1 tube is fully turned on, and the diode D1 is turned on. The current flows from Vin through M1, R3, R4, D1 and R5 to output the current I c , the current is approximately:

[0032]

[0033] Among them, R D1 is the on-resistance of diode D1.

[0034] If the load changes greatly, the gate voltage of the power tube will drop significantly instantly. GS Further increase to V THD1 +V THD2 When M1, D1, and D2 are all turned on, most of the current flows directly from D1 and D2 to provide I c , and D2 forms a clamping circuit to prevent VGS The gap is too big. THD1 and V THD2 are the forward conduction threshold voltages of diodes D1 and D2 respectively.

[0035] In this embodiment, Figure 4 The power detection comparator of the present invention is used to provide a control voltage for the loop regulation module and the gate discharge module by detecting the voltage difference between the power supply Vin and the output Vout. It mainly consists of three parts: (1) input sampling, which is composed of resistors R6, R7, R8, R9, PMOS tubes M4, M5, and NMOS tubes M6 and M7, wherein R6 and R7 are used to reduce the branch current, R8 and R9 are used to set the sampling voltage of Vin, and the sampling ratio is determined by adjusting the ratio of R8 and R9. M6 and M7 provide bias current. This part mainly transmits the voltage changes of Vin and Vout to the lower comparator; (2) Comparator, composed of NMOS tubes M8, M9, M10, PMOS tubes M11, M12, M13, M14, M15, M16 and resistors R10, R11, where R10, R11 are used to reduce branch current, M11, M12 are active loads, M8, M9 are input differential pair tubes, and M10 provides tail current. M13, M14, M15, M16 are the second-level common source and common gate structure to amplify the control signal. This part mainly detects the voltage difference change between Vin and Vout sampling voltage, outputs gate discharge signal Vsink and loop adjustment signal Vc, to further control the loop. When the voltage difference increases, the drain voltage of M9 decreases and the drain voltage of M8 increases, thereby reducing the output voltage Vsink of the second-stage cascode amplifier composed of M14 and M16 and increasing the drain output voltage Vctrl of M13 and M15.

[0036] Figure 5 The loop regulation module of the present invention has an Ic terminal connected to the current provided by the adaptive current source, and the loop regulation output terminal is connected to the drain end of the control NMOS tube Mc below, which is used to receive the loop regulation voltage Vctrl, and control the gate voltage of M18 and M19 through the voltage, thereby controlling the current channel flowing into the drain end of the Mc tube. M18 and M19 are high-voltage LDMOS, which are used to withstand the high voltage of the power gate. Q1, R12 and C1 convert the current flowing out of the loop regulation signal Vctrl port into a stable voltage through resistors and capacitors, M17, R13, and C2 are used to control the gate voltage of the M18 tube, wherein M17 is the main voltage control tube, and C2 and R13 are used to provide a stable control voltage for M18 after the loop is stable, while avoiding the threshold voltage V of M17. TH7This causes a loss in control voltage. M18, M19 and R14 form a channel for the loop current. When the Vctrl signal is low, the voltage at the source end of M17 is low, which makes the M18 tube open weakly and less current can pass through it. The M19 tube is controlled by the bias voltage Vb and is in a constant open state. The loop current only passes through M19 and R14. Since the resistance of R14 is large, in this case, the drain current of the control tube Mc is limited, and the overall loop will operate with a very small static current; when the Vctrl signal becomes larger, Q1 will form a stable voltage through R12 and C1 with the current flowing out of the Vctrl end, and increase the gate voltage of M17. When Vctrl>V TH17 When Vctrl-V TH17 >V GS18 When M18 is turned on, the degree of M18 opening increases, and the current passing through increases. At this time, the loop current flows through two channels at the same time, which speeds up the loop response speed. Then, the source voltage of M17 becomes consistent with Vctrl, and M18 continues to be turned on, which can maintain stability even when Vctrl changes transiently.

[0037] In this embodiment, Figure 6 The gate discharge module of the present invention has a gate discharge output connected to the gate of the control tube Mc, and its function is to receive the gate discharge signal Vsink, and discharge the output voltage of the error amplifier through the voltage control discharge NPN tube Q3 to accelerate the loop response. NMOS tubes M20, M21, M22, and M23 constitute a bias circuit for providing the bias current of the module, M24, M25, M26, M27, and Q2 constitute a clamping circuit to prevent the Vsink voltage from being too high instantly, and M28, R15, and Q3 constitute a discharge path for discharging the error amplifier output to reduce the voltage. When Vsink is a low voltage, M24, M25, M26, M27, and M28 are not turned on, and the module does not work. When the Vsink voltage is high, the five NMOS tubes are turned on, the source terminal potential of M28 increases, and the current is generated to control the base of Q3, and the NPN tube Q3 is turned on, thereby pulling down the output of the error amplifier. When Vsink is instantaneously high, since M24, M25, M26, and M27 have stronger current capabilities than M28, according to the power tube formula, the base voltage of Q2 will be higher than the base voltage of Q3. At this time, if Q2 is turned on, the Vsink voltage will be pulled down to prevent the voltage from being too high and causing damage to M28 and Q3.

[0038] The principle of the overall circuit module of the present invention is explained below: when the voltage difference between the input Vin and the output Vout is small, and the load current is small, the adaptive current source outputs a smaller current Ic, and the power detection module outputs a lower loop regulation signal Vctrl and a higher gate discharge signal Vsink, the Vctrl voltage control loop regulation module only opens the low static current channel, and the Vsink voltage pulls down the error amplifier output through the discharge path, so that the power tube gate voltage increases as soon as possible, and the LDO is in the lowest static power consumption mode as a whole; when the load current becomes larger, the adaptive current source opens other channels, thereby outputting a larger current Ic, and the loop regulation signal Vctrl output by the power detection module increases, and the gate discharge signal Vsink decreases, so that the Vctrl voltage control loop regulation module opens a large static current channel, and the Vsink voltage closes the discharge path to reduce the power tube gate voltage. The overall quiescent current of the LDO increases, which improves the response speed of the loop; when the voltage difference between the input Vin and the output Vout is large, and the load current is small, the output current Ic of the adaptive current source is still small, and the quiescent current does not increase much, but the loop current channel opens a large current channel, which facilitates rapid feedback response when Ic increases rapidly after the load increases. Figure 7 The instantaneous power-on simulation diagram of the circuit of the present invention and the traditional low-power LDO shows that the power-on speed of the present invention is much faster than that of the traditional LDO due to the existence of a large current channel, and the static current does not increase significantly after stabilization; Figure 8 The load transient response simulation diagram of the circuit of the present invention and the traditional low-power LDO is shown. When the load suddenly increases, the response speed of the circuit of the present invention is significantly faster than that of the traditional LDO circuit.

[0039] Figure 7 The upper middle part shows the output voltage of the traditional low-power LDO, and the lower part shows the output voltage waveform of the invention. It can be seen that under a larger Vin and Vout voltage difference, the response speed of the invention is much faster than that of the ordinary LDO circuit.

[0040] Figure 8 The upper middle part shows the output voltage waveform of the traditional low-power LDO when the load changes suddenly, and the lower part shows the output voltage waveform of the present invention when the load changes suddenly. It can be seen that the load transient response speed of the present invention is much faster than that of the ordinary LDO circuit.

[0041] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A low quiescent current loop adaptive regulation linear regulator, characterized in that: include: Power detection comparator, adaptive current source, loop regulation module, PMOS tube Mp, NMOS tube Mc, gate discharge module, capacitor Cm, error amplifier, bandgap reference and three resistors R1, R2, Rm; The output end of the bandgap reference is connected to the positive input end of the error amplifier; the negative input end of the error amplifier is respectively connected to one end of the resistors R1 and R2, and the output end of the error amplifier is respectively connected to the output end of the gate discharge module, one end of the resistor Rm and the gate of Mc; the other end of the resistor R2 is grounded; the other end of the resistor R1 is respectively connected to the drain of Mp and the negative input end of the power detection comparator; the positive input end of the power detection comparator is connected to the input end of the adaptive current source and the source of Mp, the first output end of the power detection comparator is connected to the first input end of the loop regulation module, and the second output end of the power detection comparator is connected to the input end of the gate discharge module; the output end of the adaptive current source is connected to the second input end of the loop regulation module; the third input end of the loop regulation module is connected to the gate of Mp, and the output end of the loop regulation module is connected to one end of Cm and the drain of Mc; the other end of Cm is connected to the other end of Rm; the source of Mc is grounded; the other end of the resistor R2 is grounded.

2. The low quiescent current loop adaptive regulation linear regulator according to claim 1, characterized in that: In the linear regulator, the positive input terminal of the power detection comparator is used as the input terminal of the entire circuit, and the Vin signal is input into the device; the drain of Mp is used as the output terminal of the device.

3. The low quiescent current loop adaptive regulation linear regulator according to claim 1, characterized in that: The power detection comparator includes: 5 NMOS tubes M6-M10, 8 PMOS tubes M4, M5, M11-M16 and 6 resistors R6-R11; one end of the resistor R6 is connected to the source of M11, the source of M12, the source of M13 and the source of M14, and the signal Vin is input; the other end of the resistor R6 is connected to the source of M4, and the gate of M4 is respectively connected to the drain of M4 and one end of R8; the other end of R8 is respectively connected to the gate of M8 and one end of R9; the other end of R9 is connected to the drain of M6; the gate of M6 is connected to the gate of M7 and the gate of M10, and the source of M6 is grounded; the source of M7 is grounded, and the drain of M7 is respectively connected to the drain of M5, the gate of M5 and the gate of M9; the source of M5 is connected to the One end of resistor R7 is connected; the other end of R7 inputs Vout signal; the source of M10 is grounded, and the drain of M10 is respectively connected to the source of M9 and the source of M8; the drain of M8 is connected to one end of resistor R10; the other end of R10 is respectively connected to the drain of M11, the gate of M11 and the gate of M13; the drain of M9 is connected to one end of resistor R11; the other end of R11 is respectively connected to the drain of M12, the gate of M12 and the gate of M14; the drain of M13 is connected to the source of M15; the gate of M15 is connected to the gate of M16 and connected to Vb2 signal, and the drain of M15 serves as the first output end of the power detection comparator; the source of M16 is connected to the drain of M14, and the drain of M16 serves as the second output end of the power detection comparator.

4. The low quiescent current loop adaptive regulation linear regulator according to claim 1, characterized in that: The adaptive current source includes a PMOS tube M1, two diodes D1-D2 and three resistors R1-R3; the source of M1 is respectively connected to one end of R3 and the positive electrode of D1 and then connected to the signal Vin, the gate of M1 is respectively connected to one end of the resistor R5 and the negative electrode of D2 and then connected to the signal Ic, the drain of M1 is respectively connected to the other end of the resistor R3 and one end of the resistor R4; the other end of the resistor R4 is respectively connected to the other end of the resistor R5, the positive electrode of D2 and the negative electrode of D1; the gate of M1 is used as the signal output end of the adaptive current source.

5. The low quiescent current loop adaptive regulation linear regulator according to claim 1, characterized in that: The loop regulation module includes: a transistor Q1, three resistors R12-R14, two capacitors C1-C2 and three NMOS tubes M17-M19; the collector of Q1 is respectively connected to the base of Q1, the gate of M17, one end of the resistor R13 and one end of the capacitor C2, and the emitter of Q1 is respectively connected to one end of the resistor R12 and one end of the capacitor C1; the other end of the resistor R12, the other end of the capacitor C1 and the other end of the capacitor C2 are all grounded; the other end of the resistor R13 is respectively connected to the source of M17 and the gate of M18; the drain of M17 is connected to the gate of M19; the drain of M18 is connected to one end of the resistor R14, the source of M18 is connected to the source of M19, and serves as the output end of the loop regulation module; the other end of the resistor R14 is connected to the drain of M19.

6. The low quiescent current loop adaptive regulation linear regulator according to claim 5, characterized in that: The collector of transistor Q1 in the loop regulation module is used as the first input terminal of the loop regulation module, the drain of M18 is used as the second input terminal of the loop regulation module, and the drain of M17 is used as the third input terminal of the loop regulation module.

7. The low quiescent current loop adaptive regulation linear regulator according to claim 1, characterized in that: The gate discharge module includes: 9 NMOS tubes M20~M28, 2 triodes Q2~Q3 and 1 resistor R15; the source of M20, the source of M21, the source of M22, the emitter of Q2, the source of M23 and the emitter of Q3 are all grounded; the drain of M20 is respectively connected to the gate of M20, the gate of M21, the gate of M22 and the gate of M23; the drain of M21 is respectively connected to the collector of Q2, the gate of M24, the gate of M25, the gate of M26 The gate of M22 is connected to the base of Q2, the source of M24, the source of M25, the source of M26 and the source of M27 respectively; the drain of M24 is connected to the drain of M23, the drain of M26, the drain of M27 and the drain of M28 respectively; the source of M28 is connected to one end of the resistor R15 and the drain of M23 respectively; the other end of R15 is connected to the base of Q3; the collector of Q3 serves as the output end of the gate discharge module.

8. The low quiescent current loop adaptive regulation linear regulator according to claim 7, characterized in that: M20, M21, M22, and M23 in the gate discharge module constitute a bias circuit for providing a bias current for the module; M24, M25, M26, M27, and Q2 constitute a clamping circuit for preventing the instantaneous voltage of the gate discharge signal from increasing; M28, R15, and Q3 constitute a discharge path for discharging the error amplifier output.

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