Solid-state disk write cache management method and device

Abstract

The embodiment of the invention discloses a solid-state disk write cache management method and device, and relates to the technical field of data processing. According to the solid-state disk write cache management method provided by the embodiment of the invention, when the write data request is received and the solid-state disk onboard cache is full, the write-back operation is executed only when the target physical block of the target chip is in the non-erased state and the effective data size of the first to-be-written-back data is equal to the size of the physical page; according to the method and the device, the waiting time delay caused by the erasing operation can be avoided, the writing delay is obviously reduced, so that the performance of the SSD is improved, the data written back each time can be ensured to be a complete physical page, and the writing operation frequency is reduced by reducing the writing operation of part of pages, so that the service life of the SSD is prolonged.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a solid state disk write cache management method and device. Background Art

[0002] A solid state drive (SSD) is a hard disk that uses solid-state electronic storage media (such as NAND Flash) as storage media. Compared with traditional mechanical hard disks (HDDs), SSDs have advantages such as faster data read and write speeds, more compact physical size, and better resistance to physical shocks. However, the NAND Flash used in SSDs has a certain write / erase life limit, and the working mechanism of NAND Flash requires that the corresponding erase operation must be completed before a new write operation is performed. This process consumes the life of the SSD, resulting in performance degradation and shortened service life after long-term operation.

[0003] In the related art, the cache hit rate is usually improved by optimizing the cache algorithm, that is, increasing the chances of data being read directly from the faster cache rather than from the slower NAND Flash. By preloading data that is expected to be frequently accessed into the cache, the number of direct writes to the NAND Flash can be significantly reduced, thereby reducing the frequency of erase operations and reducing wear on the SSD.

[0004] In actual applications, data access patterns and loads are constantly changing. For example, a server may process tasks with completely different data access patterns and loads at different times of the day. Therefore, the cache algorithm needs to be able to adapt to the changing data access patterns and loads to maintain a high cache hit rate. However, when the storage space of the SSD approaches its capacity limit, it becomes more difficult to allocate data between the cache and the NAND Flash memory. At this time, the SSD must perform garbage collection operations more frequently to clear data that is no longer needed to make room for new write requests. This will not only increase latency, but also accelerate the wear rate of the SSD, further affecting its performance and lifespan. Summary of the invention

[0005] Based on the above problems, the present application provides a solid state drive write cache management method and device, which can improve the performance and life of the SSD.

[0006] The embodiments of the present application disclose the following technical solutions:

[0007] In a first aspect, an embodiment of the present application discloses a solid state drive write cache management method, the method comprising:

[0008] When a write data request is received and the onboard cache of the solid-state disk is full, determining first data to be written back and a target physical block of a target chip corresponding to the first data to be written back, wherein the first data to be written back is the first data in a least recently used LRU linked list in the onboard cache of the solid-state disk;

[0009] When the target physical block of the target chip is in an unerased state and the valid data size of the first data to be written back is equal to the size of the physical page, the first data to be written back is written into the target physical block of the target chip corresponding to the first data to be written back.

[0010] Optionally, the method further comprises:

[0011] When the target physical block of the target chip is in an erase state, determining second data to be written back and a target physical block of the target chip corresponding to the second data to be written back, wherein the second data to be written back is the next data in the LRU linked list in the onboard cache of the solid state disk;

[0012] If the valid data size of the second data to be written back is equal to the size of the physical page, the second data to be written back is written into a target physical block of a target chip corresponding to the second data to be written back.

[0013] Optionally, the method further comprises:

[0014] If the effective data size of the second data to be written back is smaller than the size of the physical page, determining the third data to be written back, wherein the sum of the effective data size of the second data to be written back and the effective data size of the third data to be written back is equal to the size of the physical page;

[0015] The second data to be written back and the third data to be written back are written into a target physical block of a target chip corresponding to the second data to be written back.

[0016] Optionally, the method further comprises:

[0017] When a write data request is received and the onboard cache of the solid state disk is not full, the to-be-written data corresponding to the write data request is divided according to the size of the physical page to obtain a plurality of to-be-written sub-data;

[0018] The multiple sub-data to be written are added to the tail of the LRU linked list.

[0019] Optionally, determining the first data to be written back and the target physical block of the target chip corresponding to the first data to be written back includes:

[0020] Determine the first data to be written back according to the LRU linked list;

[0021] The target physical block of the target chip corresponding to the first data to be written back is determined by page mapping.

[0022] In a second aspect, an embodiment of the present application provides a solid-state disk write cache management device, the device comprising: a first determination module and a first writing module;

[0023] The first determination module is used to determine the first data to be written back and the target physical block of the target chip corresponding to the first data to be written back when a write data request is received and the onboard cache of the solid-state disk is full, wherein the first data to be written back is the first data in the least recently used LRU linked list in the onboard cache of the solid-state disk;

[0024] The first writing module is used to write the first data to be written back into the target physical block of the target chip corresponding to the first data to be written back when the target physical block of the target chip is in an unerased state and the valid data size of the first data to be written back is equal to the size of the physical page.

[0025] Optionally, the device further includes: a second determining module and a second writing module;

[0026] The second determination module is used to determine the second data to be written back and the target physical block of the target chip corresponding to the second data to be written back when the target physical block of the target chip is in an erased state, wherein the second data to be written back is the next data in the LRU linked list in the onboard cache of the solid state disk;

[0027] The second writing module is used to write the second data to be written back into a target physical block of a target chip corresponding to the second data to be written back if the valid data size of the second data to be written back is equal to the size of the physical page.

[0028] Optionally, the device further includes: a third determining module and a third writing module;

[0029] The third determination module is used to determine the third data to be written back if the effective data size of the second data to be written back is smaller than the size of the physical page, wherein the sum of the effective data size of the second data to be written back and the effective data size of the third data to be written back is equal to the size of the physical page;

[0030] The third writing module is used to write the second data to be written back and the third data to be written back into a target physical block of a target chip corresponding to the second data to be written back.

[0031] Optionally, the device further includes: a fourth determining module and a fourth writing module;

[0032] The fourth determination module is configured to, when a write data request is received and the onboard cache of the solid state disk is not full, divide the to-be-written data corresponding to the write data request according to the size of the physical page to obtain a plurality of to-be-written sub-data;

[0033] The fourth writing module is used to add the multiple sub-data to be written to the tail of the LRU linked list.

[0034] Optionally, the first determination module specifically includes: a first determination submodule and a second determination submodule;

[0035] The first determination submodule is used to determine the first data to be written back according to the LRU linked list;

[0036] The second determination submodule is used to determine the target physical block of the target chip corresponding to the first data to be written back through page mapping.

[0037] Compared with the prior art, this application has the following beneficial effects:

[0038] The embodiment of the present application discloses a method and device for managing a write cache of a solid-state disk, the method comprising: when a write data request is received and the onboard cache of the solid-state disk is full, determining the first data to be written back and the target physical block of the target chip corresponding to the first data to be written back, wherein the first data to be written back is the first data in the least recently used LRU linked list in the onboard cache of the solid-state disk; when the target physical block of the target chip is in an unerased state and the effective data size of the first data to be written back is equal to the size of the physical page, writing the first data to be written back into the target physical block of the target chip corresponding to the first data to be written back. Thus, when the write data request is received and the onboard cache of the solid-state disk is full, the write cache management method of the solid-state disk provided by the embodiment of the present application performs a write-back operation only when the target physical block of the target chip is in an unerased state and the effective data size of the first data to be written back is equal to the size of the physical page, which can not only avoid the waiting delay caused by the erase operation, significantly reduce the write delay, thereby improving the performance of the SSD, but also ensure that the data written back each time is a complete physical page, and reduce the number of write operations by reducing partial page write operations, thereby improving the life of the SSD. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0040] Figure 1A flowchart of a solid state disk write cache management method provided in an embodiment of the present application;

[0041] Figure 2 A flowchart of another solid-state drive write cache management method provided in an embodiment of the present application;

[0042] Figure 3 A schematic diagram of a solid state disk storage system provided in an embodiment of the present application;

[0043] Figure 4 A schematic diagram of a solid state disk write cache management method provided in an embodiment of the present application;

[0044] Figure 5 A schematic diagram of a solid-state drive write cache management device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] First, the technical terms involved in this application are explained:

[0046] Solid State Drive (SSD) is a storage device that uses solid-state electronic storage chips as storage media. Unlike traditional mechanical hard disk drives (HDDs) based on rotating disks, SSDs have no moving mechanical parts and mainly use NAND Flash to store data.

[0047] NAND Flash is a non-volatile storage technology that is widely used in various storage devices, such as solid-state drives (SSDs), USB flash drives, memory cards, etc. It has the characteristics of non-volatility, high density, erasability, and high cost-effectiveness.

[0048] In NAND Flash memory, the erase operation is one of the most basic and important operations. The smallest erase unit of NAND Flash memory is the flash block. A flash block usually contains multiple pages, and the page is the smallest read and write unit of NAND Flash. For example, a common configuration may be that each block contains 64 pages, and each page is 4KB in size. Before performing an erase operation, the valid data in the flash block (that is, the data that still needs to be retained) needs to be migrated to other free blocks. This process is called "data migration" or "data copying". Once the valid data is migrated, the flash block can be erased. The erase operation restores all cells in the entire block to the initial state (usually represented as "1"), making it a free storage cell that can be used to write data again.

[0049] As described above, the cache hit rate is usually improved by optimizing the cache algorithm, that is, increasing the chances of data being read directly from the faster cache rather than from the slower NAND Flash. By preloading data that is expected to be frequently accessed into the cache, the number of direct writes to the NAND Flash can be significantly reduced, thereby reducing the frequency of erase operations and reducing wear on the SSD.

[0050] In actual applications, data access patterns and loads are constantly changing. For example, a server may process tasks with completely different data access patterns and loads at different times of the day. Therefore, the cache algorithm needs to be able to adapt to the changing data access patterns and loads to maintain a high cache hit rate. However, when the storage space of the SSD approaches its capacity limit, it becomes more difficult to allocate data between the cache and the NAND Flash memory. At this time, the SSD must perform garbage collection operations more frequently to clear data that is no longer needed to make room for new write requests. This will not only increase latency, but also accelerate the wear rate of the SSD, further affecting its performance and lifespan.

[0051] After research, the inventor disclosed a method and device for managing a write cache of a solid-state disk, the method comprising: when a write data request is received and the onboard cache of the solid-state disk is full, determining the first data to be written back and the target physical block of the target chip corresponding to the first data to be written back, wherein the first data to be written back is the first data in the least recently used LRU linked list in the onboard cache of the solid-state disk; when the target physical block of the target chip is in an unerased state and the effective data size of the first data to be written back is equal to the size of the physical page, writing the first data to be written back to the target physical block of the target chip corresponding to the first data to be written back. Therefore, when a write data request is received and the onboard cache of the solid-state disk is full, the write cache management method of the solid-state disk provided by the embodiment of the present application performs a write-back operation only when the target physical block of the target chip is in an unerased state and the effective data size of the first data to be written back is equal to the size of the physical page, which can not only avoid the waiting delay caused by the erase operation, significantly reduce the write delay, thereby improving the performance of the SSD, but also ensure that the data written back each time is a complete physical page, and reduce the number of write operations by reducing partial page write operations, thereby improving the life of the SSD.

[0052] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] See also Figure 1 , which is a flow chart of a solid state disk write cache management method provided by an embodiment of the present application. The method includes:

[0054] S101: When a write data request is received and the onboard cache of the solid-state disk is full, determine the first data to be written back and the target physical block of the target chip corresponding to the first data to be written back, wherein the first data to be written back is the first data in the least recently used IRU linked list in the onboard cache of the solid-state disk.

[0055] First, the user layer initiates a write data request, which is passed to the SSD through the file system and block device layer. The SSD writes the data to be written in the write data request into the SSD onboard cache to improve the write speed and efficiency.

[0056] When the SSD receives a write data request, it needs to check the state of the SSD onboard cache to determine whether the SSD onboard cache is exhausted (i.e., full). If the SSD onboard cache is full, it means that there is no free space in the SSD onboard cache to receive the data to be written.

[0057] When a write data request is received and the SSD onboard cache is full, the first data to be written back is determined first. Specifically, the SSD onboard cache uses a Least Recently Used (LRU) linked list to manage data. The LRU linked list records the access frequency and time of the data in the SSD onboard cache. The least recently used data (that is, the data that has not been accessed for the longest time or the data with the lowest access frequency) will be placed at the head of the LRU linked list. When the SSD onboard cache is full, it is necessary to select a data from the SSD onboard cache for write back. According to the management principle of the LRU linked list, the first data at the head of the LRU linked list needs to be selected as the first data to be written back, because the first data to be written back is least likely to be accessed again immediately, so it is preferentially removed from the SSD onboard cache to make room for new data to be written.

[0058] After confirming the first data to be written back, it is necessary to determine the target physical block of the target chip corresponding to the first data to be written back through page mapping. Specifically, there is a mapping table inside the SSD, which records the correspondence between the logical address (the address seen by the user) and the physical address (the address actually stored in the flash memory). Through the mapping table, the SSD determines the physical address corresponding to the first data to be written back, specifically the target chip and the target physical block.

[0059] Exemplarily, assuming that the onboard cache of the solid-state disk is managed by an LRU linked list, the current cache status is as follows: the data pages in the onboard cache of the solid-state disk include D1, D2, D3, D4, and D5, and the LRU linked list is D1, D2, D3, D4, and D5, where D1 is the least used data and D5 is the most frequently used data. Then, when the user layer requests to write data D6, the solid-state disk will first check the status of the onboard cache of the solid-state disk. If the onboard cache of the solid-state disk is full and there is no free space to receive D6, the LRU linked list will be checked to find the least recently used data D1, and D1 will be determined as the first data to be written back. Subsequently, the physical address PBA1 corresponding to the logical address LBA1 of D1 is queried through the page mapping table, and it is determined that PBA1 is located in the physical block PB2 of chip 2. Therefore, the target physical block of the target chip corresponding to the first data to be written back D1 is the physical block PB2 of chip 2.

[0060] S102: When the target physical block of the target chip is in an unerased state and the valid data size of the first data to be written back is equal to the size of the physical page, the first data to be written back is written into the target physical block of the target chip corresponding to the first data to be written back.

[0061] After determining the first data to be written back and the target physical block of the target chip corresponding to the first data to be written back, it is necessary to first check the status of the target physical block of the target chip. This is because an important feature of flash memory is that data can only be written after the erase operation is completed. If the target physical block is undergoing an erase operation, the write operation must wait for the erase to be completed. Therefore, it is necessary to check whether the target physical block is in an unerased state. Specifically, the solid-state disk controller maintains a status table that records the current status of each physical block (for example, idle, erased, erasing, etc.). By querying this status table, it can be determined whether the target physical block of the target chip is in an unerased state.

[0062] If the target physical block of the target chip is in an unerased state, it is necessary to continue to check whether the effective data size of the first data to be written back is equal to the size of the physical page. Among them, the physical page is the smallest read and write unit in the flash memory, usually 4KB. In other words, the solid-state drive will record the effective data size of the first data to be written back, and check whether the effective data size of the first data to be written back is equal to 4KB. It should be noted that this application does not limit the size of the physical page.

[0063] When the target physical block of the target chip is in an unerased state and the effective data size of the first data to be written back is equal to the size of the physical page, a write-back operation can be performed, that is, the first data to be written back is written into the target physical block of the target chip corresponding to the first data to be written back. Specifically, first, the first data to be written back is read out from the onboard cache of the solid-state disk and transmitted to the target chip through the data bus. Secondly, the first data to be written back is written into the target physical block of the target chip. Subsequently, the mapping table inside the solid-state disk is updated to record the correspondence between the new logical address and the physical address. Finally, the status of the target physical block is updated and marked as written.

[0064] In summary, the embodiment of the present application provides a method for managing a write cache of a solid-state disk. When a write data request is received and the onboard cache of the solid-state disk is full, the write-back operation is performed only when the target physical block of the target chip is in an unerased state and the valid data size of the first data to be written back is equal to the size of the physical page. This not only avoids the waiting delay caused by the erase operation, significantly reduces the write delay, and thus improves the performance of the solid-state disk, but also ensures that each write-back data is a complete physical page. By reducing partial page write operations, the number of write operations is reduced, thereby increasing the life of the solid-state disk.

[0065] See also Figure 2 , which is a flow chart of another solid-state drive write cache management method provided by an embodiment of the present application. Figure 3 , which is a schematic diagram of a solid state disk storage system provided by an embodiment of the present application. The method includes:

[0066] S201: In response to a write data request sent by a user layer, data to be written is divided according to the size of a physical page to obtain a plurality of sub-data to be written, wherein the write data request indicates that the data to be written is written into an onboard cache of a solid state disk.

[0067] First, the user layer (such as an operating system or application) initiates a write data request, which indicates that the data to be written should be written into the onboard cache of the solid-state drive. The write data request is passed to the controller of the solid-state drive through the file system and block device layer.

[0068] After the SSD receives a write data request from the user layer, the SSD divides the data to be written into multiple sub-data to be written according to the size of the physical page. The physical page is the smallest read and write unit in the flash memory, usually 4KB.

[0069] For example, suppose the user layer sends a write data request, which contains a 12KB segment of data to be written. The SSD needs to split the 12KB segment of data to be written into multiple 4KB sub-data to be written. The sub-data to be written after segmentation are: sub-data to be written 1: first 4KB, sub-data to be written 2: middle 4KB, sub-data to be written 3: last 4KB.

[0070] S202: Determine whether the onboard cache of the solid state disk is full. If not, execute step S203; if yes, execute step S204.

[0071] First, the available space of the current SSD onboard cache is calculated based on the current SSD onboard cache usage and the total SSD onboard cache capacity. Then, the available space of the current SSD onboard cache is compared with the size of the data to be written to determine whether the SSD onboard cache is full. If the available space of the current SSD onboard cache is less than the size of the data to be written, the SSD onboard cache is full. If the available space of the current SSD onboard cache is greater than or equal to the size of the data to be written, the SSD onboard cache is not full.

[0072] For example, assuming that the capacity of the SSD onboard cache is 16KB, the space currently used in the SSD onboard cache is 10KB, and the size of the data to be written is 12KB, then since the current available space of the SSD onboard cache 16KB-10KB=6KB is less than the size of the data to be written 12KB, then the current available space of the SSD onboard cache is less than the size of the data to be written, and therefore the SSD onboard cache is full.

[0073] If the SSD onboard cache is not full (i.e., the available space is greater than or equal to the size of the data to be written), step S203 is executed. If the SSD onboard cache is full (i.e., the available space is less than the size of the data to be written), step S204 is executed.

[0074] S203: Add the sub-data to be written to the tail of the LRU linked list in the onboard cache of the solid state disk.

[0075] The LRU linked list is a cache replacement strategy used to manage data in the SSD onboard cache. In the LRU strategy, when the cache space is insufficient, the least recently accessed data is removed to make room for new data. The LRU linked list achieves this by recording the order in which the data is accessed, with the head of the linked list being the most recently accessed data and the tail of the linked list being the data that has not been accessed for the longest time.

[0076] The sub-data to be written are usually added to the tail of the LRU linked list, indicating that the sub-data to be written is one of the data that has been accessed recently. Only when the onboard cache space of the SSD is insufficient and these data have not been accessed again for a period of time, they may be moved to the front of the LRU linked list and eventually removed.

[0077] S204: Determine the target physical block of the target chip corresponding to the first sub-data to be written back by means of page mapping, wherein the first sub-data to be written back is the first data in the LRU linked list.

[0078] When the SSD onboard cache queue is full, any new write data request will trigger a write-back operation, where the goal of the write-back operation is to write the data in the SSD onboard cache back to the flash media to free up cache space to store the data to be written corresponding to the write data request.

[0079] The SSD uses the LRU algorithm to manage the SSD onboard cache. The first data in the LRU list is the data that has not been accessed for the longest time, usually the first sub-data to be written back. Figure 4 , which is a schematic diagram of a solid state drive write cache management method. Figure 4 As shown, assuming that the first data in the LRU linked list is D5, D5 is determined as the first data to be written back.

[0080] After confirming the first data to be written back, it is necessary to determine the target physical block of the target chip corresponding to the first data to be written back through page mapping. Specifically, there is a mapping table inside the SSD, which records the correspondence between the logical address (the address seen by the user) and the physical address (the address actually stored in the flash memory). Through the mapping table, the SSD determines the physical address corresponding to the first data to be written back, specifically the target chip and the target physical block. Figure 4 As shown, by querying the mapping table, it is determined that the physical address corresponding to the first to-be-written-back data D5 is located on a physical block of the target chip 2 .

[0081] S205: Determine whether the target physical block of the target chip is performing an erase operation. If not, execute S206; if yes, execute S207.

[0082] The write operation of flash memory is actually an erase-then-write process, because the physical block of flash memory must be erased before writing new data. The erase operation is a relatively time-consuming process, usually much slower than the write operation. Therefore, when performing a write-back operation, it is necessary to determine whether the target physical block is performing an erase operation to avoid conflicts and improve efficiency.

[0083] If the target physical block is not performing an erase operation, that is, the state flag of the target physical block is displayed as "free", the next operation S206 is performed. If the target physical block is performing an erase operation, that is, the state flag of the target physical block is displayed as "erasing", another operation S207 is performed.

[0084] S206: Write the first data to be written back into the target physical block of the corresponding target chip.

[0085] It should be noted that after writing the first data to be written back to the target physical block of the corresponding target chip, it is necessary to update the status flag of the target physical block and mark it as "free". The "free" state indicates that the physical block is not currently occupied by any data and can receive new write requests. By updating the status flag, the solid state drive can ensure that there will be no conflict with the physical block where data has been written in the subsequent data write operation.

[0086] S207: Determine the second data to be written back and the target physical block of the target chip corresponding to the second data to be written back, wherein the second sub-data to be written back is the next data in the LRU linked list.

[0087] If the target physical block is performing an erase operation and the first data to be written back cannot be written immediately, the next data (i.e., the next data in the LRU linked list) needs to be selected as the second data to be written back. Subsequently, the physical address corresponding to the second data to be written back is determined through the mapping table, specifically to the target chip and the target physical block.

[0088] S208: Determine whether the valid data size of the second sub-data to be written back is smaller than the size of the physical page. If not, execute step S209; if yes, execute step S210.

[0089] The second data to be written back and its corresponding target chip and target physical block have been determined through step S207, so it is necessary to determine the effective data size of the second sub-data to be written back. If the effective data size of the second sub-data to be written back is not less than the size of the physical page, step S209 is executed. If the effective data size of the second sub-data to be written back is less than the size of the physical page, step S210 is executed.

[0090] S209: Write the second data to be written back into the target physical block of the corresponding target chip.

[0091] It should be noted that after writing the second data to be written back to the target physical block of the corresponding target chip, it is necessary to update the status flag of the target physical block and mark it as "free". The "free" state indicates that the physical block is not currently occupied by any data and can receive new write requests. By updating the status flag, the solid state drive can ensure that there will be no conflict with the physical block where data has been written in the subsequent data write operation.

[0092] S210: Determine the third sub-data to be written back, wherein the sum of the valid data size of the second sub-data to be written back and the valid data size of the third sub-data to be written back is equal to the size of the physical page.

[0093] If the valid data size of the second sub-data to be written back is smaller than the size of the physical page, it is necessary to determine the third sub-data to be written back. The selection of the third sub-data to be written back should meet the following conditions: the sum of the valid data sizes of the second sub-data to be written back and the third sub-data to be written back is exactly equal to the size of the physical page. In this way, it can be ensured that when writing data back to the physical page, the physical page can be completely filled without leaving unused space.

[0094] S211: Write the second data to be written back and the third data to be written back into the target physical block of the corresponding target chip.

[0095] It should be noted that after writing the second data to be written back and the third data to be written back to the target physical block of the corresponding target chip, it is necessary to update the status flag of the target physical block and mark it as "free". The "free" state indicates that the physical block is not currently occupied by any data and can receive new write requests. By updating the status flag, the solid state drive can ensure that there will be no conflict with the physical block where data has been written in the subsequent data write operation.

[0096] In summary, the embodiment of the present application provides a method for managing a write cache of a solid-state disk. When a write data request is received and the onboard cache of the solid-state disk is full, the write-back operation is performed only when the target physical block of the target chip is in an unerased state and the valid data size of the first data to be written back is equal to the size of the physical page. This not only avoids the waiting delay caused by the erase operation, significantly reduces the write delay, and thus improves the performance of the solid-state disk, but also ensures that each write-back data is a complete physical page. By reducing partial page write operations, the number of write operations is reduced, thereby increasing the life of the solid-state disk.

[0097] See also Figure 5 , which is a schematic diagram of a solid state disk write cache management device provided by an embodiment of the present application. The solid state disk write cache management device 500 includes: a first determination module 501 and a first writing module 502.

[0098] A first determination module 501 is used to determine, when a write data request is received and the onboard cache of the solid state disk is full, first data to be written back and a target physical block of a target chip corresponding to the first data to be written back, wherein the first data to be written back is the first data in a least recently used LRU linked list in the onboard cache of the solid state disk;

[0099] The first writing module 502 is used to write the first data to be written back into the target physical block of the target chip corresponding to the first data to be written back when the target physical block of the target chip is in an unerased state and the valid data size of the first data to be written back is equal to the size of the physical page.

[0100] In some specific implementations, the solid state disk write cache management device 500 further includes: a second determination module and a second writing module;

[0101] A second determination module is used to determine the second data to be written back and the target physical block of the target chip corresponding to the second data to be written back when the target physical block of the target chip is in an erased state, wherein the second data to be written back is the next data in the LRU linked list in the onboard cache of the solid state disk;

[0102] The second writing module is used for writing the second data to be written back into a target physical block of a target chip corresponding to the second data to be written back if the valid data size of the second data to be written back is equal to the size of the physical page.

[0103] In some specific implementations, the solid state disk write cache management device 500 further includes: a third determination module and a third writing module;

[0104] A third determination module is used to determine the third data to be written back if the effective data size of the second data to be written back is smaller than the size of the physical page, wherein the sum of the effective data size of the second data to be written back and the effective data size of the third data to be written back is equal to the size of the physical page;

[0105] The third writing module is used to write the second data to be written back and the third data to be written back into the target physical block of the target chip corresponding to the second data to be written back.

[0106] In some specific implementations, the solid state disk write cache management device 500 further includes: a fourth determination module and a fourth writing module;

[0107] A fourth determination module is used for, when a write data request is received and the onboard cache of the solid state disk is not full, dividing the to-be-written data corresponding to the write data request according to the size of the physical page to obtain a plurality of to-be-written sub-data;

[0108] The fourth writing module is used to add the plurality of sub-data to be written to the tail of the LRU linked list.

[0109] In some specific implementations, the first determination module 501 specifically includes: a first determination submodule and a second determination submodule;

[0110] A first determination submodule, used to determine first data to be written back according to the LRU linked list;

[0111] The second determination submodule is used to determine the target physical block of the target chip corresponding to the first to-be-written-back data by means of page mapping.

[0112] In summary, the embodiment of the present application provides a solid-state drive write cache management device. When a write data request is received and the onboard cache of the solid-state drive is full, the write-back operation is performed only when the target physical block of the target chip is in an unerased state and the valid data size of the first data to be written back is equal to the size of the physical page. This not only avoids the waiting delay caused by the erase operation, significantly reduces the write delay, and thus improves the performance of the solid-state drive, but also ensures that each write-back data is a complete physical page. By reducing partial page write operations, the number of write operations is reduced, thereby increasing the life of the solid-state drive.

[0113] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments. The device and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components indicated as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0114] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A solid state disk write cache management method, characterized in that: The method comprises: When a write data request is received and the onboard cache of the solid-state disk is full, determining first data to be written back and a target physical block of a target chip corresponding to the first data to be written back, wherein the first data to be written back is the first data in a least recently used LRU linked list in the onboard cache of the solid-state disk; When the target physical block of the target chip is in an unerased state and the valid data size of the first data to be written back is equal to the size of the physical page, the first data to be written back is written into the target physical block of the target chip corresponding to the first data to be written back.

2. The method according to claim 1, characterized in that The method further comprises: When the target physical block of the target chip is in an erase state, determining second data to be written back and a target physical block of the target chip corresponding to the second data to be written back, wherein the second data to be written back is the next data in the LRU linked list in the onboard cache of the solid state disk; If the valid data size of the second data to be written back is equal to the size of the physical page, the second data to be written back is written into a target physical block of a target chip corresponding to the second data to be written back.

3. The method according to claim 2, characterized in that The method further comprises: If the effective data size of the second data to be written back is smaller than the size of the physical page, determining the third data to be written back, wherein the sum of the effective data size of the second data to be written back and the effective data size of the third data to be written back is equal to the size of the physical page; The second data to be written back and the third data to be written back are written into a target physical block of a target chip corresponding to the second data to be written back.

4. The method according to claim 1, characterized in that: The method further comprises: When a write data request is received and the onboard cache of the solid state disk is not full, the to-be-written data corresponding to the write data request is divided according to the size of the physical page to obtain a plurality of to-be-written sub-data; The multiple sub-data to be written are added to the tail of the LRU linked list.

5. The method according to claim 1, characterized in that: The determining the first data to be written back and the target physical block of the target chip corresponding to the first data to be written back includes: Determine the first data to be written back according to the LRU linked list; The target physical block of the target chip corresponding to the first data to be written back is determined by page mapping.

6. A solid state disk write cache management device, characterized in that: The device comprises: a first determining module and a first writing module; The first determination module is used to determine the first data to be written back and the target physical block of the target chip corresponding to the first data to be written back when a write data request is received and the onboard cache of the solid-state disk is full, wherein the first data to be written back is the first data in the least recently used LRU linked list in the onboard cache of the solid-state disk; The first writing module is used to write the first data to be written back into the target physical block of the target chip corresponding to the first data to be written back when the target physical block of the target chip is in an unerased state and the valid data size of the first data to be written back is equal to the size of the physical page.

7. The device according to claim 6, characterized in that The device further comprises: a second determining module and a second writing module; The second determination module is used to determine the second data to be written back and the target physical block of the target chip corresponding to the second data to be written back when the target physical block of the target chip is in an erased state, wherein the second data to be written back is the next data in the LRU linked list in the onboard cache of the solid state disk; The second writing module is used to write the second data to be written back into a target physical block of a target chip corresponding to the second data to be written back if the valid data size of the second data to be written back is equal to the size of the physical page.

8. The device according to claim 7, characterized in that The device further comprises: a third determining module and a third writing module; The third determination module is used to determine the third data to be written back if the effective data size of the second data to be written back is smaller than the size of the physical page, wherein the sum of the effective data size of the second data to be written back and the effective data size of the third data to be written back is equal to the size of the physical page; The third writing module is used to write the second data to be written back and the third data to be written back into a target physical block of a target chip corresponding to the second data to be written back.

9. The device according to claim 6, characterized in that The device further includes: a fourth determining module and a fourth writing module; The fourth determination module is configured to, when a write data request is received and the onboard cache of the solid state disk is not full, divide the to-be-written data corresponding to the write data request according to the size of the physical page to obtain a plurality of to-be-written sub-data; The fourth writing module is used to add the multiple sub-data to be written to the end of the LRU linked list.

10. The device according to claim 6, characterized in that The first determination module specifically includes: a first determination submodule and a second determination submodule; The first determination submodule is used to determine the first data to be written back according to the LRU linked list; The second determination submodule is used to determine the target physical block of the target chip corresponding to the first data to be written back through page mapping.

Images