Data transmission method and device based on DPU and storage medium

Abstract

The invention provides a data transmission method and device based on a DPU and a storage medium. The method comprises the following steps: caching a first data frame in a memory to a sending data buffer area through a primary PCIE bus in a data transmission mode of PIO; caching the command frame in the memory to a command sending buffer area through a primary PCIE (Peripheral Component Interface Express) bus in a PIO command transmission mode; wherein the command frame is used for indicating that the first data frame is cached in the sending data buffer area; and reading the command frame from the sending command buffer area through the first logic module, and reading and sending the first data frame from the sending data buffer area based on the instruction of the command frame. Therefore, the delay of data reading and sending can be greatly compressed, and the data transmission efficiency of the DPU is improved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a data transmission method, device and storage medium based on DPU. Background Art

[0002] In the hardware architecture design of the Data Processing Unit (DPU), the throughput of the hardware architecture can be improved through some designs, such as using a higher bus width inside the hardware architecture, increasing the clock frequency, using a higher-speed Ethernet interface media access control (MAC), etc. In addition, in addition to considering improving the throughput of the hardware architecture, how to reduce the delay in data transmission through the DPU is still an urgent problem to be solved. Summary of the invention

[0003] In view of this, the present application provides a data transmission method, device and storage medium based on DPU, which can greatly reduce the delay of data reading and sending, and improve the efficiency of DPU in data transmission.

[0004] In a first aspect, the present application provides a DPU-based data transmission method, which is applied to the DPU, and the DPU includes a sending command buffer, a sending data buffer and a first logic module. The method includes: caching a first data frame in a memory to a sending data buffer through a PCIE bus in a programmable input / output PIO data transmission mode; caching a command frame in a memory to a sending command buffer through a PCIE bus in a PIO command transmission mode; wherein the command frame is used to indicate that the first data frame has been cached in the sending data buffer; reading the command frame from the sending command buffer through the first logic module, and reading and sending the first data frame from the sending data buffer based on the indication of the command frame.

[0005] In a second aspect, the present application provides a DPU-based data transmission device, including: a cache module, used to cache a first data frame in a memory to a sending data buffer through a PCIE bus in a programmable input / output PIO data transmission mode; the cache module is also used to cache a command frame in the memory to a sending command buffer through a PCIE bus in a PIO command transmission mode; wherein the command frame is used to indicate that the first data frame has been cached in the sending data buffer; a communication module, used to read the command frame from the sending command buffer through a first logic module, and read and send the first data frame from the sending data buffer based on the indication of the command frame.

[0006] In a third aspect, the present application provides a computer-readable storage medium storing a computer program, which implements the method of the first aspect when executed by one or more processors.

[0007] In a fourth aspect, the present application provides a computer program product, comprising computer program instructions, which enable a computer to execute the method of the first aspect.

[0008] In a fifth aspect, the present application provides a computer program, which, when executed on a computer, enables the computer to execute the method of the first aspect.

[0009] The present application provides a data transmission method, device and storage medium based on DPU. When the command frame and / or the first data frame in the memory can be cached in the PIO transmission mode (corresponding to one PCIE bus), the command frame and / or the first data frame can be considered to be actively sent from the memory, so that the memory does not need to send the command frame and / or the first data frame passively by sending a read request to the memory (corresponding to at least two PCIE buses), thereby greatly compressing the delay of data reading and sending, and improving the efficiency of DPU in data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0011] Figure 1 It is a flowchart of a DPU-based data transmission method provided in an embodiment of the present application;

[0012] Figure 2 It is a flowchart of another DPU-based data transmission method provided in an embodiment of the present application;

[0013] Figure 3 is a schematic block diagram of data transmission based on DPU provided in an embodiment of the present application;

[0014] Figure 4 is a schematic block diagram of data reception based on a DPU provided in an embodiment of the present application;

[0015] Figure 5 It is a schematic diagram of the composition structure of a DPU-based data transmission device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and in detail below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the embodiments of the present application should fall within the scope of protection of the embodiments of the present application.

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0018] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0019] It should also be pointed out that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0020] It can be understood that the term "and / or" in the embodiments of the present application is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0021] To facilitate understanding of the technical solutions of the embodiments of the present application, the relevant technologies of the embodiments of the present application are described below. The following related technologies can be arbitrarily combined with the technical solutions of the embodiments of the present application as optional solutions, and they all belong to the protection scope of the embodiments of the present application.

[0022] It should be understood that DPU is a new generation of computing chip that is data-centric, input / output (I / O) intensive, and uses software-defined technology to support infrastructure resource layer virtualization. It has the ability to improve computing system efficiency, reduce the total cost of ownership of the overall system, improve data processing performance, and reduce performance loss of other computing chips.

[0023] In the hardware architecture design of DPU, some designs can improve the throughput of the hardware architecture, such as using a higher bus width, increasing the clock frequency, using a MAC with a higher Ethernet interface rate, etc. In addition, in addition to considering improving the throughput of the hardware architecture, how to reduce the delay when transmitting data through the DPU is still an urgent problem to be solved.

[0024] Based on this, the embodiment of the present application provides a data transmission method based on DPU, in which the first data frame in the memory is cached to the sending data buffer through a PCIE bus in a data transmission mode of programmable input / output (PIO); in a command transmission mode of PIO, the command frame in the memory is cached to the sending command buffer through a PCIE bus; wherein the command frame is used to indicate that the first data frame has been cached in the sending data buffer; through a first logic module, the command frame is read from the sending command buffer, and based on the indication of the command frame, the first data frame is read and sent from the sending data buffer. In this way, when the command frame and / or the first data frame in the memory are cached in the PIO transmission mode (corresponding to a PCIE bus once), the command frame and / or the first data frame can be considered to be actively sent from the memory, so that the memory does not need to be passively sent by sending a read request to the memory (corresponding to at least two PCIE buses), thereby greatly compressing the delay of data reading and sending, and improving the efficiency of DPU data transmission.

[0025] To facilitate understanding of the technical solutions of the embodiments of the present application, the technical solutions of the present application are described in detail below through specific embodiments. The above related technologies can be combined arbitrarily with the technical solutions of the embodiments of the present application as optional solutions, and they all belong to the protection scope of the embodiments of the present application. The embodiments of the present application include at least part of the following contents.

[0026] Figure 1 is a flow chart of a DPU-based data transmission method provided in an embodiment of the present application, such as Figure 1 As shown, the method is applied to a DPU, the DPU includes a sending command buffer, a sending data buffer and a first logic module, and the method may include the following steps.

[0027] S110, in a PIO data transmission mode, cache the first data frame in the memory to a sending data buffer through a PCIE bus once; in a PIO command transmission mode, cache the command frame in the memory to a sending command buffer through a PCIE bus once.

[0028] Among them, the command frame is used to indicate that the first data frame is sent in a PIO data transmission mode, and the first data frame in the memory is cached to the sending data buffer through a PCIE bus; in a PIO command transmission mode, the command frame in the memory is cached to the sending command buffer through a PCIE bus and the sending data buffer has been cached.

[0029] It should be noted that, in the embodiments of the present application, the DPU-based data transmission method can be applied to a DPU-based data transmission device.

[0030] It should also be noted that when caching the command frame and / or the first data frame in the memory through other transmission methods other than PIO, it is usually necessary to send a read request to the memory (corresponding to at least two PCIE buses) to make the memory passively send the command frame and / or the first data frame; and when caching the command frame and / or the first data frame in the memory in the PIO transmission method (corresponding to one PCIE bus), the command frame and / or the first data frame can be considered to be actively sent from the memory, thereby reducing the number of times the command frame and / or the first data frame penetrates the PCIE bus, greatly compressing the delay of data transmission.

[0031] It should be understood that the first data frame in the memory can be cached through a PCIE bus with the help of a central processing unit (CPU) in a PIO data transmission mode; and the command frame in the memory can be cached through a PCIE bus with the help of a CPU in a PIO command transmission mode.

[0032] In some embodiments, caching a first data frame in a memory to a sending data buffer through a PCIE bus may include: mapping the sending data buffer to a first position in the memory, the memory attribute of the first position being a write combine attribute; and caching a first data frame corresponding to the first position to the sending data buffer through a PCIE bus.

[0033] It should be noted that the base address register (BAR) space of PCIE is a key component for communication and resource mapping between DPU and memory, so the send data buffer can be mapped to the first position in the memory through the BAR space of PCIE.

[0034] Furthermore, with the help of the CPU, the send data buffer can be mapped to the first position in the memory through the BAR space of the PCIE.

[0035] It should be understood that the write-combining attribute is a memory optimization technique that allows the system to combine multiple small write operations into a large write operation to reduce the number of memory accesses and improve the efficiency of the write operation.

[0036] It should also be understood that when the memory attribute of the first position is a write-merge attribute, by turning on the input / output cache (IO Cache) in the CPU, when the first data frame in the CPU cache memory is used, the first data frame corresponding to the first position can be directly merged into a large data block, and then the large data block is cached to the sending data buffer, without caching the first data frame in the sending data buffer multiple times.

[0037] Through this method, by mapping the sending data buffer to the first position with a write-merging attribute, when the first data frame corresponding to the first position is transmitted, it is not necessary to cache the first data frame to the sending data buffer multiple times, but the first data frame can be directly cached to the sending data buffer once, thereby reducing the number of accesses to the memory and improving the efficiency of data transmission.

[0038] In some embodiments, caching a command frame in a memory to a send command buffer via a PCIE bus may include: mapping the send command buffer to a second location in the memory, wherein the memory attribute of the second location is a non-cacheable attribute; and caching the command frame corresponding to the second location to the send command buffer via a PCIE bus.

[0039] It should be noted that the send command buffer can be mapped to the second location in the memory through the BAR space of the PCIE.

[0040] Furthermore, the send command buffer can be mapped to the second location in the memory through the BAR space of the PCIE with the help of the CPU.

[0041] It should be understood that the non-cacheable attribute of the second position makes the command frame corresponding to the second position not cached by the cache, but can be directly obtained from the memory, so that the command frame can be cached to the send command buffer in time.

[0042] Through this method, by mapping the send command buffer to a second position with a non-cacheable attribute, the intermediate links and delays in the transmission process of the command frame corresponding to the second position can be reduced, thereby improving the efficiency of caching the command frame to the send command buffer.

[0043] In some embodiments, the number of bits of the command frame is less than a first preset number of bits.

[0044] It should be noted that the first preset number of bits may be set based on empirical rules, may be set manually, or may be set in other ways, and this is not limited in the embodiments of the present application.

[0045] Exemplarily, the first preset number of bits may be 4 Bytes.

[0046] Through this method, when the number of bits of the command frame is less than the first preset number of bits, the command frame can be cached to the sending command buffer through a PCIE transaction through an integer (Int) type write instruction, thereby improving the cache efficiency of the command frame.

[0047] S120. Read a command frame from a sending command buffer through a first logic module, and read and send a first data frame from a sending data buffer based on an instruction of the command frame.

[0048] It should be noted that the first logic module can send the first data frame read from the sending data buffer to other modules in the DPU, or to other devices outside the DPU, which is not limited in this embodiment of the present application.

[0049] It should also be noted that after reading the command frame, the first logic module can obtain, based on the instruction of the command frame, that the first data frame has been cached in the sending data buffer, so that the complete first data frame can be read from the sending data buffer subsequently.

[0050] In some embodiments, the command frame may include at least one of the following information: the length of the first data frame, the start flag of the first data frame, and the end flag of the first data frame; based on the indication of the command frame, reading the first data frame from the sending data buffer may include: based on the indication of the command frame and at least one piece of information, reading the first data frame from the sending data buffer.

[0051] It should be noted that, after the command frame indicates that the first data frame has been completely cached in the sending data buffer, the position of the first data frame in the sending data buffer may be determined based on at least one of the following:

[0052] The length of the first data frame and the start flag of the first data frame;

[0053] The length of the first data frame and the end flag of the first data frame;

[0054] The length of the first data frame, the start flag of the first data frame, and the end flag of the first data frame.

[0055] By using this method, based on the instruction of the command frame and at least one information, the first data frame is read from the sending data buffer, which can improve the reading accuracy of the first data frame, so that the first logic module can accurately read the complete first data frame, which helps to reduce errors in data transmission. In addition, the process of reading the first data frame from the sending data buffer can be automated without manual intervention, thereby improving the efficiency of data transmission.

[0056] An embodiment of the present application provides a data transmission method based on a DPU. When the command frame and / or the first data frame in the memory is cached in a PIO transmission mode (corresponding to one PCIE bus), the command frame and / or the first data frame can be considered to be actively sent from the memory, so that there is no need to send a read request to the memory (corresponding to at least two PCIE buses) to make the memory passively send the command frame and / or the first data frame, thereby greatly compressing the delay of data reading and sending, and improving the efficiency of DPU data transmission.

[0057] It should be understood that Figure 1 The process of sending data through the DPU is shown. It can be understood that data can also be received through the DPU. The data sent by the DPU and the data received by the DPU can be the same data; or the data sent by the DPU can be processed and then received by the DPU; or the data sent by the DPU and the data received by the DPU can be different data. Figure 2 The process of receiving data through the DPU is described.

[0058] Figure 2 is a flow chart of another DPU-based data transmission method provided in an embodiment of the present application, such as Figure 2 As shown, the method is applied to the DPU, and the DPU may further include a second logic module. The method may include the following steps:

[0059] S210, receiving a data packet through a second logic module, and slicing the data packet to obtain at least two data frames;

[0060] S220: If the instantaneous bandwidth of the PCIE bus at the current moment is less than the preset bandwidth, at the current moment, at least two data frames sliced ​​and processed by the second logic module are sequentially stored in at least two corresponding memory blocks through the PCIE bus.

[0061] Among them, at least two memory blocks are obtained based on slicing the memory; the storage capacity of each memory block is greater than or equal to the number of bits of the corresponding data frame, and the storage capacity of at least two memory blocks is greater than or equal to the maximum number of bits that the PCIE bus can carry.

[0062] It should be noted that the data packet and the first data frame in the aforementioned embodiment may be the same data; alternatively, the first data frame sent through the DPU may be processed to obtain a data packet, and then the data packet may be received through the DPU; alternatively, the first data frame sent through the DPU and the data packet received through the DPU may be different data, and this is not limited to the embodiments of the present application.

[0063] Exemplarily, receiving the data packet through the second logic module may include: receiving the data packet sent by the MAC through the second logic module.

[0064] It should be noted that the preset bandwidth may be the maximum bandwidth that the PCIE bus can carry, or may be set according to empirical rules, or may be set manually, and the embodiments of the present application do not limit this.

[0065] It should also be noted that when the instantaneous bandwidth of the PCIE bus at the current moment is less than the preset bandwidth, it means that the PCIE bus has idle bandwidth at the current moment, so that at least two data frames can be transmitted using the idle bandwidth, avoiding packet loss caused by transmitting at least two data frames when the PCIE bus has no idle bandwidth (corresponding to the instantaneous bandwidth is greater than or equal to the preset bandwidth).

[0066] It can be understood that when the storage capacity of each memory block is greater than or equal to the number of bits of the corresponding data frame, and the storage capacity of at least two memory blocks is greater than or equal to the maximum number of bits that the PCIE bus can carry, each memory block can store the corresponding data frame, and at least two memory blocks can store all data transmitted by the PCIE bus, avoiding packet loss due to insufficient memory.

[0067] Exemplarily, the maximum number of bits that a PCIE bus can carry may be 128 Byte, 256 Byte, 512 Byte or 1024 Byte, etc., which is not limited in the embodiments of the present application.

[0068] In some embodiments, the DPU may further include a receiving data buffer, and the method may further include: if the instantaneous bandwidth of the PCIE bus at the current moment is greater than or equal to the preset bandwidth, sending at least two data frames to the receiving data buffer through the second logic module; caching at least two data frames through the receiving data buffer; if the instantaneous bandwidth of the PCIE bus at the next moment after the current moment is less than the preset bandwidth, then at the next moment, the at least two data frames cached in the receiving data buffer are stored in sequence in the corresponding at least two memory blocks through the PCIE bus.

[0069] It should be noted that, when the instantaneous bandwidth of the PCIE bus at the current moment is greater than or equal to the preset bandwidth, it means that the instantaneous bandwidth of the PCIE bus at the current moment has reached the upper limit and cannot respond to the PCIE write request transaction. At this time, at least two data frames on the line can be cached through the receiving data buffer, and at least two data frames can be transmitted when the PCIe bus has idle bandwidth (corresponding to the instantaneous bandwidth is less than the preset bandwidth), thereby reducing the probability of packet loss.

[0070] Through this method, when the instantaneous bandwidth of the PCIE bus at the current moment is greater than or equal to the preset bandwidth, it means that the PCIE bus has no idle bandwidth at the current moment. At this time, at least two data frames are cached by receiving the data buffer, and at least two data frames are transmitted when the PCIE bus has idle bandwidth at the next moment (corresponding to the instantaneous bandwidth being less than the preset bandwidth), thereby avoiding packet loss caused by transmitting at least two data frames when the PCIE bus has no idle bandwidth.

[0071] In some embodiments, the second data frame may include at least one of a frame header, a payload, and invalid fill data; wherein the invalid fill data is used to fill idle bits in the second data frame; the frame header may include at least one of the following: the timestamp of the second data frame, the length of the second data frame, the length of the payload, the start flag of the second data frame, the end flag of the second data frame, the frame type of the second data frame, the data type of the payload, the error frame identifier of the second data frame, and the frame status of the second data frame.

[0072] The second data frame and the first data frame are the same frame, or the second data frame is any frame of at least two data frames.

[0073] It should be noted that in the frame structure of the second data frame, the effective load may not be able to effectively fill the entire data frame, so the idle bits in the second data frame need to be filled with invalid filling data so that the length of the second data frame meets the frame length requirement.

[0074] Exemplarily, the content of the invalid filling data can be any content, such as 0xFF or 0x00, etc., which is not limited in this embodiment of the present application.

[0075] It should be noted that in the frame structure of the second data frame, the payload is the data portion actually transmitted in the second data frame. By encapsulating the actually transmitted data portion in the second data frame and transmitting it through the network, the efficiency and reliability of communication can be greatly improved.

[0076] It should also be noted that the timestamp of the second data frame can be used to record the sending or receiving time of the second data frame, so that the transmission delay, jitter and other performance indicators of the second data frame in the network can be calculated, which is helpful to evaluate network performance and optimize network design; at least one of the length of the second data frame, the length of the payload, the start flag of the second data frame, and the end flag of the second data frame can be used to accurately locate the position of the second data frame, so that the second data frame can be accurately read and transmitted; the frame type of the second data frame and / or the data type of the payload can be used to indicate the data type carried by the second data frame, which helps to reduce communication failures and data loss caused by data type identification errors; the error frame identifier of the second data frame can enable erroneous data to be detected and discarded in a timely manner during data transmission, thereby reducing the possibility of data loss. Through the error frame identifier, the data received by the receiving end can be complete and undamaged, which helps to improve the reliability of data communication; the frame status of the second data frame can be used by the receiving end and the sending end to promptly detect whether the second data frame is lost, thereby ensuring data synchronization between the receiving end and the sending end.

[0077] It can be understood that the number of bits of the frame header may be smaller than the second preset number of bits, so that the second data frame does not occupy too much PCIE effective bandwidth overhead.

[0078] Exemplarily, the number of bits of the frame header may be 8 bytes, 16 bytes, etc., which is not limited in the embodiments of the present application.

[0079] In some embodiments, slicing the data packet to obtain at least two data frames may include: if the mode of the second logic module is a mode other than the Cut-Through mode, then after updating the mode of the second logic module to the Cut-Through mode, slicing the data packet to obtain at least two data frames.

[0080] Exemplarily, other modes may be a store and forward mode, a fragment discard mode, etc., which is not limited in the embodiments of the present application.

[0081] It can be understood that the direct forwarding mode itself has the advantages of fast forwarding rate, reduced delay and improved overall throughput. It enables the second logic module to transmit the data packet without waiting for the entire data packet to be received before transmitting the data packet, but can transmit at least two data frames after slicing in sequence, thereby reducing the delay in the data transmission process.

[0082] Through this method, by updating the mode of the second logic module to the direct forwarding mode, the efficiency of the second logic module in transmitting at least two data frames can be improved.

[0083] The embodiment of the present application provides a data transmission method based on a DPU, which slices the received data packet through a second logic module, and then sequentially stores the obtained at least two data frames into corresponding at least two memory blocks, which can reduce the transmission delay of the data packet and improve the efficiency of the DPU in data transmission. In addition, when the PCIE bus has idle bandwidth at the current moment, at least two data frames are transmitted, avoiding packet loss caused by transmitting at least two data frames when the PCIE bus has no idle bandwidth.

[0084] The following describes in detail the DPU-based data transmission method provided in the above embodiment in combination with specific application scenarios.

[0085] Figure 3 is a schematic block diagram of a method of transmitting data based on a DPU provided in an embodiment of the present application. Figure 3 As shown, the schematic block diagram may include a DPU 350 and a memory 340. The DPU 350 may include a send data buffer 310, a send command buffer 320 and a first logic module 330. There are at least two positions (corresponding to position 1 and position 2) in the memory 340. Among them, the sending end of the send data buffer 310 is connected to the first receiving end of the first logic module 330, the sending end of the send command buffer 320 is connected to the second receiving end of the first logic module 330, and the sending end of the first logic module 330 is connected to other modules in the DPU 350 or other devices other than the DPU 350; the receiving end of the send data buffer 310 is connected to the first end of the memory 340, and the receiving end of the send command buffer 320 is connected to the second end of the memory 340. The process of data transmission based on the DPU 350 may include:

[0086] The sending data buffer 310 is mapped to position 1 in the memory 340 (corresponding to the first position in the aforementioned embodiment), and the memory 340 attribute of position 1 is a write-merge attribute; and the sending data buffer 310 caches the first data frame corresponding to position 1 through a PCIE bus in a PIO data transmission mode; the sending command buffer 320 is mapped to position 2 in the memory 340 (corresponding to the second position in the aforementioned embodiment), and the memory 340 attribute of position 2 is a non-cacheable attribute; and the sending command buffer 320 caches the command frame corresponding to position 2 through a PCIE bus in a PIO command transmission mode, wherein the command frame is used to indicate that the first data frame has been cached in the sending data buffer 310; the first logic module 330 reads the command frame from the sending command buffer 320, and based on the indication of the command frame, reads the first data frame from the sending data buffer 310, and sends the first data frame to other modules in the DPU 350 or other devices other than the DPU 350.

[0087] The technical solution provided by the embodiment of the present application caches the command frame and / or the first data frame in the memory in a PIO transmission mode (corresponding to one PCIE bus). The command frame and / or the first data frame can be considered to be actively sent from the memory, so that there is no need to send a read request to the memory (corresponding to at least two PCIE buses) to make the memory passively send the command frame and / or the first data frame, thereby greatly compressing the delay of data reading and sending, and improving the efficiency of DPU data transmission.

[0088] Figure 4 is a schematic block diagram of a method for receiving data based on a DPU provided in an embodiment of the present application. Figure 4 As shown, the schematic block diagram may include a DPU 350 and a memory 340. The DPU 350 may include a second logic module 410, a receiving data buffer 420 and a media access control 430. The memory 340 includes at least three memory blocks after the memory 340 is sliced. Among them, the receiving end of the second logic module 410 is connected to the sending end of the media access control 430, and the receiving end of the media access control 430 is connected to other modules in the DPU 350 or other devices other than the DPU 350; the sending end of the second logic module 410 is connected to the receiving end of the receiving data buffer 420, and the sending end of the receiving data buffer 420 is connected to one end of the memory 340. Taking the example of slicing a data packet to obtain three data frames, the process of data reception based on the DPU 350 may include:

[0089] The media access control 430 receives data packets from other modules in the DPU 350 or other devices except the DPU 350, and sends the data packets to the second logic module 410; after receiving the data packet, the second logic module 410 slices the data packet to obtain three data frames; when the instantaneous bandwidth of the PCIE bus at the current moment is greater than or equal to the preset bandwidth, the second logic module 410 sends the three data frames to the receiving data buffer 420, and the receiving data buffer 420 caches the three data frames; when the instantaneous bandwidth of the PCIE bus at the next moment after the current moment is less than the preset bandwidth, the receiving data buffer 420 stores the cached three data frames in sequence in the three memory blocks in the memory 340 through the PCIE bus at the next moment.

[0090] Among them, the three memory blocks are obtained based on slicing the memory 340; the storage capacity of each memory block is greater than or equal to the number of bits of the corresponding data frame, and the storage capacity of the three memory blocks is greater than or equal to the maximum number of bits that the PCIE bus can carry.

[0091] The technical solution provided in the embodiment of the present application can reduce the transmission delay of the data packet and improve the efficiency of the DPU in data transmission by slicing the received data packet through the second logic module and then sequentially storing the obtained at least two data frames in the corresponding at least two memory blocks. In addition, when the PCIE bus has idle bandwidth at the current moment, at least two data frames are transmitted to avoid packet loss caused by transmitting at least two data frames when the PCIE bus has no idle bandwidth.

[0092] The preferred embodiments of the present application are described in detail above in conjunction with the accompanying drawings. However, the present application is not limited to the specific details in the above embodiments. Within the technical concept of the present application, the technical solution of the present application can be subjected to a variety of simple modifications, and these simple modifications all belong to the protection scope of the present application. For example, the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present application will not further explain various possible combinations. For another example, the various different embodiments of the present application can also be arbitrarily combined, as long as they do not violate the idea of ​​the present application, they should also be regarded as the contents disclosed in the present application. For another example, under the premise of no conflict, the various embodiments and / or the technical features in the various embodiments described in the present application can be arbitrarily combined with the prior art, and the technical solution obtained after the combination should also fall within the protection scope of the present application.

[0093] It should also be understood that in the various method embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0094] Based on the same inventive concept as the above embodiments, Figure 5 is a schematic diagram of the composition structure of a DPU-based data transmission device provided in an embodiment of the present application, such as Figure 5 As shown, the DPU-based data transmission device 500 may include a cache module 510 and a communication module 520, wherein:

[0095] The cache module 510 is used to cache the first data frame in the memory to the sending data buffer through a PCIE bus in a programmable input / output PIO data transmission mode;

[0096] The cache module 510 is further used to cache the command frame in the memory to the sending command buffer through a PCIE bus in a PIO command transmission mode; wherein the command frame is used to indicate that the first data frame has been cached in the sending data buffer;

[0097] The communication module 520 is used to read a command frame from a sending command buffer through a first logic module, and read and send a first data frame from a sending data buffer based on an instruction of the command frame.

[0098] In some embodiments, Figure 5 As shown, the DPU-based data transmission device 500 may further include a mapping module 530; wherein:

[0099] A mapping module 530, configured to map a send data buffer to a first location in a memory, wherein a memory attribute of the first location is a write-combining attribute;

[0100] The cache module 510 is further configured to cache the first data frame corresponding to the first position into a sending data buffer through a PCIE bus.

[0101] In some embodiments, the mapping module 530 is also used to map the send command buffer to a second location in the memory, and the memory attribute of the second location is a non-cacheable attribute; and the cache module 510 is also used to cache the command frame corresponding to the second location to the send command buffer through a PCIE bus.

[0102] In some embodiments, the command frame includes at least one of the following information: the length of the first data frame, the start flag of the first data frame, and the end flag of the first data frame; the communication module 520 is also used to read the first data frame from the sending data buffer based on the indication of the command frame and at least one piece of information.

[0103] In some embodiments, Figure 5 As shown, the DPU-based data transmission device 500 may further include a slicing module 540; wherein:

[0104] The communication module 520 is further configured to receive a data packet through the second logic module;

[0105] The slicing module 540 is used to slice the data packet to obtain at least two data frames;

[0106] The cache module 510 is also used to store at least two data frames sliced ​​and processed by the second logic module in the corresponding at least two memory blocks in sequence through the PCIE bus at the current moment if the instantaneous bandwidth of the PCIE bus at the current moment is less than the preset bandwidth; wherein the at least two memory blocks are obtained based on slicing the memory; the storage capacity of each memory block is greater than or equal to the number of bits of the corresponding data frame, and the storage capacity of the at least two memory blocks is greater than or equal to the maximum number of bits that the PCIE bus can carry.

[0107] In some embodiments, the communication module 520 is also used to send at least two data frames to the receiving data buffer through the second logic module if the instantaneous bandwidth of the PCIE bus at the current moment is greater than or equal to the preset bandwidth; the cache module 510 is also used to cache at least two data frames through the receiving data buffer; if the instantaneous bandwidth of the PCIE bus at the next moment after the current moment is less than the preset bandwidth, then at the next moment, the at least two data frames cached in the receiving data buffer are stored in sequence in the corresponding at least two memory blocks through the PCIE bus.

[0108] In some embodiments, the second data frame includes at least one of a frame header, a payload and invalid padding data; wherein the invalid padding data is used to fill idle bits in the second data frame; the frame header includes at least one of the following: the length of the second data frame, the timestamp of the second data frame, the length of the payload, the start flag of the second data frame, the end flag of the second data frame, the frame type of the second data frame, the data type of the payload, the error frame identifier of the second data frame, and the frame status of the second data frame; the second data frame is the same frame as the first data frame, or the second data frame is any frame of at least two data frames.

[0109] In some embodiments, Figure 5 As shown, the DPU-based data transmission device 500 may further include an update module 550; wherein:

[0110] An updating module 550, configured to update the mode of the second logic module to the cut-through forwarding mode if the mode of the second logic module is other than the cut-through forwarding mode;

[0111] The slicing module 540 is also used to slice the data packet in the direct forwarding mode to obtain at least two data frames.

[0112] In the scheme of the embodiment of the present application, when the command frame and / or the first data frame in the memory is cached in the PIO transmission mode (corresponding to one PCIE bus), the command frame and / or the first data frame can be considered to be actively sent from the memory, so that there is no need to send a read request to the memory (corresponding to at least two PCIE buses) to make the memory passively send the command frame and / or the first data frame, thereby greatly compressing the delay of data reading and sending, and improving the efficiency of DPU data transmission.

[0113] Those skilled in the art should understand that the relevant description of the above-mentioned DPU-based data transmission device in the embodiment of the present application can be understood by referring to the relevant description of the DPU-based data transmission method in the embodiment of the present application.

[0114] An embodiment of the present application also provides a computer-readable storage medium for storing a computer program.

[0115] In some embodiments, the computer-readable storage medium can be applied to the DPU in the embodiments of the present application, and when the computer program is executed by one or more processors, it implements the corresponding processes implemented by the DPU in the various methods of the embodiments of the present application. For the sake of brevity, they are not repeated here.

[0116] An embodiment of the present application also provides a computer program product, including computer program instructions.

[0117] In some embodiments, the computer program product can be applied to the DPU in the embodiments of the present application, and the computer program instructions enable the computer to execute the corresponding processes implemented by the DPU in the various methods of the embodiments of the present application. For the sake of brevity, they will not be repeated here.

[0118] The embodiment of the present application also provides a computer program.

[0119] In some embodiments, the computer program can be applied to the DPU in the embodiments of the present application. When the computer program runs on a computer, the computer executes the corresponding processes implemented by the DPU in the various methods of the embodiments of the present application. For the sake of brevity, they will not be repeated here.

[0120] Those of ordinary skill in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of this application.

[0121] It should be noted that, in this application, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0122] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0123] The methods disclosed in several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0124] The features disclosed in several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0125] The features disclosed in several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0126] The above implementation methods are only used to illustrate the embodiments of the present application, and are not limitations on the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present application. The scope of patent protection of the embodiments of the present application should be limited by the claims.

Claims

1. A data transmission method based on DPU, characterized in that: Applied to a data processing unit DPU, the DPU includes a sending command buffer, a sending data buffer and a first logic module, the method includes: Buffering the first data frame in the memory to the sending data buffer through a PCIE bus in a programmable input / output (PIO) data transmission mode; In a PIO command transmission mode, the command frame in the memory is cached to the sending command buffer through the PCIE bus once; wherein the command frame is used to indicate that the first data frame has been cached in the sending data buffer; The command frame is read from the sending command buffer through the first logic module, and based on an instruction of the command frame, the first data frame is read from the sending data buffer and sent.

2. The method according to claim 1, characterized in that The step of caching the first data frame in the memory to the sending data buffer through a PCIE bus includes: The sending data buffer is mapped to a first position in the memory, the memory attribute of the first position is a write-merge attribute; and the first data frame corresponding to the first position is cached to the sending data buffer through the PCIE bus once.

3. The method according to claim 1, characterized in that The step of caching the command frame in the memory to the sending command buffer through the PCIE bus once includes: The sending command buffer is mapped to a second location in the memory, the memory attribute of the second location is a non-cacheable attribute; and the command frame corresponding to the second location is cached to the sending command buffer through the PCIE bus once.

4. The method according to any one of claims 1 to 3, characterized in that The command frame includes at least one of the following information: the length of the first data frame, the start flag of the first data frame, and the end flag of the first data frame; The step of reading the first data frame from the sending data buffer based on an instruction of the command frame comprises: Based on the instruction of the command frame and the at least one item of information, the first data frame is read from the sending data buffer.

5. The method according to claim 1, characterized in that The DPU further includes a second logic module, and the method further includes: Receiving a data packet through the second logic module, and slicing the data packet to obtain at least two data frames; If the instantaneous bandwidth of the PCIE bus at the current moment is less than the preset bandwidth, at the current moment, at least two of the data frames sliced ​​and processed by the second logic module are sequentially stored in the corresponding at least two memory blocks through the PCIE bus; Among them, at least two of the memory blocks are obtained based on slicing the memory; the storage capacity of each memory block is greater than or equal to the number of bits of the corresponding data frame, and the storage capacity of at least two of the memory blocks is greater than or equal to the maximum number of bits that the PCIE bus can carry.

6. The method according to claim 5, characterized in that The DPU also includes a receive data buffer, and the method further includes: If the instantaneous bandwidth of the PCIE bus at the current moment is greater than or equal to the preset bandwidth, sending at least two of the data frames to the receiving data buffer through the second logic module; Buffering at least two of the data frames by the receiving data buffer; If the instantaneous bandwidth of the PCIE bus at the next moment after the current moment is less than the preset bandwidth, at the next moment, at least two data frames cached in the receiving data buffer are sequentially stored in the corresponding at least two memory blocks through the PCIE bus.

7. The method according to claim 5 or 6, characterized in that: The second data frame includes at least one of a frame header, a payload, and invalid padding data; wherein, The invalid filling data is used to fill the idle bits in the second data frame; The frame header includes at least one of the following: the length of the second data frame, the timestamp of the second data frame, the length of the effective load, the start flag of the second data frame, the end flag of the second data frame, the frame type of the second data frame, the data type of the effective load, the error frame identifier of the second data frame, and the frame status of the second data frame; The second data frame is the same frame as the first data frame, or the second data frame is any one frame of at least two of the data frames.

8. The method according to claim 5 or 6, characterized in that: The slicing of the data packet to obtain at least two data frames includes: If the mode of the second logic module is other than the direct forwarding mode, after the mode of the second logic module is updated to the direct forwarding mode, the data packet is sliced ​​to obtain at least two data frames.

9. A data transmission device based on DPU, characterized in that: include: A cache module, used for caching the first data frame in the memory to the sending data buffer through a PCIE bus in a programmable input / output PIO data transmission mode; The cache module is further used to cache the command frame in the memory to the sending command buffer through the PCIE bus once in a PIO command transmission mode; wherein the command frame is used to indicate that the first data frame has been cached in the sending data buffer; The communication module is used to read the command frame from the sending command buffer through the first logic module, and read and send the first data frame from the sending data buffer based on the instruction of the command frame.

10. A computer-readable storage medium storing a computer program, wherein the computer program implements the method according to any one of claims 1 to 8 when executed by at least one processor.

Images