Process layer setting and displaying method in multi-process layout design

Abstract

The invention discloses a process layer setting and displaying method in multi-process layout design. The process layer setting and displaying method comprises the following steps: acquiring process layer information in a multi-process chip; adding a chip name to which the process layer belongs before the process layer name; process layers in the multi-process chip are displayed in a process layer setting window in a unified and centralized mode; and modifying the color definition of each process layer in the process layer setting window, and displaying each process layer in different colors in the layout. According to the layout design method, the chip information is added to the process layer and is intensively displayed in the process layer setting window, and the corresponding process layer information can be accurately found through top-layer design editing display or local editing to a single chip editing display, so that the layout design efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of EDA (electronic design automation), and in particular to a process layer setting and display method in multi-process layout design. Background Art

[0002] In the semiconductor industry, with the continuous development of 3D (three-dimensional) advanced packaging technology, cross-process chip integration has become the norm. This trend has brought unprecedented challenges. In the traditional single-process environment, the Layer Setting Windows (LSW, process layer setting window) in the layout design tool only displays the process layer of a single process. However, in cross-process advanced packaging, because it contains multiple chips of different processes, the process layer information in each chip is different. If the unified process layer information is forced to be used, the layout design error will be caused by the incorrect application of the process layer. Summary of the invention

[0003] In order to solve the defects of the prior art, the purpose of the present invention is to provide a process layer setting and display method in multi-process layout design. The layout design tool adds chip information to the process layer and displays it centrally in the process layer setting window. The corresponding process layer information can be accurately found in the top-level design editing and display or in-situ editing and display in a single chip.

[0004] In order to achieve the above-mentioned object, the present invention provides a method for setting and displaying process layers in a multi-process layout design, comprising:

[0005] Obtain process layer information in multi-process chips;

[0006] Add the chip name to which it belongs before the process layer name;

[0007] The process layers in the multi-process chip are displayed uniformly and centrally in a process layer setting window;

[0008] The color definition of each process layer is modified in the process layer setting window, and each process layer is displayed in a different color in the layout.

[0009] Furthermore, the step of obtaining process layer information in multi-process chips further includes: using EDA layout tools to obtain process layer information in all chips from process files, design rules and / or database files, and the process layer information includes process layer names and color definitions, as well as physical constraint rules.

[0010] Furthermore, the step of adding the chip name to which it belongs before the process layer name further includes: adding the instance name in the layout design to add the chip name to which it belongs before the process layer name in the multi-process chip; the multi-process chip includes a bottom silicon wafer, a middle silicon wafer and a top silicon wafer.

[0011] Furthermore, in the process layer setting window, it is set whether each process layer graphic in the multi-process chip is displayed and whether it can be selected.

[0012] Furthermore, when editing in-place into a chip, only the process layers of the chip to which it belongs can be highlighted and selected.

[0013] Furthermore, it also includes: in the cross-process chip package display and editing, the top-level design includes chips with top-level, middle-level, and bottom-level processes. The process layer setting window classifies and displays the process layer information of different chips, which are edited in situ into the top-level chip, and the process layer information in the top-level chip is highlighted.

[0014] On the other hand, the present invention also provides an electronic device equipped with an EDA design tool, which is used for integrated circuit layout design and processing process layers in multi-process chips to implement the process layer setting and display method in the multi-process layout design as described above.

[0015] On the other hand, the present invention also provides a computer-readable storage medium, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the process layer setting and display method in the multi-process layout design as described above.

[0016] The process layer setting and display method in the multi-process layout design provided by the present invention has the following beneficial effects compared with the prior art:

[0017] By adding chip information to the process layer and displaying it in the process layer setting window, the corresponding process layer information can be accurately found in the top-level design editing and display or in-situ editing and display in a single chip, ensuring the correct use of the process layer in the layout design, reducing the workload of later layout checking, and greatly improving the efficiency of layout design.

[0018] Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0020] Figure 1 A flow chart of a method for setting and displaying process layers in a multi-process layout design according to an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of a process layer setting window displaying chip names according to an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of display states of each layer according to an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of states of whether each layer can be selected according to an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram showing the colors of layers with the same name in different chips according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0026] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are only for exemplary purposes and are not intended to limit the scope of protection of the present invention.

[0027] The term "including" and its variations used herein are open inclusions, i.e., "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description.

[0028] It should be noted that the concepts of “first”, “second”, etc. may be mentioned in the present invention only to distinguish different devices, components or parts, and are not used to limit the order or interdependence of the functions performed by these devices, components or parts.

[0029] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more". "Plurality" should be understood as two or more.

[0030] In an embodiment of the present invention, a method for setting and displaying process layers in a multi-process layout design is provided, comprising the following steps: obtaining process layer information in a multi-process chip; adding the chip name to which the process layer belongs before the process layer name; displaying the process layers in the multi-process chip in a unified and centralized manner in a process layer setting window; modifying the color definition of each process layer in the process layer setting window, and displaying each process layer in a different color in the layout.

[0031] Figure 1 The flowchart of the process layer setting and display method in the multi-process layout design according to the embodiment of the present invention is combined with Figure 1 The embodiments of the present invention are described in further detail.

[0032] In step 101, process layer information in a multi-process chip is obtained.

[0033] In an embodiment of the present invention, the existing EDA layout tool is used to obtain the process layer information of all chips, including LPP (Layer Name Purpose Name Packet Name, indicating the process layer name and color definition) and physical constraint rules; wherein the physical constraint rules include Width (width) and Space (spacing).

[0034] In terms of obtaining process layer information, EDA tools provide the following methods:

[0035] Technology File: A technology file is a file that describes the manufacturing process of an integrated circuit, which contains information about various process layers, such as layer name, layer number, material properties, thickness, refractive index, etc. Designers can learn about the process layer information by reading the technology file.

[0036] Design Rules: Design rules are a set of rules that describe the constraints of each process layer in integrated circuit design. They are usually provided by semiconductor manufacturers to guide designers on how to use process layers correctly. Design rules include information such as the minimum width, minimum spacing, and minimum via size of each process layer.

[0037] Database Files: In integrated circuit design, designers usually use database files to store design data. These files may contain process layer information, such as geometric data of each process layer.

[0038] In step 102, the name of the chip to which it belongs is added before the name of each process layer.

[0039] In the embodiment of the present invention, the chip name (Chip Name) is added before the process layer name (Layer Name) in each chip by adding the instance name (Instance Name) in the design (Design). Figure 2 This is a schematic diagram of displaying chip names in a process layer setting window according to an embodiment of the present invention, which exemplarily shows the names of layer process chips displayed in the Layer setting window, such as Die_Bot, Die_Mid, and Die_Top.

[0040] In step 103, all process layers are displayed in a unified manner on LSW (process layer setting window).

[0041] In an embodiment of the present invention, whether each Layer Shape (process layer graphic) in the layout is displayed and can be selected can be controlled according to actual design needs. For example, a layer manager is used to manage and edit each layer. The layer manager allows us to easily view, modify and control the status of each layer. By selecting the corresponding layer in the layer manager and switching its status, the display and selectability of each layer of Shape can be quickly controlled. The display status of the layer can also be controlled by using the commands provided by the EDA software, such as using the "Layer status" command to open or close the selected Layer. This command can specify the layer to be opened or closed by entering the process layer name, selecting the layer, or using a filter. By using such a command, we can quickly control the display status of the layer and improve the efficiency of layout design. In addition, the EDA tool can also configure shortcut keys for corresponding functions to quickly control whether each layer of Shape in the layout is displayed and can be selected.

[0042] In the embodiment of the present invention, when Edit In Place (EIP for short) is performed in a specific Chip, only the Layer of the corresponding Chip can be highlighted and selected.

[0043] Figure 3 Schematic diagram of display status of each layer according to an embodiment of the present invention. Figure 3 As shown, the Layer Shape in the Chip named "Die_Mid" is invisible. Figure 4 Schematic diagram of the state of whether each layer can be selected according to an embodiment of the present invention, such as Figure 4 As shown, it means that Edit In Place is to the chip named "Die_Top". Only the Layer in the chip named Die_Top is in Active state and can be used, while the Layers in the other chips are in unusable state.

[0044] In step 104, the Packet (color definition) of each process layer is modified in the LSW window, and each process layer is displayed as a different Color in the layout.

[0045] In the embodiment of the present invention, the Color display of the Layer in each chip can be set according to actual design requirements. Figure 5 This is a schematic diagram of the color display of the layers with the same name in different chips according to an embodiment of the present invention, indicating that the layers with the same name are displayed in different colors in different chips. For example, if the layer is named M1, its colors displayed in the chips of the bottom layer (Bot, abbreviation of bottom), middle layer (Mid) and top layer (Top) are all different.

[0046] The following examples illustrate the application scenarios of the present invention:

[0047] In the cross-process chip package display and editing, Top Design includes chips of three processes: Top, Mid, and Bottom; the Layer setting window displays the Layer information of different chips in categories; EIP (in-place editing) is added to TopChip, and only the process layer information in Top Chip is highlighted.

[0048] The process layer setting and display method in the multi-process layout design provided by the present invention can centrally display the layer information in each chip in the Layer Setting window, and support the selection and display of corresponding Layer Shapes during the display and editing process. Through this method, the Layer Setting window in the EDA layout tool is used to centrally control and display the layer information in multiple processes. When displaying and editing, the corresponding process layer information can be accurately found, and the correctness of the layer use in the layout design can be determined, which reduces the workload of the later layout inspection and greatly improves the design efficiency of the layout design engineer.

[0049] In an embodiment of the present invention, an electronic device is also provided, which is equipped with an EDA design tool. The EDA design tool is used in integrated circuit layout design to process the process layers in a multi-process chip, thereby implementing the steps in the process layer setting and display method embodiment in the multi-process layout design as described above.

[0050] In an embodiment of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the steps in the embodiment of the process layer setting and display method in the multi-process layout design as described above when running.

[0051] In this embodiment, the above-mentioned computer-readable storage medium may include but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.

[0052] Those skilled in the art can understand that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention is described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions recorded in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for setting and displaying process layers in a multi-process layout design, characterized in that: The following steps are involved: Obtain process layer information in multi-process chips; Add the chip name to which it belongs before the process layer name; The process layers in the multi-process chip are displayed uniformly and centrally in a process layer setting window; The color definition of each process layer is modified in the process layer setting window, and each process layer is displayed in a different color in the layout.

2. The method for setting and displaying process layers in multi-process layout design according to claim 1, characterized in that: The step of obtaining process layer information in multi-process chips further includes: using EDA layout tools to obtain process layer information in all chips from process files, design rules and / or database files; the process layer information includes process layer names and color definitions, as well as physical constraint rules.

3. The method for setting and displaying process layers in multi-process layout design according to claim 1, characterized in that: The step of adding the chip name to which it belongs before the process layer name further includes: adding the instance name in the layout design to add the chip name to which it belongs before the process layer name in the multi-process chip; the multi-process chip includes a bottom silicon wafer, a middle silicon wafer and a top silicon wafer.

4. The method for setting and displaying process layers in multi-process layout design according to claim 1, characterized in that: In the process layer setting window, it is set whether each process layer graphic in the multi-process chip is displayed and whether it can be selected.

5. The method for setting and displaying process layers in multi-process layout design according to claim 1, characterized in that: When editing in-place into a chip, only the process layers of the chip to which it belongs can be highlighted and selected.

6. The method for setting and displaying process layers in multi-process layout design according to claim 1, characterized in that: Also includes: In the cross-process chip package display and editing, the top-level design includes chips of top-level, middle-level, and bottom-level processes. The process layer setting window displays the process layer information of different chips in a classified manner, edits them in situ into the top-level chip, and highlights the process layer information in the top-level chip.

7. An electronic device, characterized in that: The electronic device is equipped with an EDA design tool, which is used for integrated circuit layout design and processing process layers in multi-process chips to implement the process layer setting and display method in the multi-process layout design described in any one of claims 1-6.

8. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, which is loaded and executed by a processor to implement the process layer setting and display method in the multi-process layout design described in any one of claims 1-6.

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