Ball package structure determination method for LPDDR product and LPDDR product

Abstract

The embodiment of the present application provides a method for determining the ball packaging structure of an LPDDR product and an LPDDR product, belonging to the field of memory technology; the method includes determining four spaced and array-distributed packaging areas in a second packaging substrate of a target memory according to the layout information of a first packaging substrate of a compatible memory; obtaining the first position coordinates of the soldering ball corresponding to the first voltage signal configured in the compatible memory and the signal difference data between the target memory and the compatible memory; establishing a first mapping relationship between the soldering ball at the first position coordinate in the packaging area and the second voltage signal configured in the target memory; adjusting the second mapping relationship between the remaining signal configured in the target memory and the remaining soldering balls in each packaging area according to the signal difference data to determine the ball packaging structure of the second packaging substrate. The embodiment of the present application can shorten the development cycle and application risk of the target LPDDR product in a compatible scenario.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a method for determining a ball packaging structure of an LPDDR product and an LPDDR product. Background Art

[0002] With the development of science and technology, the requirements for the read and write speed of memory are getting higher and higher. Therefore, the update and iteration speed of memory product models has also increased accordingly. Especially for LPDDR products, since different models of LPDDR products have different ball packaging structures, when updating LPDDR products, it is necessary to simultaneously change the motherboard carrying LPDDR products, resulting in an increase in the development cycle and risk of LPDDR products. For example, taking LPDDR5 as an example, LPDDR5 has a higher read and write rate than LPDDR4, but in related technologies, LPDDR5 often adopts a 315 ball packaging structure, which is larger in size and has a large difference from LPDDR4 products. As a result, when switching LPDDR4 products, it is necessary to redesign the motherboard matching LPDDR5. At this time, the LPDDR product development cycle also needs to increase the motherboard development time, thereby increasing the development cycle and application risk of LPDDR products. Therefore, there is an urgent need for a method for determining the ball packaging structure of a memory, which can quickly assist in determining the ball packaging structure in a compatible scenario, thereby shortening the development cycle and application risk of the target LPDDR product. Summary of the invention

[0003] The main purpose of the embodiments of the present application is to propose a method for determining the ball packaging structure of an LPDDR product and an LPDDR product, which can shorten the development cycle and application risk of a target LPDDR product in a compatible scenario.

[0004] To achieve the above-mentioned purpose, a first aspect of an embodiment of the present application provides a method for determining a ball package structure of an LPDDR product, the method comprising:

[0005] According to the layout information of the first packaging substrate of the pre-compatible compatible memory, four packaging areas that are spaced apart and distributed in an array are determined in the second packaging substrate of the target memory; wherein the first packaging substrate and the second packaging substrate have the same size, and the total number of solder balls in the four packaging areas is the same as the total number of solder balls in the first packaging substrate;

[0006] Acquire a first position coordinate of a welding ball corresponding to a first voltage signal configured in the compatible memory, and acquire signal difference data between the target memory and the compatible memory;

[0007] Establishing a first mapping relationship between the welding ball at the first position coordinate in the packaging area and the second voltage signal configured in the target memory;

[0008] According to the signal difference data, a second mapping relationship between the remaining signals configured in the target memory and the remaining solder balls in each of the packaging areas is adjusted to determine a ball packaging structure of the second packaging substrate when a preset product requirement condition is met.

[0009] To achieve the above-mentioned purpose, the second aspect of an embodiment of the present application proposes an LPDDR product, wherein the LPDDR product includes a second packaging substrate. When the LPDDR product is used as a target memory compatible with a preset compatible memory, the ball packaging structure of the second packaging substrate is obtained by any method described in the first aspect.

[0010] The ball package structure determination method and LPDDR product of the LPDDR product proposed in the present application determine four spaced and array-distributed package areas based on the layout information of the first package substrate, thereby reducing the number of solder balls set in the second package substrate. At the same time, by first determining the first position coordinates and establishing a first mapping relationship between the solder balls at the first position coordinates in the second package substrate and the second voltage signal, at this time, the connection direction of the voltage signal on the second package substrate is consistent with the connection direction of the voltage signal on the first package substrate, thereby reducing the difference between the first package substrate and the second package substrate. At the same time, by constructing the second mapping relationship between the remaining solder balls and the remaining signals based on the signal difference data, it can be ensured that the performance meets the requirements. Therefore, the embodiment of the present application can minimize the number of solder balls and take into account the performance while ensuring that the solder ball mapping relationship is as close as possible to the compatible memory, thereby reducing the development cycle and application risk of the second package substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a flow chart of a method for determining a ball package structure of an LPDDR product provided in the present application;

[0012] Figure 2 It is a schematic diagram of the distribution of solder balls on a second packaging substrate in one embodiment of a method for determining a ball packaging structure of an LPDDR product provided in the present application;

[0013] Figure 3 It is a schematic diagram of signal distribution corresponding to each welding ball on the second packaging substrate obtained in one embodiment of the ball packaging structure determination method of the LPDDR product provided by the present application;

[0014] Figure 4It is a schematic diagram of signal distribution corresponding to each welding ball on the second packaging board under the first candidate mapping relationship in an embodiment of the ball packaging structure determination method of the LPDDR product provided by the present application;

[0015] Figure 5 is a schematic diagram of signal distribution corresponding to each welding ball on the second packaging board under the first candidate mapping relationship in another embodiment of the ball packaging structure determination method of the LPDDR product provided by the present application;

[0016] Figure 6 It is a schematic diagram of signal distribution corresponding to each welding ball on the second packaging board under the second candidate mapping relationship in one embodiment of the ball packaging structure determination method of the LPDDR product provided by the present application. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0018] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0020] First, some nouns involved in this application are analyzed:

[0021] LPDDR5, or Low Power Double Data Rate 5, is a low-power double data rate memory standard.

[0022] With the development of science and technology, the requirements for the read and write speed of memory are getting higher and higher. Therefore, the update and iteration speed of memory product models has also increased accordingly. Especially for LPDDR products, because different models of LPDDR products have different ball packaging structures, when updating LPDDR products, it is necessary to simultaneously change the motherboard carrying LPDDR products, which increases the development cycle and risk of LPDDR products. For example, LPDDR5 has a higher read and write rate than LPDDR4. For example, LPDDR5X can even reach 8.5Gbps, which is twice as fast as LPDDR4X's 4.2Gbps. However, in related technologies, LPDDR5 often adopts a 315-ball packaging structure, which is larger in size and has a big difference from LPDDR4 products. As a result, when switching LPDDR4 products, it is necessary to redesign the motherboard that matches LPDDR5. At this time, the development cycle of LPDDR products also needs to increase the motherboard development time, thereby increasing the development cycle and application risk of LPDDR products. Therefore, there is an urgent need for a method for determining the ball packaging structure of a memory, which can quickly assist in determining the ball packaging structure in a compatible scenario, thereby shortening the development cycle and application risk of a target LPDDR product. Based on this, the present application provides a method for determining the ball packaging structure of an LPDDR product and an LPDDR product, which can shorten the development cycle and application risk of a target LPDDR product when it is necessary to support a compatible scenario.

[0023] The ball package structure determination method of the LPDDR product and the LPDDR product provided in the embodiments of the present application are specifically described through the following embodiments. First, the ball package structure determination method of the LPDDR product in the embodiments of the present application is described.

[0024] The memory of the present application can be used in many general or special computer system environments or configurations, such as personal computers, server computers, handheld devices or portable devices, tablet devices, multi-processor systems, etc.

[0025] Understandably, referring to Figure 1 As shown, according to a method for determining a ball package structure of an LPDDR product provided in an embodiment of the present application, the method includes:

[0026] Step S100, according to the layout information of the first packaging substrate of the pre-compatible compatible memory, four packaging areas that are spaced apart and distributed in an array are determined in the second packaging substrate of the target memory; wherein the first packaging substrate and the second packaging substrate have the same size, and the total number of solder balls in the four packaging areas is the same as the total number of solder balls in the first packaging substrate;

[0027] Step S200, obtaining the first position coordinates of the welding ball corresponding to the first voltage signal configured in the compatible memory, and obtaining signal difference data between the target memory and the compatible memory;

[0028] Step S300, establishing a first mapping relationship between a welding ball at a first position coordinate in a packaging area and a second voltage signal configured in a target memory;

[0029] Step S400: adjusting the second mapping relationship between the remaining signals configured in the target memory and the remaining solder balls in each packaging area according to the signal difference data, so as to determine the ball packaging structure of the second packaging substrate when the preset product requirement condition is met.

[0030] Therefore, by determining four spaced and array-distributed packaging areas based on the layout information of the first packaging substrate, the number of solder balls set in the second packaging substrate is reduced. At the same time, by first determining the first position coordinates and establishing a first mapping relationship between the solder balls at the first position coordinates in the second packaging substrate and the second voltage signal, at this time, the connection direction of the voltage signal on the second packaging substrate is consistent with the connection direction of the voltage signal on the first packaging substrate, thereby reducing the difference between the first packaging substrate and the second packaging substrate. At the same time, by constructing a second mapping relationship between the remaining solder balls and the remaining signals based on the signal difference data, it can be ensured that the performance meets the requirements. Therefore, the embodiment of the present application can minimize the number of solder balls and take into account the performance while ensuring that the solder ball mapping relationship is as close as possible to that of the compatible memory, thereby reducing the development cycle and application risk of the second packaging substrate.

[0031] The performance of the target memory is better than that of the compatible memory, and the target memory is an LPDDR product that can replace the compatible memory and has higher performance. The packaging area is the area where the solder balls are arranged, and the embodiment of the present application does not impose too many restrictions on the packaging structure of the compatible memory. The spacing of the packaging areas can enhance the anti-interference ability of the LPDDR product, and the total number of solder balls deployed in the four packaging areas is kept consistent with that in the first packaging substrate, which can reduce the number of solder balls of the target memory while also being compatible with the motherboard of the memory. Moreover, since the number of solder balls of the target memory is reduced relative to the existing packaging structure of the target memory, the packaging structure of the target memory obtained by the embodiment of the present application is smaller in size. Among them, each solder ball corresponds to a signal.

[0032] The layout information includes, for example, the size of the first package substrate (such as thickness, width, length, etc.), the number of solder balls, the size of the solder balls, the interval, etc.

[0033] The first voltage signal is a voltage signal required for the compatible memory to work normally, as shown in FIG. Figure 3 As shown, the first voltage signal includes VDD1 、V DD2 、V DDQ and V SS The second voltage signal is a voltage signal required for the target memory to work normally. For example, the second voltage signal includes V DD1 、V DD2H 、V DD2L 、V DDQ and V SS . Establishing the first mapping relationship indicates that the solder ball at the first position coordinate in the first packaging area can be used to transmit the second voltage signal. In some embodiments, there are multiple first voltage signals and second voltage signals, and then there are multiple first position coordinates, and the types of voltage signals connected to the solder balls at the same first position coordinates of the first packaging substrate and the second packaging substrate are the same. By first determining the mapping relationship between the voltage signal and the solder ball, the embodiment of the present application can facilitate the determination of the mapping relationship between the remaining signals and the solder ball.

[0034] The signal difference data characterizes the difference in the signal of the solder ball connection at the same position of the target memory and the compatible memory. The present application does not limit how to adjust the second mapping relationship between the remaining signals and the remaining solder balls. Those skilled in the art can adjust by combining and replacing each solder ball one by one, and can determine whether the ball packaging structure of the second packaging substrate meets the product requirements through simulation. Product requirements such as performance, etc.

[0035] It is understandable that a greater number of solder balls requires more solder lines, which results in a larger size of the LPDDR product.

[0036] For example, refer to Figure 2 and Figure 3 As shown, taking the target memory as LPDDR5 and the compatible memory as LPDDR4 as an example, referring to step S100, the following can be obtained: Figure 2 The second packaging substrate shown in Figure 2 As shown, each packaging area of ​​the second packaging substrate is set to a 5*10 solder ball matrix, the solder balls in the same row are distributed at equal intervals, and the solder balls in the same column are distributed at equal intervals. Referring to steps S200 to S400, the following can be obtained: Figure 3 The signal diagram of the solder ball definition on the second package substrate is shown. At this time, by redefining the signal of the solder balls on the second package substrate and rearranging the number of solder balls, a ball package structure compatible with LPDDR4 and LPDDR5 performance can be obtained.

[0037] It is understandable that obtaining the signal difference data between the target memory and the compatible memory includes:

[0038] Classify the signals of the target memory and the compatible memory according to the functional signal type, the power signal type and other types;

[0039] Determine, according to the classification result, a first association relationship between a plurality of first functional signals configured in the compatible memory and a plurality of second functional signals of the target memory under the functional signal type;

[0040] Determine, according to the classification result, a second association relationship between a plurality of first remaining signals configured in the compatible memory under the remaining type and a plurality of second remaining signals of the target memory;

[0041] Signal difference data is obtained according to the first association relationship and the second association relationship.

[0042] Classifying the signals and processing them separately based on the classification results can improve the efficiency of adjustment.

[0043] Functional signal type is used to distinguish signals with functions, such as clock enable signal (CKE0_A), clock signal (CK_t_A), etc. Power signal type is used to distinguish signals that provide voltage, such as V DD1 ; The remaining types are used to distinguish signals other than functional signal types and power signal types, such as NC, etc. The signals corresponding to the remaining types include at least reserved idle signals (i.e. Figure 3 NC shown).

[0044]

[0045] Table 1

[0046] The first association relationship represents the usage mapping relationship between the first functional signal and the second functional signal, so that based on the first association relationship, the newly added functional signals of the target memory relative to the compatible memory and the redundant functional signals of the compatible memory relative to the target memory can be determined, as well as the functional signals with the same usage in the target memory and the compatible memory can be determined.

[0047] The second association relationship represents the usage mapping relationship between the first remaining signal and the second remaining signal. Therefore, the remaining signals newly added to the target memory relative to the compatible memory and the remaining signals redundant to the compatible memory relative to the target memory can be determined based on the second association relationship.

[0048] It can be understood that the number of functional signals in the target memory is less than or equal to the sum of the number of functional signals in the compatible memory and the number of reserved idle signals.

[0049] Exemplarily, taking the compatible memory as LPDDR4 and the target memory as LPDDR5 as an example, in order to satisfy the LPDDR5 compatibility with LPDDR4 motherboard, the signals of LPDDR4 and LPDDR5 are classified as shown in Table 1.

[0050] Referring to Table 1 above, it can be seen that compared with LPDDR4 products, LPDDR5 has an additional CA6 signal, two groups of WCK differential signals (WCK[1:0]_t_[A:B] and WCK[1:0]_c_[A:B]), VDD2H and VDD2L signals, and reduces one ODT / ZQ signal and two groups of CKE signals (one group is CKE0_A, CKE0_B, and the other group is CKE1_A, CKE1_B). Among them, V DD2H and V DD2L Function and V DD Therefore, V DD2H and V DD2L can be regarded as V DD At this time, as shown in Table 1, a first association relationship can be obtained that records the newly added function signal (CA6 signal and 2 groups of WCK differential signals), redundant function signals (clock enable signals (CKE0_A, CKE1_A, CKE0_B, CKE1_B), ODT_CA_A, ODT_CA_B) and general function signals (such as DQ[15:0]_[A:B], etc.). Similarly, as shown in Table 1, a second association relationship that records the reserved idle signal NC and the performance signal DNU can be obtained.

[0051] It is understandable that the first voltage signal and the second voltage signal are provided in plurality; and the method further comprises:

[0052] Determine, according to the classification result, a third association relationship between the plurality of first voltage signals and the plurality of second voltage signals under the power signal type;

[0053] Establishing a first mapping relationship between the welding ball at the first position coordinate of each packaging area and the second voltage signal of the target memory includes:

[0054] Determine a third mapping relationship between the second voltage signal and the first position coordinates according to the third association relationship and each first position coordinate;

[0055] According to the third mapping relationship, a first mapping relationship between the welding balls at the first position coordinates of each packaging area and each second voltage signal is established.

[0056] In some embodiments, the second voltage signal shown in Table 1 includes V DD1 、V DD2H、 V DD2L 、V DDQ and V SSThe first voltage signal includes V DD1 、V DD2 、V DDQ and V SS The third association relationship records the mapping relationship between the first voltage signal and the second voltage signal. For example, referring to Table 1, the third association relationship records the mapping relationship between the first voltage signal and the second voltage signal in the compatible memory. DDQ and V in the target memory DDQ One-to-one correspondence, compatible with V in memory DD2 and V in the target memory DD2H、 V DD2L One to one correspondence.

[0057] It can be understood that adjusting the first mapping relationship between the remaining signals in the target memory and the remaining solder balls in each packaging area according to the signal difference data includes:

[0058] According to the first association relationship, determining redundant function signals and common function signals from the plurality of first function signals and determining newly added function signals from the plurality of second function signals;

[0059] According to the second association relationship, determining a reserved idle signal and a performance signal from the plurality of first remaining signals;

[0060] Determine second position coordinates in the first packaging substrate corresponding to the redundant function signal, the reserved idle signal, and the performance signal one by one;

[0061] According to the first association relationship and the second association relationship, a fourth mapping relationship is established between the solder balls at the third position coordinates in the packaging area and the universal function signal; wherein the third position coordinates represent the positions in the packaging area other than the first position coordinates and the second position coordinates;

[0062] The mapping relationship is adjusted according to the newly added function signal, the performance signal and each second position coordinate.

[0063] The reserved idle signal means that the reserved signal can be replaced by other signals, such as signals that can be replaced by function signals or power signals, and the performance signal is a signal that can affect performance (such as DNU). The adjustment efficiency can be improved by first establishing the fourth mapping relationship for the general function signal and then adjusting the newly added function signal and performance signal.

[0064] It is understandable that the general function signal includes a clock input signal and the newly added function signal includes a differential signal, and the mapping relationship is adjusted according to the newly added function signal and each second position coordinate, including:

[0065] Acquire fourth position coordinates in the package area corresponding to the clock input signal one by one;

[0066] The mapping relationships between the solder balls at the fourth position coordinates and the second position coordinates in each packaging area and the clock input signal and the differential signal are adjusted multiple times.

[0067] By including both the input signal and the differential signal as adjustments, it is possible to further ensure that the performance meets the requirements.

[0068] It is understandable that the differential signal is set in multiple ways, and the mapping relationship between the solder balls at the fourth position coordinates and the second position coordinates in each packaging area and the clock input signal and the differential signal is adjusted multiple times, including:

[0069] The plurality of differential signals are respectively set at positions of a plurality of different first position combinations composed of different second position coordinates to obtain a plurality of first candidate mapping relationships;

[0070] The plurality of differential signals are respectively set at positions of different second position combinations composed of different fourth position coordinates and second position coordinates to obtain a second candidate mapping relationship.

[0071] For example, refer to Figures 4 to 6 As shown, the second position coordinates are A1, A2, A5, A8, A11, A12, B1, B12, G2, G11, J4, J5, K5, K8, N5, N8, P4, P5, T2, AA1, AA12, AB1, AB2, AB11, AB12. The fourth position coordinates include: J8, J9, P8, P8. At this time, when different second position coordinates are combined, the following can be obtained: Figure 4 and Figure 5 The mapping diagram of the signal of the second package substrate and the solder ball is shown in FIG. When the fourth position coordinate and the second position coordinate are combined to participate in the signal adjustment, the following can be obtained: Figure 3 and Figure 6 The mapping diagram of signals and solder balls on the second package substrate is shown.

[0072] In some embodiments, reference Figure 3 and Figure 6 As shown, the general function signal also includes a reset signal. The fifth position coordinate of the reset signal is used in the signal adjustment, and then the result is Figure 3 and Figure 6 The locations of CA6 and RESET_n mappings are shown.

[0073] It is understandable that determining the ball packaging structure of the second packaging substrate that meets the preset product requirement conditions includes:

[0074] Obtaining a first memory performance simulation result corresponding to the first candidate mapping relationship, and obtaining a second memory performance simulation result corresponding to the second candidate mapping relationship;

[0075] Compare the first memory performance simulation result with the second memory performance simulation result, and select a first candidate mapping relationship with the best performance simulation result as the target mapping relationship;

[0076] According to the target mapping relationship, the first mapping relationship and the fourth mapping relationship, a ball packaging structure of the second packaging substrate that meets preset product requirement conditions is obtained.

[0077] Exemplarily, the ball packaging structure of the second packaging substrate is adjusted as follows: Figures 3 to 6 There are four types shown as examples, among which, Figure 3 and Figure 6 The corresponding second candidate mapping relationship is: Figure 4 and Figure 5 The corresponding first candidate mapping relationship is based on Figure 3 The ball packaging structure is simulated to obtain the first simulation result. Figure 4 The ball packaging structure is simulated to obtain the second simulation result. Figure 5 The ball packaging structure is simulated to obtain the third simulation result. Figure 6 The ball package structure is simulated to obtain a fourth simulation result. When the first simulation result is better than the second simulation result, the third simulation result and the fourth simulation result, then Figure 3 The ball packaging result shown is the ball packaging structure when the product requirement conditions are met.

[0078] It is understandable that, according to an LPDDR product provided by the present application, the LPDDR product includes a second packaging substrate. When the LPDDR product is used as a target memory compatible with a preset compatible memory, the ball packaging structure of the second packaging substrate is obtained by the above method.

[0079] For example, Figure 2 As shown in FIG. 1 , the second package substrate is divided into 12 columns (respectively 1 to 12 columns) and 22 rows (respectively A to AB rows), wherein a gap is reserved between the outermost columns and the second package substrate. The four package areas are as follows Figure 2 As shown, each package area is provided with 10 rows and 5 columns of solder balls, and the solder balls in each package area are arranged at equal intervals. The distance between two adjacent solder balls is defined as the solder ball pitch, and two solder ball pitches are spaced between two adjacent package areas. Those skilled in the art can selectively set the number of solder balls in the package area according to the actual requirements of the number of solder balls in the target memory and the compatible memory.

[0080] For example, taking LPDDR4 as the compatible memory and LPDDR5 as the target memory, the above method can be used to design LPDDR5 into a 200-ball packaging structure. By redefining the mapping relationship between solder balls and signals for the 200-ball package, the 200-ball packaging method of the LPDDR5 product can be realized, thereby doubling the speed based on LPDDR4. At the same time, the target memory can be compatible with the product design motherboard of LPDDR4. At this time, the entire development cycle of the LPDDR5 product will be reduced accordingly, and the application risk will also be reduced accordingly.

[0081] It can be understood that two adjacent packaging areas are separated by two solder ball pitches, and the solder ball pitch is used to characterize the distance between two adjacent solder balls in the arrangement direction of the two adjacent packaging areas.

[0082] It is understandable that the embodiment of the present application does not limit the diameter of the welding balls, nor does it limit the spacing between the welding balls. The spacing between the welding balls in different directions is not limited and can be the same or different. Figure 2 As shown, the solder ball spacing in the horizontal and vertical directions is different, such as Figure 2 As shown, the horizontal solder ball spacing is 0.8 mm; the vertical solder ball spacing is 0.65 mm.

[0083] It is understandable that the target memory is set to LPDDR5, the compatible memory is set to LPDDR4, the remaining signals of LPDDR5 include A channel clock input signal, A channel differential signal, B channel clock input signal and B channel differential signal, the A channel differential signal and the B channel differential signal are symmetrically arranged up and down, and the two groups of differential signals in the A channel differential signal and the B channel differential signal are respectively located in the two package areas distributed on the left and right and are adjacently symmetrically distributed. At this time, referring to the above steps S100~S400, the following can be obtained: Figure 3 The diagram shows the signals defined on each solder ball on the second package substrate.

[0084] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0085] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0086] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0087] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0088] The terms "including" and "having" and any variations thereof in the specification of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products or apparatuses.

[0089] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0090] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0091] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0092] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0093] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0094] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A method for determining a ball package structure of an LPDDR product, characterized in that: The method comprises: According to the layout information of the first packaging substrate of the pre-compatible compatible memory, four packaging areas that are spaced apart and distributed in an array are determined in the second packaging substrate of the target memory; wherein the first packaging substrate and the second packaging substrate have the same size, and the total number of solder balls in the four packaging areas is the same as the total number of solder balls in the first packaging substrate; Acquire a first position coordinate of a welding ball corresponding to a first voltage signal configured in the compatible memory, and acquire signal difference data between the target memory and the compatible memory; Establishing a first mapping relationship between the welding ball at the first position coordinate in the packaging area and the second voltage signal configured in the target memory; According to the signal difference data, adjusting the second mapping relationship between the remaining signal configured in the target memory and the remaining solder balls in each of the packaging areas to determine the ball packaging structure of the second packaging substrate when the preset product requirement conditions are met; The step of acquiring signal difference data between the target memory and the compatible memory includes: Classifying the signals of the target memory and the compatible memory according to the functional signal type, the power signal type and other types; Determine, according to the classification result, a first association relationship between a plurality of first functional signals configured in the compatible memory and a plurality of second functional signals of the target memory under the functional signal type; Determine, according to the classification result, a second association relationship between a plurality of first remaining signals configured in the compatible memory and a plurality of second remaining signals of the target memory under the remaining type; Obtaining the signal difference data according to the first association relationship and the second association relationship; The step of adjusting the second mapping relationship between the remaining signals configured in the target memory and the remaining solder balls in each of the packaging areas according to the signal difference data includes: According to the first association relationship, determining redundant function signals and common function signals from the plurality of first function signals and determining newly added function signals from the plurality of second function signals; Determine a reserved idle signal and a performance signal from the plurality of first remaining signals according to the second association relationship; Determine second position coordinates in the first packaging substrate corresponding to the redundant function signal, the reserved idle signal, and the performance signal one by one; According to the first association relationship and the second association relationship, a fourth mapping relationship is established between the solder balls at the third position coordinates in the packaging area and the universal function signal; wherein the third position coordinates represent the positions in the packaging area other than the first position coordinates and the second position coordinates; A mapping relationship is adjusted according to the newly added function signal, the performance signal and each of the second position coordinates.

2. The method for determining the ball package structure of an LPDDR product according to claim 1, characterized in that: There are a plurality of the first voltage signal and the second voltage signal; and the method further includes: Determine, according to the classification result, a third association relationship between the plurality of first voltage signals and the plurality of second voltage signals under the power signal type; The step of establishing a first mapping relationship between the welding ball at the first position coordinate of the packaging area and the second voltage signal of the target memory includes: Determine a third mapping relationship between the second voltage signal and the first position coordinates according to the third association relationship and each of the first position coordinates; A first mapping relationship between the welding ball at the first position coordinate in the packaging area and each of the second voltage signals is established according to the third mapping relationship.

3. The method for determining the ball package structure of an LPDDR product according to claim 1, characterized in that: The general function signal includes a clock input signal and the newly added function signal includes a differential signal, and the mapping relationship adjustment according to the newly added function signal, the performance signal and each of the second position coordinates includes: Acquire fourth position coordinates in the packaging area that correspond one-to-one to the clock input signal; The mapping relationships between the fourth position coordinates in each packaging area and the solder balls at each second position coordinate and the clock input signal and the differential signal are adjusted multiple times.

4. The method for determining the ball package structure of an LPDDR product according to claim 3, characterized in that: The differential signal is provided in plurality, and the mapping relationship between the solder balls at the fourth position coordinates and the second position coordinates in each packaging area and the clock input signal and the differential signal is adjusted multiple times, respectively, including: The plurality of differential signals are respectively set at positions of a plurality of different first position combinations composed of different second position coordinates to obtain a plurality of first candidate mapping relationships; The plurality of differential signals are respectively set at positions of different second position combinations consisting of different fourth position coordinates and different second position coordinates to obtain a second candidate mapping relationship.

5. The method for determining the ball package structure of the LPDDR product according to claim 4, characterized in that: The determining of the ball packaging structure of the second packaging substrate when the preset product requirement condition is met includes: Obtaining a first memory performance simulation result corresponding to the first candidate mapping relationship, and obtaining a second memory performance simulation result corresponding to the second candidate mapping relationship; Compare the first memory performance simulation result with the second memory performance simulation result, and select the first candidate mapping relationship with the best performance simulation result as the target mapping relationship; According to the target mapping relationship, the first mapping relationship and the fourth mapping relationship, a ball packaging structure of the second packaging substrate that meets preset product requirement conditions is obtained.

6. A LPDDR product, characterized in that: The LPDDR product includes a second packaging substrate. When the LPDDR product is used as a target memory compatible with a preset compatible memory, a ball packaging structure of the second packaging substrate is obtained by the method described in any one of claims 1 to 5.

7. The LPDDR product according to claim 6, characterized in that: Two adjacent packaging areas are spaced apart by two solder ball pitches, and each solder ball pitch is used to characterize the distance between two adjacent solder balls in the arrangement direction of the two adjacent packaging areas.

8. The LPDDR product according to claim 6, characterized in that: The target memory is set to LPDDR5, the compatible memory is set to LPDDR4, the remaining signals of the LPDDR5 include an A-channel clock input signal, an A-channel differential signal, a B-channel clock input signal and a B-channel differential signal, the A-channel differential signal and the B-channel differential signal are symmetrically arranged up and down, and the two groups of differential signals in the A-channel differential signal and the B-channel differential signal are respectively located in two packaging areas distributed on the left and right and are adjacently symmetrically distributed.

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