Operation method of memory system, data reading method of memory, and memory system

Abstract

The invention provides an operation method of a storage system, a data reading method of a memory and the storage system, relates to the field of storage, and solves the problems that the reading retry rate of an NAND flash memory is increased and the reading performance is reduced due to threshold voltage deviation of a storage unit. According to the specific scheme, the operation method of the storage system comprises the steps that firstly, according to the number N of N word lines and offset voltage information, an offset voltage value corresponding to a selected word line in the N word lines is determined, the N word lines are adjacent word lines in a storage block Block of a memory, and data are stored in K storage units coupled with the N word lines, k and N are positive integers, and the offset voltage information is used for indicating an offset voltage value corresponding to N. Then, a data read command is sent to the memory, the data read command is used for instructing the memory to generate a read voltage according to the offset voltage value, and the read voltage is applied to the selected word line.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of storage, and in particular to an operating method of a storage system, a data reading method of a memory, and a storage system. Background Art

[0002] 3D NAND flash memory includes multiple storage blocks, each storage block includes multiple pages, and each page includes multiple storage cells. When some pages in a storage block are written with data, the storage block can be called an open block, and when all pages in a storage block are written with data, the storage block can be called a closed block.

[0003] As the demand for 3D NAND flash memory storage capacity continues to increase, 3D NAND flash memory continues to develop in the direction of device size reduction and stacking more layers, which will lead to an increase in the read retry ratio of the 3D NAND flash memory, a decrease in the read performance of the 3D NAND flash memory, and a poor user experience. Summary of the invention

[0004] The embodiments of the present disclosure provide a storage system operation method, a storage data reading method and a storage system, which solve the problem that the read retry rate of the NAND flash memory increases and the read performance decreases due to the threshold voltage offset of the storage unit.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a method for operating a storage system is provided, the method comprising: first, determining an offset voltage value corresponding to a selected word line among the N word lines according to the number N of N word lines and offset voltage information, the N word lines being adjacently arranged word lines in a storage block Block of a memory, and K storage cells coupled to the N word lines storing data, K and N being positive integers, and the offset voltage information being used to indicate an offset voltage value corresponding to N. Then, sending a data read command to the memory, the data read command being used to instruct the memory to generate a read voltage according to the offset voltage value, and to apply the read voltage to the selected word line.

[0007] Optionally, the offset voltage information may be in a table format or in other formats, which is not limited in the embodiments of the present disclosure.

[0008] Optionally, the selected word line may be one of N word lines, or may be a plurality of N word lines, which is not limited in the embodiments of the present disclosure.

[0009] Optionally, types of the K storage cells include at least one of a single-level cell, a multi-level cell, a triple-level cell and a quadruple-level cell, which is not limited in the embodiments of the present disclosure.

[0010] The operating method of the storage system provided by the embodiment of the present disclosure determines the offset voltage value corresponding to the selected word line among the N word lines according to the number N of N word lines and the offset voltage information, wherein the N word lines are word lines arranged adjacently in the storage block, and the K storage cells coupled to the N word lines store data. It can be understood that the offset voltage value determined by the embodiment of the present disclosure takes into account that when the number of word lines for writing data in the storage block is different, the offset amount of the threshold voltage of the storage cell in the storage block is different, so the offset voltage value determined by the embodiment of the present disclosure is more accurate, and the read voltage determined based on the offset voltage value is more accurate, thereby reducing the read retry rate of the memory and improving the read performance.

[0011] In some embodiments, the above-mentioned determining the offset voltage value corresponding to a selected word line among the N word lines based on the number N of N word lines and the offset voltage information includes: determining the offset voltage value corresponding to the selected word line based on N, the position information of the selected word line and the offset voltage information, the position information of the selected word line is used to indicate the position of the selected word line among the N word lines, and the offset voltage information is also used to indicate the offset voltage value corresponding to N and the position information of the selected word line.

[0012] The operating method of the storage system provided by the embodiment of the present disclosure determines the corresponding bias voltage value according to the position information of the selected word line among N word lines, which can further improve the accuracy of the offset voltage value. The memory applies a read voltage to the selected word line according to the offset voltage value, thereby further reducing the read retry rate and improving the read performance.

[0013] In some embodiments, the selected word line includes the first selected word line or the second selected word line, the first selected word line includes the 1st word line to the N-1th word line, and the second selected word line includes the Nth word line; according to N, the position information and the offset voltage information of the selected word line, determining the offset voltage value corresponding to the selected word line includes: according to N, the position information and the offset voltage information of the first selected word line, determining the first offset voltage value corresponding to the first selected word line. Alternatively, according to N, the position information and the offset voltage information of the second selected word line, determining the second offset voltage value corresponding to the second selected word line, the first offset voltage value is less than the second offset voltage value.

[0014] Optionally, the first selected word line includes one of the 1st to N-1th word lines, or includes a plurality of the 1st to N-1th word lines, which is not limited in the embodiments of the present disclosure.

[0015] In some embodiments, among the above-mentioned K memory cells, the memory cell coupled to the selected word line is programmed into multiple programming states, and the above-mentioned determining the offset voltage value corresponding to the selected word line among the N word lines based on the number N of the N word lines and the offset voltage information includes: determining the offset voltage value corresponding to the selected word line according to N, the position information of the selected word line, the preset read voltage of the selected memory cell and the offset voltage information, the selected memory cell is the memory cell coupled to the selected word line among the K memory cells, the preset read voltage of the selected memory cell is the read voltage corresponding to the programming state of the selected memory cell, and the offset voltage information is also used to indicate the offset voltage value corresponding to N, the position information of the selected word line and the preset read voltage of the selected memory cell.

[0016] Optionally, the selected memory cell may be a memory cell coupled to the selected word line, or may be a plurality of memory cells coupled to the selected word line, which is not limited in the embodiments of the present disclosure.

[0017] The operating method of the storage system provided in the embodiment of the present disclosure determines the corresponding offset voltage value according to the preset read voltage corresponding to each programming state of the storage unit, which can further improve the accuracy of the offset voltage value. The memory applies a read voltage to the selected word line according to the offset voltage value, thereby further reducing the read retry rate and improving the read performance.

[0018] In some embodiments, the above-mentioned storage block also includes M word lines arranged adjacent to the N word lines, and L storage cells coupled to the M word lines, the M word lines are arranged adjacent to each other, no data is stored in the L storage cells, M is an integer greater than or equal to 0, and L is a positive integer; the offset voltage information is determined based on a first threshold voltage distribution when data is stored in the K storage cells, and a second threshold voltage distribution when the K storage cells and the L storage cells store data.

[0019] On the other hand, a method for reading data from a memory is also provided, the method comprising: first receiving a data read command, the data read command being used to instruct the memory to generate a read voltage according to an offset voltage value, and to apply the read voltage to a selected word line among N word lines, the offset voltage value being determined according to the number N of the N word lines and offset voltage information, the N word lines being word lines adjacently arranged in a storage block Block of the memory, and data being stored in K storage cells coupled to the N word lines, K and N being positive integers, and the offset voltage information being used to indicate an offset voltage value corresponding to N. Then, according to the data read command, a read voltage is generated and applied to the selected word line.

[0020] In some embodiments, the above-mentioned offset voltage value is determined based on N, the position information of the selected word line and the offset voltage information. The position information of the selected word line is used to indicate the position of the selected word line among the N word lines, and the offset voltage information is also used to indicate the offset voltage value corresponding to N and the position information of the selected word line.

[0021] In some embodiments, the selected word line includes the first selected word line or the second selected word line, the first selected word line includes the 1st word line to the N-1th word line, the second selected word line includes the Nth word line, and the offset voltage value includes the first offset voltage value or the second offset voltage value. The first offset voltage value is determined according to N, the position information of the first selected word line, and the offset voltage information, and the second offset voltage value is determined according to N, the position information of the second selected word line, and the offset voltage information, and the first offset voltage value is less than the second offset voltage value.

[0022] In some embodiments, among the above-mentioned K memory cells, the memory cell coupled to the selected word line is programmed into multiple programming states; the offset voltage value is determined based on N, the position information of the selected word line, the preset read voltage of the selected memory cell and the offset voltage information, the selected memory cell is the memory cell coupled to the selected word line among the K memory cells, the preset read voltage of the selected memory cell is the read voltage corresponding to the programming state of the selected memory cell, and the offset voltage information is also used to indicate the offset voltage value corresponding to N, the position information of the selected word line and the preset read voltage of the selected memory cell.

[0023] In some embodiments, the storage block further includes M word lines disposed adjacent to the N word lines, and L storage cells coupled to the M word lines, the M word lines are disposed adjacent to each other, no data is stored in the L storage cells, M is an integer greater than or equal to 0, and L is a positive integer. The offset voltage information is determined based on a first threshold voltage distribution when data is stored in the K storage cells, and a second threshold voltage distribution when the K storage cells and the L storage cells store data.

[0024] On the other hand, a storage system is provided, which includes a controller and a memory coupled to the controller. The controller is configured to determine the offset voltage value corresponding to the selected word line among the N word lines according to the number N of the N word lines and the offset voltage information, the N word lines are word lines arranged adjacently in the storage block Block of the memory, and the K storage cells coupled to the N word lines store data, K and N are positive integers, and the offset voltage information is used to indicate the offset voltage value corresponding to N. The controller is also configured to send a data read command to the memory, the data read command is used to instruct the memory to generate a read voltage according to the offset voltage value, and apply the read voltage to the selected word line. The memory is configured to receive the data read command, and according to the data read command, generate and apply the read voltage to the selected word line.

[0025] In some embodiments, the controller is also configured to determine an offset voltage value corresponding to a selected word line based on N, position information of the selected word line and offset voltage information, wherein the position information of the selected word line is used to indicate the position of the selected word line among the N word lines, and the offset voltage information is also used to indicate an offset voltage value corresponding to N and the position information of the selected word line.

[0026] In some embodiments, the selected word line includes the first selected word line or the second selected word line, the first selected word line includes the 1st word line to the N-1th word line, and the second selected word line includes the Nth word line. The controller is further configured to determine the first offset voltage value corresponding to the first selected word line according to N, the position information of the first selected word line, and the offset voltage information. Alternatively, the controller is further configured to determine the second offset voltage value corresponding to the second selected word line according to N, the position information of the second selected word line, and the offset voltage information, and the first offset voltage value is less than the second offset voltage value.

[0027] In some embodiments, among the K memory cells, the memory cell coupled to the selected word line is programmed into a plurality of programming states. The controller is further configured to determine an offset voltage value corresponding to the selected word line according to N, the position information of the selected word line, a preset read voltage of the selected memory cell, and offset voltage information, wherein the selected memory cell is a memory cell coupled to the selected word line among the K memory cells, the preset read voltage of the selected memory cell is a read voltage corresponding to the programming state of the selected memory cell, and the offset voltage information is further used to indicate an offset voltage value corresponding to N, the position information of the selected word line, and the preset read voltage of the selected memory cell.

[0028] On the other hand, a computer-readable storage medium is provided, which stores a computer program. When the computer program runs on a processor, the processor executes the storage system operation method provided in the aforementioned aspect, or executes the memory data reading method provided in the aforementioned another aspect.

[0029] It can be understood that the beneficial effects that can be achieved by the data reading method, storage system and computer-readable storage medium provided by the above embodiments of the present disclosure can refer to the beneficial effects of the operating method of the storage system above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0031] Figure 1 is a schematic structural diagram of an electronic device according to some embodiments;

[0032] Figure 2 is a schematic diagram of the structure of a memory according to some embodiments;

[0033] Figure 3 is a schematic diagram of the structure of a storage array according to some embodiments;

[0034] Figure 4 is a schematic diagram of a threshold voltage distribution curve according to some embodiments;

[0035] Figure 5 is a flowchart of an operating method of a storage system according to some embodiments;

[0036] Figure 6 FIG. 4 is a schematic diagram of another threshold voltage distribution curve according to some embodiments. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0038] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0039] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0040] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0041] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0042] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0043] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0044] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0045] Before introducing the embodiments of the present disclosure, the technical terms and background technologies involved in the present disclosure are first introduced.

[0046] The term "three-dimensional memory" refers to a semiconductor device formed by a string of memory cell transistors (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on the main surface of a substrate or a source layer and extending in a direction perpendicular to the substrate or the source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., the lateral surface) of the substrate or the source layer. The string address is the address corresponding to the "memory cell string". The "selected word line (word line, WL)" is the word line corresponding to the word line address in the read request instruction, and the "unselected word line" is the word line other than the word line corresponding to the word line address in the read request instruction.

[0047] Read retry ratio: refers to the ratio of the number of successful data reads to the total number of attempts to read data within a certain number of reads. It is one of the important indicators for measuring the read performance and stability of memory, and can reflect the reliability and performance of the memory.

[0048] A word line for writing data refers to a storage unit coupled to the word line in which data is stored. For ease of description, the word line is referred to as a word line for writing data in the embodiments of the present disclosure.

[0049] A word line with no data written therein means that no data is stored in a storage unit coupled to the word line. For ease of description, the word line is referred to as a word line with no data written therein in the embodiments of the present disclosure.

[0050] Dummy data: This data is usually used for testing, demonstration, or teaching purposes.

[0051] Single level cell (SLC): Each memory cell has only one storage bit and can only store one data item.

[0052] Multi-level cell (MLC): Each memory cell has two storage bits and can store two data items.

[0053] Triple level cell (TLC): Each memory cell has three storage bits and can store three data items simultaneously.

[0054] Quad level cell (QLC): Each memory cell has four storage bits and can store four data items simultaneously.

[0055] like Figure 1As shown, a storage system 100 is usually provided in an electronic device 10. The storage system 100 includes a memory 200 and a controller 300. The controller 300 is coupled to the memory 200, and data can be read from the memory 200 or written to the memory 200 through the controller 300.

[0056] It is understood that the storage system 100 may include a controller 300 and one or more memories 200. For example, in one embodiment, the controller 300 and a single memory 200 may be integrated into a memory card. The memory card may include a PCMCIA (PC) card, a compact flash card (CF card), a smart media card (SM card), a memory stick, a multimedia card (MMC), a secure digital card (SD card), a universal flash storage (UFS), etc. Among them, the multimedia card may be divided into MMC, a reduced-size MMC (RS-MMC), a mini MMC (MMCmicro), etc.; the secure digital card includes SD, a mini SD card (miniSD), a micro SD card (microSD), a secure digital high capacity SD card (SDHC), etc. Further, the memory card may also include a memory card connector for coupling the memory card to a host.

[0057] In another embodiment, the controller 300 and the plurality of memories 200 may be integrated into a solid state disk (SSD). The SSD may further include an SSD connector for coupling the SSD to a host. In some embodiments, the storage capacity and / or operating speed of the SSD is greater than the storage capacity and / or operating speed of the memory card. In addition, the electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc., and the embodiments of the present disclosure are not limited thereto.

[0058] like Figure 2 As shown, the memory 200 generally includes a memory array 210 and peripheral circuits. The peripheral circuits include a connection terminal 221, a control logic circuit 222, a register 223, a voltage generator 224, a row driver 225, a column driver 226, and a page buffer 227.

[0059] The connection terminal 221 is mainly used to receive the read instruction and write instruction sent by the controller 300 and send the read data to the controller 300. The control logic circuit 222 is mainly used to control the row driver 225 to connect the voltage generator 224 with the corresponding word line according to the received read instruction, and control the column driver 226 to connect the voltage generator 224 with the corresponding bit line (BL), so as to read the corresponding data. The register 223 includes an address register, a status register, etc. Among them, the address register is used to store the word line address and the string address in the read request instruction. The status register is used to store the current state of the memory, including the ready and busy states. When the control logic circuit 222 is reading data from the storage array 210 or writing data to the storage array 210, the state stored in the status register is the "busy" state, and the next read or write operation cannot be performed. When the storage array 210 completes the reading process or the writing process, the state stored in the status register is switched to the "ready" state, and the next read or write operation can be performed. The page buffer 227 includes a first register and a second register, wherein the first register is used to cache data read from the storage array 210 , and the second register is used to cache data transferred from the first register.

[0060] The memory array 210 in the memory 200 may include a plurality of memory cells arranged at the intersection of word lines and bit lines. According to the difference in the structure of the memory array 210, the memory may be divided into a two-dimensional memory and a three-dimensional memory. Figure 3 As shown, it is a schematic diagram of the structure of a storage array 210 in a three-dimensional memory, the storage array 210 includes word lines WL1-WL3 and bit lines BL1-BL7, a plurality of storage cells on each word line perpendicular to each bit line form a page 2111, and a plurality of storage cells on each bit line perpendicular to each word line form a storage cell string 2112. A top selective gate (TSG) is provided at the top of each storage cell string 2112, and a bottom selective gate (BSG) is provided at the bottom. Multiple storage cell strings 2112 can be provided on each bit line, and each word line can be coupled to storage cells in multiple storage cell strings 2112. The difference between a two-dimensional memory and a three-dimensional memory is that in a two-dimensional memory, there is only one storage cell in a storage cell string 2112 perpendicular to each bit line.

[0061] The smallest unit of programming in NAND flash memory is page, taking a certain storage cell in a page as an example. When data needs to be stored in the storage cell, the conduction voltage can be input to the top selection tube (TSG) and the bottom selection tube (BSG) respectively to turn on the top selection tube and the bottom selection tube, and then the programming voltage is applied to the word line coupled to the storage cell, and the programming enable voltage is applied to the bit line coupled to the storage cell, so that the threshold voltage (Vth) of the storage cell can be programmed to achieve information storage. When data needs to be read from the storage cell, the conduction voltage can be input to the top selection tube and the bottom selection tube respectively to turn on the top selection tube and the bottom selection tube, and then the read voltage is applied to the word line coupled to the storage cell, and the conduction voltage is applied to the bit line coupled to the storage cell, so that information can be read.

[0062] As the demand for memory storage capacity continues to increase, memory is constantly developing in the direction of shrinking device size. For example, in the storage array of 3D NAND flash memory, the thickness of each layer of word lines is getting thinner and thinner, and the spacing between each layer of word lines is getting smaller and smaller. At the same time, the development towards the direction of increasing the number of stacked layers will lead to more and more serious capacitive coupling effect and back pattern dependency (BPD). This will cause the threshold voltage distribution of the storage cells in the open block of the 3D NAND flash memory to be offset compared with the threshold voltage distribution of the storage cells in the completed block, resulting in an increase in the read retry rate when reading data from the storage cells in the open block, a decrease in read performance, and a poor user experience.

[0063] For example, a storage cell in a storage block is a triple-level cell (TLC). Figure 4 As shown in (a), when all word lines in the storage block are word lines for writing data, it can be understood that at this time, all pages in the storage block are written with data, and the storage block can be called a completion block. Since the capacitive coupling effect between the word lines for writing data in the completion block is strong, and the back bias effect is strong, the charge changes between the storage cells in the completion block can offset each other, and the threshold voltage distribution offset of the storage cells in the completion block is small, which can also be called the initial threshold voltage shift (IVS) is small. The threshold voltage distribution curve of the storage cells in the completion block is as follows Figure 4 The completed block curve shown in (b).

[0064] like Figure 4As shown in (a), when part of the word lines in the storage block are word lines for writing data, and the rest are word lines for not writing data, it can be understood that at this time, part of the pages in the storage block are written with data, and the storage block can be called an open block. Since the capacitive coupling effect between the word lines for writing data in the open block is weak, and the back bias effect is weak, the charge changes between the storage cells in the open block cannot offset each other, resulting in a large offset in the threshold voltage distribution of the storage cells in the open block. The threshold voltage distribution curve of the storage cells in the open block is as follows Figure 4 The open block curve shown in (b).

[0065] in, Figure 4 The "L6" and "L7" shown in (b) represent different programming states. Figure 4 (b) in the figure is exemplified with the two programming states. According to the completion block curve and the open block curve, it can be understood that compared with the threshold voltage distribution of the storage cells in the completion block in each programming state, the threshold voltage distribution of the storage cells in the open block in each corresponding programming state has a certain offset, which will result in an increase in the read retry rate and a decrease in the read performance when reading data from the storage cells in the open block, resulting in a poor user experience.

[0066] In order to solve this problem, when a storage block is an open block, dummy data can be written into the storage cell coupled to the word line where no data is written, and the storage block is transformed into a completed block, thereby enhancing the capacitive coupling effect and back bias effect between the word lines in the storage block, so that the charge changes between the storage cells in the storage block can offset each other, reducing the offset of the threshold voltage distribution, so as to reduce the read retry rate and improve the read performance. However, writing dummy data in an open block will result in higher power consumption of the memory.

[0067] Through experimental tests, it is found that the offset of the threshold voltage distribution of the storage cells in the storage block is related to the number of word lines written in the storage block. In order to solve the above problems, the embodiments of the present disclosure provide a storage system operation method and a memory data reading method. The two methods determine the offset voltage value corresponding to the selected word line in the storage block according to the number of data word lines written in the storage block, and apply a read voltage to the selected word line according to the offset voltage value, thereby reducing the read retry rate of the memory and improving the read performance to improve the user experience. The two methods can be applied to the above storage system 100, and the embodiments of the present disclosure take the application of the method to the above storage system 100 as an example for illustrative description.

[0068] like Figure 5 As shown, it is a flowchart of a storage system operation method and a memory data reading method provided by an embodiment of the present disclosure, and the method includes steps S501-S504.

[0069] S501, the controller 300 determines the offset voltage value corresponding to the selected word line among the N word lines according to the number N of the N word lines and the offset voltage information. The N word lines are adjacently arranged word lines in the storage block of the memory 200, and the K storage cells coupled to the N word lines store data, K and N are positive integers, and the specific values ​​of N and K are not limited in the embodiment of the present disclosure. It can be understood that the above-mentioned N word lines are word lines for writing data. The offset voltage information is used to indicate the offset voltage value corresponding to N.

[0070] Optionally, the above offset voltage information may be in a table format or other formats, which is not limited in the embodiments of the present disclosure. The following embodiments of the present disclosure take the table format as an example for illustrative description.

[0071] Exemplarily, the offset voltage information may be as shown in Table 1 below. According to Table 1, different numbers of N word lines correspond to an offset voltage value, respectively. For example, when the N word lines include 1 word line, it corresponds to an offset voltage value of 0.2, and when the N word lines include 2 word lines, it corresponds to an offset voltage value of 0.1. Thus, according to the number N of N word lines and Table 1, the offset voltage value corresponding to the selected word line among the N word lines may be determined.

[0072] Table 1

[0073] The number of N word lines Offset voltage value 1 0.2 2 0.1 …… ……

[0074] Optionally, the selected word line may be one of N word lines, or may be a plurality of N word lines, which is not limited in the embodiments of the present disclosure.

[0075] For example, when the N word lines include 10 word lines, the selected word line may be one word line among the 10 word lines, or may be three word lines among the 10 word lines.

[0076] Optionally, types of the K storage cells include at least one of a single-level cell, a multi-level cell, a triple-level cell and a quadruple-level cell, which is not limited in the embodiments of the present disclosure.

[0077] Through experimental tests, it was found that when the selected word line is located at a different position among the N word lines, the threshold voltage offset of the storage unit coupled to the selected word line is different. The controller 300 determines the corresponding bias voltage value according to the position information of the selected word line among the N word lines, thereby further improving the accuracy of the offset voltage value. The memory 200 applies a read voltage to the selected word line according to the offset voltage value, thereby further reducing the read retry rate and improving the read performance.

[0078] In a possible embodiment, the controller 300 determines the offset voltage value corresponding to a selected word line among the N word lines according to the number N of the N word lines and the offset voltage information, including: the controller 300 determines the offset voltage value corresponding to the selected word line according to N, the position information of the selected word line and the offset voltage information, the position information of the selected word line is used to indicate the position of the selected word line among the N word lines, and the offset voltage information is also used to indicate the offset voltage value corresponding to N and the position information of the selected word line.

[0079] Specifically, the selected word line may include the first selected word line or the second selected word line, the first selected word line includes the 1st word line to the N-1th word line, and the second selected word line includes the Nth word line. The controller 300 determines the offset voltage value corresponding to the selected word line according to N, the position information of the selected word line, and the offset voltage information, including: the controller 300 determines the first offset voltage value corresponding to the first selected word line according to N, the position information of the first selected word line, and the offset voltage information, or the controller 300 determines the second offset voltage value corresponding to the second selected word line according to N, the position information of the second selected word line, and the offset voltage information, and the first offset voltage value is less than the second offset voltage value.

[0080] Exemplarily, when the offset voltage information is also used to indicate the offset voltage value corresponding to N and the position information of the selected word line, the offset voltage information may be as shown in Table 2. According to Table 2, when the N word lines include different numbers of word lines and the selected word line is located at different positions in the N word lines, the selected word line corresponds to different offset voltage values.

[0081] For example, combined with Figure 6 In (a), a storage block includes G word lines, where G is a positive integer greater than or equal to N.

[0082] When n word lines among the G word lines are word lines for writing data, and n is a positive integer, the storage block can be called a first open block, the number of the above N word lines is n, the first selected word lines include the 1st word line WL0 to the N-1th word line WLn-1, and the second selected word lines include the Nth word line WLn. According to Table 2, the offset voltage value corresponding to the first selected word line is O1, and the offset voltage value corresponding to the second selected word line is O1'.

[0083] When n+m word lines among the G word lines are word lines for writing data, and m is a positive integer, the storage block can be called a second open block, the number of the above-mentioned N word lines is n+m, the first selected word lines include the 1st word line WL0 to the N-1th word line WLn+m-1, and the second selected word lines include the Nth word line WLn+m. According to Table 2, the offset voltage value corresponding to the first selected word line is O2, and the offset voltage value corresponding to the second selected word line is O2'.

[0084] When n+y word lines among the G word lines are word lines for writing data, y is a positive integer and greater than m, the storage block can be called a third open block, the number of the above-mentioned N word lines is n+y, the first selected word line includes the 1st word line WL0 to the N-1th word line WLn+y-1, and the second selected word line includes WLn+y. According to Table 2, the offset voltage value corresponding to the first selected word line is O3, and the offset voltage value corresponding to the second selected word line is O3'.

[0085] When all the G word lines are word lines for writing data, the storage block can be called a completed block. The number of the above-mentioned N word lines is G. The first selected word line includes the 1st word line WL0 to the N-1th word line WLG-1, and the second selected word line includes WLG. According to Table 2, the offset voltage values ​​corresponding to the first selected word line and the second selected word line are both 0.

[0086] Table 2

[0087]

[0088]

[0089] Optionally, the first selected word line includes one of the 1st to N-1th word lines, or includes a plurality of the 1st to N-1th word lines, which is not limited in the embodiments of the present disclosure.

[0090] Through experimental tests, it was found that when the storage cell coupled to the selected word line is programmed to different programming states, the threshold voltage offset of the storage cell is different. The controller 300 determines the corresponding offset voltage value according to the preset read voltage corresponding to each programming state of the storage cell, thereby further improving the accuracy of the offset voltage value. The memory 200 applies a read voltage to the selected word line according to the offset voltage value, thereby further reducing the read retry rate and improving the read performance.

[0091] In a possible embodiment, among the K memory cells, the memory cells coupled to the selected word line are programmed into a plurality of programming states. The controller 300 determines the offset voltage value corresponding to the selected word line among the N word lines according to the number N of the N word lines and the offset voltage information, including:

[0092] The offset voltage value corresponding to the selected word line is determined according to N, the position information of the selected word line, the preset read voltage of the selected storage cell, and the offset voltage information. The selected storage cell is a storage cell coupled to the selected word line among the K storage cells, the preset read voltage of the selected storage cell is a read voltage corresponding to the programming state of the selected storage cell, and the offset voltage information is also used to indicate the offset voltage value corresponding to N, the position information of the selected word line, and the preset read voltage of the selected storage cell.

[0093] Exemplarily, when the offset voltage information is also used to indicate N, the position information of the selected word line, and the offset voltage value corresponding to the preset read voltage of the selected memory cell, the offset voltage information may be as shown in Table 3. According to Table 3, when the memory cell coupled to the selected word line is programmed to different programming states corresponding to different preset read voltages, the selected word line corresponds to different offset voltage values.

[0094] For example, combined with Figure 6 In (a), a storage block includes G word lines, and the storage cells coupled to the G word lines are three-level cells. The storage cells coupled to the G word lines can be programmed to 8 programming states. Except for the first programming state, the erase state, the preset read voltages corresponding to the second programming state to the eighth programming state are V1 to V7, respectively.

[0095] When n word lines among the G word lines are word lines for writing data, the selected word line is the first selected word line, the first selected word line includes the 1st word line WL0 to the N-1th word line WLn-1, the selected storage cell is the storage cell coupled to the first selected word line and programmed to the second programming state, and the preset read voltage of the selected storage cell is V1, it can be seen from Table 3 that the offset voltage value corresponding to the selected word line at this time is O1-V1.

[0096] When n word lines among the G word lines are word lines for writing data, the selected word line is the second selected word line, the second selected word line includes the Nth word line WLn, the selected storage cell is a storage cell coupled to the second selected word line and programmed to the 5th programming state, and the preset read voltage of the selected storage cell is V4, it can be seen from Table 3 that the offset voltage value corresponding to the selected word line at this time is O1-U4.

[0097] It can be understood that when the number N of selected word lines is n+m, n+y or G, the selected word line is the first selected word line or the second selected word line, the selected storage cell is a storage cell coupled to the selected word line and programmed to any programming state, and the selected storage cell corresponds to any preset read voltage, the corresponding offset voltage value can be determined according to Table 3, and the embodiments of the present disclosure will not be repeated here.

[0098] Table 3

[0099]

[0100] Optionally, the selected storage cell may be a storage cell coupled to the selected word line, or may be a plurality of storage cells coupled to the selected word line, which is not limited in the embodiments of the present disclosure.

[0101] In a possible embodiment, the storage block also includes M word lines arranged adjacent to the N word lines, and L storage cells coupled to the M word lines, the M word lines are arranged adjacent to each other, no data is stored in the L storage cells, M is an integer greater than or equal to 0, and L is a positive integer. The embodiments of the present disclosure do not limit the specific values ​​of M and L.

[0102] Exemplarily, when M is equal to 0, the storage block includes N word lines, and the N word lines are all word lines for writing data, and the storage block can be called a completed block. When M is greater than 0, the storage block includes N+M word lines, of which N word lines are word lines for writing data and M word lines are word lines for not writing data, and the storage block can be called an open block.

[0103] The above offset voltage information is determined based on the first threshold voltage distribution when data is stored in the K storage cells, and the second threshold voltage distribution when the K storage cells and the L storage cells store data. It can be understood that when M is equal to 0, the above offset voltage information is determined based on the first threshold voltage distribution when the storage block is a completed block, and the second threshold voltage distribution when the storage block is a completed block. When M is greater than 0, the above offset voltage information is determined based on the first threshold voltage distribution when the storage block is an open block, and the second threshold voltage distribution when the storage block is a completed block.

[0104] The embodiment of the present disclosure takes determining the offset voltage information shown in Table 3 as an example for illustrative explanation. The process of determining the remaining offset voltage information can refer to the following description, and the embodiment of the present disclosure will not be repeated here.

[0105] For example, Figure 6 As shown in (a), a storage block includes G word lines, G=N+M, M is greater than 0, the storage block is a first open block, the number N is n, and the storage cells coupled to the G word lines are three-level cells.

[0106] The threshold voltage distribution curve of the memory cell coupled to the first word line WL0 to the N-1th word line WLn-1 is as follows: Figure 6 The threshold voltage distribution curve of the memory cell coupled to the Nth word line WLn is shown in (b) of the open block curve. Figure 6 The open block curves shown in (c) in FIG. It can be understood that the two open block curves are curves corresponding to the first threshold voltage distribution when data is stored in K memory cells.

[0107] When all the word lines of the G word lines are word lines for writing data, the threshold voltage distribution curve of the memory cells coupled to the G word lines is as follows: Figure 6 The completion block curve shown in (b) of Figure 6The completion block curve shown in (c) in FIG. It can be understood that the two completion block curves are curves corresponding to the second threshold voltage distribution when K memory cells and L memory cells store data.

[0108] Wherein, L0 to L7 represent different programming states, and V1 to V7 represent preset read voltages corresponding to the memory cells in each programming state.

[0109] according to Figure 6 (b) and Figure 6 As shown in (c) of FIG. 1 , by comparing the completed block curve with the open block curve, the corresponding offset voltage value of the selected memory cell coupled to the selected word line and programmed to any programming state when the selected word line is located at different positions among the N word lines can be determined. Figure 6 In (b), it can be determined that when the selected word line is the first word line WL0 located in the N word lines, and the memory cell coupled to the first word line WL0 is programmed to the programming state L1, corresponding to the preset read voltage V1, the offset voltage value corresponding to the selected word line is O1-V1. The specific process of determining the above offset voltage information according to the curve corresponding to the first threshold voltage distribution and the curve corresponding to the second threshold voltage distribution can refer to the above description, and the embodiments of the present disclosure will not be repeated here.

[0110] In a possible embodiment, the above offset voltage information may be stored in the controller 300 .

[0111] S502 : The controller 300 sends a data read command to the memory 200 , where the data read command is used to instruct the memory 200 to generate a read voltage according to the offset voltage value and apply the read voltage to the selected word line.

[0112] S503: The memory 200 receives a data read command.

[0113] S504 : The memory 200 generates and applies a read voltage to the selected word line according to the data read command.

[0114] The operation method of the storage system and the data reading method of the memory provided by the embodiment of the present disclosure determine the offset voltage value corresponding to the selected word line among the N word lines according to the number N of N word lines and the offset voltage information, wherein the N word lines are word lines arranged adjacently in the storage block of the memory 200, and the K storage cells coupled to the N word lines store data. It can be understood that the offset voltage value determined by the embodiment of the present disclosure takes into account that when the number of data word lines written in the storage block is different, the offset of the threshold voltage of the storage cell in the storage block is different, so the offset voltage value determined by the embodiment of the present disclosure is more accurate, and the read voltage determined based on the offset voltage value is more accurate, thereby reducing the read retry rate of the memory 200 and improving the read performance. At the same time, compared with the solution of writing virtual data in an open block, the power consumption of the memory 200 can be reduced.

[0115] The present disclosure also provides a storage system, which includes a controller and a memory coupled to the controller. The structure of the storage system can be as follows: Figure 1 The structure of the storage system 100 is shown in FIG. 1 . The embodiment of the present disclosure takes the structure of the storage system 100 as an example for illustrative description.

[0116] The controller 300 is configured to determine the offset voltage value corresponding to the selected word line among the N word lines according to the number N of the N word lines and the offset voltage information, the N word lines are word lines arranged adjacently in the storage block Block of the memory, and the K storage cells coupled to the N word lines store data, K and N are positive integers, and the embodiments of the present disclosure do not limit the specific values ​​of N and K. The offset voltage information is used to indicate the offset voltage value corresponding to N.

[0117] Optionally, the offset voltage information may be in a table format or in other formats, which is not limited in the embodiments of the present disclosure.

[0118] Optionally, the selected word line may be one of N word lines, or may be a plurality of N word lines, which is not limited in the embodiments of the present disclosure.

[0119] Optionally, types of the K storage cells include at least one of a single-level cell, a multi-level cell, a triple-level cell and a quadruple-level cell, which is not limited in the embodiments of the present disclosure.

[0120] The controller 300 is further configured to send a data read command to the memory 200 , where the data read command is used to instruct the memory 200 to generate a read voltage according to the offset voltage value and apply the read voltage to the selected word line.

[0121] The memory 200 is configured to receive a data read command, and generate and apply a read voltage to a selected word line according to the data read command.

[0122] In a possible embodiment, the controller 300 is further configured to determine an offset voltage value corresponding to a selected word line based on N, position information of the selected word line and offset voltage information, wherein the position information of the selected word line is used to indicate the position of the selected word line among the N word lines, and the offset voltage information is also used to indicate an offset voltage value corresponding to N and the position information of the selected word line.

[0123] In a possible embodiment, the selected word line includes a first selected word line or a second selected word line, the first selected word line includes the 1st word line to the N-1th word line, and the second selected word line includes the Nth word line.

[0124] The controller 300 is further configured to determine a first offset voltage value corresponding to the first selected word line according to N, position information of the first selected word line and offset voltage information.

[0125] Alternatively, the controller 300 is further configured to determine a second offset voltage value corresponding to the second selected word line according to N, position information of the second selected word line and offset voltage information, and the first offset voltage value is smaller than the second offset voltage value.

[0126] Optionally, the first selected word line includes one of the 1st to N-1th word lines, or includes a plurality of the 1st to N-1th word lines, which is not limited in the embodiments of the present disclosure.

[0127] In a possible embodiment, among the K storage cells, the storage cells coupled to the selected word line are programmed into a plurality of programming states. The controller 300 is further configured to determine the offset voltage value corresponding to the selected word line according to N, the position information of the selected word line, the preset read voltage of the selected storage cell, and the offset voltage information, wherein the selected storage cell is the storage cell coupled to the selected word line among the K storage cells, the preset read voltage of the selected storage cell is the read voltage corresponding to the programming state of the selected storage cell, and the offset voltage information is further used to indicate the offset voltage value corresponding to N, the position information of the selected word line, and the preset read voltage of the selected storage cell.

[0128] Optionally, the selected storage cell may be a storage cell coupled to the selected word line, or may be a plurality of storage cells coupled to the selected word line, which is not limited in the embodiments of the present disclosure.

[0129] The storage system provided by the embodiment of the present disclosure determines the offset voltage value corresponding to the selected word line among the N word lines according to the number N of N word lines and the offset voltage information, wherein the N word lines are word lines arranged adjacently in the storage block of the memory 200, and data is stored in the K storage cells coupled to the N word lines. It can be understood that the offset voltage value determined by the embodiment of the present disclosure takes into account that when the number of word lines for writing data in the storage block is different, the offset amount of the threshold voltage of the storage cell in the storage block is different, so the offset voltage value determined by the embodiment of the present disclosure is more accurate, and the read voltage determined based on the offset voltage value is more accurate, so that the read retry rate of the memory 200 can be reduced and the read performance can be improved.

[0130] Based on this, the embodiment of the present disclosure further provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the following Figure 5 The operating method of the storage system or the data reading method of the storage system is shown.

[0131] The above detailed description of the operation method of the storage system and the data reading method of the memory, as well as the analysis of beneficial effects, can all be correspondingly referenced to the storage system and the computer-readable storage medium, and the embodiments of the present application will not be repeated here.

[0132] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for operating a storage system, characterized in that: The method comprises: Determine, according to the number N of N word lines and offset voltage information, an offset voltage value corresponding to a selected word line among the N word lines, the N word lines being word lines adjacently arranged in a storage block Block of a memory, and K storage cells coupled to the N word lines storing data, K and N being positive integers, and the offset voltage information being used to indicate the offset voltage value corresponding to N; A data read command is sent to the memory, wherein the data read command is used to instruct the memory to generate a read voltage according to the offset voltage value and apply the read voltage to the selected word line.

2. The method according to claim 1, characterized in that The step of determining the offset voltage value corresponding to the selected word line among the N word lines according to the number N of the N word lines and the offset voltage information includes: The offset voltage value corresponding to the selected word line is determined according to N, the position information of the selected word line and the offset voltage information, wherein the position information of the selected word line is used to indicate the position of the selected word line among the N word lines, and the offset voltage information is also used to indicate the offset voltage value corresponding to N and the position information of the selected word line.

3. The method according to claim 2, characterized in that The selected word line includes a first selected word line or a second selected word line, the first selected word line includes a 1st word line to an N-1th word line, and the second selected word line includes an Nth word line; The determining the offset voltage value corresponding to the selected word line according to N, the position information of the selected word line and the offset voltage information includes: Determine a first offset voltage value corresponding to the first selected word line according to N, the position information of the first selected word line and the offset voltage information; or, A second offset voltage value corresponding to the second selected word line is determined according to N, the position information of the second selected word line and the offset voltage information, and the first offset voltage value is smaller than the second offset voltage value.

4. The method according to claim 1, characterized in that: Among the K memory cells, the memory cells coupled to the selected word line are programmed into a plurality of programming states, and determining the offset voltage value corresponding to the selected word line among the N word lines according to the number N of the N word lines and the offset voltage information includes: The offset voltage value corresponding to the selected word line is determined according to N, the position information of the selected word line, the preset read voltage of the selected storage cell and the offset voltage information, the selected storage cell is a storage cell coupled to the selected word line among the K storage cells, the preset read voltage of the selected storage cell is a read voltage corresponding to the programming state of the selected storage cell, and the offset voltage information is also used to indicate the offset voltage value corresponding to N, the position information of the selected word line and the preset read voltage of the selected storage cell.

5. The method according to any one of claims 1 to 4, characterized in that The storage block also includes M word lines arranged adjacent to the N word lines, and L storage cells coupled to the M word lines, the M word lines are arranged adjacent to each other, no data is stored in the L storage cells, M is an integer greater than or equal to 0, and L is a positive integer; the offset voltage information is determined based on a first threshold voltage distribution when data is stored in the K storage cells, and a second threshold voltage distribution when the K storage cells and the L storage cells store data.

6. A method for reading data from a memory, characterized in that: The method comprises: Receive a data read command, the data read command is used to instruct the memory to generate a read voltage according to an offset voltage value, and apply the read voltage to a selected word line among N word lines, the offset voltage value is determined according to the number N of the N word lines and offset voltage information, the N word lines are word lines adjacently arranged in a storage block Block of the memory, and data is stored in K storage cells coupled to the N word lines, K and N are positive integers, and the offset voltage information is used to indicate the offset voltage value corresponding to N; According to the data read command, the read voltage is generated and applied to the selected word line.

7. The method according to claim 6, characterized in that The offset voltage value is determined based on N, the position information of the selected word line and the offset voltage information. The position information of the selected word line is used to indicate the position of the selected word line among the N word lines. The offset voltage information is also used to indicate the offset voltage value corresponding to N and the position information of the selected word line.

8. The method according to claim 7, characterized in that The selected word line includes a first selected word line or a second selected word line, the first selected word line includes a 1st word line to an N-1th word line, the second selected word line includes an Nth word line, and the offset voltage value includes a first offset voltage value or a second offset voltage value; The first offset voltage value is determined based on N, the position information of the first selected word line and the offset voltage information, the second offset voltage value is determined based on N, the position information of the second selected word line and the offset voltage information, and the first offset voltage value is smaller than the second offset voltage value.

9. The method according to claim 6, characterized in that Among the K storage cells, the storage cell coupled to the selected word line is programmed into multiple programming states; the offset voltage value is determined based on N, the position information of the selected word line, the preset read voltage of the selected storage cell and the offset voltage information, the selected storage cell is the storage cell coupled to the selected word line among the K storage cells, the preset read voltage of the selected storage cell is the read voltage corresponding to the programming state of the selected storage cell, and the offset voltage information is also used to indicate the offset voltage value corresponding to N, the position information of the selected word line and the preset read voltage of the selected storage cell.

10. The method according to any one of claims 6 to 9, characterized in that: The storage block also includes M word lines arranged adjacent to the N word lines, and L storage cells coupled to the M word lines, the M word lines are arranged adjacent to each other, no data is stored in the L storage cells, M is an integer greater than or equal to 0, and L is a positive integer; the offset voltage information is determined based on a first threshold voltage distribution when data is stored in the K storage cells, and a second threshold voltage distribution when the K storage cells and the L storage cells store data.

11. A storage system, characterized in that: The storage system includes a controller, and a memory coupled to the controller; The controller is configured to determine an offset voltage value corresponding to a selected word line among the N word lines according to the number N of the N word lines and offset voltage information, the N word lines being word lines adjacently arranged in a storage block Block of the memory, and K storage cells coupled to the N word lines storing data, K and N being positive integers, and the offset voltage information being used to indicate the offset voltage value corresponding to N; The controller is further configured to send a data read command to the memory, wherein the data read command is used to instruct the memory to generate a read voltage according to the offset voltage value and apply the read voltage to the selected word line; The memory is configured to receive the data read command, and generate and apply the read voltage to the selected word line according to the data read command.

12. The storage system according to claim 11, characterized in that: The controller is further configured to determine the offset voltage value corresponding to the selected word line based on N, the position information of the selected word line and the offset voltage information, wherein the position information of the selected word line is used to indicate the position of the selected word line among the N word lines, and the offset voltage information is also used to indicate the offset voltage value corresponding to N and the position information of the selected word line.

13. The storage system according to claim 12, characterized in that: The selected word line includes a first selected word line or a second selected word line, the first selected word line includes a 1st word line to an N-1th word line, and the second selected word line includes an Nth word line; The controller is further configured to determine a first offset voltage value corresponding to the first selected word line according to N, the position information of the first selected word line and the offset voltage information; or, The controller is further configured to determine a second offset voltage value corresponding to the second selected word line according to N, position information of the second selected word line and the offset voltage information, wherein the first offset voltage value is smaller than the second offset voltage value.

14. The storage system according to claim 11, characterized in that: Among the K memory cells, the memory cells coupled to the selected word line are programmed into a plurality of programming states; The controller is further configured to determine the offset voltage value corresponding to the selected word line based on N, the position information of the selected word line, the preset read voltage of the selected storage cell and the offset voltage information, wherein the selected storage cell is a storage cell coupled to the selected word line among the K storage cells, the preset read voltage of the selected storage cell is a read voltage corresponding to the programming state of the selected storage cell, and the offset voltage information is further used to indicate the offset voltage value corresponding to N, the position information of the selected word line and the preset read voltage of the selected storage cell.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program runs on a processor, the processor executes the storage system operation method as described in any one of claims 1 to 5, or executes the memory data reading method as described in any one of claims 6 to 10.

Images