A Hardware Implementation Method and System for Epilepsy Detection Based on Machine Learning

Abstract

This application relates to the field of biomedical signal processing technology, and particularly to a hardware implementation method and system for epilepsy detection based on machine learning. The method includes: First, obtain a data set and construct a classification detection model based on SVM. The classification detection model includes a preprocessing module, a feature extraction module, a normalization processing module, and a classification module. Then, simulate the classification detection model through Vitis HLS to generate an RTL calculation model. Finally, package the RTL calculation model into a single IP core that can be called. The single IP core forms a data path with the CPU through the AXI-4 protocol to achieve high-speed data transmission from the PC side to the chip side, so as to realize real-time detection of epilepsy signals. The hardware implementation method for epilepsy detection based on machine learning provided by this application solves the problems that it is difficult to balance the computing speed and resource consumption in the traditional epilepsy detection system, and the accuracy loss is too large due to the computing method and hardware characteristics during the migration process of the software-side model to the hardware side.

Description

Technical Field

[0001] This application relates to the technical field of biomedical signal processing, and particularly relates to a hardware implementation method and system for epilepsy detection based on machine learning. Background Art

[0002] Epilepsy is a common neurological disorder, typically characterized by sudden episodes of abnormal electrical activity in the brain. Early warning and detection of epileptic seizures are crucial for the treatment and management of patients. Traditional epilepsy detection methods rely on the monitoring and analysis of electroencephalogram (EEG) signals. However, due to the complexity of EEG signals, manual analysis is often time-consuming and vulnerable to noise interference. Therefore, automated epilepsy detection methods have become a research hotspot.

[0003] With the development of machine learning and deep learning technologies, significant progress has been made in epilepsy detection methods based on signal processing and data mining. Traditional machine learning methods, such as support vector machine (SVM), random forest, K-nearest neighbor (KNN), etc., achieve epilepsy detection by extracting features from EEG signals and training classification models. SVM has become a commonly used method in epilepsy detection due to its high efficiency and good generalization ability in small-sample data. To improve the detection accuracy, signal processing techniques such as wavelet transform are usually combined to extract features from EEG signals.

[0004] In terms of hardware implementation, with the continuous development of high-performance computing platforms, especially the rise of field-programmable gate arrays (FPGAs) and high-level synthesis (Vitis HLS) tools, it has also become a trend to use hardware acceleration to implement machine learning algorithms. Hardware implementation can not only significantly improve the computing speed but also enable real-time epilepsy monitoring on edge computing devices, providing immediate detection and warning services for epilepsy patients.

[0005] Existing epilepsy detection systems generally have the following disadvantages in terms of hardware implementation: (1) Insufficient resource utilization; when using a central processing unit (CPU) or a graphics processing unit (GPU) for epilepsy detection, the algorithm usually executes according to a general computing process, lacking optimization for the hardware, resulting in low utilization of hardware resources, especially when dealing with a large amount of data. In particular, for the two computationally intensive tasks of signal feature extraction and classification, it is difficult to achieve efficient parallel processing on the hardware. (2) Low energy efficiency; due to the lack of hardware-level optimization, existing epilepsy detection systems often consume a large amount of energy when processing large-scale EEG data. This is particularly disadvantageous for real-time monitoring devices because they need to operate stably for a long time and ensure low power consumption. (3) Lack of hardware acceleration support; traditional systems usually do not make full use of the advantages of hardware accelerators such as FPGAs, resulting in the computational process of signal processing and classification being overly dependent on software, with a large bottleneck in implementation and unable to fully utilize the parallel processing advantages of FPGAs. Summary of the Invention

[0006] The embodiments of the present application provide a method and system for hardware implementation of epilepsy detection based on machine learning, which solve the problems that it is difficult to balance the computing speed and resource consumption in traditional epilepsy detection systems and the excessive accuracy loss caused by the computing method and hardware characteristics during the migration process of the software-side model to the hardware side.

[0007] To solve the above technical problems, in a first aspect, the embodiments of the present application provide a method for hardware implementation of epilepsy detection based on machine learning, including the following steps: First, obtain a data set and construct a classification detection model based on SVM; the classification detection model includes a preprocessing module, a feature extraction module, a normalization processing module, and a classification module; then, simulate the classification detection model through Vitis HLS to generate a register transfer level (RTL) computing model; finally, package the RTL computing model into a single integrated circuit intellectual property core (referred to as an IP core for short) that can be called, and the single IP core forms a data path with the CPU through the Advanced eXtensible Interface (AXI-4) protocol to achieve high-speed data transmission from the personal computer side (referred to as the PC side) to the chip side, so as to realize real-time detection of epilepsy signals.

[0008] In some exemplary embodiments, the classification detection model obtains the optimal training parameters through training on the software side and transfers the optimal training parameters to the hardware side to implement only the classification test task on the hardware side.

[0009] In some exemplary embodiments, the single IP core receives the data to be classified stored by the CPU and outputs the classification result.

[0010] In some exemplary embodiments, the data set includes raw epilepsy data samples and raw non-epilepsy data samples; after obtaining the data set and before constructing the SVM-based classification detection model, it further includes: dividing the data set into a test set and a training set, respectively labeling the epilepsy signals and non-epilepsy signals with 1 and -1, and sending the raw data with labels into the preprocessing module for preprocessing.

[0011] In some exemplary embodiments, the preprocessing module includes a band-pass filter of 0.5Hz to 32Hz, and the band-pass filter is used to filter the raw electroencephalogram signals.

[0012] In some exemplary embodiments, the feature extraction module is used to extract features from the filtered signals, obtain a fusion feature formed by a two-dimensional array combination of the maximum value and the standard deviation, and send the fusion feature as input data to the classification detection model for training.

[0013] In some exemplary embodiments, the feature extraction module uses the discrete wavelet transform method to extract features from the filtered signals; the feature extraction process includes: first performing mirror padding to expand the boundary and using one-dimensional convolution to reduce the computational amount; then performing downsampling processing, only retaining the data at odd indices to further reduce the data amount; calculating multiple feature combinations and testing the multiple feature combinations to obtain the best feature combination as the fusion feature; the fusion feature is a two-dimensional array combination of the maximum value and the standard deviation obtained by the data sample through the feature extraction process.

[0014] In some exemplary embodiments, the normalization module is used to perform a feature normalization process on the fusion feature; the normalization process includes: after subtracting the average value from the fusion feature, dividing by the standard deviation of the fusion feature to complete the feature extraction normalization process, eliminating the offset and scale differences between different features.

[0015] In some exemplary embodiments, the classification module is used to perform SVM classification on the normalized features; the SVM classification process includes RBF (radial basis function kernel) kernel function calculation and a decision-making process; the RBF kernel function calculation includes: subtracting the support vector from the normalized feature vector and calculating the sum of squares to obtain the square value of the Euclidean distance, and then calculating the Gaussian radial basis function to obtain the RBF kernel value; multiplying each RBF kernel value by the corresponding weight coefficient and accumulating to complete the weighted summation process; finally adding the bias term to generate the final decision value; the decision-making process includes: setting the decision boundary to 0, assigning it to class 1 if it is greater than 0, corresponding to the decision result of the interictal period of epilepsy; assigning it to class -1 if it is less than 0, corresponding to the decision result of the preictal period of epilepsy.

[0016] Second aspect, the embodiments of the present application further provide a hardware implementation system for epilepsy detection based on machine learning, which uses the hardware implementation method for epilepsy detection based on machine learning described in the above embodiments to perform real-time detection on epilepsy signals, including: a classification detection model module and an RTL calculation model module; wherein, the classification detection model module includes a preprocessing module, a feature extraction module, a normalization processing module and a classification module; the RTL calculation model module is used to simulate the classification detection model through Vitis HLS to generate an RTL calculation model; and package the RTL calculation model into a single IP core that can be called, and the single IP core forms a data path through the AXI-4 protocol CPU to achieve high-speed data transmission from the PC side to the chip side, so as to realize the real-time detection of epilepsy signals.

[0017] The technical solutions provided by the embodiments of the present application have at least the following advantages:

[0018] The embodiments of the present application provide a hardware implementation method and system for epilepsy detection based on machine learning. The method includes the following steps: First, obtain a data set and construct a classification detection model based on SVM; the classification detection model includes a preprocessing module, a feature extraction module, a normalization processing module and a classification module; then, simulate the classification detection model through Vitis HLS to generate an RTL calculation model; finally, package the RTL calculation model into a single IP core that can be called, and the single IP core forms a data path through the AXI-4 protocol CPU to achieve high-speed data transmission from the PC side to the chip side, so as to realize the real-time detection of epilepsy signals. The hardware implementation method for epilepsy detection based on machine learning provided by the present application solves the problems that it is difficult to balance the computing speed and resource consumption in the traditional epilepsy detection system and the excessive accuracy loss caused by the computing method and hardware characteristics during the migration of the software-side model to the hardware side. Description of the Drawings

[0019] One or more embodiments are illustrated by the pictures in the corresponding drawings. These illustrative descriptions do not limit the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation.

[0020] Figure 1 It is a flowchart of a hardware implementation method for epilepsy detection based on machine learning provided by an embodiment of the present application.

[0021] Figure 2 It is a comparison diagram of the software and hardware structures of an epilepsy classification model provided by an embodiment of the present application.

[0022] Figure 3 It is a flowchart of feature extraction and normalization provided by an embodiment of the present application.

[0023] Figure 4The SVM classification flowchart provided by an embodiment of the present application.

[0024] Figure 5 The hardware structure diagram of epilepsy signal classification provided by an embodiment of the present application. Detailed implementation manners

[0025] As can be seen from the background art, existing epilepsy detection systems generally have technical problems such as insufficient resource utilization, low energy efficiency, and lack of hardware acceleration support in hardware implementation.

[0026] In terms of hardware implementation, with the continuous development of high-performance computing platforms, especially the rise of FPGA and Vitis HLS tools, it has also become a trend to use hardware acceleration to implement the hardware acceleration of machine learning algorithms. Hardware implementation can not only significantly improve the computing speed, but also realize real-time epilepsy monitoring on edge computing devices, providing instant detection and warning services for epilepsy patients. The process of developing an epilepsy detection system with Vitis HLS is as follows:

[0027] 1. Model design. When developing an epilepsy detection system with Vitis HLS, it is first necessary to conduct a requirements analysis and model design of the system. The epilepsy detection system usually includes steps such as signal acquisition, preprocessing, feature extraction, and classification. Developers need to select appropriate algorithms and models according to the specific requirements of epilepsy monitoring. For example, select feature extraction methods suitable for EEG (electroencephalogram) signal processing, such as wavelet transform, Fourier transform, etc., and at the same time select appropriate classification algorithms (such as SVM, neural network) to detect epileptic seizures. At this stage, the overall architecture of the system and the requirements for hardware acceleration will be determined.

[0028] 2. Algorithm mapping. After designing appropriate epilepsy detection algorithms, the next step is to map these algorithms to the hardware resources of the FPGA. In traditional Vitis HLS development, developers need to consider data types (such as floating-point numbers, fixed-point numbers) and their representations on hardware, select appropriate data storage and transmission methods, such as double data rate synchronous dynamic random access memory (DDR storage), on-chip storage, etc., and the allocation of computing resources. This process includes analyzing the hardware acceleration requirements of the algorithms, and converting algorithms such as feature extraction and classification calculations into hardware modules for parallel computing and pipelining on the FPGA.

[0029] 3. Circuit Design. Based on Vitis HLS, developers write hardware circuits using high-level languages (such as C / C++) to describe each module in the system. In the epilepsy detection system, the hardware design usually includes a feature extraction module (such as a wavelet transform module), a classifier module (such as an SVM classifier), a data transmission module, etc. Vitis HLS uses automated tools to convert these high-level designs into a hardware description language (HDL) suitable for FPGA implementation. The key at this stage is to ensure that each module in the design can achieve parallel computing, reduce data transmission latency, and maximize the utilization of FPGA hardware resources.

[0030] 4. Functional Simulation. After the hardware circuit design is completed, developers need to perform functional simulation and verification on the design to ensure that the logical functions of the hardware modules are correctly implemented. In the traditional Vitis HLS development process, this step is crucial and is mainly carried out through simulation tools. Developers need to use actual epilepsy EEG signals for testing and evaluate the operation results of the hardware circuit on the FPGA platform. This includes testing key calculation processes such as the feature extraction module and the classification module to verify their accuracy, stability, and real-time processing capabilities. Performance evaluation can also be carried out after functional simulation to ensure that the hardware design can meet the requirements of real-time performance and classification accuracy.

[0031] To solve the technical problems of insufficient resource utilization, low energy efficiency, and lack of hardware acceleration support in the hardware implementation of the epilepsy detection system, the embodiments of the present application provide a hardware implementation method and system for epilepsy detection based on machine learning. The method includes the following steps: First, obtain a data set and construct a classification detection model based on SVM; the classification detection model includes a preprocessing module, a feature extraction module, a normalization processing module, and a classification module; then, simulate the classification detection model through Vitis HLS to generate an RTL calculation model; finally, package the RTL calculation model into a single IP core that can be called. The single IP core forms a data path with the CPU through the AXI-4 protocol to achieve high-speed data transmission from the PC side to the chip side, so as to achieve real-time detection of epilepsy signals. The present application provides a hardware implementation method and system for epilepsy detection based on machine learning, which solves the problems that it is difficult to balance the computing speed and resource consumption in the traditional epilepsy detection system and the excessive accuracy loss caused by the computing method and hardware characteristics during the migration of the software-side model to the hardware side.

[0032] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are proposed to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present application can still be implemented.

[0033] See Figure 1 , the embodiment of the present application provides a hardware implementation method for epilepsy detection based on machine learning, including the following steps:

[0034] Step S101, obtain a data set and construct a classification detection model based on SVM; the classification detection model includes a preprocessing module, a feature extraction module, a normalization processing module, and a classification module.

[0035] Step S102, simulate the classification detection model through Vitis HLS to generate an RTL calculation model.

[0036] Step S103, package the RTL calculation model into a single IP core that can be called. The single IP core forms a data path with the CPU through the AXI-4 protocol to achieve high-speed data transmission from the PC side to the chip side, so as to achieve real-time detection of epilepsy signals.

[0037] In order to detect abnormal EEG signals during the seizure period of epilepsy patients, the present application designs a classification detection model based on SVM, which overall includes a complete set of processes for preprocessing, feature extraction, and classification of epilepsy EEG signals. Through the simulation and synthesis of Vitis HLS, a complete RTL calculation model is generated and packaged into a single IP core that can be called. With the AXI-4 protocol, high-speed data interaction with the CPU is achieved to achieve timely detection of epilepsy signals.

[0038] The classification detection model based on SVM is first implemented in software form: for 700 original data samples of epilepsy and 700 non-epilepsy, they are divided into a test set and a training set in a ratio of 2:8, and labels of 1 and -1 are respectively assigned to epilepsy and non-epilepsy signals. The original data with labels is sent to the filtering module for preprocessing. Usually, the EEG signal frequency of epilepsy patients is lower than 32Hz, and the 0Hz frequency EEG signal brings a large amount of noise artifacts. Therefore, the present application uses a band-pass filter of 0.5Hz to 32Hz to filter the original EEG signal. After that, the present application extracts features from the filtered signal. Considering the balance between resource utilization and classification accuracy, through testing, classification in the case of the combination of these two features, the maximum value and the variance value, can achieve better classification accuracy while saving computing resources. The present application uses wavelet transform to extract features from the filtered signal. In order to ensure the consistency of the dimension and the closeness of the numerical range between different features, the present application normalizes the extracted features, thus greatly improving the training efficiency of the model. The normalized features are sent to the SVM training module to obtain the training parameters of the model, and then the classification task of the test set is completed on the software side. The comparison diagram of the software and hardware structures of the epilepsy classification model is as Figure 2As shown. After the software side divides the training set and the test set, it outputs the test set data to the hardware side. The hardware side also completes the filtering preprocessing, feature extraction and normalization of the data. Different from the software side, when performing the SVM classification task, the hardware side receives the training parameters from the software side and does not need to train itself. Using the existing training parameters, the hardware side completes the classification task of epileptic and non-epileptic signals, and also obtains the classification accuracy. On the basis of being accurate to 0.01, there is no difference in the calculation results of the software and hardware.

[0039] In some embodiments, the classification detection model obtains the optimal training parameters through training on the software side and transfers the optimal training parameters to the hardware side, and only implements the classification test task on the hardware side.

[0040] In some embodiments, a single IP core receives the data to be classified stored by the CPU and outputs the classification result.

[0041] In some embodiments, the data set includes epileptic raw data samples and non-epileptic raw data samples; after obtaining the data set and before constructing the SVM-based classification detection model, it further includes: dividing the data set into a test set and a training set, and respectively labeling the epileptic signals and non-epileptic signals with 1 and -1, and sending the raw data with labels to the preprocessing module for preprocessing.

[0042] In some embodiments, the preprocessing module includes a band-pass filter of 0.5Hz to 32Hz, and the band-pass filter is used to filter the original EEG signals.

[0043] In some embodiments, the feature extraction module is used to extract features from the filtered signal, obtain a fusion feature formed by a two-dimensional array combination of the maximum value and the standard deviation, and use the fusion feature as input data to be sent into the classification detection model for training.

[0044] In some embodiments, the feature extraction module uses the discrete wavelet transform method to extract features from the filtered signal; the feature extraction process includes: first performing mirror padding to expand the boundary, using one-dimensional convolution to reduce the amount of calculation; then performing downsampling processing, only retaining the data at odd indices to further reduce the amount of data; calculating multiple feature combinations and testing the multiple feature combinations to obtain the best feature combination as the fusion feature; the fusion feature is a two-dimensional array combination of the maximum value and the standard deviation obtained by the data sample through the feature extraction process.

[0045] In some embodiments, the normalization module is used to perform a feature normalization process on the fusion feature; the normalization process includes: after subtracting the mean M from the fusion feature, dividing by the standard deviation of the fusion feature to complete the process of feature extraction normalization, eliminating the offset and scale difference between different features.

[0046] In some embodiments, the classification module is used to perform SVM classification on the normalized features; the SVM classification process includes RBF kernel function calculation and a decision-making process; the RBF kernel function calculation includes: subtracting the support vector from the normalized feature vector and finding the sum of squares to obtain the square value of the Euclidean distance, and then calculating the Gaussian radial basis function to obtain the RBF kernel value; multiplying each RBF kernel value by the corresponding weight coefficient and accumulating them, that is, completing the weighted summation process; finally, adding the bias term to generate the final decision value; the decision-making process includes: setting the decision boundary to 0, if it is greater than 0, it is assigned to class 1, corresponding to the decision result of the interictal period of epileptic seizures; if it is less than 0, it is assigned to class -1, corresponding to the decision result of the pre-ictal period of epileptic seizures.

[0047] The following details the hardware implementation method for epilepsy detection based on machine learning provided by this application through specific embodiments.

[0048] This application aims to provide an efficient and low-power epilepsy classification method by combining hardware acceleration and machine learning algorithms. An SVM machine learning model for classifying the pre-ictal and interictal conditions of epileptic EEG signals is constructed on an FPGA, including preprocessing, feature extraction, normalization processing of epileptic EEG signals, and the implementation of classification tasks, which can efficiently classify and detect epileptic seizure EEG signals at the hardware end using a pre-trained model.

[0049] The training and test data used in this application come from the CHB-MIT (Children's Hospital Boston - Massachusetts Institute of Technology) epilepsy dataset. The sampling rate of this data is 256Hz. Through preprocessing, this application uses 1024 sampling data points at a sampling time of 5s as a sample. A total of 1400 data samples (700 for epilepsy and 700 for non-epilepsy) are sent into the software model to implement the division of the training set and the test set and label them. Then, they are sent into a Finite Impulse Response (FIR) filter to perform a filtering process with a filtering range of 0.5 - 32Hz. The filtering coefficients are generated by the FDA (the built-in toolbox FDAtools in Matlab). The filtering process is the preprocessing of the data. The filtered data undergoes discrete wavelet transform to obtain two optimal feature combinations: the maximum value and the variance value. After the feature combination is normalized, the SVM training process is carried out on the software side to obtain the support vector SV, the support vector weight Wt, and the bias term Bias. These three together constitute the parameters generated by training and will be transmitted to both the software side and the hardware side for use in the classification task. The SVM test module, that is, the classification module, receives the labeled test set data and the parameters obtained from the training of the training set, completes the judgment of the test samples, and outputs the judgment results. The judgment results are compared with the labeled results to accumulate the final test accuracy. Different from the software side, the hardware side does not need to perform the model training process and directly uses the parameters obtained from the software model training to perform the classification task, greatly reducing the waste of storage resources and computing resources. The classifier model of this design is trained on the PC side and tested on both the FPGA and the PC side to compare its classification accuracy.

[0050] After testing various feature combinations, the optimal feature combination is determined: the maximum value and the standard deviation. A single 1024-point data sample undergoes a feature extraction process to obtain a two-dimensional array combination of the maximum value and the standard deviation, which is called the fused feature and is sent as input data into the machine learning model for training. This feature ensures the minimum computing resource occupancy under the premise of the model training efficiency, and the small number of features also ensures the simplicity of the calculation during the training and testing processes. As Figure 3 shown, this embodiment uses the discrete wavelet transform method to complete the feature extraction process: First, mirror padding is performed to expand the boundary. Since the calculation of the maximum value and the standard deviation usually requires traversing the signal data, one-dimensional convolution is used to reduce the calculation amount. If the required feature scale of the model changes, the one-dimensional convolution method can also effectively decompose the signal into high-frequency components and low-frequency components. Then, downsampling is performed, and only the data at odd indices is retained to further reduce the data volume. After that, the feature normalization process is calculated and executed: After the combined feature is subtracted by the average value, it is divided by the standard deviation of the combined feature to complete the feature extraction normalization process, eliminating the offset and scale differences between different features.

[0051] AsFigure 4 The normalized features shown still contain the feature information required for SVM classification within a small numerical fluctuation range. The support vectors SV, weight coefficients Wt, and bias term Bias obtained from software-side training are used for SVM classification. The SVM classification process on the hardware side includes the RBF kernel function calculation and the decision-making process: The use of the RBF kernel function avoids the mapping of features in the high-dimensional space and increases the generalization of the model to a certain extent. The normalized feature vector is subtracted from the support vector and the sum of squares is calculated to obtain the square value of the Euclidean distance, and then the Gaussian radial basis function is calculated to obtain the final RBF kernel value. Each RBF kernel needs to be multiplied by the corresponding weight coefficient and accumulated, that is, the weighted summation process is completed, and finally the bias term is added to generate the final decision value. The decision-making process is similar to the boundary judgment in SVM. In this routine, the decision boundary is set to 0. If it is greater than 0, it is assigned to class 1, otherwise it is -1, corresponding to the decision results of the interictal and preictal periods of epilepsy respectively.

[0052] The design process of the traditional FPGA signal processing module is completed by writing RTL code. The hardware modules are connected through a hardware description language to obtain good resource utilization and acceleration performance with the lowest-level code description. Considering the complexity of the complete epilepsy signal classification module and the large amount of data processing, the writing of RTL code is quite difficult, which not only prolongs the development cycle but also poses challenges to the maintenance of the overall code model. In this embodiment, the C++ language is used to develop a complete epilepsy signal classification model on Vivado HLS under Xilinx, including a filtering module in the data preprocessing part, a feature extraction and normalization module implemented by the discrete wavelet transform method, and a classification decision module using the SVM method with an RBF kernel. To minimize the consumption of computing resources and storage resources on the FPGA development board, we deploy the SVM training model on the software side for implementation, obtain the optimal parameters through software-side training, and transfer them to the hardware module to only implement the classification test task on the hardware side. Figure 5 The epilepsy signal classification hardware structure diagram is shown. The overall epilepsy classification module is integrated into a single IP core, which can form a data path with the CPU through the AXI-4 protocol to achieve high-speed data transmission from the PC side to the chip side. Since only a single IP core is generated, the situation of too long data links and the complexity of Block Design are avoided, greatly improving the simplicity of the hardware structure.

[0053] The present application provides a hardware implementation method for epilepsy detection based on machine learning. On the one hand, by providing a modular implementation method for a complete epilepsy signal classification scheme, the present application encapsulates the three calculation processes of data preprocessing, feature extraction and normalization, and SVM classification using only a single IP core, avoiding the problem of too long data transmission paths existing in multiple IP cores, and the IP core can be conveniently configured parametrically. Different from the complex block design structures formed by multiple IPs in other epilepsy signal classification hardware models, this classification module is integrated into a single IP core, directly receiving the original data to be classified transmitted via the AXI bus and stored by the CPU, and outputting the classification result.

[0054] On the other hand, the present application uses the method of combining the CPU-FPGA software and hardware to implement epilepsy signal classification, avoiding the consumption of storage resources and computing resources brought by the training of machine learning models on the hardware side. The on-chip random access memory (RAM) only needs to store the parameters obtained by CPU training and the classification data. The SVM training part is completed on the software side, and the hardware side only needs to store the parameters and the data to be classified, without saving the training data, reducing the register and computing resource overhead.

[0055] In addition, the present application completes the SVM model training and classification tasks with the two-dimensional fusion features composed of the maximum value and the standard deviation, greatly reducing the computational complexity and resource consumption with a small number of features while ensuring the classification accuracy. That is to say, the two-dimensional fusion features composed of the maximum value and the standard deviation in the present application maintain a high SVM classification accuracy with the least number of features. Other SVM classification models require a larger number of features, and this method reduces the amount of computation required for training and classification, saving computing resources. It should be noted that the highly integrated epilepsy signal classification calculation module of the present application uses Vitis HLS under Xilinx, is developed using the C++ language and completes simulation synthesis, and outputs RTL-level code.

[0056] The hardware resource utilization rate of the epilepsy detection model is shown in Table 1, where all the resources in the first column of Table 1 are FPGA on-chip resources.

[0057] Table 1 Hardware Resource Utilization Rate of Epilepsy Detection Model

[0058]

[0059] In addition, the embodiment of the present application also provides a hardware implementation system for epilepsy detection based on machine learning, which uses the hardware implementation method for epilepsy detection based on machine learning described in the above embodiment to perform real-time detection on epilepsy signals, including: a classification detection model module and an RTL calculation model module; wherein, the classification detection model module includes a preprocessing module, a feature extraction module, a normalization processing module and a classification module; the RTL calculation model module is used to simulate the classification detection model through Vitis HLS to generate an RTL calculation model; and package the RTL calculation model into a single IP core that can be called, and the single IP core forms a data path with the AXI-4 protocol CPU to achieve high-speed data transmission from the PC side to the chip side, so as to achieve real-time detection of epilepsy signals.

[0060] Compared with the prior art, the hardware implementation method for epilepsy detection based on machine learning provided by the present application has the following advantages: (1) High-efficiency acceleration and low power consumption; by using FPGA for hardware acceleration in the present application, while ensuring the computing efficiency, the power consumption is significantly reduced by optimizing the hardware design and fixed-point arithmetic. In addition, the parallel computing ability of FPGA can maximize the utilization of hardware resources, maintaining high-efficiency computing performance while reducing power consumption. This solution is particularly suitable for running on embedded devices or mobile devices and has a better energy efficiency ratio. (2) Flexible hardware programmability and scalability; by adopting the FPGA platform and Vitis HLS tool in the present application, the design of hardware modules can be flexibly adjusted. For example, feature extraction algorithms, SVM classification algorithms, etc. can be optimized according to actual application requirements, and even algorithm parameters can be adjusted through configuration files or firmware updates. The FPGA platform also supports later expansion, such as adding more functional modules or adjusting the computing resource configuration, greatly improving the flexibility and scalability of the system. (3) Seamless cooperation between hardware and software; in the present application, the deep integration of hardware and software is achieved through the Vitis HLS tool, and high-speed data transmission and sharing of training parameters are realized between the hardware side and the software side through the AXI-4 protocol. The hardware side directly performs classification tasks by receiving the training model parameters transmitted from the software side without retraining, thus saving computing resources and improving the overall working efficiency of the system.

[0061] In the present application, C simulation, synthesis, and co-simulation are completed in the Vitis HLS software. The program runs without error, and the obtained classification results are synchronously compared with the software side, and the absolute error is less than 0.01, which can be ignored. The resource occupancy results after synthesis are shown in Table 1. Taking the X7Z035FFG676-2 development board used in this experiment as an example: the resource occupancy rates of block random access memory (BRAM), look-up table (LUT), and digital signal processing unit (DSP) are all less than 10%, showing good resource utilization.

[0062] With the above technical solution, the embodiments of the present application provide a hardware implementation method and system for epilepsy detection based on machine learning. The method includes the following steps: First, obtain a data set and construct a classification detection model based on SVM. The classification detection model includes a preprocessing module, a feature extraction module, a normalization processing module, and a classification module. Then, simulate the classification detection model through Vitis HLS to generate an RTL calculation model. Finally, package the RTL calculation model into a single IP core that can be called. The single IP core forms a data path with the CPU through the AXI-4 protocol to achieve high-speed data transmission from the PC side to the chip side, so as to realize the real-time detection of epilepsy signals. The hardware implementation method for epilepsy detection based on machine learning provided by the present application solves the problems that it is difficult to balance the computing speed and resource consumption in the traditional epilepsy detection system and the excessive accuracy loss caused by the computing method and hardware characteristics during the migration of the software-side model to the hardware side.

[0063] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A hardware implementation method for epilepsy detection based on machine learning, characterized in that: The following steps are involved: Acquire a data set and construct a classification detection model based on SVM; the classification detection model includes a preprocessing module, a feature extraction module, a normalization processing module and a classification module; The classification detection model is simulated by Vitis HLS to generate an RTL calculation model; The RTL computing model is packaged into a single IP core that can be called. The single IP core forms a data path through the AXI-4 protocol CPU to achieve high-speed data transmission from the PC end to the chip end, so as to achieve real-time detection of epilepsy signals. The classification detection model obtains optimal training parameters by training on the software side, and transmits the optimal training parameters to the hardware side, and only implements the classification test task on the hardware side; the training parameters of the classification detection model trained on the software side include support vectors, support vector weights and bias items; The feature extraction module is used to extract features from the filtered signal to obtain a fusion feature formed by a two-dimensional array combination of the maximum value and the standard deviation, and send the fusion feature as input data to the classification detection model for training; The feature extraction module uses discrete wavelet transform method to extract features from the filtered signal; The feature extraction process includes: First, mirror padding is performed to expand the boundary, and one-dimensional convolution is used to reduce the amount of calculation; Then downsampling is performed to retain only the data under odd indexes, further reducing the amount of data; Calculate and obtain multiple feature combinations, test the multiple feature combinations, and obtain the best feature combination as a fusion feature; the fusion feature is a two-dimensional array combination of the maximum value and standard deviation obtained by the data sample through the feature extraction process; The classification module is used to perform SVM classification on the normalized features; the SVM classification process includes RBF kernel function calculation and decision process.

2. The method for realizing epilepsy detection hardware based on machine learning according to claim 1, characterized in that: The single IP core receives the data to be classified stored by the CPU and outputs the classification result.

3. The method for realizing epilepsy detection hardware based on machine learning according to claim 1, characterized in that: The data set includes epilepsy raw data samples and non-epilepsy raw data samples; After obtaining the dataset and before building the SVM-based classification detection model, it also includes: The data set is divided into a test set and a training set, and the epileptic signal and the non-epileptic signal are labeled with 1 and -1 respectively, and the raw data with the labels are sent to the preprocessing module for preprocessing.

4. The method for realizing epilepsy detection hardware based on machine learning according to claim 1, characterized in that: The preprocessing module includes a bandpass filter of 0.5 Hz to 32 Hz, and the bandpass filter is used to filter the original EEG signal.

5. The method for realizing epilepsy detection hardware based on machine learning according to claim 1, characterized in that: The normalization processing module is used to perform a feature normalization process on the fused features; The normalization process includes: subtracting the average value from the fused feature and dividing it by the standard deviation of the fused feature to complete the feature extraction normalization process, thereby eliminating the offset and scale differences between different features.

6. The method for realizing hardware implementation of epilepsy detection based on machine learning according to claim 1, characterized in that: The calculation of RBF kernel function includes: subtracting the support vector from the normalized feature vector and calculating the square sum to get the square value of the Euclidean distance, and then calculating the Gaussian radial basis function to get the RBF kernel value; multiplying each RBF kernel value with the corresponding weight coefficient and accumulating them to complete the weighted summation process; finally, adding the bias term to generate the final decision value; The judgment process includes: setting the judgment boundary to 0, if it is greater than 0, it is assigned to category 1, which corresponds to the judgment result between epileptic seizures; if it is less than 0, it is assigned to category -1, which corresponds to the judgment result before the epileptic seizure.

7. A machine learning-based epilepsy detection hardware implementation system, using the machine learning-based epilepsy detection hardware implementation method according to any one of claims 1 to 6 to perform real-time detection of epilepsy signals, characterized in that: include: Classification detection model module and RTL calculation model module; among them, The classification detection model module includes a preprocessing module, a feature extraction module, a normalization processing module and a classification module; The RTL computing model module is used to simulate the classification detection model through Vitis HLS to generate an RTL computing model; and package the RTL computing model into a single IP core that can be called. The single IP core forms a data path through the AXI-4 protocol CPU to realize high-speed data transmission from the PC end to the chip end, so as to realize real-time detection of epilepsy signals.

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