A low dielectric film based on layered compounds and its preparation method and application

Abstract

The present invention relates to the technical field of integrated circuit manufacturing, and discloses a low dielectric film based on a layered compound, a preparation method thereof, and an application thereof. The present invention provides a layered compound: [M x (OH) y ] z+ [(A n‑ ) z / n ].mH2O or [M 1x1 M 2x2 (OH) y ] z+ [(A n‑ ) z / n ].mH2O, where [M x (OH) y ] z+ or [M 1x1 M 2x2 (OH) y ] z+ Forming positively charged layers, the enlarged interlayer distance can be inserted into the anion A n‑ and a method for preparing a low-dielectric thin film based on the layered compound. The film exhibits excellent dielectric properties (k < 1.9), low dielectric loss (< 0.02), and good insulation, while maintaining an excellent Young's modulus (YM > 20 GPa). Its mechanical strength meets the requirements for back-end interconnect dielectrics, and it has broad practical application prospects in the chip back-end interconnect industry. It can also be used as a transistor insulating layer material, reducing interface traps between the insulating layer and the active layer of thin-film transistors, and improving the transistor's carrier mobility and on-off ratio.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing and relates to a low-dielectric material with a layered porous structure, which can be used as an interlayer insulating film of a semiconductor element or as a substrate of a circuit component, or applied to a chip back-end interconnection medium. Background Art

[0002] With the increasing popularity of 5G and intelligent technologies, chips are at the core of future technological progress. An insulating material is required in the chip's back-end structure to separate the conductive parts (copper interconnects on the chip) from each other and mechanically support the chip structure. In the past, porous organic silica glass was generally used, with a k of 2.4-3.0 and an elastic modulus of 5-10GPa, which is still far from ideal dielectric properties. With the miniaturization of integrated circuits and denser packaging, the width and spacing of interconnect lines are constantly decreasing, and the parasitic effects caused by interconnect resistance (R) and capacitance (C) are becoming increasingly significant. There is an urgent need to develop materials with lower dielectric constants (k < 2.4), high modulus (> 15GPa), high thermal stability (400°C), hydrophobicity, nanometer thickness, and good adhesion.

[0003] Porous materials have been widely studied as interconnect dielectric layers due to their excellent dielectric properties. However, due to their high degree of crystallinity and insolubility, the film forming process is difficult, and grain boundary defects and intergranular cracks often exist. Layered compounds retain their porous properties, which hinders ion conduction and produces low polarization, and have the characteristics of low crystallinity and easy processing into films, and are expected to be used as new low-dielectric materials. Taking α-Ni(OH)2 as an example, the layers are randomly stacked along the c-axis, and intercalated substances (water or anions) exist in the interlayer channels. α-Ni(OH)2 is prone to anion exchange. During the exchange process, the interlayer spacing and crystallinity will change due to the different volumes of anion spaces. At present, only a few works have reported the dielectric properties of α-phase compounds as electrode materials, and there has been no relevant literature reporting the application of α-phase compounds in ultra-low dielectric films. However, according to theoretical calculations, its static dielectric constant is ε ⊥ =3.55,ε \\ =3.30, showing great potential as a new interlayer dielectric. Its unique interlayer structure connects the layers with anions, ensuring stable mechanical strength. Furthermore, unlike other porous materials, this material possesses excellent thermal stability, ensuring normal operation even at high temperatures.

[0004] In response to the shortcomings of current interconnect media, the present invention proposes an ultra-low dielectric thin film material based on layered compounds, which combines the advantages of ultra-low dielectric, high mechanical strength, adjustable film thickness, and easy scale-up preparation. Summary of the Invention

[0005] In response to the shortcomings of the existing technology and based on the current requirements for the performance of the back-end interconnect dielectric layer, the present invention proposes a low-dielectric film based on layered compounds and its preparation method and application, which has excellent dielectric properties, low dielectric loss, good insulation, high breakdown field strength, while maintaining an excellent Young's modulus.

[0006] In order to achieve the above object, the present invention provides the following technical solutions: As a first aspect, a low dielectric film based on a layered compound is provided, wherein the layered compound is [M x (OH) y ] z+ [(A n- ) z / n ].mH2O or [M 1x1 M2 x2 (OH) y ] z+ [(A n- ) z / n ].mH2O; where M, M1, M2 are metal ions, A n- is an interlayer anion, x, x1, x2, y, z, m, n are non-negative numbers; x (OH) y ] z+ or [M1 x1 M2 x2 (OH) y ] z+ Forming positively charged layers, anions are inserted into the expanded interlayer spacing, and the interlayer anions A n- The layered structure is supported by van der Waals force; and the low dielectric film is formed by spin coating deposition of the layered compound.

[0007] Furthermore, the metal ion is Li + , Ca 2+ Mg 2+ 、Al 3+ 、Fe 2+ 、Co 2+ 、Ni 2+ 、Cu 2+ 、Zn 2+ 、Mn 2+ 、Y 2+ 、Yb 2+ One or more of .

[0008] Furthermore, the anion is SiF6 2- 、GeF6 2- 、TiF6 2- ,NbOF5 2- 、[(CH2)4(CO2)] 2- 、SO4 2- 、CO32- 、NO3 - PO4 3- 、Cl - Br - , one or more surfactants with organic groups.

[0009] Furthermore, the surfactant with an organic group includes SDS, CTAB, SDBS, and Tween 80.

[0010] As a second aspect, the present invention provides a method for preparing a low dielectric film based on a layered compound, comprising the following steps:

[0011] Fully dispersing the layered compound in an organic solvent to prepare a spin coating solution;

[0012] A substrate is provided, and a spin coating liquid is spin-coated on the substrate.

[0013] Preferably, the spin coating speed is 1000-8000 rpm, the spin coating time is 30-60 s, and the concentration of the spin coating solution is 0.5-15 mg / ml.

[0014] Furthermore, the layered compound is prepared by the following method: dissolving metal salt powder in an organic solvent to make the metal salt concentration be 0.02 to 0.1 mol / L, adding an organic base to precipitate the layered compound, and washing to obtain the layered compound;

[0015] Furthermore, the organic solvent is an alcohol solvent, the organic base is selected from aliphatic amines and aromatic amines, and the metal ions in the metal salt are selected from Li + , Ca 2+ Mg 2+ 、Al 3+ 、Fe 2+ 、Co 2+ 、Ni 2+ 、Cu 2+ 、Zn 2+ 、Mn 2+ 、Y 2+ 、Yb 2+ , anion is selected from SiF6 2- 、GeF6 2- 、TiF6 2- ,NbOF5 2- 、[(CH2)4(CO2)] 2- 、SO4 2- 、CO3 2- 、NO3 - PO4 3- 、Cl - Br -, surfactants with organic groups, the surfactants with organic groups include SDS, CTAB, SDBS, and Tween 80.

[0016] Furthermore, the thin film prepared by the spin coating method is subjected to supercritical CO2 extraction to extract small organic molecules between the layers.

[0017] Preferably, the extraction temperature is 60-100° C., the extraction pressure is 10-14 MPa, and the extraction time is 2-4 h.

[0018] As a third aspect, the present invention provides a method for patterning the low dielectric film, wherein patterning is performed by photolithography, dry and wet etching, and deposition, comprising the following steps:

[0019] coating the low dielectric thin film on a substrate to form a dense film layer on the substrate;

[0020] Spin-coating a photoresist on the low dielectric film;

[0021] The photoresist layer is exposed through a photomask, and a specific pattern can be formed after development;

[0022] Required materials can be deposited on the pattern, and a specific pattern can be formed on the low dielectric film after stripping; or the developed low dielectric film can be etched by dry or wet methods to form grooves.

[0023] As a fourth aspect, the present invention provides an application of the low-dielectric film as described above: as an interlayer dielectric or a substrate for a circuit component of a chip back-end interconnect.

[0024] As a fifth aspect, the present invention further provides a thin film transistor: comprising an active layer (03), an insulating layer (02), a gate electrode (01), a source electrode (04), and a drain electrode (05), wherein the insulating layer (02) comprises a first insulating layer (021) and a second insulating layer (022) formed by the low dielectric thin film, which are sequentially located on the gate electrode (01); the active layer (03) is located on the insulating layer (02), and the source electrode (04) and the drain electrode (05) are located on the active layer (03); or the source electrode (04) and the drain electrode (05) are located on the insulating layer (02), and then covered with a layer of the active layer (03);

[0025] Alternatively, the low dielectric film is positioned as an insulating layer (02) on the gate (01), the active layer (03) is positioned on the insulating layer (02), and the source (04) and the drain (05) are positioned on the active layer (03); or the source (04) and the drain (05) are positioned on the insulating layer (02) and then covered with an active layer (03).

[0026] The beneficial effects of the present invention are as follows:

[0027] (1) The present invention proposes a new ultra-low dielectric material based on layered compounds, which has high porosity. Supercritical extraction can replace small organic molecules between layers, while increasing the interlayer spacing, increasing the porosity of the film, and hindering ion conduction, which greatly reduces the electrical conductivity and ensures a low dielectric constant. In addition, the interlayer anions contain chemical bonds with low polarizability, such as Si-F bonds. The low-crystallization compound colloids are densely packed, and the interlayer anion columns in the microstructure support the layered structure, ensuring that the film also has excellent mechanical strength. It achieves the combination of ultra-low dielectric (k<2.0), high mechanical strength (YM>20GPa), adjustable film thickness, and easy scale-up preparation. The performance is far higher than the dielectric materials reported in the current literature. In practical applications, it also has good insulation and a certain breakdown field strength. And it can still maintain a good working state at a high temperature of 300°C, so that the film can be used as an interlayer dielectric for chip back-end interconnection.

[0028] (2) This invention proposes a novel method for preparing layered compound thin films. A simple spin coating method can produce continuous, dense dielectric films with adjustable thickness and smooth surfaces. The spin coating method can be used to prepare wafer-scale dielectric films, facilitating large-scale industrial production.

[0029] (3) Patterning is achieved on the film surface by photolithography, dry and wet etching. This has broad practical application prospects in the chip back-end interconnection industry. The present invention also provides an application of ultra-low dielectric films in transistors, reducing interface traps between the insulating layer and the active layer of thin-film transistors and improving the carrier mobility and on / off ratio of transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the low dielectric film structure based on layered compounds and back-end interconnection diagram of the present invention;

[0031] Figure 2 is the XRD pattern of Example 1 of the present invention;

[0032] Figure 3 Performance graphs of Example 1 of the present invention, where (a) and (b) show the morphology of the low-dielectric film; (c) shows the relationship between the dielectric constant and frequency of Example 1; (d) shows the relationship between dielectric loss and frequency; (e) shows the breakdown field strength performance; and (f) shows the relationship between leakage current and voltage.

[0033] Figure 4 Graphs of dielectric properties of Examples 2-5 of the present invention, including (a) a graph showing the relationship between dielectric constant and frequency; (b) a graph showing the relationship between dielectric loss and frequency;

[0034] Figure 5 Graph showing the mechanical properties of Example 4 of the present invention, where (a) and (b) are Young's modulus and hardness of the film, respectively;

[0035] Figure 6 Graphs of dielectric properties of Example 6 of the present invention, including (a) a graph showing the relationship between dielectric constant and frequency for Example 6; and (b) a graph showing the relationship between dielectric loss and frequency for Example 6.

[0036] Figure 7 Graphs showing the dielectric properties of Example 7 of the present invention, (a) and (b) showing the relationship between the dielectric constant and dielectric loss and frequency of Example 7, respectively;

[0037] Figure 8 This is the XRD pattern of Example 8 of the present invention;

[0038] Figure 9 Graphs showing the performance of Example 8 of the present invention, where (a) and (b) are SEM images of the thin film; (c) is a graph showing the relationship between the dielectric constant and frequency of Example 8; (d) is a graph showing the relationship between the dielectric loss and frequency; (e) and (f) are Young's modulus and hardness of Example 8 of the present invention;

[0039] Figure 10 This is the XRD pattern of Example 9 of the present invention;

[0040] Figure 11 Performance graphs of Example 9 of the present invention, where (a) and (b) show the film morphology; (c) shows the relationship between the dielectric constant and frequency of Example 9; (d) shows the relationship between the dielectric loss and frequency; (e) and (f) show the Young's modulus and hardness of Example 9 of the present invention;

[0041] Figure 12 10 is a device structure diagram of embodiment 10 of the present invention;

[0042] Figure 13 1 is a device structure diagram of embodiment 11 of the present invention;

[0043] Figure 14 1 is a device structure diagram of embodiment 12 of the present invention;

[0044] Figure 15 This is a device structure diagram of Example 13 of the present invention. DETAILED DESCRIPTION

[0045] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.

[0046] Unless otherwise specified, all raw materials used in this invention are commonly available commercially. The silicon wafers used in this invention were purchased from Shanghai Zixi Electronic Technology Co., Ltd. and were highly doped with p++. The silicon dioxide wafers were purchased from Hefei Kejing Materials Technology Co., Ltd. and were 300nm SiO2, N-type doped. The spin coater was purchased from Shanghai Sanyan Technology Co., Ltd., model SYSC-100A.

[0047] Example 1α-Ni(OH)2-SiF6

[0048] (1) Preparation of α-Ni(OH)2-SiF6: Add 1 mmol of nickel hexafluorosilicate hexahydrate (NiSiF6.6H2O) to 50 ml of methanol and stir until homogeneous. Add 2-5 mmol of triethylamine until uniformly mixed. All of the above processes are carried out at room temperature. Finally, add 4-8 mmol of pyrazine and stir at 50-60°C for 1-2 days. After the reaction is completed, remove the supernatant by centrifugation (3000-10000 rpm, 15-30 min), add fresh methanol solution and soak for 12 hours. Repeat the above washing process 3 times.

[0049] (2) Preparation of α-Ni(OH)2-SiF6 spin coating solution: The wet solid was fully dispersed in methanol solvent to prepare a 5 mg / ml spin coating solution.

[0050] (3) Silicon wafer surface treatment: The silicon wafer surface is placed in acetone, isopropyl alcohol, and deionized water for ultrasonic cleaning for 15-30 minutes, and then blown dry with high-purity nitrogen for later use.

[0051] (4) α-Ni(OH)2-SiF6 film formation by spin coating: The silicon wafer was covered with the spin coating liquid and rotated at a speed of 2000 rpm (acceleration 200 rpm / s) for 30-60 s.

[0052] (5) Post-treatment: Keep the spin-coated film in a vacuum oven at 60-100°C for 6-12 hours (drying). Electrodes with different patterns are constructed on the film surface by photolithography and magnetron sputtering for subsequent dielectric performance testing. The organic small molecules between the layers are extracted by supercritical CO2 at an extraction temperature of 60-100°C, an extraction pressure of 10-14 MPa, and an extraction time of 2-4 hours. High-temperature thermal annealing is performed at an annealing temperature of 150°C for 3-24 hours.

[0053] The dielectric constant of the material was measured by LCR meter. According to the parallel plate capacitor theory, the dielectric constant of the material is k = Cs × d / (ε0 × S), where ε0 represents the vacuum dielectric constant, S represents the area of the top circular electrode, and d is the average thickness of the film. The thickness of the dielectric film obtained is 33nm. 6At 100 Hz, the dielectric constant is 1.61. Dielectric loss is maintained below 0.02, with no significant energy loss. Supercritical extraction displaces small organic molecules from the interlayers, increasing the interlayer spacing and porosity of the film, ensuring a low dielectric constant. Furthermore, the interlayer anions contain Si-F bonds with low polarizability.

[0054] The film's leakage current was measured using a semiconductor parameter analyzer. The leakage current was less than 1 nA over a bias voltage range of -2 V to +2 V, demonstrating the dielectric's excellent insulation properties. Its breakdown field strength was 1.1 MV / cm, demonstrating the dielectric's robustness.

[0055] Example 2-3

[0056] α-Ni(OH)2-SiF6 was prepared according to the method of Example 1, except that the spin coating speeds were 1000 rpm and 3000 rpm in 2-3 (other conditions not specified were the same as in Example 1). The obtained film thicknesses were 39.3 nm and 26.4 nm, respectively, and the dielectric properties were shown in Table 1. Figure 4 , the film thickness decreases with the increase of spin coating speed, the film quality remains unchanged, and the dielectric properties measured for different film thicknesses remain consistent. This is because different spin coating speeds do not affect the composition and layered structure of the film.

[0057] Examples 4-5

[0058] α-Ni(OH)2-SiF6 was prepared according to the method of Example 1, except that the concentration of the spin coating solution was 10 mg / ml and 15 mg / ml respectively (other conditions not specified were the same as those of Example 1). The obtained film thicknesses were 53.5 nm and 61.5 nm respectively, and the dielectric properties were shown in Table 1. Figure 4 The film thickness increases with the increase of spin-coating liquid concentration, among which the dielectric constant of the 61.5nm film is slightly higher than the other values. This is because the surface roughness of the film increases slightly with the increase of film thickness, which causes the dielectric constant value measured based on the MIM structure to fluctuate.

[0059] The film's mechanical properties were measured through continuous depth nanoindentation. The Young's modulus of Example 4 was 28.3 GPa, and the hardness was 2.0 GPa, meeting the requirements for back-end interconnect dielectrics. The densely packed low-crystalline nickel hydroxide colloids, with interlayer anion columns supporting the layered structure, ensure the film's excellent mechanical strength.

[0060] Examples 6-7

[0061] α-Ni(OH)2-SiF6 was prepared according to the method of Example 1, except that the thermal annealing temperatures in 6-7 were 250°C and 300°C respectively (other conditions not specified were consistent with those in Example 1). The dielectric properties were shown in FIG. Figure 6 、 7 After high temperature treatment, the dielectric constant increases slightly but is still within the reliable range. This is because high temperature can compress the interlayer spacing and reduce the porosity.

[0062] Example 8 α-Co(OH)2-GeF6

[0063] (1) Preparation of α-Co(OH)2-GeF6: Add 1 mmol of cobalt hexafluorosilicate hexahydrate (CoGeF6·6H2O) to 50 ml of methanol and stir until homogeneous. Add 2-5 mmol of triethylamine until uniformly mixed. All of the above processes are carried out at room temperature. Finally, add 4-8 mmol of pyrazine and stir at 50-60°C for 1-2 days. After the reaction is completed, remove the supernatant by centrifugation (10,000 rpm, 30 min), add fresh methanol solution and soak for 12 hours. Repeat the above washing process 3 times.

[0064] (2) Preparation of α-Co(OH)2-GeF6 spin coating solution: The wet solid was fully dispersed in methanol solvent to prepare a 1-15 mg / ml spin coating solution.

[0065] (3) Silicon wafer surface treatment: The silicon wafer surface is placed in acetone, isopropyl alcohol, and deionized water for ultrasonic cleaning for 15-30 minutes, and then blown dry with high-purity nitrogen for later use.

[0066] (4) Spin coating of α-Co(OH)2-GeF6: Add the spin coating solution to the silicon wafer and spin it at a speed of 1000-8000 rpm (acceleration 200 rpm / s) for 30-60 s.

[0067] (5) Post-treatment: The spin-coated α-Co(OH)2-GeF6 film is kept in a vacuum oven at 60-100°C for 6-12 hours. Electrodes with different patterns are constructed on the film surface by photolithography and magnetron sputtering for subsequent dielectric performance testing. The organic small molecules between the layers are extracted by supercritical CO2 at an extraction temperature of 60-100°C, an extraction pressure of 10-14 MPa, and an extraction time of 2-4 hours. High-temperature thermal annealing is performed at an annealing temperature of 60-120°C for 3-24 hours.

[0068] The dielectric constant of the material was measured by LCR meter, and the thickness of the dielectric film was 65nm. 6 At 100 Hz, the dielectric constant is 4.11. The dielectric loss is generally maintained within the range of less than 0.05, with no significant energy loss. There is still room for further improvement in dielectric performance.

[0069] The membrane's mechanical properties were measured through continuous depth nanoindentation, yielding a Young's modulus of 30.5 GPa and a hardness of 2.2 GPa, meeting the requirements for back-end interconnect dielectrics.

[0070] Example 9α-Ni(OH)2-GeF6

[0071] (1) Preparation of α-Ni(OH)2-GeF6: Add 1 mmol of nickel hexafluorosilicate hexahydrate (NiGeF6·6H2O) to 50 ml of methanol and stir until homogeneous. Add 2-5 mmol of triethylamine until uniformly mixed. The above process is carried out at room temperature. Finally, add 4-8 mmol of pyrazine and react in a reactor at 150°C for 6 hours. After the reaction is completed, remove the supernatant by centrifugation (10,000 rpm, 30 minutes), add fresh methanol solution and soak for 12 hours. Repeat the above washing process 3 times.

[0072] (2) Preparation of α-Ni(OH)2-GeF6 spin coating solution: The wet solid was fully dispersed in methanol solvent to prepare a 1-10 mg / ml spin coating solution.

[0073] (3) Silicon wafer surface treatment: The silicon wafer surface is placed in acetone, isopropyl alcohol, and deionized water for ultrasonic cleaning for 15-30 minutes, and then blown dry with high-purity nitrogen for later use.

[0074] (4) α-Ni(OH)2-GeF6 spin coating: Add the spin coating solution on the silicon wafer and spin it at a speed of 1000-8000 rpm (acceleration 200 rpm / s) for 30-60 seconds.

[0075] (5) Post-treatment: The spin-coated α-Ni(OH)2-GeF6 film is kept in a vacuum oven at 60-100°C for 6-12 hours. Electrodes with different patterns are constructed on the film surface by photolithography and magnetron sputtering for subsequent dielectric performance testing. The organic small molecules between the layers are extracted by supercritical CO2 at an extraction temperature of 60-100°C, an extraction pressure of 10-14 MPa, and an extraction time of 2-4 hours. High-temperature thermal annealing is performed at an annealing temperature of 60-120°C for 3-24 hours.

[0076] The dielectric constant of the material was measured by LCR meter, and the thickness of the dielectric film was 50nm. 6 At Hz frequency, the dielectric constant is 1.95. The dielectric loss is basically kept within the range of less than 0.05, with no obvious energy loss.

[0077] The membrane's mechanical properties were measured through continuous depth nanoindentation, yielding a Young's modulus of 35.8 GPa and a hardness of 1.0 GPa, meeting the requirements for back-end interconnect dielectrics.

[0078] Example 10

[0079] Thin film transistor 100, combined with Figure 12 As shown, the transistor 100 includes an active layer 03, source / drain electrodes 04 and 05 electrically connected to the active layer 03, a first insulating layer 021 and a second insulating layer 022 corresponding to the active layer, and a gate 01. An ultra-low dielectric film, serving as the second insulating layer 022, is located between the active layer 03 and the first insulating layer 021. Together, the ultra-low dielectric film and the first insulating layer 021 form the insulating layer 02 of the transistor 100. The low dielectric film can reduce energy dislocation between the insulating layer and the active layer, reducing interface traps and thereby improving the electrical performance of the transistor.

[0080] The present invention provides a method for manufacturing a thin film transistor, comprising the following steps:

[0081] S1. Provide a substrate (silicon dioxide wafer), wherein highly doped silicon is used as the gate 01 and SiO2 is used as the first insulating layer 021;

[0082] S2, forming a second insulating layer 022 on the first insulating layer 021;

[0083] S3, forming an active layer 03 on the second insulating layer 022;

[0084] S4 , fabricating source and drain electrodes 04 and 05 on the active layer 03 .

[0085] First, a highly doped SiO2 silicon wafer is hydrophilized. A spin-coating process is then used to form an ultra-low dielectric thin film on the substrate as the second insulating layer 022. After the insulating layer 02 is formed, the active layer 03 is formed by atomic layer deposition or spin coating. The active layer can be made of materials such as metal oxides and organic semiconductors. Finally, source and drain electrodes 04 and 05 are formed above the active layer by magnetron sputtering or electron beam evaporation. The electrodes can be made of highly conductive materials such as Au, Pt, and Al.

[0086] Example 11

[0087] Thin film transistor 200, combined with Figure 13 As shown, the production method comprises the following steps:

[0088] S1. Provide a substrate (silicon dioxide wafer), wherein highly doped silicon is used as the gate 01 and SiO2 is used as the first insulating layer 021;

[0089] S2, forming a second insulating layer 022 on the first insulating layer 021;

[0090] S3, forming source and drain electrodes 04 and 05 on the second insulating layer 022;

[0091] S4 , forming an active layer 03 on the source-drain electrodes 04 and 05 .

[0092] First, a highly doped silicon wafer containing SiO2 is hydrophilized. A spin-coating process is then used to form an ultra-low dielectric thin film on the substrate as the second insulating layer 022. After the insulating layer 02 is formed, source and drain electrodes 04 and 05 are fabricated using methods such as magnetron sputtering and electron beam evaporation. These electrodes can be made of highly conductive materials such as Au, Pt, and Al. Finally, the active layer 03 is formed using atomic layer deposition or spin coating. The active layer can be made of materials such as metal oxides and organic semiconductors.

[0093] Example 12

[0094] Thin film transistor 300, combined Figure 14 As shown, it includes an active layer 03, source and drain electrodes 04 and 05 electrically connected to the active layer 03, an insulating layer 02 corresponding to the active layer, and a gate 01. The ultra-low dielectric film as the insulating layer 02 is located between the active layer 03 and the gate 01.

[0095] The present invention provides a method for manufacturing a thin film transistor, comprising the following steps:

[0096] S1. Provide a substrate (highly doped silicon wafer), wherein the highly doped silicon serves as the gate 01;

[0097] S2, forming an insulating layer 02 on the gate 01;

[0098] S3, forming an active layer 03 on the insulating layer 02;

[0099] S4 , fabricating source and drain electrodes 04 and 05 on the active layer 03 .

[0100] First, a highly doped silicon wafer is hydrophilized. An ultra-low dielectric thin film is then formed on the substrate via spin coating, serving as the insulating layer 02. After this layer 02 is formed, the active layer 03 is fabricated via atomic layer deposition or spin coating. The active layer can be made of materials such as metal oxides and organic semiconductors. Finally, source and drain electrodes 04 and 05 are fabricated above the active layer via magnetron sputtering or electron beam evaporation. These electrodes can be made of highly conductive materials such as Au, Pt, and Al.

[0101] Example 13

[0102] Thin film transistor 400, combined with Figure 15 As shown, the production method comprises the following steps:

[0103] S1. Provide a substrate (highly doped silicon wafer), wherein the highly doped silicon serves as the gate 01;

[0104] S2, forming an insulating layer 02 on the gate 01;

[0105] S3, forming source and drain electrodes 04 and 05 on the insulating layer 02;

[0106] S4 , forming an active layer 03 on the source-drain electrodes 04 and 05 .

[0107] First, a highly doped silicon wafer is hydrophilized. An ultra-low dielectric thin film is then formed on the substrate via spin coating, serving as the insulating layer 02. After the insulating layer 02 is formed, source and drain electrodes 04 and 05 are fabricated using methods such as magnetron sputtering and electron beam evaporation. These electrodes can be made of highly conductive materials such as Au, Pt, and Al. Finally, the active layer 03 is formed using atomic layer deposition or spin coating. The active layer can be made of materials such as metal oxides and organic semiconductors.

Claims

1. A low dielectric film based on a layered compound, characterized in that The layered compound is [M x (OH) y ] z+ [(A n- ) z / n ]·mH2O or [M 1 x1 M 2 x2 (OH) y ] z+ [(A n- ) z / n ]·mH2O; Among them, M, M1, M2 are metal ions, A n- is an interlayer anion, x, x1, x2, y, z, m, n are non-negative numbers; x (OH) y ] z+ or [M 1 x1 M 2 x2 (OH) y ] z+ Forming positively charged layers, anions are inserted into the expanded interlayer spacing, and the interlayer anions A n- The layered structure is supported by van der Waals forces; the metal ions are Li + , Ca 2+ Mg 2+ 、Al 3+ 、Fe 2+ 、Co 2+ 、Ni 2+ 、Cu 2+ 、Zn 2+ 、Mn 2+ 、Y 2+ 、Yb 2+ One or more of; the low dielectric film is formed by spin coating deposition of a layered compound.

2. The low dielectric film according to claim 1, wherein The anion is SiF6 2- 、GeF6 2- 、TiF6 2- ,NbOF5 2- 、[(CH2)4(CO2)] 2- 、SO4 2- 、CO3 2- 、NO3 - PO4 3- 、Cl - Br - , one or more surfactants with organic groups.

3. The low dielectric film according to claim 2, wherein: The surfactant with an organic group includes SDS, CTAB, SDBS, and Tween 80.

4. A method for preparing a low dielectric film based on a layered compound, characterized in that: The following steps are involved: The layered compound according to claim 1 is fully dispersed in an organic solvent to prepare a spin coating solution; A substrate is provided, and a spin coating liquid is spin-coated on the substrate.

5. The preparation method according to claim 4, characterized in that The layered compound is prepared by the following method: dissolving metal salt powder in an organic solvent to make the metal salt concentration be 0.02-0.1 mol / L, adding an organic base until the layered compound is precipitated, and washing to obtain the layered compound; The organic solvent is an alcohol solvent, and the organic base is selected from aliphatic amines and aromatic amines.

6. The preparation method according to claim 4, characterized in that The thin film prepared by the spin coating method is subjected to supercritical CO2 extraction to extract small organic molecules between layers.

7. A method for patterning a low dielectric film according to claim 1, characterized in that: Patterning is performed by photolithography, dry and wet etching, and deposition, including the following steps: coating the low dielectric thin film on a substrate to form a dense film layer on the substrate; Spin coating a photoresist on the low dielectric film; The photoresist layer is exposed through a photomask and a specific pattern is formed after development; Deposit the required material on the pattern, and form a specific pattern on the low dielectric film after stripping; or perform dry and wet etching on the developed low dielectric film to form a groove.

8. An application of the low dielectric film according to claim 1, characterized in that: A substrate that serves as an interlayer dielectric or path component for back-end interconnection of a chip.

9. A thin film transistor comprising an active layer (03), an insulating layer (02), a gate (01), a source electrode (04), and a drain electrode (05), characterized in that: The insulating layer (02) includes a first insulating layer (021) and a second insulating layer (022) formed by the low dielectric film according to claim 1, which are sequentially located on the gate (01); the active layer (03) is located on the insulating layer (02), and the source (04) and the drain (05) are located on the active layer (03); or the source (04) and the drain (05) are located on the insulating layer (02), and then covered with an active layer (03); Or the low dielectric film is located on the gate (01) as an insulating layer (02), the active layer (03) is located on the insulating layer (02), and the source (04) and the drain (05) are located on the active layer (03); or the source (04) and the drain (05) are located on the insulating layer (02) and then covered with an active layer (03).

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