Chip mounting apparatus, mounting method, and manufacturing method of semiconductor device

Abstract

The invention provides a chip mounting apparatus, a mounting method and a manufacturing method of a semiconductor device, and provides a technology capable of enabling a bare chip and a surface of a substrate to be activated and bonded. The chip mounting apparatus includes: a first mounting head that picks up a bare chip; a first mounting table for holding the substrate; and a plasma irradiator which performs plasma irradiation on the surface of the bare chip picked up by the first mounting head and the surface of the substrate held by the first mounting table.

Description

Technical Field

[0001] The present disclosure relates to a chip mounting device, and can be applied to, for example, a flip chip mounting machine that performs surface activated bonding. Background Art

[0002] The chip mounting device (semiconductor manufacturing device, mounting device) has a flip chip mounting machine, which picks up a bare chip separated from a wafer and having bumps on the surface, and flips the picked-up bare chip over so that the surface faces down (face down) and mounts it on a substrate (for example, JP Patent Gazette No. 2023-45346).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2023-45346 Summary of the invention

[0006] The object of the present disclosure is to provide a technique capable of activating bonding between a bare chip and a surface of a substrate. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0007] The following is a brief description of a typical outline of the present disclosure.

[0008] That is, the chip mounting device comprises: a first mounting head for picking up a bare chip; a first mounting table for holding a substrate; and a plasma irradiator for performing plasma irradiation on the surface of the bare chip picked up by the first mounting head and the surface of the substrate held by the first mounting table.

[0009] Effects of the Invention

[0010] According to the present disclosure, surface activated bonding can be performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a plan view schematically showing a flip chip mounter in the embodiment.

[0012] Figure 2 It is shown Figure 1 A schematic cross-sectional view of a main portion of a wafer supply unit is shown.

[0013] Figure 3 yes Figure 1 A schematic front view of the periphery of a pickup unit in a flip chip mounter is shown.

[0014] Figure 4 yes Figure 1 A schematic side view of a temporary pressure-bonding portion of a placement section in a flip chip placement machine is shown.

[0015] Figure 5 yes Figure 1 A schematic side view of an actual pressure-bonding portion of a placement section in a flip chip placement machine is shown.

[0016] Figure 6 It is shown Figure 1 A block diagram showing a schematic configuration of a control system of a flip chip mounter.

[0017] Figure 7 It shows the use of Figure 1 FIG. 1 is a flow chart of a mounting method implemented by a flip chip mounting machine.

[0018] Figure 8 It is shown Figure 1 A diagram showing the configuration of a plasma irradiator.

[0019] Fig. 9 It is a diagram for explaining the plasma irradiation method in the first mounting portion.

[0020] Fig.10 It is a diagram for explaining the plasma irradiation method in the first mounting portion.

[0021] Fig.11 It is a diagram for explaining the plasma irradiation method in the first modification.

[0022] Fig.12 It is a diagram for explaining the plasma irradiation method in the first modification.

[0023] Fig.13 It is a diagram for explaining the plasma irradiation method in the second modification.

[0024] Fig.14 It is a diagram for explaining the plasma irradiation method in the second modification.

[0025] Fig.15 (a) and Fig.15 (b) is a diagram for explaining the mounting process in the third modification example.

[0026] Fig.16 (a) and Fig.16 (b) is a diagram for explaining the mounting process in the third modification example.

[0027] The reference numerals are described as follows:

[0028] 1Flip chip mounter (chip mounting device)

[0029] 41a Temporary crimping head (first mounting head)

[0030] 46a Temporary crimping station (first mounting station)

[0031] 90 Plasma Irradiator DETAILED DESCRIPTION

[0032] The following is an explanation of the embodiments using the drawings. However, in order to make the explanation clear, the following description and drawings are appropriately omitted and simplified. In addition, sometimes the same component is marked with the same figure mark and repeated description is omitted. In addition, in order to make the explanation clearer, sometimes the width, thickness, shape, etc. of each part of the drawings are schematically shown compared with the actual form.

[0033] use Figure 1 to Figure 5 The configuration of a flip chip mounter as one embodiment of a chip mounting apparatus will be described. Figure 1 It is a schematic plan view showing a configuration example of a flip chip mounter in the embodiment. Figure 2 It is shown Figure 1 A schematic cross-sectional view of a main portion of a wafer supply unit is shown. Figure 3 yes Figure 1 A schematic front view of the periphery of a pickup unit in a flip chip mounter is shown. Figure 4 yes Figure 1 A schematic side view of a temporary pressure-bonding portion of a placement section in a flip chip placement machine is shown. Figure 5 yes Figure 1 A schematic side view of an actual pressure-bonding portion of a placement section in a flip chip placement machine is shown.

[0034] like Figure 1 As shown, the flip chip mounter 1 generally includes a wafer supply unit 10, a pickup unit 20, an intermediate stage unit 30, a mount unit 40, a conveying unit 50, a substrate supply unit 60, a substrate unloading unit 70, and a control unit (control device) 80. The Y2-Y1 direction is the front-to-back direction of the flip chip mounter 1, the X2-X1 direction is the left-to-right direction, and the Z1-Z2 direction is the up-down direction. The wafer supply unit 10 is arranged at the front side of the flip chip mounter 1, and the mount unit 40 is arranged at the rear side.

[0035] The wafer supply unit 10 includes a wafer cassette elevator 11 , a wafer holding table 12 , and a peeling unit 13 .

[0036] The wafer box elevator 11 moves a wafer box (not shown) for storing a plurality of wafer rings WR up and down to a wafer transfer height. A wafer correction groove (not shown) aligns the wafer ring WR supplied from the wafer box elevator 11. A wafer extractor (not shown) takes out the wafer ring WR from the wafer box and supplies it to the wafer holding table 12, or takes it out from the wafer holding table 12 and stores it in the wafer box.

[0037] A wafer W is adhered (attached) to the dicing tape DT, and the wafer W is divided into a plurality of bare chips D. The dicing tape DT is held by a wafer ring WR. The wafer W is, for example, a semiconductor wafer or a glass wafer, and the bare chips D as workpieces are semiconductor chips, glass chips, or MEMS (Micro Electro Mechanical Systems).

[0038] like Figure 2 As shown, the wafer holding table 12 has an expansion ring 15 for holding the wafer ring WR and a support ring 17 for horizontally positioning the dicing tape DT. The wafer holding table 12 is moved in the X1-X2 direction and the Y1-Y2 direction by a driving unit not shown in the figure, so that the picked-up bare chip D is moved to the position of the peeling unit 13. In addition, the wafer holding table 12 rotates the wafer ring WR in the XY plane using a driving unit not shown in the figure. The peeling unit 13 moves in the up and down direction using a driving unit not shown in the figure. The peeling unit 13 peels the bare chip D from the dicing tape DT.

[0039] like Figure 1 as well as Figure 3 As shown, the pickup unit 20 has a pickup head 21 and a wafer recognition camera 24. The pickup head 21 is provided with a collet 22 for adsorbing and holding the peeled bare chip D at the front end. The pickup head 21 picks up the bare chip D from the wafer supply unit 10 and places the surface (surface) on which the metal electrode De of the bare chip D is formed facing upward on the intermediate stage 31. The pickup head 21 moves in the Z1-Z2 direction, the X1-X2 direction, and the Y1-Y2 direction.

[0040] The wafer recognition camera 24 confirms the pick-up position of the bare chip D picked up from the wafer W, or performs a surface inspection of the bare chip D.

[0041] like Figure 1 as well as Figure 3 As shown, the intermediate stage unit 30 includes an intermediate stage 31 on which a bare chip D is placed, and a stage recognition camera 34 for recognizing the bare chip D on the intermediate stage 31. The intermediate stage 31 includes a turning stage 31a and a pick-up stage 31b. The bare chip D is placed on the turning stage 31a with the surface facing upward, and the turning stage 31a is turned over so that the surface of the bare chip D faces downward and the bare chip D is placed on the pick-up stage 31b. The placed bare chip D is temporarily held on the pick-up stage 31b.

[0042] like Figure 1 As shown, the mounting portion 40 has a temporary crimping portion 40a and an actual crimping portion 40b. Figure 4As shown, the temporary crimping section 40a has a temporary crimping head 41a as a first mounting head, a substrate recognition camera 44a, a temporary crimping table 46a as a first mounting station, and a plasma irradiator 90. The temporary crimping head 41a has a collet 42a that sucks and holds the bare chip D at the front end, similarly to the pickup head 21. The temporary crimping head 41a moves in the Y1-Y2 direction. The substrate recognition camera 44a captures the position recognition mark (not shown) of the substrate S to identify the mounting position. The temporary crimping table 46a rises when the bare chip D is placed on the substrate S, and supports the substrate S from below. The temporary crimping table 46a has a suction port (not shown) for vacuum adsorption of the substrate S, and can fix the substrate S. According to this structure, the temporary crimping head 41a picks up the bare chip D from the intermediate stage 31, and mounts the bare chip D on the conveyed substrate S based on the camera data of the substrate recognition camera 44a.

[0043] like Figure 5 As shown, the actual crimping section 40b has an actual crimping head 41b as a second mounting head, a substrate recognition camera 44b, and an actual crimping table 46b as a second mounting table. The actual crimping head 41b has a collet 42b that presses the bare chip D to the substrate S. The actual crimping head 41b moves in the Y1-Y2 direction. The actual crimping table 46b rises when the bare chip D is placed on the substrate S, and supports the substrate S from below. The actual crimping table 46b has a suction port (not shown) for vacuum adsorption of the substrate S, which can fix the substrate S. The actual crimping table 46b heats the substrate S using a heating device 461. According to this structure, the actual crimping head 41b actually crimps the bare chip D temporarily crimped on the substrate S to the substrate S. The load or load-bearing time of the actual crimping head 41b for actual crimping is greater than the load or load-bearing time of the temporary crimping head 41a for temporary crimping. In order to confirm the crimping state of the bare chip D, the substrate recognition camera 44b photographs the bare chip D and the substrate S.

[0044] like Figure 1 As shown, the conveying unit 50 has conveying passages 51 and 52 for moving the substrate S in the X1-X2 direction. The conveying passages 51 and 52 are arranged in parallel. According to this structure, the conveying unit 50 takes out the substrate S from the substrate supply unit 60, moves the substrate S along the conveying passages 51 and 52 through the temporary crimping station 46a and the actual crimping station 46b to the substrate unloading unit 70, and delivers the substrate S to the substrate unloading unit 70.

[0045] The substrate supply unit 60 takes out and stores the substrate S carried into the transport jig and supplies it to the transport unit 50. The substrate unloading unit 70 stores the substrate S transported by the transport unit 50 in the transport jig.

[0046] use Figure 6 The control system of the flip chip mounter 10 will be described. Figure 6 It is shown Figure 1 A block diagram showing a schematic configuration of a control system of a flip chip mounter.

[0047] The control system 8 includes a control unit (control device) 80, a drive unit 86, a signal unit 87, and an optical system 88. The control unit 80 is generally configured as a computer mainly including a control / calculation device 81 composed of a CPU (Central Processing Unit), a storage device 82, an input / output device 83, a bus 84, and a power supply unit 85. The storage device 82 includes a main storage device 82a and an auxiliary storage device 82b. The main storage device 82a is composed of a RAM (Random Access Memory) storing a processing program, etc. The auxiliary storage device 82b is composed of a HDD (Hard Disk Drive) or SSD (Solid State Drive) storing control data or image data required for control, etc. In addition, an external storage device can be connected to the control unit 80.

[0048] The input / output device 83 includes a monitor 83a for displaying the device status or information of the flip chip mounter 1, a touch panel 83b for inputting the operator's instructions, a mouse 83c for operating the monitor 83a, and an image acquisition device 83d for acquiring image data from the optical system 88. The input / output device 83 also includes a motor control device 83e and an I / O signal control device 83f. The motor control device 83e controls the XY stage (not shown) of the wafer supply unit 10, the pickup head stage, the drive unit of the mounting head stage, the drive unit of the peeling unit 13, etc. The I / O signal control device 83f acquires a signal from the signal unit 87 or controls the signal unit 87. The signal unit 87 includes switches or knobs for controlling the brightness of various sensors or lighting devices. The optical system 88 includes a wafer recognition camera 24, a stage recognition camera 34, and substrate recognition cameras 44a and 44b. The wafer recognition camera 24, the stage recognition camera 34, and the substrate recognition cameras 44a and 44b digitize light intensity or color. The control / calculation device 81 acquires necessary data via the bus 84 and performs calculations to control the pickup head 21 and the like or to send information to the monitor 83a and the like.

[0049] The control unit 80 saves the image data captured by the wafer recognition camera 24, the stage recognition camera 34, and the substrate recognition cameras 44a and 44b to the storage device 82 via the image acquisition device 83d. The control / calculation device 81 is used to perform positioning of the bare chip D and the substrate S and appearance inspection of the bare chip D and the substrate S using software programmed based on the stored image data. Based on the positions of the bare chip D and the substrate S calculated by the control / calculation device 81, the drive unit 86 is driven by the software through the motor control device 83e. According to this process, the bare chip on the wafer is positioned, and the pickup head stage and the placement head stage are operated to place the bare chip D on the substrate S.

[0050] The control unit 80 can be configured by installing the above-mentioned program stored in an external storage device into a computer. The external storage device includes, for example, an HDD, a USB memory, or an SSD. The auxiliary storage device 82b or the external storage device is configured as a recording medium that can be read by a computer. Hereinafter, these are also collectively referred to as recording media. When the term recording medium is used in this specification, there are cases where only the auxiliary storage device 82b is included, only the external storage device is included, or both are included. In addition, providing a program or data to a computer and providing a program or data from a computer to an external device can be performed without using an external storage device, but using communication means such as the Internet and a dedicated line.

[0051] use Figure 7 A part of the manufacturing process of a semiconductor device (a manufacturing method of a semiconductor device) using the flip chip mounter 1 will be described. Figure 7 It shows that the Figure 1 1 is a flowchart of a method for manufacturing a semiconductor device using a flip chip mounter. In the following description, the operation of each component constituting the flip chip mounter 1 is controlled by the control unit 80.

[0052] (Wafer loading process: process S1)

[0053] A wafer cassette (not shown) containing wafer rings WR is loaded into the cassette elevator 11 . A dicing tape DT to which bare chips D separated from the wafer W are attached is attached to the wafer ring WR. The wafer supply unit 10 takes out the wafer ring WR from the wafer cassette filled with the wafer ring WR and carries it into the wafer holding table 12 .

[0054] The wafer W is, for example, a semiconductor wafer, and the bare chip D as the workpiece is a semiconductor chip. On the dicing tape DT, the surface of the bare chip D faces upward, as shown in FIG. Figure 2 As shown, for example, on the surface of a bare chip D, a metal electrode De is provided in an opening between insulating films Di.

[0055] (Substrate loading process: process S2)

[0056] The transport jig storing the substrate S is put into the substrate supply unit 60. The substrate supply unit 60 takes out the substrate S from the transport jig. The taken-out substrate S is transported to the mounting unit 40 via the transport unit 50. On the surface of the substrate S, a metal electrode Se is provided in the opening between the insulating film Si and the insulating film Si (see Fig. 9 ).

[0057] (Picking process: process S3)

[0058] After step S1, the wafer holding table 12 moves in a manner capable of picking up the desired bare chip D from the dicing tape DT. The wafer recognition camera 24 photographs the bare chip D. The bare chip D is positioned and surface inspected based on the image data acquired by photographing. By performing image processing on the image data, the offset (X, Y, θ directions) of the bare chip D on the wafer holding table 12 relative to the bare chip position reference point of the flip chip mounter is calculated and positioned. In addition, with respect to the bare chip position reference point, the specified position of the wafer holding table 12 is maintained as the initial setting of the device in advance. By performing image processing on the image data, the surface inspection of the bare chip D is performed.

[0059] The peeling unit 13 moves upward so that the upper surface of the peeling unit 13 contacts the back surface of the dicing tape DT. Then, the peeling unit 13 adsorbs the dicing tape DT. The pickup head 21 descends while evacuating the collet 22, and lands on the bare chip D to be peeled, adsorbing the bare chip D. The pickup head 21 raises the collet 22 to peel the bare chip D from the dicing tape DT. Thus, the bare chip D is picked up by the pickup head 21.

[0060] The pickup head 21 moves from the pickup position along the X1-X2 direction to above the turning table 31a of the intermediate table 31. The pickup head 21 descends and places the bare chip D held by the collet 22 on the turning table 31a. The turning table 31a rotates 180 degrees, so that the surface (front) on which the metal electrode De of the bare chip D is formed is turned over and faces downward, and the bare chip D is placed on the pickup table 31b.

[0061] The stage recognition camera 34 takes a picture of the bare chip D on the pick-up stage 31b. The bare chip D is positioned and surface inspected based on the image data obtained by the shooting. By performing image processing on the image data, the offset (X, Y, θ directions) of the bare chip D on the pick-up stage 31b relative to the bare chip position reference point of the flip chip mounter is calculated and positioned. In addition, regarding the bare chip position reference point, the specified position of the pick-up stage 31b is maintained as the initial setting of the device in advance. By performing image processing on the image data, the surface inspection of the bare chip D is performed.

[0062] The pickup head 21 that has conveyed the bare chip D to the intermediate stage 31 returns to the wafer holding stage 12. According to the above-mentioned steps, the next bare chip D is peeled off from the dicing tape DT, and thereafter, the bare chips D are peeled off one by one from the dicing tape DT according to the same steps.

[0063] (Mounting process: process S4)

[0064] The conveying unit 50 conveys the substrate S to the temporary crimping table 46a. The substrate recognition camera 44a photographs the substrate S placed on the temporary crimping table 46a. The substrate S is positioned and surface inspected based on the image data obtained by photographing. By performing image processing on the image data, the offset (X, Y, θ directions) of the substrate S relative to the substrate position reference point of the flip chip mounting machine 1 is calculated. In addition, regarding the substrate position reference point, the specified position of the mounting unit 40 is maintained as the initial setting of the device in advance. By performing image processing on the image data, the surface inspection of the substrate S is performed.

[0065] The suction position of the temporary pressing head 41a is corrected according to the deviation of the bare chip D on the intermediate stage 31 calculated in step S3, and the temporary pressing head 41a is lowered and uses the collet 42a to suck the bare chip D. Then, the temporary pressing head 41a rises and picks up the bare chip D from the intermediate stage 31. The temporary pressing head 41a holds the bare chip D with the collet 42a and moves from above the intermediate stage 31 to above the substrate S.

[0066] The plasma irradiator 90 moves below the temporary pressure-bonding head 41a and above the substrate S. The plasma irradiator 90 irradiates plasma to the surface of the bare chip D and the surface of a predetermined portion of the substrate S (plasma treatment) to activate the respective surfaces. Thereafter, the plasma irradiator 90 is moved back.

[0067] The temporary crimping head 41a descends to temporarily crimp the bare chip D held by the collet 42a onto a predetermined portion of the substrate S. Thus, the insulating film Di on the surface of the bare chip D and the insulating film Si on the surface of the substrate S are bonded.

[0068] The board recognition camera 44a captures an image of the bare chip D mounted on the board S. Based on the image data acquired by the capture, an inspection is performed to determine whether the bare chip D is mounted at a desired position (inspection of the relative position of the bare chip D and the board S).

[0069] The temporary pressing head 41a that temporarily presses the bare chip D to the substrate S returns to the intermediate stage 31. According to the above steps, the next bare chip D is picked up from the intermediate stage 31 and temporarily press-bonded to the substrate S. These steps are repeated to temporarily press-bond the bare chips D to all the substrates S.

[0070] The conveying unit 50 conveys the substrate S to the actual crimping table 46b. The heating device 461 heats the substrate S on the actual crimping table 46b. The actual crimping head 41b moves from the retreat position to above the bare chip D temporarily crimped to the substrate S. The actual crimping head 41b descends, and the bare chip D is actually crimped to the substrate S using the collet 42b. By the heating and pressurization, the metal electrode De on the surface of the bare chip D and the metal electrode Se on the surface of the substrate S are bonded. The substrate recognition camera 44b photographs the bare chip D and the substrate S. A surface inspection (confirmation of the crimping state) is performed based on the image data obtained by photographing.

[0071] (Substrate unloading process: process S5)

[0072] The substrate S on which the bare chip D is mounted is transported to the substrate unloading unit 70. The substrate unloading unit 70 stores the substrate S in a transport jig. The transport jig storing the substrate S is unloaded from the flip chip mounting machine 1.

[0073] Next, use Figure 8 The plasma irradiator 90 will be described. Figure 8 It is shown Figure 1 A diagram showing the configuration of a plasma irradiator.

[0074] The plasma irradiator 90 performs remote atmospheric pressure plasma treatment (surface activation treatment) at room temperature. The plasma irradiator 90 is composed of a gas inlet 91, a gas inlet nozzle 92, a plasma generating unit 93, and a nozzle 94, and the plasma generating unit 93 is connected to a high-frequency power supply 95. In this structure, the processing gas is introduced from the gas inlet 91, passes through the inside of the gas inlet nozzle 92 and flows in the direction of the nozzle 94. During the flow, high-frequency electricity is applied in the plasma generating unit 93 by the high-frequency power supply 95 to activate the passing processing gas and generate active species AS of the processing gas. The active species AS generated inside the plasma generating unit 93 are transported to the inside of the nozzle 94 by the gas flow and ejected from the gas supply hole 96 provided in the nozzle 94. A plurality of gas supply holes 96 are respectively provided on the side opposite to the bare chip D (upper side) and the side opposite to the substrate S (lower side). The gas inlet 91 is connected to the supply source of the processing gas via a pipe 101, a valve 102, and a flow controller 103. The pipe 101 , the valve 102 , and the flow rate controller 103 may be included in the plasma irradiator 90 .

[0075] As the material of the gas introduction nozzle 92, a material with low conductivity, generally called an insulator, such as glass, quartz glass, or alumina, is used. However, a portion of the gas introduction nozzle 92 that is not in contact with the electrode in the plasma generation unit 93 may be made of a metal generally called a conductor, such as stainless steel or aluminum (Al). The shape of the gas introduction nozzle 92 is a tube shape in order to introduce gas in the central portion, and its cross section may be circular or rectangular.

[0076] As the processing gas, nitrogen (N) gas can be used, for example. Thus, in the plasma generating unit 93, nitrogen plasma is generated by applying high frequency electricity. The surface activation treatment is performed by irradiating the active species AS emitted by the plasma to the surface of the bare chip D and the substrate S. Surface activation treatment refers to improving chemical reactivity by giving energy to the interatomic bonds of the material, breaking the interatomic bonds and putting them in an unstable state. The processing gas is not limited to nitrogen, and rare gases such as argon (Ar) and helium (He) can also be used.

[0077] use Fig. 9 as well as Fig.10 A method of surface activation treatment of the bare chip D and the substrate S using the plasma irradiator 90 will be described. Fig. 9 as well as Fig.10 It is a diagram for explaining the plasma irradiation method in the first mounting portion.

[0078] like Fig. 9 As shown, the temporary crimping head 41a picks up the bare chip D from the intermediate stage 31 and transports it to the upper side of the placement position of the substrate S. Here, the bare chip D has, for example, a metal electrode De of copper (Cu) or gold (Au) and an insulating film Di of polyimide or the like formed on its surface. The substrate S has, for example, a metal electrode of Cu or Au and an insulating film of polyimide or the like formed on its surface.

[0079] like Fig.10 As shown, the plasma irradiator 90 moves between the bare chip D and the substrate S. The plasma irradiator 90 irradiates the surface of the substrate S with plasma in parallel with the plasma irradiation on the surface of the bare chip D. More specifically, the plasma irradiator 90 irradiates plasma from a plurality of gas supply holes 96 provided at the upper and lower parts of the nozzle 94. The plasma irradiation time is, for example, preferably less than 5 seconds, more preferably about 1 second. Thus, the insulating film Di of the bare chip D and the insulating film Si of the substrate S are activated. Thereafter, the temporary pressing head 41a descends, and the bare chip D is placed and pressed on the substrate S. Thus, the insulating film Di of the bare chip D is bonded to the insulating film Si of the substrate S.

[0080] According to the present embodiment, the bare chip D and the substrate S are irradiated with plasma just before being joined, so that mounting (joining) can be performed without contacting the activated joining surface. In addition, before joining, the joining surface is not easily deactivated. Thus, the joining strength between the bare chip D and the substrate S is improved. In addition, the joining is performed in a state where the joining surface is activated, so that poor joining can be reduced.

[0081] According to the present embodiment, since surface activated bonding can be performed, hybrid bonding (mounting) is possible. Thus, hybrid mounting can achieve narrow pitch of mounting positions, thereby improving integration. In addition, the installation of core particle technology can also be achieved by hybrid mounting. Core particle technology refers to the technology of dividing the CPU, GPU, accelerator, etc. that constitute an integrated circuit into multiple chips according to their functions, and manufacturing these chips separately using the best process and then combining them into one chip and packaging them. In core particle technology, for example, a silicon interposer is used that has a redistribution layer (RDL) having electrodes of Cu and Au and an insulating film of polyimide or the like formed on its surface.

[0082] According to this embodiment, the plasma treatment is performed in the atmosphere, so a vacuum chamber is not required. This can suppress the size increase of the flip chip mounter. This can be achieved by simply adding a plasma irradiator, so it can be achieved by modifying an existing device.

[0083] <Modification>

[0084] Hereinafter, several representative variations of the embodiments are illustrated. In the following description of the variations, the same reference numerals as those in the above-mentioned embodiments may be used for parts having the same configuration and function as those described in the above-mentioned embodiments. Then, the description of this part may be appropriately cited in the above-mentioned embodiments within the scope of technical non-contradiction. In addition, part of the above-mentioned embodiment and all or part of the plurality of variations may be appropriately combined and applied within the scope of technical non-contradiction.

[0085] (First Modification)

[0086] use Fig.11 as well as Fig.12 The plasma irradiation method in the first modification example will be described. Fig.11 as well as Fig.12 It is a diagram for explaining the plasma irradiation method in the first modification.

[0087] In the embodiment, an example is described in which one plasma irradiator 90 irradiates plasma to the bare chip D and the substrate S at the same timing. However, two plasma irradiators may irradiate plasma to the bare chip D and the substrate S at different timings.

[0088] For example, the temporary press-bonding portion 40a includes a first plasma irradiator 90a and a second plasma irradiator 90b. The first plasma irradiator 90a has a gas supply hole 96 only on the side (upper side) opposite to the bare chip D. The second plasma irradiator 90b has a gas supply hole 96 only on the side (lower side) opposite to the substrate S.

[0089] First, if Fig.11 As shown, the first plasma irradiator 90a moves from the retreat position to below the bare chip D. Then, the first plasma irradiator 90a irradiates the surface of the bare chip D with plasma.

[0090] Next, if Fig.12 As shown, the first plasma irradiator 90a moves to the retreat position, and the second plasma irradiator 90b moves between the bare chip D and the substrate S. Then, the second plasma irradiator 90b irradiates plasma to the surface of the substrate S. Thereafter, the second plasma irradiator 90b moves to the retreat position.

[0091] (Second Modification)

[0092] use Fig.13 as well as Fig.14 The plasma irradiation method in the second modification example will be described. Fig.13 as well as Fig.14 It is a diagram for explaining the plasma irradiation method in the second modification.

[0093] In the embodiment, an example is described in which plasma is irradiated to the bare chip D and the substrate S at the same timing by one plasma irradiator 90 , but plasma may be irradiated to the bare chip D and the substrate S at different timings by one plasma irradiator.

[0094] The plasma irradiator 90 has gas supply holes 96 on the side (upper side) opposite to the bare chip D and on the side (lower side) opposite to the substrate S, similarly to the embodiment. Then, the upper gas supply hole 96 and the lower gas supply hole 96 are configured to perform plasma irradiation independently. The surface of the bare chip D may be irradiated with plasma first, or the surface of the substrate S may be irradiated with plasma first.

[0095] First, if Fig.13 As shown, the plasma irradiator 90 moves from the retreat position between the bare chip D and the substrate S. Then, the plasma irradiator 90 irradiates the surface of the bare chip D with plasma.

[0096] Next, if Fig.14 As shown, the plasma irradiator 90 irradiates plasma toward the surface of the substrate S. Thereafter, the plasma irradiator 90 moves to a retreat position.

[0097] In addition, the plasma irradiator 90 may have the gas supply hole 96 only on the side (upper side) opposite to the bare chip D or the side (lower side) opposite to the substrate S, that is, only on one side. Then, the plasma irradiator 90 can be turned over or the direction (irradiation direction) of the gas supply hole 96 can be changed. Fig.13 as well as Fig.14 As shown, plasma can be irradiated to the bare chip D and the substrate S at different timings by one plasma irradiator.

[0098] (Third Modification)

[0099] use Fig.15 (a) Fig.15 (b) Fig.16 (a) and Fig.16 (b) illustrates the mounting process in the third variation. Fig.15 (a) is a diagram showing the positions (initial position, pickup position) of various elements when the first mounting head picks up a bare chip from the intermediate stage. Fig.15 (b) is a diagram showing the positions of various elements (plasma irradiation positions) when the plasma irradiator irradiates plasma onto the bare chip and the substrate. Fig.16 (a) is a diagram showing the positions (mounting positions) of various elements when the first mounting head mounts a bare chip on a substrate. Fig.16 (b) is a diagram showing a state where each element returns to an initial position.

[0100] In the embodiment, an example is described in which the temporary pressing head 41a is horizontally moved and raised and lowered to pick up the bare chip D or place the bare chip D on the substrate S. However, the present invention is not limited thereto. For example, after the temporary pressing head 41a is moved onto the intermediate stage 31, only the raising and lowering action is performed to move the wafer holding stage 12, the intermediate stage 31, the temporary pressing stage 46a, and the plasma irradiator 90.

[0101] like Fig.15 As shown in (a), the wafer holding stage 12, the intermediate stage 31, the temporary pressure bonding stage 46a, the first plasma irradiator 90a and the second plasma irradiator 90b are arranged along the Y1-Y2 direction and can move along the Y1-Y2 direction.

[0102] After the bare chip D is picked up by the temporary press head 41a, Fig.15 As shown by the arrow in (a), the wafer holding stage 12, the intermediate stage 31, the temporary pressing stage 46a, the first plasma irradiator 90a and the second plasma irradiator 90b move in the Y2 direction. Fig.15The position shown in (b) is provided with the wafer holding stage 12, the intermediate stage 31, the temporary pressing stage 46a, the first plasma irradiator 90a and the second plasma irradiator 90b. In this state, the first plasma irradiator 90a and the second plasma irradiator 90b irradiate the bare chip D and the substrate S with plasma.

[0103] After the plasma irradiation, the wafer holding stage 12, the intermediate stage 31, the temporary pressing stage 46a and the first plasma irradiator 90a move in the Y2 direction. The second plasma irradiator 90b moves in the Y1 direction. Then, Fig.16 The temporary pressure bonding stage 46a, the first plasma irradiator 90a, and the second plasma irradiator 90b are arranged at the position shown in (a). In this state, the temporary pressure bonding head 41a bonds the bare chip D to the substrate S.

[0104] After mounting, the wafer holding stage 12, the intermediate stage 31, the temporary pressing stage 46a and the first plasma irradiator 90a move in the Y1 direction. Fig.16 The position shown in (b) is where the wafer holding stage 12, the intermediate stage 31, the temporary pressure bonding stage 46a, the first plasma irradiator 90a, and the second plasma irradiator 90b are arranged.

[0105] As mentioned above, the disclosure proposed by the inventor of the present disclosure has been specifically described based on the embodiment and the modified example, but the present disclosure is not limited to the above-mentioned embodiment and the modified example, and various changes can be made, of course.

[0106] In the embodiment, an example in which the actual pressure-bonding portion 40 b is provided in the mounting portion 40 has been described, but the actual pressure-bonding portion 40 b may be provided outside the flip chip mounting machine 1 .

[0107] In the embodiment, an example in which the reversing mechanism is provided on the intermediate stage has been described. However, the reversing mechanism may be provided on the pickup reversing head, and the bare chip may be received from the pickup reversing head by the transfer head and placed on the intermediate stage.

[0108] Furthermore, in the embodiment, an example has been described in which there is one intermediate stage unit and one mounting unit, but there may be a plurality of each.

[0109] Furthermore, in the embodiment, an example in which a single placement head is used has been described, but a plurality of placement heads may be used.

Claims

1. A chip mounting device, characterized in that: have: A first placement head that picks up the bare die; a first mounting stage for holding a substrate; and A plasma irradiator irradiates plasma to the surface of the bare chip picked up by the first mounting head and the surface of the substrate held by the first mounting stage.

2. The chip mounting device according to claim 1, characterized in that: The plasma irradiator has a gas supply hole for ejecting plasma upward and a gas supply hole for ejecting plasma downward.

3. The chip mounting device according to claim 2, characterized in that: The invention further includes a control device configured to perform upward plasma irradiation and downward plasma irradiation in parallel using the plasma irradiator.

4. The chip mounting device according to claim 2, characterized in that: The invention further includes a control device configured to cause the plasma irradiator to perform upward plasma irradiation and downward plasma irradiation at different timings.

5. The chip mounting device according to claim 1, characterized in that: The plasma irradiator has a gas supply hole for ejecting plasma in one direction. The die mounting device further includes a control device configured to direct the gas supply holes upward and irradiate plasma, and then direct the gas supply holes downward and irradiate plasma.

6. The chip mounting device according to claim 1, characterized in that: The plasma irradiator includes a first plasma irradiator having a gas supply hole for ejecting plasma upward, and a second plasma irradiator having a gas supply hole for ejecting plasma downward.

7. The chip mounting device according to claim 6, characterized in that: The device further includes a control device configured to perform plasma irradiation upward by the first plasma irradiator and plasma irradiation downward by the second plasma irradiator in parallel.

8. The chip mounting device according to claim 6, characterized in that: The device further includes a control device configured to perform plasma irradiation upward by the first plasma irradiator and plasma irradiation downward by the second plasma irradiator at different timings.

9. The chip mounting device according to claim 1, characterized in that: Also available: a second mounting head for applying pressure to the bare chip placed on the substrate; and The second mounting station includes a heating device for heating the substrate on which the bare chip is mounted.

10. An installation method, characterized in that: have: The process of picking up workpieces; A process for maintaining a substrate; a step of irradiating the surface of the picked-up workpiece and the surface of the held substrate with plasma; and The step of attaching the plasma-irradiated workpiece to the plasma-irradiated substrate.

11. A method for manufacturing a semiconductor device, characterized in that: Includes the installation method of claim 10.

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