Semiconductor chip welding method and device
Through thermal field scanning and pulsed reflow heating treatment, combined with real-time melt state detection, atmosphere switching and dynamic cooling, the problem of 'non-complete reflow' of solder joints in multi-layer stacked packaging is solved, and the welding quality and packaging reliability are improved.
Patent Information
- Application Number
- CN202510173105.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-17
- Publication Date
- 2025-03-18
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
The existing multi-layer stacked packaging reflow soldering process is difficult to accurately perform melt monitoring and partitioning temperature control for different chip layers, resulting in "non-complete reflow" of local solder joints and subsequent failure.
By performing thermal field scanning on the multi-layer stacked package, a thermal field partition diagram is generated, pulse reflux heating is used, and the melting state of the solder joint is monitored in real time, atmosphere switching and local reheating are performed, and the cooling rate of the solder joint is finally controlled through dynamic cooling.
The fine control of solder joints of multi-layer stacked packaging is achieved, which reduces micro voids and stress concentration, and improves welding quality and packaging reliability.