Electronic package and fabrication method thereof

Abstract

The invention relates to an electronic package and a manufacturing method thereof, which comprises the following steps: configuring an electronic component on a substrate, coating the electronic component with a packaging layer, embedding a frame body protruding out of the substrate in the packaging layer, and dispersing thermal stress through the frame body so as to prevent the electronic package from warping.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, in particular to an anti-warping electronic package and a manufacturing method thereof. Background Art

[0002] Flip-Chip semiconductor package is a packaging structure that uses flip chip method for electrical connection. It connects the active surface of the chip to the substrate through a plurality of solder bumps, and a plurality of solder balls that can be used as input / output (I / O) terminals are planted on the other surface of the substrate. This design can not only greatly reduce the package size and make the ratio of chip to substrate closer, but also eliminate the existing wire design to reduce impedance and improve electrical properties, thus avoiding signal distortion during transmission. Therefore, it has become the mainstream packaging technology for the next generation of chips.

[0003] However, when highly integrated semiconductor chips are in operation, a large amount of heat is generated. The packaging colloid covering the semiconductor chip is actually a poor heat transfer material with a thermal conductivity of only 0.8W / mk. If the heat generated by the semiconductor chip cannot be effectively dissipated, it will cause damage to the semiconductor chip and product reliability issues. Therefore, in order to improve the heat dissipation efficiency of semiconductor packages, the idea of ​​adding heat sinks to the packages came into being.

[0004] like Figure 1 As shown, in the conventional method of manufacturing a flip-chip semiconductor package 1 with integrated heat sink, a semiconductor chip 11 is firstly placed on a package substrate 10 with its active surface 11a by means of flip-chip bonding (i.e., through conductive bumps 110 and primer 111). Then, a heat sink 13 is directly placed on the inactive surface 11b of the semiconductor chip 11 via a thermal interface material (TIM) layer 12, without adhering the heat sink 13 to the package substrate 10. Thus, the conductive bumps 110 that electrically connect the semiconductor chip 11 and the package substrate 10 are not subjected to the thermal stress generated by the difference in thermal expansion coefficients between the heat sink 13 and the package substrate 10, thereby avoiding the problem of cracking.

[0005] However, in this type of semiconductor package, there is no effective solution to the problem of substrate warping. In fact, when corresponding to a semiconductor package with a large chip size, it will be extremely sensitive to the problem of substrate warping. In the case of a large chip size, as long as the substrate has a slight warping problem, the solder bumps on the edge of the flip-chip chip will not be easy to adhere to the substrate, resulting in problems such as electrical connection failure.

[0006] Therefore, how to provide a flip-chip semiconductor package that does not cause warping and can effectively provide ball flatness is a problem that the industry is eager to solve. Summary of the invention

[0007] In view of the various deficiencies of the above-mentioned prior art, the present invention provides an electronic package, comprising: a substrate; an electronic component, which is disposed on the substrate and electrically connected to the substrate; a packaging layer, which is formed on the substrate to cover the electronic component; and a frame, which is embedded in the packaging layer and protrudes out of the substrate.

[0008] The present invention also provides a method for manufacturing an electronic package, comprising: providing a substrate; arranging electronic components and a frame on the substrate, wherein the frame is configured to protrude outside the substrate; and forming a packaging layer on the substrate so that the packaging layer covers the electronic components and the frame.

[0009] The aforementioned electronic package and its manufacturing method further include providing a supporting structure to place a plurality of the substrates on the supporting structure. After forming the packaging layer, each of the substrates is singulated and the supporting structure is removed.

[0010] In the aforementioned electronic package and its manufacturing method, a support member having a plurality of openings is disposed on the bearing structure, and a plurality of substrates are disposed in the plurality of openings respectively.

[0011] In the aforementioned electronic package and its manufacturing method, the packaging layer covers the side surface of the substrate.

[0012] In the aforementioned electronic package and its manufacturing method, the frame is annular and surrounds the outer periphery of the electronic component.

[0013] In the aforementioned electronic package and its manufacturing method, the frame is distributed on the outside of the electronic component in a discontinuous manner.

[0014] In the aforementioned electronic package and its manufacturing method, the frame includes a main body and a bending portion, wherein the main body extends from the inside of the substrate to the outside of the substrate, and the bending portion is connected to one end of the main body protruding from the substrate and is perpendicular to the main body.

[0015] In the aforementioned electronic package and its manufacturing method, the bent portion of the frame is opposite to the side surface of the substrate.

[0016] In the aforementioned electronic package and its manufacturing method, the frame is partially exposed outside the packaging layer.

[0017] In the aforementioned electronic package and its manufacturing method, the electronic component is partially exposed from the packaging layer.

[0018] In the aforementioned electronic package and its manufacturing method, the frame does not contact the substrate.

[0019] The aforementioned electronic package and its manufacturing method further include forming a shielding layer on the packaging layer.

[0020] In the aforementioned electronic package and its manufacturing method, the frame is made of metal material or semiconductor material.

[0021] In the aforementioned electronic package and its manufacturing method, the frame is suspended below the portion protruding from the side surface of the substrate.

[0022] From the above, it can be seen that in the electronic package and its manufacturing method of the present invention, thermal stress is mainly dispersed by the frame, so as to avoid the packaging layer from warping during thermal cycles, and by setting the frame to protrude from the substrate, it is convenient to arrange other electronic components around the electronic component, without increasing the size of the substrate, thereby reducing the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The figure is a cross-sectional schematic diagram of a conventional heat dissipation type semiconductor package.

[0024] FIG. 2A to FIG. 2D It is a cross-sectional schematic diagram of the method for manufacturing the electronic package of the present invention.

[0025] Figure 3A for Figure 2D Schematic diagram of the cross-section viewed from above.

[0026] Figure 3B and Figure 3C for Figure 3A Schematic diagrams of other embodiments.

[0027] Figure 4 FIG. 4 is a cross-sectional schematic diagram of an electronic package according to another embodiment of the present invention.

[0028] FIG. 5A to FIG. 5C FIG. 4 is a cross-sectional schematic diagram of an electronic package according to yet another embodiment of the present invention.

[0029] Figure 5A-1 for Figure 5A Schematic diagram of the cross-section viewed from above.

[0030] Fig. 6A and Figure 6B FIG. 4 is a cross-sectional schematic diagram of an electronic package according to yet another embodiment of the present invention.

[0031] Figure 7 FIG. 4 is a cross-sectional schematic diagram of an electronic package according to yet another embodiment of the present invention.

[0032] Figure 8 FIG. 4 is a cross-sectional schematic diagram of an electronic package according to yet another embodiment of the present invention.

[0033] Main component symbols

[0034] 1 Semiconductor Package

[0035] 10 Package substrate

[0036] 11. Semiconductor Chip

[0037] 11a Action surface

[0038] 11b Non-active surface

[0039] 110 Conductive bump

[0040] 111 Primer

[0041] 12 TIM layer

[0042] 13 Heat sink

[0043] 2,2a,2b,2c,2d,2e,2f,2g,2h electronic packaging

[0044] 20 substrate

[0045] 20a First side

[0046] 20b Second side

[0047] 20c Side

[0048] 21 Electronic components

[0049] 21a Action surface

[0050] 21b Non-active surface

[0051] 210 Conductive bump

[0052] 211 Primer

[0053] 22,22a,22b,22c,22d,22e,22f,22g,22h frame

[0054] 221 Main body

[0055] 222 Bending part

[0056] 23 Adhesive layer

[0057] 24 Encapsulation layer

[0058] 24a First surface

[0059] 24b Second surface

[0060] 24c Side

[0061] 25 Conductive element

[0062] 26 Shielding layer

[0063] 30 Load-bearing structure

[0064] 30a First side

[0065] 30b Second side

[0066] 31 Support

[0067] 310 Opening

[0068] S,L Cutting path. DETAILED DESCRIPTION

[0069] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0070] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any modification of the structure, change in the proportion relationship, or adjustment of the size should still fall within the scope of the technical contents disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "one", "first", and "second" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0071] FIG. 2A to FIG. 2D It is a cross-sectional schematic diagram of a method for manufacturing an electronic package 2 of the present invention.

[0072] like Figure 2A As shown, a supporting structure 30 having a first side 30a and a second side 30b opposite to each other is provided. A supporting member 31 having a plurality of openings 310 is disposed on the first side 30a of the supporting structure 30, so that substrates 20 are disposed in the openings 310 of the supporting member 31. In this embodiment, two substrates 20 are respectively disposed in adjacent openings 310, but the present invention is not limited thereto.

[0073] The supporting structure 30 may be a temporary supporting board, which may include, for example, a supporting board formed by an organic polymer board or a copper foil substrate, but the present invention is not limited to the above.

[0074] The substrate 20 may be a package substrate (substrate) having a core layer and a circuit portion or a circuit structure without a core layer (coreless). In the present embodiment, the substrate 20 includes at least one dielectric layer and a circuit layer combined with the dielectric layer, such as a fan-out type redistribution layer (RDL) specification. The substrate 20 has a first side 20a and a second side 20b opposite to each other, wherein the second side 20b of the substrate 20 is joined to the first side 30a of the supporting structure 30.

[0075] It should be understood that the substrate 20 may also be other carrier units for carrying chips, such as a leadframe, a wafer, a silicon interposer, or other boards with metal routing, etc., and is not limited to the above.

[0076] like Figure 2B As shown, at least one electronic component 21 is disposed on the first side 20 a of the substrate 20 through a plurality of conductive bumps 210 , and a coating layer such as a primer 211 is filled and formed between the first side 20 a of the substrate 20 and the electronic component 21 to cover the conductive bumps 210 .

[0077] The electronic component 21 is an active component, a passive component or a combination of the two, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. In this embodiment, the electronic component 21 is a semiconductor chip, which has an active surface 21a and an inactive surface 21b opposite to each other, and the active surface 21a has a plurality of electrode pads (not shown), so that the electrode pads are combined and electrically connected to the circuit layer of the substrate 20 in a flip chip manner through a plurality of conductive bumps 210 such as solder materials.

[0078] In other embodiments, the electronic component 21 may be electrically connected to the circuit layer of the substrate 20 by bonding multiple wires; or, the electronic component 21 may directly contact the circuit layer of the substrate 20. It should be understood that there are many ways to electrically connect the electronic component 21 to the substrate 20, and the required type and number of electronic components 21 may be placed on the substrate 20, which are not limited to the above.

[0079] Furthermore, the frame 22 is disposed on the first side 20 a of the substrate 20 and protrudes out of the side edge of the substrate 20 .

[0080] The frame 22 is a metal frame such as copper or a semiconductor frame such as silicon or glass, and can be bonded to the substrate 20 via an adhesive layer 23 such as adhesive. In this embodiment, the frame 22 is flat and is disposed parallel to the first side 20a of the substrate 20 and extends outward to protrude outside the substrate 20.

[0081] like Figure 2C As shown, a packaging layer 24 is formed on the first side 30 a of the supporting structure 30 , so that the packaging layer 24 covers the support member 31 , the substrate 20 , the electronic component 21 and the frame 22 .

[0082] The packaging layer 24 has a first surface 24a and a second surface 24b opposite to each other. In this embodiment, the first surface 24a of the packaging layer 24 is higher than the inactive surface 21b of the electronic component 21 and completely covers the electronic component 21, and the second surface 24b of the packaging layer 24 is flush with the first side 30a of the supporting structure 30 and the second side 20b of the substrate 20.

[0083] In this embodiment, the encapsulation layer 24 is an insulating material, such as polyimide (PI), dry film, encapsulation colloid or molding compound such as epoxy. For example, the encapsulation layer 24 can be formed on the first side 30a of the supporting structure 30 by a process such as liquid compound, injection, lamination or compression molding.

[0084] like Figure 2D As shown, each substrate 20 is subjected to a singulation process. In this embodiment, according to the cutting path S (such as Figure 2C As shown in FIG. 4 , the encapsulation layer 24 is cut to define a side surface 24c adjacent to the first surface 24a and the second surface 24b.

[0085] In this embodiment, the cutting path S is set to make the side surface 24c of the packaging layer 24 located outside the side surface 20c of the substrate 20. In other words, the packaging layer 24 surrounds the side surface 20c of the substrate 20. Furthermore, in this embodiment, the frame 22 protrudes from the side surface 20c of the substrate 20, but is not exposed from the side surface 24c of the packaging layer 24.

[0086] In addition, in this embodiment, if Figure 3A As shown, the frame 22 may be formed in a ring shape and continuously surround the outer periphery of the electronic component 21. Alternatively, in other embodiments, the frame 22 may also be distributed on the outer side of the electronic component 21 in a discontinuous manner, for example, Figure 3BAs shown, the frame 22 can be symmetrically formed on two opposite sides of the electronic component 21 and not connected to each other, or as shown in FIG. Figure 3C As shown, the frame 22 may surround the outer periphery of the electronic component 21 but be interrupted in the middle. In addition, the packaging layer 24 may be formed between the electronic component 21 and the frame 22 and on the outer periphery of the frame 22.

[0087] In addition, after removing the supporting structure 30, a plurality of conductive elements 25 such as metal pillars such as copper pillars, metal bumps coated with insulating blocks, solder balls, solder balls with core copper balls (Cu core balls) or other conductive structures can be set on the second side 20b of the substrate 20 to obtain the electronic package 2 of the present invention.

[0088] Based on the above, the manufacturing method of the present invention mainly disperses thermal stress through the design of the frame 22, thereby avoiding warping during thermal cycles. Furthermore, since the frame 22 is configured to protrude from the substrate 20, it is convenient to arrange other electronic components around the electronic component 21 without increasing the size of the substrate 20, thereby reducing the manufacturing cost.

[0089] In the following, various embodiments of the electronic package 2 of the present invention will be described in more detail. The components of the electronic packages 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h of different embodiments that are identical or corresponding to the electronic package 2 are denoted by the same or corresponding element symbols, and the description of the identical parts is omitted.

[0090] first, Figure 4 A cross-sectional schematic diagram showing an electronic package 2a of the present invention is shown as follows: Figure 4 As shown, in the electronic package 2a, the longitudinal section of the frame 22a can be formed into an L-shape, and includes a main body 221 and a bent portion 222. The main body 221 is provided on the substrate 20 through the adhesive layer 23 and extends outside the substrate 20, and the bent portion 222 is connected to an end of the main body 221 protruding from the substrate 20 and is perpendicular to the main body 221, so that the bent portion 222 is parallel to the side 20c of the substrate 20 and faces the side 20c of the substrate 20. By forming the frame 22a into an L-shape, thermal stress can be better dispersed, and warping can be avoided during thermal cycles.

[0091] Furthermore, FIG. 5A to FIG. 5C The cross-sectional schematic diagrams of the electronic packages 2b, 2c, and 2d of the present invention are shown as follows: FIG. 5A to FIG. 5CAs shown in FIG. 2 , in the electronic package 2b, 2c, 2d, the frame 22b, 22c, 22d may be partially exposed from the packaging layer 24. Specifically, the frame 22b may be extended in the lateral direction to be exposed from the side 24c of the packaging layer 24, or even the frame 22b may be suspended below the portion protruding from the side 20c of the substrate 20 without the packaging layer 24 (e.g., Figure 5A or the height of the frame 22c in the vertical direction may be increased so that it is exposed on the first surface 24a of the packaging layer 24 (as shown); Figure 5B or when the frame 22d is L-shaped, the length of the bent portion 222 of the frame 22d can be increased and extended downward to the second surface 24b (such as the second surface 24b) of the packaging layer 24 exposed. Figure 5C By partially exposing the packaging layer 24 to the surface of the frames 22b, 22c, and 22d, thermal cycling can be better promoted.

[0092] In addition, in addition to changing the shape and size of the frame 22b, 22c, 22d, the frame 22b, 22c, 22d can also be exposed to the packaging layer 24 by changing the cutting path of the singulation process. For example, if the cutting is performed using the cutting path L so that the cutting path passes through the frame 22b, the frame 22b can be exposed without changing the shape and size of the frame 22b. It should be understood that the cutting path of the singulation process can be set according to demand and is not particularly limited.

[0093] in addition, Figure 5A-1 for Figure 5A The top cross-sectional diagram of Figure 5A-1 As shown, the frame 22b can be symmetrically formed on opposite sides of the electronic component 21, and a portion of the surface of the frame 22b is exposed on the side 24c of the packaging layer 24. However, the present invention is not limited thereto, and the frame 22b can also be formed as a continuous or discontinuous ring, or its shape or size can be changed as required.

[0094] in addition, Fig. 6A and Figure 6B The cross-sectional schematic diagrams of the electronic packages 2e and 2f of the present invention are shown as follows: Fig. 6A and Figure 6B As shown, in the electronic package 2e, 2f, the frame 22e, 22f may not contact the substrate 20, and may not be bonded to the substrate 20, and the packaging layer 24 is formed between the substrate 20 and the frame 22e, 22f.

[0095] In order to produce such a structure, the Figure 2BIn the steps shown in the figure, the frame 22e, 22f is not directly placed on the substrate 20. For example, the flat frame 22e can be placed on the support member 31 so that it extends above the substrate 20 but does not contact the substrate 20, so that after forming the packaging layer 24 and performing the singulation process, the electronic package 2e (such as Fig. 6A Alternatively, the L-shaped frame 22f can be placed between the support member 31 and the substrate 20 by using the bent portion 222, and the main body 221 of the frame 22f can be extended above the substrate 20 but not in contact with the substrate 20, so that the electronic package 2f (as shown) can be obtained after the packaging layer 24 is formed and the singulation process is performed. Figure 6B As shown). It should be understood that the above manufacturing method is only an exemplary embodiment for illustration, and different methods can also be used to manufacture the electronic packages 2e, 2f.

[0096] in addition, Figure 7 A cross-sectional schematic diagram showing an electronic package 2g of the present invention is shown as follows: Figure 7 As shown, in the electronic package 2g, the inactive surface 21b of the electronic component 21 is exposed on the first surface 24a of the packaging layer 24. To this end, a flattening process can be performed, such as removing part of the material of the packaging layer 24 (even part of the material of the inactive surface 21b of the electronic component 21) by grinding, so that the first surface 24a of the packaging layer 24 is flush with the inactive surface 21b of the electronic component 21, so that the inactive surface 21b of the electronic component 21 is exposed on the first surface 24a of the packaging layer 24. In this way, the heat dissipation performance of the electronic component 21 itself can be improved, which helps to improve the thermal cycle.

[0097] also, Figure 7 The frame 22g of the electronic package 2g is shown to be exposed on the side 24c of the packaging layer 24, but the present invention is not limited to this. The frame 22g may also be exposed on the first surface 24a or the second surface 24b of the packaging layer 24, or the frame 22g may not be exposed on the packaging layer 24.

[0098] in addition, Figure 8 A cross-sectional schematic diagram showing an electronic package 2h of the present invention is shown as follows: Figure 8 As shown, in the electronic package 2h, based on Figure 7In the electronic package 2g, after the singulation process, a shielding layer 26 is formed on the side 24c and the first surface 24a of the packaging layer 24, so that the shielding layer 26 contacts the frame 22h at the side 24c of the packaging layer 24, and contacts the electronic component 21 at the first surface 24a of the packaging layer 24. In addition, when the shielding layer 26 is formed based on other embodiments, the shielding layer 26 may also contact the frame 22h at the first surface 24a or the second surface 24b of the packaging layer 24, or may not contact the frame 22h. It should be understood that the shielding layer 26 may contact or not contact the electronic component 21 as required, without particular limitation.

[0099] Therefore, in the manufacturing method of the present invention, the shielding layer 26 is mainly designed to prevent the electronic component 21 from being affected by electromagnetic interference (EMI).

[0100] The present invention also provides an electronic package 2, 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, including: a substrate 20, an electronic component 21, a packaging layer 24 and a frame 22, 22a, 22b, 22c, 22d, 22e, 22f, 22g, 22h.

[0101] The electronic component 21 is disposed on the substrate 20 and electrically connected to the substrate 20 .

[0102] The packaging layer 24 is formed on the substrate 20 to cover the electronic component 21, wherein the packaging layer 24 has a first surface 24a and a second surface 24b opposite to each other and a side surface 24c adjacent to the first surface 24a and the second surface 24b, and the second surface 24b of the packaging layer 24 is flush with the second side 20b of the substrate 20.

[0103] The frames 22 , 22 a , 22 b , 22 c , 22 d , 22 e , 22 f , 22 g , and 22 h are embedded in the packaging layer 24 , and the frames 22 , 22 a , 22 b , 22 c , 22 d , 22 e , 22 f , 22 g , and 22 h protrude from the substrate 20 .

[0104] In one embodiment, the packaging layer 24 covers the side surface 20 c of the substrate 20 .

[0105] In one embodiment, the frame 22 is annular and surrounds the outer circumference of the electronic component 21 .

[0106] In one embodiment, the frame 22 is distributed on the outer side of the electronic component 21 in a discontinuous manner.

[0107] In one embodiment, the frame 22a, 22d, 22f includes a main body 221 and a bending portion 222, wherein the main body 221 extends from the inner side of the substrate 20 to the outer side of the substrate 20, and the bending portion 222 is connected to one end of the main body 221 protruding from the substrate 20 and is perpendicular to the main body 221.

[0108] In one embodiment, the bent portion 222 of the frame 22 a , 22 d , 22 f is opposite to the side surface 20 c of the substrate 20 .

[0109] In one embodiment, the frames 22 b , 22 c , 22 d , 22 e , 22 f , and 22 g are partially exposed from the packaging layer 24 .

[0110] In one embodiment, the electronic component 21 is partially exposed from the packaging layer 24 .

[0111] In one embodiment, the frames 22e, 22f do not contact the substrate.

[0112] In one embodiment, the electronic package 2 h further includes a shielding layer 26 formed on the packaging layer 24 .

[0113] In one embodiment, the frames 22 , 22 a , 22 b , 22 c , 22 d , 22 e , 22 f , 22 g , and 22 h are made of metal material or semiconductor material.

[0114] In summary, the electronic package and the manufacturing method thereof of the present invention can disperse the thermal stress in the electronic package through the design of the frame, thereby preventing the packaging layer from warping during thermal cycles.

[0115] Furthermore, since the frame is configured to protrude from the substrate, the frame only occupies a small portion of the outer space of the substrate, which is conducive to arranging other electronic components around the electronic component without increasing the size of the substrate, thereby reducing the manufacturing cost.

[0116] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. An electronic package, comprising: substrate; an electronic component disposed on the substrate and electrically connected to the substrate; A packaging layer formed on the substrate to cover the electronic component; as well as The frame is embedded in the packaging layer and protrudes out of the substrate.

2. The electronic package of claim 1, wherein: The packaging layer covers the side surface of the substrate.

3. The electronic package of claim 1, wherein: The frame is annular and surrounds the outer periphery of the electronic component.

4. The electronic package of claim 1, wherein: The frame is distributed on the outer side of the electronic component in a discontinuous manner.

5. The electronic package of claim 1, wherein: The frame includes a main body and a bending portion, wherein the main body extends from the inner side of the substrate to the outer side of the substrate, and the bending portion is connected to one end of the main body protruding from the substrate and is perpendicular to the main body.

6. The electronic package of claim 5, wherein: The bent portion of the frame is opposite to the side surface of the substrate.

7. The electronic package of claim 1, wherein: The frame is partially exposed from the packaging layer.

8. The electronic package of claim 1, wherein: The electronic component is partially exposed from the packaging layer.

9. The electronic package of claim 1, wherein: The frame does not contact the substrate.

10. The electronic package of claim 1, wherein: The electronic package also includes a shielding layer formed on the packaging layer.

11. The electronic package of claim 1, wherein: The frame is made of metal material or semiconductor material.

12. The electronic package of claim 1, wherein: The frame is suspended below a portion protruding from the side surface of the substrate.

13. A method for manufacturing an electronic package, comprising: providing a substrate; An electronic component and a frame are arranged on the substrate, wherein the frame is configured to protrude out of the substrate; as well as A packaging layer is formed on the substrate so that the packaging layer covers the electronic element and the frame.

14. The method for manufacturing an electronic package according to claim 13, wherein: The manufacturing method further comprises providing a carrying structure to place a plurality of the substrates on the carrying structure, and after forming the packaging layer, performing a singulation process on each of the substrates, and removing the carrying structure.

15. The method for manufacturing an electronic package according to claim 14, wherein: A supporting member with a plurality of openings is arranged on the bearing structure so that a plurality of substrates are arranged in the plurality of openings respectively.

16. The method for manufacturing an electronic package according to claim 13, wherein: The packaging layer covers the side surface of the substrate.

17. The method for manufacturing an electronic package according to claim 13, wherein: The frame is annular and surrounds the outer periphery of the electronic component.

18. The method for manufacturing an electronic package according to claim 13, wherein: The frame is distributed on the outer side of the electronic component in a discontinuous manner.

19. The method for manufacturing an electronic package according to claim 13, wherein: The frame includes a main body and a bending portion, wherein the main body extends from the inner side of the substrate to the outer side of the substrate, and the bending portion is connected to one end of the main body protruding from the substrate and is perpendicular to the main body.

20. The method for manufacturing an electronic package according to claim 19, wherein: The bent portion of the frame is opposite to the side surface of the substrate.

21. The method for manufacturing an electronic package as claimed in claim 13, wherein: The frame is partially exposed from the packaging layer.

22. The method for manufacturing an electronic package according to claim 13, wherein: The electronic component is partially exposed from the packaging layer.

23. The method for manufacturing an electronic package according to claim 13, wherein: The frame does not contact the substrate.

24. The method for manufacturing an electronic package as claimed in claim 13, wherein: The manufacturing method also includes forming a shielding layer on the packaging layer.

25. The method for manufacturing an electronic package as claimed in claim 13, wherein: The frame is made of metal material or semiconductor material.

26. The method for manufacturing an electronic package as claimed in claim 13, wherein: The frame is suspended below a portion protruding from the side surface of the substrate.

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