Method for extracting carrier concentration and thickness through horizontal asymmetric double Schottky junction CV test

Abstract

The invention provides a method for extracting carrier concentration and thickness through a horizontal asymmetric double Schottky junction CV test, and belongs to the technical field of detection methods. The invention provides a method for extracting carrier concentration and thickness through a horizontal asymmetric double Schottky junction CV test. The method comprises the following steps: constructing an equivalent circuit model of a horizontal asymmetric Schottky junction; preparing electrodes with different areas on a semiconductor epitaxial wafer conforming to the model to form a horizontal asymmetric Schottky junction, and testing to obtain a barrier capacitance C-V curve; and fitting a barrier capacitance C-V curve according to the equivalent circuit diagram model to obtain the carrier concentration and thickness. According to the invention, the electrical information and the thickness information of the insulating or semi-insulating epitaxial material grown on the conductive substrate can be determined, and the problems of influence of the conductivity of the substrate on a test result and difficulty in preparation of an ohmic electrode are effectively avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of detection methods, and in particular to a method for extracting carrier concentration and thickness through horizontal asymmetric double Schottky junction CV testing. Background Art

[0002] In recent years, gallium oxide has attracted great attention from research institutions and enterprises around the world in the fields of power electronic devices and new generation deep ultraviolet optoelectronic devices due to its excellent material performance indicators such as "ultra-wide bandgap", "high breakdown field strength" and "large-size wafer substrate". Looking at the structure of the semiconductor industry chain, the development of emerging industries is inseparable from the continuous research and development of materials and devices.

[0003] Among them, the key link to realize the application of Ga2O3 semiconductor devices in various fields is to prepare Ga2O3 epitaxial thin film materials with high crystal quality and precisely controllable electrical properties according to the device structure requirements. Therefore, it is very necessary to effectively characterize the thickness, carrier concentration and other information of Ga2O3 epitaxial thin films. Usually, the electrical properties of epitaxial films can be obtained through Hall tests or traditional CV tests, but it is difficult to directly obtain relevant information through Hall tests for insulating epitaxial thin film materials on conductive substrates. On the one hand, it is difficult to form a stable and reliable ohmic contact on the surface of gallium oxide; on the other hand, the film thickness is usually much smaller than the substrate. At this time, the conductivity of the substrate will exceed the conductivity of the film. In this case, measuring the Hall effect of thin film semiconductor materials requires a complex formula to eliminate the influence of the conductive substrate, and it is difficult to obtain effective and reliable electrical properties. Summary of the invention

[0004] In view of this, the object of the present invention is to provide a method for extracting carrier concentration and thickness through horizontal asymmetric double Schottky junction CV testing. The method of the present invention can clearly define the electrical information and thickness information of insulating or semi-insulating epitaxial materials grown on a conductive substrate, effectively avoiding the influence of substrate conductivity on the test results and the problem that ohmic electrodes are difficult to prepare.

[0005] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0006] The present invention provides a method for extracting carrier concentration and thickness through horizontal asymmetric double Schottky junction CV test, comprising the following steps:

[0007] Construct an equivalent circuit model of a horizontal asymmetric Schottky junction;

[0008] Electrodes of different sizes are prepared on semiconductor epitaxial wafers that meet the model to form a horizontal asymmetric Schottky junction, and the barrier capacitance CV curve is obtained by testing;

[0009] The barrier capacitance CV curve is fitted according to the equivalent circuit diagram model to obtain the carrier concentration and thickness, wherein the thickness refers to the thickness of the upper insulating or semi-insulating epitaxial layer on the semiconductor epitaxial wafer that conforms to the model.

[0010] Preferably, the equivalent circuit model of the horizontal asymmetric Schottky junction includes an upper insulating or semi-insulating epitaxial layer, a lower conductive semiconductor substrate layer, an asymmetric Schottky contact electrode and a depletion layer, wherein the asymmetric Schottky contact electrode is arranged on the surface of the upper insulating or semi-insulating epitaxial layer, and the depletion layer is arranged below the asymmetric Schottky contact electrode.

[0011] Preferably, the semiconductor epitaxial wafer conforming to the model is composed of an epitaxial insulating or semi-insulating material and a conductive substrate.

[0012] Preferably, the semiconductor epitaxial wafer conforming to the model comprises a conductive substrate and an insulating or semi-insulating layer formed by oxygen annealing the conductive substrate, wherein the temperature of the oxygen annealing is 800 to 1500° C. and the time is 0.5 to 72 hours.

[0013] Preferably, the barrier capacitance CV curve is obtained based on a horizontal asymmetric double Schottky junction CV test of a semiconductor epitaxial wafer that conforms to the model.

[0014] Preferably, the area ratio of the horizontal asymmetric Schottky junction is S S / S L <0.1, S S is the area of ​​the small electrode in the horizontal asymmetric Schottky junction, the S L is the area of ​​the large electrode in the horizontal asymmetric Schottky junction.

[0015] Preferably, the calculation formula for the carrier concentration is formula (2):

[0016]

[0017] In the formula, e is the elementary charge, N D is the carrier density, ε0 ​​is the vacuum dielectric constant, ε r is the relative dielectric constant of Ga2O3, k is The slope of the graph.

[0018] Preferably, the calculation formula of the carrier thickness is formula (5):

[0019]

[0020] Where d is the thickness, ε0 is the dielectric constant of vacuum, and ε r is the relative dielectric constant of Ga2O3, S Sis the area of ​​the small electrode in the horizontal asymmetric Schottky junction, C is the capacitance under forward bias conditions, and V>0V represents forward bias.

[0021] Preferably, the electrode is made of metal material.

[0022] The present invention provides a method for extracting carrier concentration and thickness through horizontal asymmetric double Schottky junction CV test, comprising the following steps: constructing an equivalent circuit model of a horizontal asymmetric Schottky junction; preparing electrodes of different sizes on a semiconductor epitaxial wafer that meets the model to form a horizontal asymmetric Schottky junction, and testing to obtain a barrier capacitance CV curve; fitting the barrier capacitance CV curve according to the equivalent circuit diagram model to obtain the carrier concentration and thickness, wherein the thickness refers to the thickness of an upper insulating or semi-insulating epitaxial layer on the semiconductor epitaxial wafer that meets the model.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] The present invention discloses a method for extracting carrier concentration and thickness through horizontal asymmetric double Schottky junction CV test, which can clarify the electrical information and thickness information of insulating or semi-insulating epitaxial materials grown on a conductive substrate, and effectively avoid the influence of substrate conductivity on the test results and the problem that ohmic electrodes are difficult to prepare. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of growing insulating or semi-insulating epitaxial materials on a conductive substrate;

[0026] Figure 2 It is the equivalent circuit diagram of double Schottky junction with horizontal structure;

[0027] Figure 3 It is the CV test result of Example 1;

[0028] Figure 4 for image;

[0029] Figures 1-2 1 is the upper insulating or semi-insulating epitaxial layer, 2 is the lower conductive semiconductor substrate layer, 3 is the asymmetric Schottky contact electrode, 4 is the depletion layer, 5 and 6 are Schottky contacts with different area sizes (S S and S L ) is the high resistance layer and depletion layer capacitor below, and 7 is the n-type semiconductor resistor connecting the two capacitors 5 and 6. DETAILED DESCRIPTION

[0030] The present invention provides a method for extracting carrier concentration and thickness through horizontal asymmetric double Schottky junction CV test, comprising the following steps:

[0031] Construct an equivalent circuit model of a horizontal asymmetric Schottky junction;

[0032] Electrodes of different sizes are prepared on semiconductor epitaxial wafers that meet the model to form a horizontal asymmetric Schottky junction, and the barrier capacitance CV curve is obtained by testing;

[0033] The barrier capacitance CV curve is fitted according to the equivalent circuit model to obtain the carrier concentration and thickness, wherein the thickness refers to the thickness of the upper insulating or semi-insulating epitaxial layer on the semiconductor epitaxial wafer that conforms to the model, and is also the thickness of the upper insulating or semi-insulating epitaxial layer in the equivalent circuit model of the horizontal asymmetric Schottky junction.

[0034] The present invention constructs an equivalent circuit model of a horizontal asymmetric Schottky junction.

[0035] In the present invention, the equivalent circuit model of the horizontal asymmetric Schottky junction preferably includes an upper insulating or semi-insulating epitaxial layer, a lower conductive semiconductor substrate layer, an asymmetric Schottky contact electrode and a depletion layer, wherein the asymmetric Schottky contact electrode is arranged on the surface of the upper insulating or semi-insulating epitaxial layer, and the depletion layer is arranged below the asymmetric Schottky contact electrode.

[0036] In the present invention, the area ratio of the horizontal asymmetric Schottky junction is preferably S S / S L <0.1, S S is the area of ​​the small electrode in the horizontal asymmetric Schottky junction, the S L is the area of ​​the large electrode in the horizontal asymmetric Schottky junction.

[0037] In the present invention, the material of the upper insulating or semi-insulating epitaxial layer is preferably a semiconductor material, more preferably silicon carbide, gallium nitride or gallium oxide.

[0038] In the present invention, the material of the lower conductive semiconductor substrate layer is preferably n-Ga2O3.

[0039] The present invention prepares electrodes of different sizes on a semiconductor epitaxial wafer that meets the model to form a horizontal asymmetric Schottky junction, and obtains a barrier capacitance CV curve through testing.

[0040] In the present invention, the semiconductor epitaxial wafer conforming to the model is preferably composed of an epitaxial insulating or semi-insulating material and a conductive substrate.

[0041] In the present invention, the semiconductor epitaxial wafer that conforms to the model preferably includes a homoepitaxial insulating or semi-insulating material on a conductive substrate, or the semiconductor epitaxial wafer that conforms to the model preferably includes a conductive substrate and an insulating or semi-insulating layer formed by oxygen annealing the conductive substrate, and the temperature of the oxygen annealing treatment is preferably 800-1500°C, specifically 800, 900, 1000, 1100, 1200, 1300, 1400 or 1500°C, and the time is preferably 0.5-72h, specifically 0.5, 1, 4, 8, 10, 15, 20, 24, 36 or 72h.

[0042] In the present invention, the material of the electrode is preferably a metal material, more preferably Au, Ni, Pt, Al, Cu, Mg or Pd, and the metal material is preferably made by magnetron sputtering or electron beam evaporation.

[0043] In the present invention, the barrier capacitance CV curve is preferably obtained based on a horizontal asymmetric double Schottky junction CV test of a semiconductor epitaxial wafer that conforms to the model.

[0044] After obtaining the equivalent circuit model and the barrier capacitance CV curve, the present invention fits the barrier capacitance CV curve according to the equivalent circuit model to obtain the carrier concentration and thickness.

[0045] The principle of the present invention is as follows:

[0046] Figure 1 Schematic diagram of growing insulating or semi-insulating epitaxial materials on a conductive substrate, where 1 is an upper insulating or semi-insulating epitaxial layer (high resistance layer), 2 is a lower conductive semiconductor substrate layer, and 3 is an asymmetric Schottky contact electrode. The formation of a Schottky junction between the sample and the asymmetric Schottky contact electrode is equivalent to a Schottky junction with a semi-insulating layer inserted between a metal and a semiconductor, which can be regarded as a metal-insulator-semiconductor structure. The gate characteristics of the metal-insulator-semiconductor structure are usually characterized by CV measurements between the gate metal and the semiconductor metal ohmic contact. Under accumulation conditions, the capacitance of the high resistance layer can be obtained. However, in the case of Au / high resistance Ga2O3 / UID Ga2O3 (Au is an asymmetric Schottky contact electrode, high resistance Ga2O3 is an upper insulating or semi-insulating epitaxial layer, and UID Ga2O3 is a lower conductive semiconductor substrate layer), when the forward DC bias is applied, there is no energy barrier for electrons to travel from UID Ga2O3 to high resistance Ga2O3, so the information of the high resistance layer cannot be obtained. Therefore, an equivalent circuit model of the horizontal asymmetric Schottky junction was constructed and the corresponding CV curve was measured, so that the DC current was suppressed under forward bias, and the thickness of the high-resistance layer and the corresponding electrical information were obtained through CV curve fitting analysis. Figure 2is the equivalent circuit diagram of the horizontal double Schottky junction, in which 3 is the Schottky contact electrode, 4 is the depletion layer, 5 and 6 are Schottky contacts with different area sizes (S S and S L ) and the depletion layer capacitance below, are essentially treated as capacitors (C S and C L ), 7 is the n-type semiconductor resistor connecting the two capacitors, which is regarded as a resistor (R); the entire circuit consists of capacitor C S , C L , resistor R and semiconductor parameter LCR tester are connected in series. At the same time, a forward DC bias (V) is applied to a small area (S S ) on a Schottky contact. In this case, the high-resistance layer thickness (d) is independent of V, while the depletion layer thickness (d S and d L ) changes with the change of V; and, under forward bias and reverse bias, the depletion layer thickness d S and d L It is much smaller than the thickness d of the high-resistance layer and can be ignored.

[0047] According to the above principle, a homoepitaxial insulating or semi-insulating material on a conductive substrate is selected as a model material, and the sample formed by oxygen annealing the conductive substrate (the temperature is preferably 800-1500°C, and the time is preferably 0.5-72h) can also be regarded as a layer of insulating or semi-insulating material grown homoepitaxially on an unannealed UID substrate; Au, Ni, Pt, Al, Cu, Mg or Pd materials are prepared on the model material sample using magnetron sputtering or electron beam evaporation to prepare Schottky contact electrodes, and CV tests of horizontal structures are performed.

[0048] Derivation process of carrier concentration of epitaxial materials:

[0049] The Mott-Schottky equation is expressed as formula (1):

[0050]

[0051] In the formula, e is the elementary charge, N D is the carrier density, k B is the Boltzmann constant, T is the temperature, V fb is the flat band potential, and V is the applied external voltage. According to the Mott-Schottky equation, the functional relationship between the sample capacitance and the applied external voltage can be determined to obtain Image, the slope k of the image is obtained as Therefore, the carrier concentration N D It can be expressed as formula (2):

[0052]

[0053] Epitaxial material thickness derivation process:

[0054] According to the above equivalent circuit model, taking into account the imaginary part of the entire admittance, the capacitance (C) measured by the semiconductor parameter analyzer can be expressed by formula (3):

[0055]

[0056] Where ω is the angular frequency, C SL It is C S and C L The series capacitance, C SL Expressed by formula (4):

[0057]

[0058] Where ε0 is the dielectric constant of vacuum, ε r is the relative dielectric constant of Ga2O3. In the present invention, the n-type semiconductor bulk resistance R is small, C SL The capacitance is small, ω 2 C SL 2 R 2 can be ignored, and simplifying formula (3) yields C≈C SL At the same time, when a forward bias is applied (V>0V), and the Schottky contact electrode area is larger than S S / S L When <0.1, formula (4) can be simplified to At this time, the thickness d of the high resistance layer is approximately expressed by formula (5):

[0059]

[0060] Combined with the above formula derivation, the test data is fitted to obtain the carrier concentration and thickness of the epitaxial material.

[0061] The technical solutions in the present invention will be described clearly and completely below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] Example 1

[0063] The cleaned single crystal substrate sample was placed face up in the center of a square zirconia crucible and placed in a high temperature muffle furnace for annealing at 1000℃ for 8h in an oxygen atmosphere. The surface of the substrate after annealing was coated with a 120nm Au electrode by magnetron sputtering. The smaller electrode area S S The larger electrode area S is a circle with a diameter of 0.25 mm. L is a circle with a diameter of 1 mm. The CV test results of this sample are as follows Figure 3 As shown, according to the CV test results, Images, such as Figure 4 As shown, the slope k obtained by fitting is 9.92×10 16 , Substitute into formula (2) The calculated carrier concentration is 1.43×10 14 cm -3 , the linear fit is 99.964%; Figure 3 As shown, when V>0V, C is 2.15~2.23×10 -9 F, substitute into formula (5) The fitting results show that the thickness of the high-resistance layer d is 194.7~202.0nm. (ε r =8.85×10 -12 F·M, ε0=10).

[0064] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A method for extracting carrier concentration and thickness through horizontal asymmetric double Schottky junction CV test, characterized in that: The following steps are involved: Construct an equivalent circuit model of a horizontal asymmetric Schottky junction; Electrodes of different sizes are prepared on semiconductor epitaxial wafers that meet the model to form a horizontal asymmetric Schottky junction, and the barrier capacitance CV curve is obtained by testing; The barrier capacitance CV curve is fitted according to the equivalent circuit diagram model to obtain the carrier concentration and thickness, wherein the thickness refers to the thickness of the upper insulating or semi-insulating epitaxial layer on the semiconductor epitaxial wafer that conforms to the model.

2. The method according to claim 1, characterized in that The equivalent circuit model of the horizontal asymmetric Schottky junction includes an upper insulating or semi-insulating epitaxial layer, a lower conductive semiconductor substrate layer, an asymmetric Schottky contact electrode and a depletion layer. The asymmetric Schottky contact electrode is arranged on the surface of the upper insulating or semi-insulating epitaxial layer, and the depletion layer is arranged below the asymmetric Schottky contact electrode.

3. The method according to claim 1, characterized in that: The semiconductor epitaxial wafer conforming to the model is composed of an epitaxial insulating or semi-insulating material and a conductive substrate.

4. The method according to claim 1 or 3, characterized in that: The semiconductor epitaxial wafer conforming to the model comprises a homoepitaxial insulating or semi-insulating material on a conductive substrate.

5. The method according to claim 1 or 3, characterized in that: The semiconductor epitaxial wafer conforming to the model comprises a conductive substrate and an insulating or semi-insulating layer formed by oxygen annealing the conductive substrate, wherein the temperature of the oxygen annealing is 800 to 1500° C. and the time is 0.5 to 72 hours.

6. The method according to claim 1, characterized in that The barrier capacitance CV curve is obtained based on a horizontal asymmetric double Schottky junction CV test of a semiconductor epitaxial wafer that conforms to the model.

7. The method according to claim 1, characterized in that The area ratio of the horizontal asymmetric Schottky junction is S S / S L <0.1, S S is the area of ​​the small electrode in the horizontal asymmetric Schottky junction, the S L is the area of ​​the large electrode in the horizontal asymmetric Schottky junction.

8. The method according to claim 1, characterized in that: The calculation formula of the carrier concentration is formula (2): In the formula, e is the elementary charge, N D is the carrier density, ε0 ​​is the vacuum dielectric constant, ε r is the relative dielectric constant of Ga2O3, k is The slope of the graph.

9. The method according to claim 1, characterized in that: The calculation formula of the carrier thickness is formula (5): Where d is the thickness, ε0 is the dielectric constant of vacuum, and ε r is the relative dielectric constant of Ga2O3, S S is the area of ​​the small electrode in the horizontal asymmetric Schottky junction, C is the capacitance under forward bias conditions, and V>0V represents forward bias.

10. The method according to claim 1, characterized in that The electrode is made of metal material.

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