Display device and structure

Abstract

The invention relates to a display device and a structure. According to an aspect of the present disclosure, a display device includes: a substrate configured to define a plurality of pixel regions and a plurality of transmissive regions disposed between the plurality of pixel regions; a plurality of pixels disposed in the plurality of pixel regions and each including a plurality of sub-pixels; light emitting elements respectively disposed in the plurality of sub-pixels and each including a first electrode; and a repair line disposed between a pair of adjacent sub-pixels among the plurality of sub-pixels, in which the light emitting elements of the pair of sub-pixels are disposed such that the first electrode is directed toward the repair line. Therefore, the repair lines can be formed to repair the plurality of sub-pixels when the plurality of sub-pixels have defects, so that the yield of the display device is improved.

Description

Technical Field

[0001] The present disclosure relates to a transparent display device, and more particularly, to a transparent display device using a light emitting diode. Background Art

[0002] As display devices used for monitors of computers, televisions, mobile phones, and the like, there are organic light emitting displays (OLEDs) configured to emit light autonomously and liquid crystal displays (LCDs) requiring a separate light source.

[0003] The application range of the display device is diversified from monitors of computers and televisions to personal mobile devices, and research on a display device having a wide display area and having reduced volume and weight is being conducted.

[0004] In addition, recently, a display device including a light emitting diode (LED) has attracted attention as a next-generation display device. Since LEDs are made of inorganic materials rather than organic materials, LEDs are more reliable than liquid crystal display devices or organic light emitting display devices and have a longer service life. In addition, LEDs can be turned on or off quickly, have excellent luminous efficiency, high impact resistance and high stability, and display high-brightness images. Summary of the invention

[0005] The present disclosure provides a transparent display device with high transmittance.

[0006] The present disclosure provides a display device in which an opaque line and a plurality of pixels are formed to overlap each other, thereby increasing the area of ​​a transmission region.

[0007] Another object to be achieved by the present disclosure is to provide a display device having a repair line for repairing a plurality of sub-pixels, thereby improving the yield.

[0008] Another object to be achieved by the present disclosure is to provide a display device, wherein the repair line is configured as a single-layer structure made of a transparent conductive material, thereby simplifying the structure of the repair line.

[0009] Another object of the present disclosure is to provide a display device, wherein the repair line is made of only a transparent conductive material, thereby minimizing the reduction in transmittance of the transmission area.

[0010] Another object to be achieved by the present disclosure is to provide a display device, wherein the light emitting elements are symmetrically arranged so that a plurality of repair lines are arranged so as not to overlap each other.

[0011] Another object to be achieved by the present disclosure is to provide a display device, in which the light-emitting elements of a pair of adjacent sub-pixels are symmetrically arranged so that a plurality of repair lines can be arranged within the shortest straight-line distance.

[0012] Another object of the present disclosure is to provide a display device, wherein a repair line connecting two light emitting elements has a shortest length, so that the resistance of the repair line can be increased, and the display device can operate with low power consumption.

[0013] Another object to be achieved by the present disclosure is to provide a display device, wherein a plurality of red light emitting elements, a plurality of green light emitting elements, and a plurality of blue light emitting elements can be arranged at uniform intervals.

[0014] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

[0015] According to one aspect of the present disclosure, a display device includes: a substrate configured to define a plurality of pixel regions spaced apart from each other and a plurality of transmission regions disposed between the plurality of pixel regions; a plurality of pixels disposed in the plurality of pixel regions and each including a plurality of sub-pixels; a light-emitting element disposed in the plurality of sub-pixels and each including a first electrode; and a repair line disposed between a pair of adjacent sub-pixels in the plurality of sub-pixels, wherein the light-emitting elements of the pair of sub-pixels are disposed so that the first electrode points to the repair line. Thus, a repair line can be formed to repair the plurality of sub-pixels when they are defective, thereby improving the yield of the display device.

[0016] Additional details of example implementations are included in the detailed description and accompanying drawings.

[0017] According to the present disclosure, a transparent display device with improved transmittance can be realized.

[0018] According to the present disclosure, opaque components may be disposed to overlap each other among components of a display device, thereby ensuring a maximum area of ​​a transmission region of the display device.

[0019] According to the present disclosure, the opaque line and the plurality of pixels may be formed to overlap each other, thereby increasing the area of ​​the transmission region.

[0020] According to the present disclosure, a repair line can be formed to repair a plurality of sub-pixels, thereby improving the yield of a display device.

[0021] According to the present disclosure, the repair line can be made of a transparent conductive material, thereby simplifying the structure of the repair line.

[0022] According to the present disclosure, the repair line may be made of only the transparent conductive material, thereby minimizing the reduction in transmittance of the transmission area.

[0023] According to the present disclosure, a plurality of repair lines are disposed not to overlap each other, so that the plurality of repair lines can be formed as a single layer on the same layer.

[0024] According to the present disclosure, light emitting elements of a pair of sub-pixels connected to each other during a repair process are arranged to be symmetrical so that a plurality of repair lines can be formed within the shortest straight line distance between the two light emitting elements.

[0025] According to the present disclosure, a repair line connecting two light emitting elements has the shortest straight line length, so that line resistance can be reduced and a display device can be operated with low power consumption.

[0026] According to the present disclosure, a plurality of red light emitting elements, a plurality of green light emitting elements, and a plurality of blue light emitting elements may be arranged at uniform intervals, thereby improving image quality.

[0027] The effects according to the present disclosure are not limited to the above-exemplified contents, and more various effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a schematic configuration diagram of a display device according to one embodiment of the present disclosure;

[0030] Figure 2A is a partial cross-sectional view of a display device according to an embodiment of the present disclosure;

[0031] Figure 2B is a perspective view of a tiled display device according to an embodiment of the present disclosure;

[0032] Figure 3 is a schematic enlarged top plan view of a display area of ​​a display device according to an embodiment of the present disclosure;

[0033] Figure 4 is an enlarged top view of a display device according to an embodiment of the present disclosure;

[0034] Figure 5A and Figure 5B is a cross-sectional view of a sub-pixel of a display device according to an embodiment of the present disclosure; and

[0035] Figure 6 is a cross-sectional view of a sub-pixel of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] By referring to the example embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will be clear. However, the present disclosure is not limited to the example embodiments disclosed herein, but will be implemented in various forms. The example embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0037] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings used to describe the example embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the present disclosure, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Unless a term is used with the term "only", terms such as "including", "having" and "consisting of..." used herein are generally intended to allow the addition of other components. Unless otherwise expressly stated, any reference to the singular may include the plural.

[0038] Even if not explicitly stated, components are interpreted as including normal margins of error.

[0039] When terms such as “on,” “above,” “below,” and “beside” are used to describe the positional relationship between two components, one or more components may be located between the two components unless the terms are used together with the terms “immediately” or “directly.”

[0040] When an element or layer is disposed “on” another element or layer, the further layer or element may be directly interposed on the other element or between the two elements or layers.

[0041] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below can be the second component in the technical concept of the present disclosure.

[0042] Like reference numbers generally refer to like elements throughout this disclosure.

[0043] For convenience of description, the size and thickness of each component shown in the drawings are illustrated, and the present disclosure is not limited to the size and thickness of the illustrated components.

[0044] The features of the various embodiments of the present disclosure may be partially or completely attached or combined with each other, and may be interlocked and operated in various ways technically, and the embodiments may be performed independently or in association with each other.

[0045] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0046] Figure 1 Schematic configuration diagram of a display device according to an embodiment of the present disclosure. For ease of description, Figure 1 Only the display panel PN, the gate driving part GD, the data driving part DD, and the timing controller TC are illustrated among the respective constituent elements of the display device 100 .

[0047] Reference Figure 1 The display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driving part GD configured to provide various types of signals to the display panel PN, and a timing controller TC configured to control the data driving part gate driving part GD and the data driving part DD.

[0048] The gate driving part GD supplies a plurality of scan signals to the plurality of scan lines SL in response to a plurality of gate control signals supplied from the timing controller TC. Figure 1 It is illustrated that a single gate driving part GD is disposed to be spaced apart from one side of the display panel PN. However, the number and arrangement of the gate driving parts GD are not limited thereto.

[0049] The data driving part DD provides data voltages to the plurality of data lines DL in response to a plurality of data control signals and image data provided from the timing controller TC. The data driving part DD may convert the image data into data voltages by using reference gamma voltages and provide the converted data voltages to the plurality of data lines DL.

[0050] The timing controller TC aligns image data input from the outside and provides the image data to the data driving part DD. The timing controller TC can generate a gate control signal and a data control signal by using a synchronization signal (i.e., a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal) input from the outside. In addition, the timing controller TC can control the gate driving part GD and the data driving part DD by providing the generated gate control signal and data control signal to the gate driving part GD and the data driving part DD.

[0051] The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL may cross each other, and a plurality of sub-pixels SP may be formed at intersections between the scan lines SL and the data lines DL.

[0052] A display area AA and a non-display area NA may be defined on the display panel PN.

[0053] The display area AA is an area of ​​the display device 100 that displays an image. The display area AA may include a plurality of sub-pixels SP constituting a plurality of pixels PX and a pixel circuit configured to operate the plurality of sub-pixels SP. The plurality of sub-pixels SP are the minimum units constituting the display area AA. n sub-pixels SP may constitute a single pixel PX. Thin film transistors and the like for operating the plurality of light-emitting elements 120 may be respectively arranged in the plurality of sub-pixels SP. The plurality of light-emitting elements 120 may be differently defined according to the type of the display panel PN. For example, in the case where the display panel PN is an inorganic light-emitting display panel, the light-emitting element 120 may be a light-emitting diode (LED) or a micro light-emitting diode (micro LED).

[0054] A plurality of signal lines for transmitting various types of signals to a plurality of sub-pixels SP are provided in the display area AA. For example, the plurality of signal lines may include a plurality of data lines DL for providing data voltages to the plurality of sub-pixels SP and a plurality of scan lines SL for providing scan signals to the plurality of sub-pixels SP. The plurality of scan lines SL may extend in one direction in the display area AA and be connected to the plurality of sub-pixels SP. The plurality of data lines DL may extend in a direction different from one direction in the display area AA and be connected to the plurality of sub-pixels SP. In addition, a low potential power line VSS, a high potential power line VDD, etc. may also be provided in the display area AA. However, the present disclosure is not limited thereto.

[0055] The non-display area NA may be defined as an area where an image is not displayed (i.e., an area extending from the display area AA). The non-display area NA may include link lines and pad electrodes for transmitting signals to the sub-pixels SP in the display area AA. Alternatively, the non-display area NA may include driver ICs such as a gate driver IC and a data driver IC.

[0056] In addition, the non-display area NA may be located on the rear surface of the display panel PN (ie, a surface where the sub-pixels SP do not exist). Alternatively, the non-display area NA may not be included. However, the present disclosure is not limited to the configurations shown in the drawings.

[0057] In addition, driving parts such as a gate driving part GD, a data driving part DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driving part GD may be installed in the non-display area NA by a gate-in-panel (GIP) method, or may be installed between a plurality of sub-pixels SP by a gate-in-area (GIA) method in the display area AA.

[0058] For example, the data driving component DD and the timing controller TC may be formed on separate flexible films and printed circuit boards, and the display panel PN, the data driving component DD, and the timing controller TC may be electrically connected by bonding the flexible film and the printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN.

[0059] As another example, in the case where the gate driving part GD is installed in the display area AA by the GIA method and the side lines SRL connecting the signal lines on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN are formed to bond the flexible film and the printed circuit board to the rear surface of the display panel PN, the non-display area NA on the front surface of the display panel PN can be minimized. Therefore, in the case where the gate driving part GD, the data driving part DD and the timing controller TC are connected to the display panel PN by the above method, a zero frame in which there is substantially no frame can be achieved. Figure 2A and Figure 2B Description A more detailed description.

[0060] Figure 2A is a partial cross-sectional view of a display device according to an embodiment of the present disclosure. Figure 2B It is a stereoscopic view of a tiled display device according to an embodiment of the present disclosure.

[0061] A plurality of pad electrodes for transmitting various types of signals to a plurality of sub-pixels SP are disposed in the non-display area NA on the display panel PN. For example, a first pad electrode PAD1 configured to transmit signals to a plurality of sub-pixels SP is disposed in the non-display area NA on the front surface of the display panel PN. A second pad electrode PAD2 electrically connected to a driving component such as a flexible film and a printed circuit board is disposed in the non-display area NA on the rear surface of the display panel PN.

[0062] In this case, although not shown in the drawings, various types of signal lines (eg, scan lines SL, data lines DL, etc.) connected to the plurality of sub-pixels SP may extend from the display area AA to the non-display area NA and be electrically connected to the first pad electrode PAD1.

[0063] In addition, the side line SRL is disposed on the side surface of the display panel PN. The side line SRL may electrically connect the first pad electrode PAD1 on the front surface of the display panel PN and the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, a signal received from a driving component on the rear surface of the display panel PN may be transmitted to a plurality of sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Therefore, the driving component is disposed on the rear surface of the display panel PN, and a signal transmission route is defined between the front surface and the rear surface of the display panel PN, which may minimize the area of ​​the non-display region NA on the front surface of the display panel PN.

[0064] In addition, refer to Figure 2B , a tiled display device TD having a large screen can be realized by connecting a plurality of display devices 100. In this case, Figure 2A As shown, in the case of implementing the tiled display device TD by using the display device 100 with a minimized frame, a seam area between the display devices 100 where no image is displayed may be minimized, thereby improving display quality.

[0065] For example, a plurality of sub-pixels SP may constitute a single pixel PX. An interval D1 between the most peripheral pixels PX of one display device 100 and the most peripheral pixels PX of another display device 100 adjacent to the one display device 100 may be implemented to be equal to an interval D1 between pixels PX in one display device 100. Therefore, when a constant interval of pixels PX is implemented between display devices 100 and display devices 100, a seam area may be minimized.

[0066] However, if Figure 2A and Figure 2B As shown, the display device 100 according to the embodiment of the present disclosure may be a general display device having a frame. However, the present disclosure is not limited thereto.

[0067] In the following, reference will be made to Figures 3 to 6 The display panel PN of the display device 100 according to the embodiment of the present disclosure is described in more detail.

[0068] Figure 3 is a schematic enlarged top view of a display area of ​​a display device according to an embodiment of the present disclosure. Figure 4 is an enlarged top view of a display device according to an embodiment of the present disclosure. Figure 5A and Figure 5B is a cross-sectional view of a sub-pixel of a display device according to an embodiment of the present disclosure. Figure 6 is a cross-sectional view of a sub-pixel of a display device according to an embodiment of the present disclosure. For example, Figure 4 is an enlarged top view of a pixel PX. Figure 5Ais a cross-sectional view of a B-type sub-pixel SPb, Figure 5B is a cross-sectional view of an A-type sub-pixel SPa. Figure 6 is a cross-sectional view of a B-type sub-pixel SPb after the repair process is completed. For ease of description, Figure 3 Only a plurality of light emitting elements 120, a plurality of repair lines WRL, a plurality of first connection electrodes CE1, a second connection electrode CE2, and a scan line SL are illustrated. Figure 4 , the first connection electrode CE1 and the second connection electrode CE2 are indicated by thick solid lines, and their shadows are omitted. The shadows of the first reflective electrode RE1 and the second reflective electrode RE2 are omitted.

[0069] Reference Figure 3 The display area AA includes a plurality of pixel areas UPA and a plurality of transmission areas TA.

[0070] A plurality of pixel areas UPA are formed in the display area AA. The plurality of pixel areas UPA are areas where pixels PX are provided and display images. The plurality of pixel areas UPA may be arranged to be spaced apart from each other (e.g., in a row direction R), and wherein a plurality of transmission areas TA are interposed therebetween. For example, the plurality of pixel areas UPA may be arranged in a plurality of rows and columns.

[0071] A plurality of sub-pixels SP constituting a pixel PX are arranged in each of a plurality of pixel areas UPA. The plurality of sub-pixels SP may each include a light emitting element 120 and a pixel circuit and emit light independently. For example, the plurality of sub-pixels SP may include first sub-pixels SP1a and SP1b, second sub-pixels SP2a and SP2b, and third sub-pixels SP3a and SP3b that emit light beams of different colors. For example, the first sub-pixels SP1a and SP1b may be red sub-pixels, the second sub-pixels SP2a and SP2b may be green sub-pixels, and the third sub-pixels SP3a and SP3b may be blue sub-pixels. However, the present disclosure is not limited thereto. In the present disclosure, a configuration in which the plurality of sub-pixels SP include three sub-pixels SP is described. However, the plurality of sub-pixels SP may include four or more sub-pixels SP that also include sub-pixels SP that display additional colors including white.

[0072] Hereinafter, it is assumed that one pixel PX includes two first subpixels SP1a and SP1b, two second subpixels SP2a and SP2b, and two third subpixels SP3a and SP3b (ie, two red subpixels, two green subpixels, and two blue subpixels). However, the configuration of the pixel PX is not limited thereto.

[0073] A plurality of sub-pixels SP constituting one pixel PX are arranged in a line in the column direction C. A plurality of sub-pixels SP may be arranged in the column direction and overlap with the line extending in the column direction. For example, a plurality of sub-pixels SP may overlap with the data line DL, the reference line RL, the high potential power line VDD, the low potential power line VSS, etc. extending in the column direction. The pixel area UPA may be formed in an area where a plurality of opaque lines are arranged, so that the area of ​​the transmission area TA may be ensured in the entire display area AA. The pixel area UPA in which a plurality of sub-pixels SP are arranged may be an area having a low transmittance and being substantially opaque due to the configuration of the pixel circuit, the light emitting element 120, etc. arranged in the plurality of sub-pixels SP. Therefore, a plurality of sub-pixels SP in the pixel area UPA may be arranged to overlap with the opaque line (e.g., the data line DL, the reference line RL, the low potential power line VSS, and the high potential power line VDD) extending in the column direction C. Therefore, a plurality of sub-pixels SP in the pixel area UPA are arranged to overlap with a plurality of lines, so that the area of ​​the opaque area may be reduced in the entire display area AA, and the area of ​​the increased transmission area TA may be formed.

[0074] In addition, a plurality of sub-pixels SP included in one pixel PX may be arranged in regions at two opposite sides of the scan line SL. For example, in a region at one side of the scan line SL, one of a pair of first sub-pixels SP1a and SP1b, one of a pair of second sub-pixels SP2a and SP2b, and one of a pair of third sub-pixels SP3a and SP3b may be arranged sequentially in the column direction. In addition, in a region at the other side of the scan line SL, the remainder of a pair of first sub-pixels SP1a and SP1b, the remainder of a pair of second sub-pixels SP2a and SP2b, and the remainder of a pair of third sub-pixels SP3a and SP3b may be arranged sequentially in the column direction. Therefore, a plurality of sub-pixels SP constituting one pixel PX may be arranged in the column direction in the order of the first sub-pixel SP1b, the second sub-pixel SP2b, the third sub-pixel SP3b, the first sub-pixel SP1a, the second sub-pixel SP2a, and the third sub-pixel SP3a. However, the arrangement order of the plurality of sub-pixels SP may be changed differently. However, the present disclosure is not limited thereto.

[0075] In addition, the light emitting element 120 of each of the plurality of sub-pixels SP may be connected to and operated with the first connection electrode CE1 and the second connection electrode CE2. The first connection electrode CE1 is an electrode configured to electrically connect the light emitting element 120 and the driving transistor DT, and the second connection electrode CE2 is an electrode configured to electrically connect the light emitting element 120 and the high potential power line VDD. In this case, the repair line WRL may be connected to some of the first connection electrodes CE1 among the plurality of first connection electrodes CE1. The repair line WRL may be connected only to the first connection electrodes CE1 of some of the sub-pixels SP. When a defect occurs subsequently, the repair line WRL may be electrically connected to any one of the remaining first connection electrodes CE1 to which the repair line WRL is not connected, so that the defective sub-pixel SP may be repaired.

[0076] In addition, in the present disclosure, a configuration has been described in which the light emitting element 120 is electrically connected to the high potential power line VDD and the driving transistor DT is connected to the low potential power line VSS. However, according to the pixel structure, the light emitting element 120 may be connected to the low potential power line VSS, and the driving transistor DT may be connected to the high potential power line VDD. However, the present disclosure is not limited thereto. In addition, in the case where the light emitting element 120 is connected to the low potential power line VSS and the driving transistor DT is connected to the high potential power line VDD, the first connection electrode CE1 may be connected to the light emitting element 120 and the low potential power line VSS, and the second connection electrode CE2 may be connected to the driving transistor DT and the light emitting element 120. In contrast, the first connection electrode CE1 may be connected to the light emitting element 120 and the driving transistor DT, and the second connection electrode CE2 may be connected to the light emitting element 120 and the low potential power line VSS.

[0077] Hereinafter, for ease of description, among the plurality of sub-pixels SP, the sub-pixel SP whose first connection electrode CE1 is connected to the repair line WRL will be referred to as an A-type sub-pixel SPa and described, and the sub-pixel SP whose first connection electrode CE1 is not connected to the repair line WRL will be referred to as a B-type sub-pixel SPb and described. In some embodiments, the repair line WRL is connected to the first connection electrode CE1 of the A-type sub-pixel, extends through the adjacent transmission area TA, and extends into the pixel area UPA of the adjacent B-type sub-pixel without contacting the adjacent B-type sub-pixel.

[0078] Some of the plurality of sub-pixels SP disposed in one pixel area UPA may be A-type sub-pixels SPa, and the remaining sub-pixels SP may be B-type sub-pixels SPb. One of a pair of first sub-pixels SP1a and SP1b, one of a pair of second sub-pixels SP2a and SP2b, and one of a pair of third sub-pixels SP3a and SP3b may be the A-type sub-pixel SPa. The remaining one of the pair of first sub-pixels SP1a and SP1b, the remaining one of the pair of second sub-pixels SP2a and SP2b, and the remaining one of the pair of third sub-pixels SP3a and SP3b may be the B-type sub-pixel SPb. For example, the pixel PX disposed in one pixel area UPA may include a first A-type sub-pixel SP1a, a first B-type sub-pixel SP1b, a second A-type sub-pixel SP2a, a second B-type sub-pixel SP2b, a third A-type sub-pixel SP3a, and a third B-type sub-pixel SP3b.

[0079] In each pixel area UPA of some of the plurality of pixel areas UPA, the A-type sub-pixel SPa may be disposed in an area at a first side of the scan line SL, and the B-type sub-pixel SPb may be disposed in an area at a second side of the scan line SL opposite to the first side. For example, in some of the pixel areas UPA, the sub-pixels SP may be disposed in a column direction in the order of a first A-type sub-pixel SP1a, a second A-type sub-pixel SP2a, a third A-type sub-pixel SP3a, a first B-type sub-pixel SP1b, a second B-type sub-pixel SP2b, and a third B-type sub-pixel SP3b.

[0080] In the remaining pixel area UPA among the plurality of pixel areas UPA, the B-type sub-pixel SPb may be disposed in an area at one side of the scan line SL, and the A-type sub-pixel SPa may be disposed in an area at the other side of the scan line SL. In the remaining pixel area UPA, the sub-pixels SP may be disposed in a column direction in the order of a first B-type sub-pixel SP1b, a second B-type sub-pixel SP2b, a third B-type sub-pixel SP3b, a first A-type sub-pixel SP1a, a second A-type sub-pixel SP2a, and a third A-type sub-pixel SP3a.

[0081] Therefore, in the pixel area UPA set in the nth column, the A-type sub-pixel SPa can be set in the area at one side of the scan line SL. In the pixel area UPA set in the (n+1)th column, the A-type sub-pixel SPa can be set in the area at the other side of the scan line SL.

[0082] In addition, some pixel areas UPA in the area where the A-type sub-pixels SPa are arranged at one side of the scan line SL and the remaining pixel areas UPA in the area where the A-type sub-pixels SPa are arranged at the other side of the scan line SL may be arranged in different columns. In this case, the A-type sub-pixels SPa and the B-type sub-pixels SPb may be arranged alternately in the row direction. For example, the first A-type sub-pixel SP1a and the first B-type sub-pixel SP1b may be arranged alternately in the same row. The second A-type sub-pixel SP2a and the second B-type sub-pixel SP2b may be arranged alternately in the same row. The third A-type sub-pixel SP3a and the third B-type sub-pixel SP3b may be arranged alternately in the same row.

[0083] In addition, a group of multiple A-type sub-pixels Spa and a group of multiple B-type sub-pixels SPb may also be alternately arranged in the column direction. For example, a group of A-type sub-pixels Spa including a first A-type sub-pixel SP1a, a second A-type sub-pixel SP2a, and a third A-type sub-pixel SP3a and a group of B-type sub-pixels SPb including a first B-type sub-pixel SP1b, a second B-type sub-pixel SP2b, and a third B-type sub-pixel SP3b may be alternately arranged in the column direction.

[0084] The repair line WRL and the A-type sub-pixel SPa can be used to repair the B-type sub-pixel SPb, and the repair line WRL and the B-type sub-pixel SPb can be used to repair the A-type sub-pixel SPa. When a circuit defect occurs on the A-type sub-pixel Spa, the repair line WRL can be used to connect the light-emitting element 120 of the A-type sub-pixel SPa to the circuit of the B-type sub-pixel SPb and operate the light-emitting element 120. Conversely, when a circuit defect occurs on the B-type sub-pixel SPb, the repair line WRL can be used to connect the light-emitting element 120 of the B-type sub-pixel SPb to the circuit of the A-type sub-pixel SPa and operate the light-emitting element 120.

[0085] Therefore, in the case where all the sub-pixels SP of the plurality of A-type sub-pixels SPa and the plurality of B-type sub-pixels SPb are operated when the display device 100 is operated, when a defect occurs in any one of the plurality of sub-pixels SP, the display quality may be deteriorated. However, in the display device 100 according to the embodiment of the present disclosure, even if a defect occurs in any one of the plurality of sub-pixels SP, the light emitting element 120 of the defective sub-pixel SP is connected to the driving transistor DT of the A-type sub-pixel SPa or the B-type sub-pixel SPb adjacent to the defective sub-pixel SP, so that the defective sub-pixel SP may appear to operate normally.

[0086] As another example, when the display device 100 is operated, one of the one or more B-type sub-pixels SPb among the plurality of A-type sub-pixels SPa may be implemented as a substantially operated main sub-pixel, and the remaining A-type sub-pixels SPa or the remaining B-type sub-pixels SPb may be implemented as redundant sub-pixels for repairing defective main sub-pixels. A pixel circuit is formed in the redundant sub-pixel. Even if a defect occurs on the pixel circuit of the main sub-pixel, the pixel circuit of the redundant sub-pixel may be connected to the light-emitting element of the main sub-pixel and the light-emitting element of the main sub-pixel may be normally operated.

[0087] Next, the light emitting element 120 of the A-type sub-pixel SPa and the light emitting element 120 of the B-type sub-pixel SPb may be symmetrically arranged with respect to the repair line WRL. The repair line WRL is arranged between the first connection electrode CE1 of the A-type sub-pixel SPa and the first connection electrode CE1 of the B-type sub-pixel SPb. Therefore, the A-type sub-pixel SPa and the B-type sub-pixel SPb arranged in columns adjacent to each other may be formed so that the first connection electrodes CE1 face each other. The first connection electrode CE1 of the A-type sub-pixel SPa may be arranged to face the B-type sub-pixel SPb, and the first connection electrode CE1 of the B-type sub-pixel SPb may also be arranged to face the A-type sub-pixel Spa. Therefore, the arrangement direction of the light emitting element 120 having the first electrode 124 connected to the first connection electrode CE1 may vary according to the position of the first connection electrode CE1.

[0088] For example, the light emitting element 120 of the A-type sub-pixel SPa may be arranged so that the first electrode 124 is directed toward the B-type sub-pixel SPb, and the light emitting element 120 of the B-type sub-pixel SPb may be arranged so that the first electrode 124 is directed toward the A-type sub-pixel SPa. For example, in the A-type sub-pixel SPa in the nth column, the first electrode 124 of the light emitting element 120 is arranged to be directed toward the (n+1)th column. In the B-type sub-pixel SPb in the (n+1)th column, the first electrode 124 of the light emitting element 120 may be arranged to be directed toward the nth column.

[0089] In addition, the arrangement direction of the light emitting element 120 of the A-type sub-pixel SPa disposed in one pixel area UPA may be opposite to the arrangement direction of the light emitting element 120 of the B-type sub-pixel SPb. For example, in the pixel area UPA of the nth column, the light emitting element 120 of the A-type sub-pixel SPa may be arranged so that the first electrode 124 is directed toward the (n+1)th column, and the light emitting element 120 of the B-type sub-pixel SPb may be arranged so that the first electrode 124 is directed toward the (n-1)th column.

[0090] In one pixel area UPA, the arrangement direction of the light emitting element 120 of the A-type sub-pixel SPa is opposite to the arrangement direction of the light emitting element 120 of the B-type sub-pixel SPb, so that one second connection electrode CE2 commonly connected to the plurality of light emitting elements 120 may have a sawtooth shape. The second connection electrode CE2 may extend straight in the column direction and have a sawtooth shape to correspond to the second electrode 125 of the light emitting element 120 of each sub-pixel SP. For example, in one pixel area UPA, the second electrode 125 of the light emitting element 120 of the A-type sub-pixel SPa may be disposed to be biased toward one side of the pixel area UPA, and the second electrode 125 of the light emitting element 120 of the B-type sub-pixel SPb may be disposed to be biased toward the other side of the pixel area UPA. Therefore, the second connection electrode CE2 may be formed in a sawtooth shape to correspond to the position of the second electrode 125 of the light emitting element 120. For example, the second connection electrode CE2 may include a portion disposed on the A-type sub-pixel SPa and adjacent to one side of the pixel area UPA and a portion disposed on the B-type sub-pixel SPb and adjacent to the other side of the pixel area UPA. In addition, since the groups of A-type subpixels Spa and the groups of B-type subpixels SPb are alternately arranged in the same column, the portion of the second connection electrode CE2 adjacent to one side of the pixel area UPA and the portion of the second connection electrode CE2 adjacent to the other side of the pixel area UPA can be alternately arranged.

[0091] Next, the B-type subpixel SPb includes a welding area WA. The welding area WA is an area where a welding process is performed by irradiating the area with a laser beam during a repair process. An area where the repair line WRL overlaps with the first reflective electrode RE1 of the B-type subpixel SPb may be defined as the welding area WA to be irradiated with a laser beam during a repair process. The repair process may be performed by electrically connecting the repair line WRL to the first connection electrode CE1 of the B-type subpixel SPb by irradiating the welding area WA with a laser beam. FIG. 5A to FIG. 6 A repair process using the repair line WRL is described in detail.

[0092] Next, the plurality of transmission areas TA are areas other than the area in the display area AA where the plurality of lines and the plurality of pixel areas UPA are disposed. The plurality of transmission areas TA have a relatively high transmittance. The transmission areas TA transmit light so that the background located on the rear surface of the display device 100 is visible from the front surface of the display device 100. The plurality of transmission areas TA may be disposed to be spaced apart from each other and wherein the plurality of lines and the plurality of pixel areas UPA are interposed between the transmission areas TA. The plurality of transmission areas TA may be disposed to surround the plurality of pixel areas UPA. Therefore, the display device 100 according to an embodiment of the present disclosure may be implemented as a transparent display device 100 including the plurality of transmission areas TA.

[0093] Reference Figures 4 to 5B , each of the plurality of sub-pixels SP includes a pixel circuit and a light emitting element 120. For example, the pixel circuit may include a first transistor T1, a second transistor T2, a driving transistor DT, and a storage capacitor Cst and operate the light emitting element 120. In addition, the plurality of sub-pixels SP disposed in one pixel area UPA may be connected to a scan line SL, a plurality of data lines DL, a reference line RL, a high potential power line VDD, and a low potential power line VSS and provided with various types of signals.

[0094] First, the substrate 110 is a component for supporting various constituent elements included in the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, etc. In addition, the substrate 110 may include plastic such as a polymer and may be made of a material having flexibility.

[0095] A light blocking layer LS is disposed on each of the plurality of sub-pixels SP on the substrate 110. The light blocking layer LS blocks light entering a driving active layer DACT of a driving transistor DT to be described below from the lower side of the substrate 110. The light blocking layer LS may block light entering the driving active layer DACT of the driving transistor DT, thereby minimizing leakage current.

[0096] The buffer layer 111 is disposed on the substrate 110 and the light blocking layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 can be configured as a single layer or a multilayer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto. However, depending on the type of the substrate 110 or the type of the transistor, the buffer layer 111 may not be included. However, the present disclosure is not limited thereto.

[0097] The driving transistor DT, the first transistor T1 , and the second transistor T2 are disposed in each of the plurality of sub-pixels SP on the buffer layer 111 .

[0098] The driving transistor DT, the first transistor T1, and the second transistor T2 of each of the plurality of sub-pixels SP may be a P-type thin film transistor or an N-type thin film transistor. For example, in a P-type thin film transistor, positive holes move from the source to the drain, so that current can flow from the source to the drain. In an N-type thin film transistor, electrons move from the source to the drain, so that current can flow from the drain to the source. In the following, it is assumed that the driving transistor DT, the first transistor T1, and the second transistor T2 are P-type thin film transistors in which current flows from the source to the drain for explanation. However, the present disclosure is not limited thereto.

[0099] First, a driving transistor DT is disposed in each of a plurality of sub-pixels SP on the buffer layer 111. The driving transistor DT is a transistor for controlling a driving current supplied to the light emitting element 120. In one pixel area UPA, the driving transistors DT of the plurality of sub-pixels SP may be arranged in a line in a column direction. The plurality of driving transistors DT of the plurality of sub-pixels SP may overlap an area where a reference line RL and a data line DL are disposed while being arranged in a line.

[0100] The driving transistor DT includes a driving active layer DACT, a driving gate DGE, a driving source DSE, and a driving drain DDE.

[0101] The driving active layer DACT is disposed on the buffer layer 111. The driving active layer DACT may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, the present disclosure is not limited thereto.

[0102] The gate insulating layer 112 is disposed on the driving active layer DACT. The gate insulating layer 112 is an insulating layer for insulating the driving active layer DACT and the driving gate DGE. The gate insulating layer 112 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0103] The driving gate DGE is disposed on the gate insulating layer 112. The driving gate DGE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.

[0104] The first interlayer insulating layer 113a is disposed on the driving gate DGE. A contact hole is formed in the first interlayer insulating layer 113a, and the driving source electrode DSE is connected to the driving active layer DACT through the contact hole. The first interlayer insulating layer 113a is an insulating layer for protecting components disposed below the first interlayer insulating layer 113a. The first interlayer insulating layer 113a may be configured as a single layer or a multilayer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0105] The driving source electrode DSE is disposed on the first interlayer insulating layer 113a. The driving source electrode DSE is electrically connected to the driving active layer DACT through a contact hole formed in the first interlayer insulating layer 113a and the gate insulating layer 112. In addition, the driving source electrode DSE may be electrically connected to the second transistor T2. The driving source electrode DSE may be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0106] The second interlayer insulating layer 113b and the first passivation layer 114a are disposed on the first interlayer insulating layer 113a, and the driving drain electrode DDE is disposed on the first passivation layer 114a. The driving drain electrode DDE is electrically connected to the driving active layer DACT through a contact hole formed in the first passivation layer 114a, the second interlayer insulating layer 113b, the first interlayer insulating layer 113a, and the gate insulating layer 112. In addition, the driving drain electrode DDE may be electrically connected to the low potential power line VSS through a contact hole formed in the first passivation layer 114a. The driving drain electrode DDE may be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0107] The second interlayer insulating layer 113b is disposed on the first interlayer insulating layer 113a. The second interlayer insulating layer 113b is an insulating layer for protecting components disposed below the second interlayer insulating layer 113b. The second interlayer insulating layer 113b may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0108] The first passivation layer 114a is disposed on the second interlayer insulating layer 113b. The first passivation layer 114a is an insulating layer for protecting components disposed below the first passivation layer 114a. The first passivation layer 114a may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0109] Next, a first transistor T1 is disposed on the buffer layer 111 in each of the plurality of sub-pixels SP. The first transistor T1 may be a transistor configured to send a data voltage to the driving gate DGE of the driving transistor DT. The first transistor T1 may be referred to as a switching transistor. In this case, in one pixel area UPA, a plurality of first transistors T1 of a plurality of sub-pixels SP may be arranged in a line in a row direction and overlap the scan line SL.

[0110] For example, the scan line SL may extend in the row direction on the gate insulating layer 112 and be arranged to cross the plurality of pixel areas UPA. In addition, the first transistor T1 of a pair of first sub-pixels SP1a and SP1b, the first transistor T1 of a pair of second sub-pixels SP2a and SP2b, and the first transistor T1 of a pair of third sub-pixels SP3a and SP3b may be arranged in sequence along the scan line SL. For example, the first transistor T1 of the first B-type sub-pixel SP1b at the other side of the scan line SL, the first transistor T1 of the first A-type sub-pixel SP1a at one side of the scan line SL, the first transistor T1 of the second B-type sub-pixel SP2b at the other side of the scan line SL, the first transistor T1 of the second A-type sub-pixel SP2a at one side of the scan line SL, the first transistor T1 of the third B-type sub-pixel SP3b at the other side of the scan line SL, and the first transistor T1 of the third A-type sub-pixel SP3a at one side of the scan line SL may be arranged in sequence in the row direction.

[0111] In this case, the first transistors T1 of a pair of first sub-pixels SP1a and SP1b may be disposed adjacent to each other and share one data line DL. In addition, the first transistors T1 of a pair of second sub-pixels SP2a and SP2b may also be disposed adjacent to each other and share one data line DL. Finally, the first transistors T1 of a pair of third sub-pixels SP3a and SP3b may also be disposed adjacent to each other and share one data line DL.

[0112] The first transistor T1 includes a first active layer ACT1, a first gate GE1, a first source SE1, and a first drain DE1.

[0113] The first active layer ACT1 is disposed on the buffer layer 111. The first active layer ACT1 may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, the present disclosure is not limited thereto.

[0114] The first gate GE1 is disposed on the gate insulating layer 112. The first gate GE1 may be electrically connected to the scan line SL. For example, the first gate GE1 may be integrated with the scan line SL. The first gate GE1 may be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0115] The first drain electrode DE1 is disposed on the first interlayer insulating layer 113a. The first drain electrode DE1 is electrically connected to the first active layer ACT1 through a contact hole formed in the first interlayer insulating layer 113a and the gate insulating layer 112. In addition, the first drain electrode DE1 may also be electrically connected to the second gate GE2 of the second transistor T2 through the contact hole of the first interlayer insulating layer 113a. The first drain electrode DE1 may be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0116] The first source electrode SE1 is disposed on the first passivation layer 114a. The first source electrode SE1 is electrically connected to the first active layer ACT1 through the first passivation layer 114a, the second interlayer insulating layer 113b, and the contact hole of the first interlayer insulating layer 113a. In addition, the first source electrode SE1 may be electrically connected to the data line DL. For example, the first source electrode SE1 may be integrated with the data line DL. The first source electrode SE1 may be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0117] In this case, the first source SE1 of the first transistor T1 of the subpixel SP disposed at one side of the scan line SL may be connected to the data line DL in the region disposed at the other side of the scan line SL. In addition, the first source SE1 of the first transistor T1 of the subpixel SP disposed at the other side of the scan line SL may be connected to the data line DL in the region at one side of the scan line SL. For example, the first source SE1 of the first transistor T1 of the A-type subpixel SPa located at one side of the scan line SL may be connected to the data line DL in the region at the other side of the scan line SL. The first source SE1 of the first transistor T1 of the B-type subpixel SPb located at the other side of the scan line SL may be connected to the data line DL in the region at the other side of the scan line SL.

[0118] Therefore, in the first transistor T1 of the pair of first sub-pixels SP1a and SP1b, the first source SE1 and the first drain DE1 may be arranged alternately. The first source SE1 of the first transistor T1 of one of the pair of first sub-pixels SP1a and SP1b may be arranged at one side of the scan line SL, and the first source SE1 of the first transistor T1 of the other of the pair of first sub-pixels SP1a and SP1b may be arranged at the other side of the scan line SL. Similar to the first transistor T1 of the pair of first sub-pixels SP1a and SP1b, the first source SE1 of the first transistor T1 of the pair of second sub-pixels SP2a and SP2b and the first source SE1 of the first transistor T1 of the pair of third sub-pixels SP3a and SP3b may also be arranged in one side region and the other side region of the scan line SL.

[0119] Therefore, in a region on one side of the scan line SL, the first source SE1 of the first subpixel SP1a and SP1b, the first drain DE1 of the first subpixel SP1a and SP1b, the first source SE1 of the second subpixel SP2a and SP2b, the first drain DE1 of the second subpixel SP2a and SP2b, the first source SE1 of the third subpixel SP3a and SP3b, and the first drain DE1 of the third subpixel SP3a and SP3b may be sequentially disposed. In addition, in a region on the other side of the scan line SL, the first drain DE1 of the first subpixel SP1a and SP1b, the first source SE1 of the first subpixel SP1a and SP1b, the first drain DE1 of the second subpixel SP2a and SP2b, the first source SE1 of the second subpixel SP2a and SP2b, the first drain DE1 of the third subpixel SP3a and SP3b, and the first source SE1 of the third subpixel SP3a and SP3b may be sequentially disposed.

[0120] Next, a second transistor T2 is disposed on the buffer layer 111 in each of the plurality of sub-pixels SP. The second transistor T2 may be a transistor configured to sense and compensate for the threshold voltage of the driving transistor DT. The second transistor T2 may be referred to as a sensing transistor. The second transistors T2 of the plurality of sub-pixels SP may be disposed on the left or right sides of the plurality of sub-pixels SP, respectively, and may be arranged in a line in the column direction. For example, the second transistors T2 of the first sub-pixels SP1a and SP1b, the second transistors T2 of the second sub-pixels SP2a and SP2b, and the second transistors T2 of the third sub-pixels SP3a and SP3b disposed at one side of the scan line SL may be disposed on the right side of each sub-pixel SP. The second transistors T2 of the first sub-pixels SP1a and SP1b, the second transistors T2 of the second sub-pixels SP2a and SP2b, and the second transistors T2 of the third sub-pixels SP3a and SP3b disposed at the other side of the scan line SL may be disposed on the left side of each sub-pixel SP.

[0121] For example, the scan line SL extending in the row direction may include a protruding portion protruding in the column direction in each of the plurality of pixel areas UPA. The portion of the scan line SL protruding in the column direction may be disposed adjacent to the left or right side of the plurality of sub-pixels SP and overlap the plurality of second transistors T2. For example, the protruding portion of the scan line SL protruding toward an area on one side may be disposed on the right side of the plurality of sub-pixels SP and serve as the second gate GE2 of the second transistors T2 of the plurality of sub-pixels SP. The protruding portion of the scan line SL protruding toward an area on the other side may be disposed at the left side of the plurality of sub-pixels SP and serve as the second gate GE2 of the second transistors T2 of the plurality of sub-pixels SP.

[0122] The second transistor T2 includes a second active layer ACT2, a second gate GE2, a second source SE2, and a second drain DE2.

[0123] The second active layer ACT2 is disposed between the buffer layer 111 and the gate insulating layer 112. The second active layer ACT2 may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, the present disclosure is not limited thereto.

[0124] In this case, the second active layers ACT2 of the adjacent plurality of sub-pixels SP may be connected to each other. For example, the second active layers ACT2 of the first sub-pixels SP1a and SP1b, the second active layers ACT2 of the second sub-pixels SP2a and SP2b, and the second active layers ACT2 of the third sub-pixels SP3a and SP3b, which are disposed at one side of the scan line SL, may extend in the column direction and be connected to each other and to one second drain electrode DE2 together. In addition, the second active layers ACT2 of the first sub-pixels SP1a and SP1b, the second active layers ACT2 of the second sub-pixels SP2a and SP2b, and the second active layers ACT2 of the third sub-pixels SP3a and SP3b, which are disposed at the other side of the scan line SL, may also extend in the column direction and be connected to each other and to one second drain electrode DE2 together.

[0125] That is, the connection portion of the channel region of the second active layer ACT2 for connecting the reference line RL and the plurality of sub-pixels SP is made of a transparent material of the second active layer ACT2 rather than an opaque conductive material, so that the transmittance can be increased at the outermost periphery of the pixel area UPA. In addition, the connection portion of the channel region of the second active layer ACT2 for connecting the reference line RL and the plurality of sub-pixels SP is made of the material of the second active layer ACT2, so that the contact hole can be eliminated and the structure of the pixel area UPA can be simplified.

[0126] In this case, the second active layer ACT2 may also be connected to the driving active layer DACT of the driving transistor DT. That is, the driving active layer DACT and the second active layer ACT2 may be integrated with each other, and the driving source electrode DSE and the second source electrode SE2 respectively connected to the driving active layer DACT and the second active layer ACT2 may be electrically connected to each other.

[0127] Next, the second gate GE2 is disposed between the gate insulating layer 112 and the first interlayer insulating layer 113a. The second gate GE2 may be electrically connected to the scan line SL. For example, the second gate GE2 may be integrated with and electrically connected to a protruding portion extending from the scan line SL in the column direction. The second gate GE2 may be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0128] The second source electrode SE2 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The second source electrode SE2 is electrically connected to the second active layer ACT2 through the contact holes of the first interlayer insulating layer 113a and the gate insulating layer 112. In addition, the second source electrode SE2 and the driving source electrode DSE may be electrically connected to each other. The second source electrode SE2 and the driving source electrode DSE may be disposed on the same layer, made of the same material, connected to each other and integrated with each other. That is, a conductive layer disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b and electrically connected to the driving active layer DACT and the second active layer ACT2 may be used as the second source electrode SE2 or the driving source electrode DSE. The second source electrode SE2 may be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof). However, the present disclosure is not limited thereto.

[0129] The second drain electrode DE2 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The second drain electrode DE2 is electrically connected to the second active layer ACT2 through the contact holes of the first interlayer insulating layer 113a and the gate insulating layer 112. In addition, the second drain electrode DE2 may be connected to the auxiliary reference line RLA through the contact holes formed in the first interlayer insulating layer 113a, the gate insulating layer 112, and the buffer layer 111. Therefore, the second drain electrode DE2 may be electrically connected to the reference line RL through the auxiliary reference line RLA. The second drain electrode DE2 may be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0130] In addition, a reference line RL is disposed on the first passivation layer 114a. The reference line RL may extend in the column direction and be disposed to cross the plurality of pixel areas UPA. In this case, the reference line RL may be disposed to be spaced apart from the second transistor T2 without overlapping the second transistor T2. For example, the reference line RL may be disposed between a data line DL connected to the first sub-pixels SP1a and SP1b and a data line DL connected to the second sub-pixels SP2a and SP2b. An auxiliary reference line RLA extending in the row direction may also be disposed to electrically connect the reference line RL and the second transistor T2.

[0131] The auxiliary reference line RLA is disposed between the substrate 110 and the buffer layer 111 in each of the plurality of pixel areas UPA. At least a portion of the auxiliary reference line RLA may be disposed to overlap with an area where the scan line SL is disposed. The auxiliary reference line RLA may intersect with the reference line RL, and the reference line RL and the auxiliary reference line RLA may be electrically connected to each other at the intersection. For example, the reference line RL may be electrically connected to the auxiliary reference line RLA through a contact hole formed in the first passivation layer 114a, the second interlayer insulating layer 113b, the first interlayer insulating layer 113a, the gate insulating layer 112, and the buffer layer 111. In addition, one end of the auxiliary reference line RLA may be connected to the second drain DE2 of the second transistor T2 disposed at one side of the scan line SL, and the other end of the auxiliary reference line RLA may be connected to the second drain DE2 of the second transistor T2 disposed at the other side of the scan line SL.

[0132] In this case, a plurality of second transistors T2 disposed at one side of the scan line SL may share one second drain electrode DE2, and a plurality of second transistors T2 disposed at the other side of the scan line SL may share one second drain electrode DE2. For example, the second active layers ACT2 of the plurality of second transistors T2 disposed at one side or the other side of the scan line SL may be connected to each other and integrated. The integrated second active layer ACT2 may be connected to one second drain electrode DE2. Therefore, the plurality of second transistors T2 may share one second drain electrode DE2 without separately including the second drain electrode DE2, so that the structure of the sub-pixel SP may be simplified, and a portion of the opaque conductive layer may be eliminated, which may improve the transmittance.

[0133] Next, a storage capacitor Cst is disposed on the substrate 110. The storage capacitor Cst is connected to the driving source electrode DSE and the driving gate electrode DGE of the driving transistor DT. The storage capacitor Cst can store charges and maintain a predetermined potential difference between the driving source electrode DSE and the driving gate electrode DGE of the driving transistor DT. Therefore, since the potential difference between the driving gate electrode DGE and the driving source electrode DSE is maintained, a predetermined driving current can be provided to the light emitting element 120 while the light emitting element 120 emits light.

[0134] The storage capacitor Cst includes a first capacitor electrode C1, a second capacitor electrode C2, and a third capacitor electrode C3. The first capacitor electrode C1 is disposed between the substrate 110 and the buffer layer 111. The first capacitor electrode C1 may be integrated with the light blocking layer LS. The second capacitor electrode C2 is disposed between the gate insulating layer 112 and the first interlayer insulating layer 113a, and overlaps with the first capacitor electrode C1. The second capacitor electrode C2 may be integrated with the driving gate DGE and electrically connected to the driving gate DGE. The third capacitor electrode C3 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b, and overlaps with the first capacitor electrode C1 and the second capacitor electrode C2. The third capacitor electrode C3 may be integrated with the driving source electrode DSE and electrically connected to the driving source electrode DSE. In addition, the third capacitor electrode C3 may be electrically connected to the first capacitor electrode C1 through a contact hole formed in the first interlayer insulating layer 113a, the gate insulating layer 112, and the buffer layer 111. The first capacitor electrode C1, the second capacitor electrode C2, and the third capacitor electrode C3 may be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto. Therefore, the storage capacitor Cst includes the first capacitor electrode C1 and the third capacitor electrode C3 connected to the driving source electrode DSE and the second capacitor electrode C2 connected to the driving gate electrode DGE, thereby maintaining a predetermined voltage difference between the driving gate electrode DGE and the driving source electrode DSE.

[0135] Next, an auxiliary electrode AE ​​is disposed on the first passivation layer 114a. The auxiliary electrode AE ​​is an electrode for electrically connecting the driving source electrode DSE and the first reflective electrode RE1. The driving source electrode DSE and the first reflective electrode RE1 may be electrically connected to each other through the auxiliary electrode AE. The auxiliary electrode AE ​​may be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0136] The low potential power line VSS is arranged on the second interlayer insulating layer 113b. The low potential power line VSS may be arranged in the column direction and overlap with a plurality of pixel areas UPA. The low potential power line VSS may be electrically connected to the driving drain electrode DDE through a contact hole formed in the first passivation layer 114a. The low potential power line VSS may be arranged to overlap with all the multiple lines (e.g., data lines DL and reference lines RL) extending in the column direction. The low potential power line VSS may have a relatively large width so that the low potential power line VSS may overlap with both the data lines DL and the reference lines RL. The low potential power line VSS may be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof). However, the present disclosure is not limited thereto.

[0137] In this case, the low potential power line VSS can be set between the data line DL and the region where at least the channel of the driving transistor DT is set among the components of the pixel circuit, and the voltage fluctuation of the driving transistor DT caused by the voltage change of the data line DL is minimized. First, in order to ensure the area of ​​the transmission area TA, a line such as the data line DL can be set to overlap with the pixel area UPA. However, in the case where the data line DL to which different voltages are applied according to the frame is set to overlap with the driving transistor DT, etc., the voltage change of the data line DL may affect the driving transistor DT, and the driving current may fluctuate. Therefore, the low potential power line VSS applied with a constant voltage is set to at least cover the driving gate DGE formed with the channel of the driving transistor DT, and the data line DL is set on the low potential power line VSS, which can suppress the voltage change of the data line DL from affecting the driving transistor DT. Therefore, the low potential power line VSS used as a blocking film can be set between the driving transistor DT and the data line DL, thereby minimizing the voltage fluctuation of the driving transistor DT.

[0138] In addition, since the low potential power line VSS covers most of the pixel area UPA, a plurality of opening portions may be formed in the low potential power line VSS to electrically connect the data line DL and the reference line RL disposed on the low potential power line VSS and other components disposed below the low potential power line VSS. For example, the plurality of opening portions of the low potential power line VSS may be disposed to correspond to the contact hole through which the first source electrode SE1 and the first active layer ACT1 are connected and the contact hole through which the driving drain electrode DDE and the driving active layer DACT are connected. For example, Figure 5A As shown, the driving drain electrode DDE may be connected to the driving active layer DACT in a region where an opening portion of the low potential power line VSS is provided.

[0139] Next, a reference line RL is disposed on the first passivation layer 114a. The reference line RL may be disposed in a column direction and overlapped with a plurality of pixel areas UPA. The reference line RL may be electrically connected to a plurality of second transistors T2 through an auxiliary reference line RLA. The reference line RL may be made of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof). However, the present disclosure is not limited thereto.

[0140] A plurality of data lines DL are disposed on the first passivation layer 114a. The plurality of data lines DL may extend in a column direction and overlap with a plurality of pixel areas UPA. The plurality of data lines DL may include a data line DL connected to a first transistor T1 of a plurality of first sub-pixels SP1a and SP1b, a data line DL connected to a first transistor T1 of a plurality of second sub-pixels SP2a and SP2b, and a data line DL connected to a first transistor T1 of a plurality of third sub-pixels SP3a and SP3b. For example, a data line DL connected to the first sub-pixels SP1a and SP1b, a reference line RL, a data line DL connected to the second sub-pixels SP2a and SP2b, and a data line DL connected to the third sub-pixels SP3a and SP3b may be sequentially disposed from the left side of the pixel area UPA.

[0141] Next, a second passivation layer 114b is disposed on the driving transistor DT, the first transistor T1, the second transistor T2, the storage capacitor Cst, the low potential power line VSS, the reference line RL, and the data line DL. The second passivation layer 114b may be an insulating layer for protecting components disposed below the second passivation layer 114b. The second passivation layer 114b may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0142] The first planarization layer 115a is disposed on the second passivation layer 114b. The first planarization layer 115a may planarize the upper portion of the substrate 110 provided with a plurality of transistors and the storage capacitor Cst. For example, the first planarization layer 115a may be configured as a single layer or multiple layers and made of a photoresist or acrylic-based organic material. However, the present disclosure is not limited thereto.

[0143] In addition, although not shown in the figure, an additional passivation layer may be disposed on the first planarization layer 115a. For example, a single-layer or multi-layer passivation layer configured as silicon oxide (SiOx) or silicon nitride (SiNx) may be disposed on the first planarization layer 115a and protect components disposed below the passivation layer.

[0144] Next, a plurality of first reflective electrodes RE1 are disposed on the first planarization layer 115a. The plurality of first reflective electrodes RE1 may be disposed in the plurality of sub-pixels SP, respectively, and electrically connect the driving transistor DT and the light emitting element 120. In addition, the plurality of first reflective electrodes RE1 may reflect light emitted from the light emitting element 120 to the outside of the display device 100. The plurality of first reflective electrodes RE1 may be electrically connected to the auxiliary electrode AE ​​through a first contact hole CH1 formed in one or more insulating layers (e.g., the first planarization layer 115a and the second passivation layer 114b). Therefore, the plurality of first reflective electrodes RE1 may be electrically connected to the driving source electrode DSE of the driving transistor DT through the auxiliary electrode AE. The plurality of first reflective electrodes RE1 may be made of an opaque conductive material having a high reflection efficiency, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. However, the present disclosure is not limited thereto.

[0145] In this case, the first contact hole CH1 through which the first reflective electrode RE1 and the auxiliary electrode AE ​​are connected does not overlap with the first connection electrode CE1 and the repair line WRL to be described below. The first contact hole CH1 through which the first reflective electrode RE1 is electrically connected to the driving transistor DT may be disposed to be spaced apart from the welding area WA. Figure 5A , in the B-type sub-pixel SPb, the first reflective electrode RE1 may include a portion overlapping the welding area WA, a portion connected to the first contact hole CH1, and a portion connected to the first connection electrode CE1. Figure 5B , in the A-type sub-pixel SPa, the first reflective electrode RE1 may include a portion connected to the first contact hole CH1 and a portion connected to the first connection electrode CE1.

[0146] The first contact hole CH1 is a portion to be destroyed by irradiation with a laser beam during the dark spot process. The first contact hole CH1 may be disposed so as not to overlap with the first connection electrode CE1 and the repair line WRL. The first contact hole CH1 may be disposed in an area where the first connection electrode CE1 and the repair line WRL are not disposed, which may suppress damage to the first connection electrode CE1 and the repair line WRL during the dark spot process.

[0147] For example, refer to Figure 5A , in the B-type subpixel SPb, the repair line WRL may be disposed to overlap only the welding area WA, and the repair line WRL may not overlap the first contact hole CH1 through which the first reflective electrode RE1 and the auxiliary electrode AE ​​are connected. In addition, the contact hole through which the first connection electrode CE1 and the first reflective electrode RE1 are connected and the first connection electrode CE1 may not overlap the first contact hole CH1.

[0148] For example, refer to Figure 5B, in the A-type sub-pixel SPa, the first connection electrode CE1 and the repair line WRL may not overlap with the first contact hole CH1. In this case, although Figure 5B Although not shown in the cross-sectional view of FIG. 1 , the repair line WRL and the first connection electrode CE1 may be connected to each other in a region where the first contact hole CH1 is not provided. Figure 3 and Figure 4 As shown in the top view.

[0149] Therefore, the region of the first contact hole CH1 to be irradiated with the laser beam is disposed in a region different from regions where the repair line WRL and the first connection electrode CE1 are disposed, so that the repair line WRL and the first connection electrode CE1 may be protected from being damaged by the laser beam.

[0150] Next, a second reflective electrode RE2 or a high potential power line VDD is disposed on the first planarization layer 115a. The second reflective electrode RE2 and the high potential power line VDD may be integrated and configured to provide a high potential power supply voltage to the light emitting element 120 and reflect the light emitted from the light emitting element 120 to the outside of the display device 100. The second reflective electrodes RE2 of a plurality of sub-pixels SP may be connected to each other and integrated with each other. The second reflective electrode RE2 and the high potential power line VDD may extend in the column direction and be arranged to overlap with the light emitting element 120. The second reflective electrode RE2 and the high potential power line VDD may be arranged to overlap with a plurality of data lines DL, a reference line RL, and a low potential power line VSS. The second reflective electrode RE2 and the high potential power line VDD may be made of an opaque conductive material with high reflection efficiency, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. However, the present disclosure is not limited thereto.

[0151] The third passivation layer 114c is disposed on the plurality of first reflective electrodes RE1 and the second reflective electrode RE2. The third passivation layer 114c may be an insulating layer for protecting components disposed under the third passivation layer 114c. The third passivation layer 114c may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0152] The bonding layer AD is disposed on the third passivation layer 114c. The bonding layer AD may be formed on the front surface of the substrate 110 and fix the light emitting element 120 disposed on the bonding layer AD. The bonding layer AD may be made of a photocurable bonding material that can be cured by light. For example, the bonding layer AD may be made of any one of a material selected from an adhesive polymer, an epoxy resin resist, a UV resin, a polyimide-based material, an acrylic-based material, a polyurethane-based material, and polydimethylsiloxane (PDMS). However, the present disclosure is not limited thereto.

[0153] A plurality of light emitting elements 120 are disposed on the bonding layer AD and in each of the plurality of sub-pixels SP. The light emitting element 120 may be an element configured to emit light by current, and include a red light emitting element 120R configured to emit red light, a green light emitting element 120G configured to emit green light, and a blue light emitting element 120B configured to emit blue light. The combination of the light emitting elements 120 may realize various colors including white. For example, the light emitting element 120 may be a light emitting diode (LED) or a micro LED. However, the present disclosure is not limited thereto.

[0154] The red light emitting element 120R may be disposed in the first sub-pixel SP1a and SP1b, the green light emitting element 120G may be disposed in the second sub-pixel SP2a and SP2b, and the blue light emitting element 120B may be disposed in the third sub-pixel SP3a and SP3b. A plurality of light emitting elements 120 disposed in one pixel area UPA may be disposed in a line in the column direction. In addition, the plurality of light emitting elements 120 may be disposed in the plurality of sub-pixels SP, respectively, and disposed to overlap with the second reflective electrode RE2.

[0155] Each of the plurality of light emitting elements 120 includes a first semiconductor layer 121 , a light emitting layer 122 , a second semiconductor layer 123 , a first electrode 124 , a second electrode 125 , and an encapsulation film 126 .

[0156] The first semiconductor layer 121 is disposed on the bonding layer AD, and the second semiconductor layer 123 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may each be a layer formed by doping a specific material with n-type and p-type impurities. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may each be a layer formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP) or gallium arsenide (GaAs) with n-type and p-type impurities. In addition, the p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc. The n-type impurity may be silicon (Si), germanium, tin (Sn), etc. However, the present disclosure is not limited thereto.

[0157] The light emitting layer 122 is disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The light emitting layer 122 may emit light by receiving positive holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123. The light emitting layer 122 may be configured as a single layer or a multi-quantum well (MQW) structure. For example, the light emitting layer 122 may be made of indium gallium nitride (InGaN), gallium nitride (GaN), etc. However, the present disclosure is not limited thereto.

[0158] The first electrode 124 is disposed on the first semiconductor layer 121. The first electrode 124 is an electrode electrically connecting the driving transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 may be a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on the top surface of the first semiconductor layer 121 exposed from the light emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be made of a conductive material (for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof). However, the present disclosure is not limited thereto.

[0159] The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on the top surface of the second semiconductor layer 123. The second electrode 125 is an electrode for electrically connecting the high potential power line VDD and the second semiconductor layer 123. In this case, the second semiconductor layer 123 may be a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be made of a conductive material (e.g., a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof). However, the present disclosure is not limited thereto.

[0160] Next, an encapsulation film 126 is provided in the form of surrounding the first semiconductor layer 121, the light emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation film 126 may be made of an insulating material and protect the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123. In addition, a contact hole exposing the first electrode 124 and the second electrode 125 may be formed in the encapsulation film 126 so that the first connection electrode CE1, the second connection electrode CE2, the first electrode 124, and the second electrode 125 may be electrically connected.

[0161] In addition, a portion of the side surface of the first semiconductor layer 121 may be exposed from the encapsulation film 126. The light emitting element 120 manufactured on the wafer may be separated from the wafer and transferred to the display panel PN. However, during the process of separating the light emitting element 120 from the wafer, a portion of the encapsulation film 126 may be torn. For example, during the process of separating the light emitting element 120 from the wafer, a portion of the encapsulation film 126 adjacent to the lower edge of the first semiconductor layer 121 of the light emitting element 120 may be torn, so that a portion of the lower side of the first semiconductor layer 121 may be exposed to the outside. Even if the lower portion of the light emitting element 120 is exposed from the encapsulation film 126, the first connection electrode CE1 and the second connection electrode CE2 are formed after forming the second planarization layer 115b and the third planarization layer 115c covering the side surface of the first semiconductor layer 121, thereby reducing short circuit defects.

[0162] Next, the second planarization layer 115 b and the third planarization layer 115 c are disposed on the bonding layer AD and the light emitting element 120 .

[0163] The second planarization layer 115b may partially overlap the side surfaces of the plurality of light emitting elements 120 and fix and protect the plurality of light emitting elements 120. The second planarization layer 115b may cover the torn portion of the encapsulation film 126 protecting the side surface of the first semiconductor layer 121 of the light emitting element 120. Therefore, the contact between the connection electrode and the first semiconductor layer 121 and the subsequent short circuit defect may be suppressed.

[0164] The third planarization layer 115c is formed to cover the upper side of the second planarization layer 115b and the light emitting element 120. A contact hole exposing the first electrode 124 and the second electrode 125 of the light emitting element 120 may be formed in the third planarization layer 115c. The first electrode 124 and the second electrode 125 of the light emitting element 120 may be exposed from the third planarization layer 115c. However, the third planarization layer 115c is partially disposed in the region between the first electrode 124 and the second electrode 125, thereby reducing short circuit defects. The second planarization layer 115b and the third planarization layer 115c may each be configured as a single layer or a multilayer, and, for example, made of a photoresist or an acrylic-based organic material. However, the present disclosure is not limited thereto.

[0165] A plurality of first and second link electrodes CE1 and CE2 are disposed on the third planarization layer 115c.

[0166] The plurality of first connection electrodes CE1 are electrodes configured to electrically connect the first electrodes 124 of the light emitting elements 120 in the plurality of sub-pixels SP and the driving transistor DT. The first connection electrode CE1 may be electrically connected to the first electrode 124 exposed from the third planarization layer 115c, and at the same time, electrically connected to the first reflective electrode RE1 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the third passivation layer 114c. Therefore, the first electrode 124 and the driving source electrode DSE may be electrically connected through the first connection electrode CE1, the first reflective electrode RE1, and the auxiliary electrode AE.

[0167] The second connection electrode CE2 is an electrode that electrically connects the high potential power line VDD and the second electrode 125 of the light emitting element 120. The second connection electrode CE2 may be electrically connected to the second electrode 125 exposed from the third planarization layer 115c, and may be electrically connected to the second reflective electrode RE2 or the high potential power line VDD through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, and the third passivation layer 114c. Therefore, the second electrode 125 and the high potential power line VDD may be electrically connected through the second connection electrode CE2.

[0168] The first and second connection electrodes CE1 and CE2 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, the present disclosure is not limited thereto.

[0169] In addition, the drawings illustrate that the driving source electrode DSE of the driving transistor DT is electrically connected to the first electrode 124 of the light emitting element 120. However, the driving drain electrode DDE of the driving transistor DT and the second electrode 125 of the light emitting element 120 may be electrically connected according to the type of the driving transistor DT and the design of the pixel circuit. However, the present disclosure is not limited thereto.

[0170] Next, a black matrix BM is disposed on the third planarization layer 115c, the first connection electrode CE1, and the second connection electrode CE2 in the pixel area UPA. The black matrix BM may be disposed to be spaced apart from the light emitting element 120 by a predetermined interval. The black matrix BM may be disposed on the boundary between the plurality of sub-pixels SP and partially cover the first connection electrode CE1 and the second connection electrode CE2. The black matrix BM may be disposed to be spaced apart from the transmission area TA. The black matrix BM may be made of an opaque material such as a black resin to reduce color mixing between the plurality of sub-pixels SP. However, the present disclosure is not limited thereto.

[0171] The protective layer 116 is disposed on the first connection electrode CE1, the second connection electrode CE2 and the black matrix BM. The protective layer 116 is a layer for protecting components disposed below the protective layer 116. The protective layer 116 may be configured as a single layer or multiple layers made of an organic material such as benzocyclobutene, a light-transmitting epoxy resin, a photoresist, an acrylic-based organic material, or an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx). However, the present disclosure is not limited thereto.

[0172] In addition, an illumination inspection process for detecting defective sub-pixels SP may be performed during the process of manufacturing the display device 100. For example, a defective sub-pixel SP that does not emit light may be detected by operating a plurality of light-emitting elements 120 in a state where a plurality of light-emitting elements 120, a first connection electrode CE1, and a second connection electrode CE2 are formed. For example, the defective sub-pixel SP may be caused by a defect in a pixel circuit, a transfer defect of the light-emitting element 120, or a foreign object. Therefore, in the display device 100 according to an embodiment of the present disclosure, a process of repairing the defective sub-pixel SP may be performed, thereby improving the quality of the display device 100.

[0173] For example, when a defect occurs on any one of the plurality of sub-pixels SP, the repair line WRL may be used to connect the light emitting element 120 of the defective sub-pixel SP to the pixel circuit of the normal sub-pixel SP, so that the light emitting element 120 of the defective sub-pixel SP can be operated by the pixel circuit of the normal sub-pixel SP. Therefore, a plurality of repair lines WRL for repair are provided in the display device 100.

[0174] Refer to Figures 3 to 5B , a plurality of repair lines WRL are disposed on the third planarization layer 115c. When a defective sub-pixel SP occurs, the plurality of repair lines WRL are lines for electrically connecting the light emitting element 120 of the defective sub-pixel SP to the driving transistor DT of a normal adjacent sub-pixel SP. The light emitting element 120 of the defective sub-pixel SP can be operated by being connected to the driving transistor DT of a normal sub-pixel SP via the repair line WRL. Therefore, even if a defect occurs on the circuit of the sub-pixel SP, the light emitting element 120 can be operated by connecting the light emitting element 120 to the circuit of another sub-pixel SP using the repair line WRL, thereby eliminating the dark spot defect.

[0175] A plurality of repair lines WRL may be disposed between sub-pixels SP of the same type. For example, the repair line WRL may be disposed between a pair of first sub-pixels SP1a and SP1b, between a pair of second sub-pixels SP2a and SP2b, and between a pair of third sub-pixels SP3a and SP3b. A plurality of repair lines WRL may be disposed between a first A-type sub-pixel SP1a and a first B-type sub-pixel SP1b, between a second A-type sub-pixel SP2a and a second B-type sub-pixel SP2b, and between a third A-type sub-pixel SP3a and a third B-type sub-pixel SP3b.

[0176] The repair line WRL may be connected to the first connection electrode CE1 of one of the pair of sub-pixels SP and disposed to be spaced apart from the first connection electrode CE1 of the other of the pair of sub-pixels SP. That is, the repair line WRL may be disposed between the first A-type sub-pixel SP1a and the first B-type sub-pixel SP1b and directly connected to the first connection electrode CE1 of the first A-type sub-pixel SP1a. The repair line WRL may be disposed between the second A-type sub-pixel SP2a and the second B-type sub-pixel SP2b and directly connected to the first connection electrode CE1 of the second A-type sub-pixel SP2a. The repair line WRL may be disposed between the third A-type sub-pixel SP3a and the third B-type sub-pixel SP3b and directly connected to the first connection electrode CE1 of the third A-type sub-pixel SP3a. In addition, the repair line WRL may be disposed to be spaced apart from the first connection electrode CE1 of each of the first B-type sub-pixel SP1b, the second B-type sub-pixel SP2b, and the third B-type sub-pixel SP3b.

[0177] The repair line WRL may be disposed between the A-type sub-pixel SPa and the B-type sub-pixel SPb disposed in different pixel areas UPA. The repair line WRL may extend from the A-type sub-pixel SPa toward the B-type sub-pixel SPb disposed in the pixel area UPA of the adjacent column within the shortest straight-line distance. The repair line WRL may extend within the shortest straight-line distance toward the B-type sub-pixel SPb disposed closest to the A-type sub-pixel SPa, and the repair line WRL may be disposed to cross the transmission area TA. Since the repair line WRL is made of a transparent conductive material like the first connection electrode CE1, even if the repair line WRL is disposed to cross the transmission area TA, the reduction in transmittance may be minimized.

[0178] For example, some of the plurality of repair lines WRL may each be disposed between the A-type sub-pixel SPa of the pixel area UPA of the nth column and the B-type sub-pixel SPb of the pixel area UPA of the (n+1)th column. Some of the remaining repair lines WRL may each be disposed between the A-type sub-pixel SPa of the pixel area UPA of the nth column and the B-type sub-pixel SPb of the pixel area UPA of the (n-1)th column. For example, the repair line WRL may be disposed between the first sub-pixels SP1a and SP1b of the (n+1)th column and one of a pair of first sub-pixels SP1a and SP1b disposed in the pixel area UPA of the nth column. In addition, the repair line WRL may be disposed between the first sub-pixels SP1a and SP1b of the (n-1)th column and the other of a pair of first sub-pixels SP1a and SP1b disposed in the pixel area UPA of the nth column. Therefore, during the repair process, a pair of sub-pixels SP included in one pixel area UPA may be respectively connected to sub-pixels SP in different pixel areas UPA.

[0179] Next, the A-type subpixel Spa can be connected to the repair line WRL, and the B-type subpixel SPb can be arranged adjacent to the repair line WRL and separated from the repair line WRL without being connected to the repair line WRL. The first connection electrode CE1 arranged in the A-type subpixel SPa can be integrated with and electrically connected to the repair line WRL. The first connection electrode CE1 arranged in the B-type subpixel SPb can be arranged to be spaced apart from the repair line WRL. Therefore, one end of each of the multiple repair lines WRL can be connected to the first connection electrode CE1 of the A-type subpixel SPa, and the other end of the repair line WRL can be arranged to be spaced apart from the first connection electrode CE1 of the B-type subpixel SPb.

[0180] In addition, in the B-type sub-pixel SPb, the repair line WRL may be disposed in the welding area WA. In the welding area WA, the first reflective electrode RE1 of the B-type sub-pixel SPb and the repair line WRL may be disposed overlapping each other. The first reflective electrode RE1 of the B-type sub-pixel SPb and the repair line WRL are disposed in the welding area WA and overlap. In the welding area WA that has not undergone the welding process, the repair line WRL and the first reflective electrode RE1 may be disposed to be spaced apart from each other, and wherein the third planarization layer 115c, the second planarization layer 115b, the bonding layer AD, and the third passivation layer 114c are interposed therebetween. In contrast, in the welding area WA that has undergone the welding process, the repair line WRL and the first reflective electrode RE1 may be connected to each other because the third planarization layer 115c, the second planarization layer 115b, the bonding layer AD, and the third passivation layer 114c are partially removed.

[0181] Hereinafter, it will be described assuming that a defect occurs on the A-type sub-pixel Spa, a dark spot process is performed on the A-type sub-pixel SPa, and a repair line WRL is connected to the B-type sub-pixel SPb to repair the A-type sub-pixel SP.

[0182] First, refer to Figure 5A , when a defect occurs on any one of the plurality of sub-pixels SP, a dark spot process may be performed to separate the pixel circuit of the defective sub-pixel SP from the light-emitting element 120. If the pixel circuit of the defective sub-pixel SP is not electrically separated from the light-emitting element 120, a bright spot defect or the like may occur due to abnormal operation of the light-emitting elements 120 of some of the defective sub-pixels SP. For example, the light-emitting element 120 of the defective sub-pixel SP continues to emit light regardless of the image, which may result in a defect of recognizing a bright spot. Therefore, the pixel circuit of the defective sub-pixel SP and the light-emitting element 120 may be separated so that a driving current is not provided to the light-emitting element 120 from the pixel circuit of the defective sub-pixel SP.

[0183] For example, the driving current transmission route between the light emitting element 120 and the pixel circuit of the defective sub-pixel SP may be eliminated by destroying the connection portion between the light emitting element 120 and the driving source electrode DSE of the driving transistor DT. For example, the light emitting element 120 and the driving transistor DT may be electrically connected to each other through the first reflective electrode RE1 and the first connection electrode CE1. In addition, the connection portion between the pixel circuit and the light emitting element 120 may be destroyed by irradiating the connection portion between the first reflective electrode RE1 and the driving transistor DT with a laser beam. For example, the portion where the first reflective electrode RE1 and the driving transistor DT are electrically connected may be destroyed by irradiating the first contact hole CH1 through which the first reflective electrode RE1 and the auxiliary electrode AE ​​are connected with a laser beam.

[0184] For example, refer to Figure 5B In the case where a defect occurs on the circuit of the A-type sub-pixel SPa, the first contact hole CH1 of the A-type sub-pixel SPa may be destroyed by irradiating the first contact hole CH1 of the A-type sub-pixel SPa with a laser beam.

[0185] As described above, the first reflective electrode RE1 may include a portion overlapping the first connection electrode CE1 and a portion not overlapping the first connection electrode CE1. The first reflective electrode RE1 and the driving transistor DT may be electrically connected through a first contact hole CH1 formed corresponding to the portion not overlapping the first connection electrode CE1. The first reflective electrode RE1 is electrically connected to the auxiliary electrode AE ​​through the first contact hole CH1, and the auxiliary electrode AE ​​is electrically connected to the driving source electrode DSE of the driving transistor DT through the contact hole of the first passivation layer 114a and the second interlayer insulating layer 113b. The first contact hole CH1 connecting the first reflective electrode RE1 and the auxiliary electrode AE ​​may overlap the first reflective electrode RE1 without overlapping the first connection electrode CE1.

[0186] In addition, the first contact hole CH1 may be irradiated with a laser beam, so that a connection portion of the first contact hole CH1 connecting the first reflective electrode RE1 and the auxiliary electrode AE ​​may be destroyed. Therefore, when the first reflective electrode RE1 and the auxiliary electrode AE ​​are electrically separated due to the destruction of the first contact hole CH1, the first reflective electrode RE1 and the driving transistor DT may also be electrically separated. Therefore, since the portion electrically connected to the first reflective electrode RE1 and the driving source electrode DSE is damaged, the driving transistor DT and the light emitting element 120 may be separated, and a bright spot defect may be suppressed.

[0187] The dark spot process can be performed by irradiating the first contact hole CH1 that does not overlap with the first connection electrode CE1 with a laser beam, which can suppress damage to the first connection electrode CE1. In particular, in the case where a defect occurs on the pixel circuit of the A-type sub-pixel SPa and the dark spot process is performed on the A-type sub-pixel SPa by irradiating the first connection electrode CE1 with a laser beam, the first connection electrode CE1 and the repair line WRL can be separated. Therefore, the light emitting element 120 of the A-type sub-pixel SPa cannot be electrically connected to the driving transistor DT of the B-type sub-pixel SPb afterwards, and the A-type sub-pixel Spa cannot be repaired. Therefore, the first contact hole CH1 to be subjected to the dark spot process is formed so as not to overlap with the first connection electrode CE1, which can minimize damage to the first connection electrode CE1 and the repair line WRL.

[0188] Next, refer to Figure 6 , the repair line WRL and the driving transistor DT of the B-type sub-pixel SPb may be electrically connected by irradiating the repair line WRL extending from the A-type sub-pixel SPa that has undergone the dark spot process with a laser beam.

[0189] First, the end portion of the repair line WRL extending from the A-type sub-pixel SPa may be disposed in the welding area WA of the B-type sub-pixel SPb in the adjacent pixel area UPA. Figure 5B , before the repair process is performed, the repair line WRL in the welding area WA of the B-type subpixel SPb is disposed to overlap with the first reflective electrode RE1 and to be spaced apart from the first reflective electrode RE1. That is, before the repair process is performed, the repair line WRL and the first reflective electrode RE1 may be disposed to be spaced apart from each other, and the third planarization layer 115c, the second planarization layer 115b, the bonding layer AD, and the third passivation layer 114c are interposed between the repair line WRL and the first reflective electrode RE1.

[0190] In addition, refer to Figure 6, a welding process of connecting the repair line WRL and the first reflective electrode RE1 by irradiating the welding area WA with a laser beam may be performed. In the case where the welding area WA is irradiated with laser, the third planarization layer 115c, the second planarization layer 115b, the bonding layer AD, and the third passivation layer 114c corresponding to the welding area WA may be destroyed so that the repair line WRL and the first reflective electrode RE1 may be connected to each other. The insulating layer between the repair line WRL and the first reflective electrode RE1 may be destroyed into an atypical shape so that the first reflective electrode RE1 and the repair line WRL may be electrically connected to each other.

[0191] Therefore, the first connection electrode CE1 of the B-type sub-pixel SPb may be electrically connected to the repair line WRL through the first reflective electrode RE1. That is, the first connection electrode CE1 may be indirectly connected to the repair line WRL through the first reflective electrode RE1.

[0192] Therefore, the driving transistor DT of the B-type subpixel SPb can be electrically connected to the first connection electrode CE1 of the light emitting element 120 of the A-type subpixel SPa through the auxiliary electrode AE, the first reflective electrode RE1 and the repair line WRL. The driving transistor DT of the B-type subpixel SPb can be electrically connected to both the first connection electrode CE1 of the A-type subpixel SPa and the first connection electrode CE1 of the B-type subpixel SPb. Therefore, the light emitting element 120 of the A-type subpixel SPa and the light emitting element 120 of the B-type subpixel SPb can be connected in parallel with the driving transistor DT of the B-type subpixel SPb and operate together.

[0193] Therefore, in the display device 100 according to the embodiment of the present disclosure, the A-type sub-pixel SPa and the B-type sub-pixel SPb can be alternately arranged in the same row, so that a plurality of repair lines WRL can be formed as a straight line extending within the shortest distance. The repair line WRL connecting the A-type sub-pixel SPa and the B-type sub-pixel SPb can extend straight in the row direction. The A-type sub-pixel SPa and the B-type sub-pixel SPb can be arranged on the same line, so that the repair line WRL can extend straight in the shortest straight distance. In addition, a pair of light-emitting elements 120 with the repair line WRL interposed therebetween can be arranged to be vertically symmetrical, so that a plurality of repair lines WRL can be formed within the shortest straight length. The repair line WRL can normally provide a driving current to the light-emitting element 120 of the defective sub-pixel SP by electrically connecting the first electrode 124 of the light-emitting element 120. In this case, a pair of light-emitting elements 120 are arranged to be vertically symmetrical, so that the two light-emitting elements 120 can be arranged in a manner that the first electrodes 124 face each other. Therefore, the distance between the first electrodes 124 of the pair of light emitting elements 120 can be minimized, and the repair line WRL can be formed in the shortest straight line length. Therefore, the structure of the repair line WRL can be simplified, the length of the repair line WRL can be reduced, and the resistance of the repair line WRL can be increased. The reduction in the length of the repair line WRL can reduce the line resistance and reduce power consumption, so that the display device 100 can operate with low power consumption.

[0194] In the display device 100 according to an embodiment of the present disclosure, all of the plurality of repair lines WRL may be formed in parallel so that the plurality of repair lines WRL may not interfere with other repair lines WRL. The plurality of repair lines WRL may each be connected to the A-type sub-pixel SPa and the B-type sub-pixel SPb that are arranged in the same row and adjacent to each other. The plurality of repair lines WRL may extend straight in the row direction and be arranged parallel to each other. Therefore, the interference between the repair lines WRL that occurs when the repair line WRL connected to the sub-pixel SP in a particular row extends toward the sub-pixel SP in another row may be suppressed. In addition, since the interference between the plurality of repair lines WRL is suppressed, the plurality of repair lines WRL do not need to be formed as a plurality of conductive layers, and the plurality of repair lines WRL may be formed as a single-layer structure made of a transparent conductive material. Therefore, the structure of the plurality of repair lines WRL may be simplified. In addition, the plurality of repair lines WRL may be formed as a single layer made of a transparent conductive material, which may minimize the reduction in transmittance caused by the plurality of repair lines WRL.

[0195] In the display device 100 according to an embodiment of the present disclosure, a plurality of red light emitting elements 120R, a plurality of green light emitting elements 120G, and a plurality of blue light emitting elements 120B may be arranged at uniform intervals, which may improve image quality. Since a plurality of repair lines WRL are arranged in a straight line in the row direction, a plurality of red light emitting elements 120R may be arranged in the same row, a plurality of green light emitting elements 120G may be arranged in the same row, and a plurality of blue light emitting elements 120B may be arranged in the same row. For example, the red light emitting element 120R may be arranged only in the nth row, the green light emitting element 120G may be arranged only in the (n+1)th row, and the blue light emitting element 120B may be arranged only in the (n+2)th row. In this case, the design of the repair line WRL is not limited thereto. The arrangement order of the plurality of red light emitting elements 120R, the plurality of green light emitting elements 120G, and the plurality of blue light emitting elements 120B in the column direction may be freely configured. For example, since the repair line WRL connecting the plurality of red light emitting elements 120R, the plurality of green light emitting elements 120G, and the plurality of blue light emitting elements 120B only connects the light emitting elements 120 disposed in the same row, the repair line WRL can be formed regardless of the arrangement order of the red light emitting elements 120R, the green light emitting elements 120G, and the blue light emitting elements 120B in the column direction. If the repair line WRL is configured to connect the light emitting elements 120 disposed in different rows, the arrangement order of the red light emitting elements 120R, the green light emitting elements 120G, and the blue light emitting elements 120B can be limited in consideration of the interference between the repair lines WRL connecting the light emitting elements 120. Therefore, according to the repair line WRL, the arrangement order of the red light emitting elements 120R, the green light emitting elements 120G, and the blue light emitting elements 120B is not limited to a specific order. Therefore, multiple red light-emitting elements 120R, multiple green light-emitting elements 120G and multiple blue light-emitting elements 120B can be arranged sequentially and alternately in the column direction, so that the spacing between the red light-emitting elements 120R, the spacing between the green light-emitting elements 120G and the spacing between the blue light-emitting elements 120B can be uniformly achieved.

[0196] Example implementations of the present disclosure may also be described as follows:

[0197] According to one aspect of the present disclosure, a display device includes: a substrate, which is configured to define a plurality of pixel areas spaced apart from each other and a plurality of transmission areas arranged between the plurality of pixel areas; a plurality of pixels, the plurality of pixels are arranged in the plurality of pixel areas and each includes a plurality of sub-pixels; light-emitting elements, the light-emitting elements are respectively arranged in the plurality of sub-pixels and each includes a first electrode; and a repair line, which is arranged between a pair of adjacent sub-pixels among the plurality of sub-pixels, and the light-emitting elements of the pair of sub-pixels are arranged so that the first electrode is guided toward the repair line.

[0198] The display device may further include a first connecting electrode, which is respectively arranged in a plurality of sub-pixels and is respectively electrically connected to the first electrode of the light-emitting element. The plurality of sub-pixels may include: A-type sub-pixels, in which the repair line is connected to the first connecting electrode; and B-type sub-pixels, in which the repair line and the first connecting electrode are spaced apart from each other.

[0199] A pair of sub-pixels disposed with a repair line interposed therebetween may be configured as an A-type sub-pixel and a B-type sub-pixel, and the light emitting elements of the A-type sub-pixel and the light emitting elements of the B-type sub-pixel may be disposed symmetrically with respect to the repair line.

[0200] The A-type sub-pixels and the B-type sub-pixels may be alternately arranged in the same row.

[0201] A repair line may be disposed between the A-type sub-pixels and the B-type sub-pixels that are in the same row and adjacent to each other.

[0202] A plurality of transmission regions may be formed between the A-type sub-pixel and the B-type sub-pixel, a repair line may be disposed to cross the plurality of transmission regions, and the repair line may be made of a transparent conductive material.

[0203] The plurality of pixels may each include both one or more A-type sub-pixels and one or more B-type sub-pixels.

[0204] The display device may also include a scan line extending in a row direction and arranged to cross multiple pixel areas, in some of the multiple pixel areas, type A sub-pixels may be arranged in an area at one side of the scan line, and type B sub-pixels may be arranged in an area at the other side of the scan line.

[0205] In the remaining pixel regions among the multiple pixel regions, type B sub-pixels can be set in the region at one side of the scan line, and type A sub-pixels can be set in the region at the other side of the scan line, and some of the pixel regions and the remaining pixel regions can be set in different columns.

[0206] The display device may further include: a driving transistor disposed on the substrate and disposed in each of the plurality of sub-pixels; one or more insulating layers disposed on the driving transistor; a first reflective electrode disposed between the one or more insulating layers and the light emitting element and electrically connected to the driving transistor through a first contact hole of the one or more insulating layers; and a planarization layer disposed on the first reflective electrode and configured to cover the light emitting element, and a first connection electrode may be disposed on the planarization layer and the light emitting element and electrically connected to the first electrode and the first reflective electrode.

[0207] The repair line may be disposed on the same layer as the first connection electrode, the repair line in the A-type subpixel may be integrated with the first connection electrode, and the repair line in the B-type subpixel may be spaced apart from the first connection electrode and may overlap a portion of the first reflective electrode.

[0208] The first reflective electrode and the repair line may be connected to each other in some of the B-type sub-pixels among the plurality of sub-pixels, and the first reflective electrode and the repair line may be spaced apart from each other in some of the remaining B-type sub-pixels among the plurality of sub-pixels with a planarization layer interposed therebetween.

[0209] The first electrodes of the light emitting elements in some of the B-type sub-pixels may be electrically connected to the first connection electrodes, the first reflective electrodes, and the driving transistors in the A-type sub-pixels of adjacent columns through the first connection electrodes, the first reflective electrodes, and the repair lines.

[0210] In the A-type sub-pixel and the B-type sub-pixel, the repair line may not overlap the first contact hole.

[0211] The display device may further include a plurality of data lines extending in a column direction on the substrate, and the plurality of pixel regions may overlap with a region where the plurality of data lines are disposed.

[0212] Although the example embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the example embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-mentioned example embodiments are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be understood to fall within the scope of the present disclosure.

[0213] The various embodiments described above can be combined to provide further embodiments. If necessary, aspects of the embodiments can be modified to employ the concepts of the various embodiments to provide additional embodiments.

[0214] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents granted by these claims. Therefore, the claims are not limited by this disclosure.

[0215] CROSS-REFERENCE TO RELATED APPLICATIONS

[0216] This application claims the priority of Korean Patent Application No. 10-2023-0121472 filed on September 13, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

Claims

1. A display device, comprising: a substrate including a plurality of pixel regions spaced apart from each other and a plurality of transmission regions disposed between the plurality of pixel regions; a plurality of pixels, the plurality of pixels being arranged in the plurality of pixel regions and each including a plurality of sub-pixels; light-emitting elements, each of which is disposed in the plurality of sub-pixels and includes a first electrode; and a repair line, wherein the repair line is arranged between a pair of adjacent sub-pixels among the plurality of sub-pixels, The light emitting elements of the pair of sub-pixels are arranged so that the first electrode is guided toward the repair line.

2. The display device according to claim 1, further comprising: first connecting electrodes, which are respectively arranged in the plurality of sub-pixels and are respectively electrically connected to the first electrode of the light-emitting element, Wherein, the plurality of sub-pixels include: A-type sub-pixel, in which the repair line is connected to the first connection electrode; A B-type sub-pixel in which the repair line and the first connection electrode are spaced apart from each other.

3. The display device according to claim 2, wherein: The pair of sub-pixels arranged such that the repair line is interposed between the pair of sub-pixels include an A-type sub-pixel and a B-type sub-pixel, and The light-emitting element of the A-type sub-pixel and the light-emitting element of the B-type sub-pixel are symmetrically arranged relative to the repair line.

4. The display device according to claim 2, wherein: The A-type sub-pixels and the B-type sub-pixels are alternately arranged in the same row.

5. The display device according to claim 4, wherein: The repair line is disposed between the A-type sub-pixel and the B-type sub-pixel that are disposed in the same row and adjacent to each other.

6. The display device according to claim 5, wherein: The plurality of transmission areas are each formed between the A-type sub-pixel and the B-type sub-pixel, the repair line crosses one or more of the plurality of transmission areas, and the repair line is made of a transparent conductive material.

7. The display device according to claim 2, wherein: Each of the plurality of pixels includes one or more A-type sub-pixels and one or more B-type sub-pixels.

8. The display device according to claim 7, further comprising: a scan line extending in a row direction and crossing one or more pixel regions among the plurality of pixel regions, Among them, in a first pixel region among the plurality of pixel regions, the A-type sub-pixel is disposed in a region on a first side of the scan line, and the B-type sub-pixel is disposed in a region on a second side of the scan line.

9. The display device according to claim 8, wherein: In a second pixel region among the plurality of pixel regions, a B-type sub-pixel is disposed in a region on the first side of the scan line, and an A-type sub-pixel is disposed in a region on the second side of the scan line, and The first pixel region and the second pixel region are arranged in different columns.

10. The display device according to claim 2, further comprising: a driving transistor disposed on the substrate and disposed in each of the sub-pixels; one or more insulating layers, the one or more insulating layers being disposed on the driving transistor; a first reflective electrode, the first reflective electrode being disposed between the one or more insulating layers and the light emitting element and being electrically connected to the driving transistor through a first contact hole of the one or more insulating layers; a planarization layer, the planarization layer being disposed on the first reflective electrode and covering the light emitting element, The first connecting electrode is disposed on the planarization layer and the light emitting element and is electrically connected to the first electrode and the first reflective electrode.

11. The display device according to claim 10, wherein: The repair line is disposed on the same layer as the first connection electrode, the repair line in the A-type sub-pixel is integrated with the first connection electrode, and the repair line in the B-type sub-pixel is spaced apart from the first connection electrode and overlaps a portion of the first reflective electrode.

12. The display device according to claim 11, wherein: The first reflective electrode and the repair line are connected to each other in a first B-type sub-pixel among the B-type sub-pixels among the plurality of sub-pixels, and Wherein, in a second B-type sub-pixel among the B-type sub-pixels among the plurality of sub-pixels, the first reflective electrode and the repair line are spaced apart from each other, and the planarization layer is interposed between the first reflective electrode and the repair line.

13. The display device according to claim 12, wherein: The first electrode of the light emitting element in the B-type sub-pixel is electrically connected to the first connection electrode, the first reflection electrode and the driving transistor in the A-type sub-pixel of the adjacent column through the first connection electrode, the first reflection electrode and the repair line.

14. The display device according to claim 10, wherein: In the A-type sub-pixel and the B-type sub-pixel, the repair line does not overlap with the first contact hole.

15. The display device according to claim 1, further comprising: A plurality of data lines extending in a column direction on the substrate, The plurality of pixel regions overlap with a region where the plurality of data lines are disposed.

16. A display device, comprising: a substrate including a plurality of pixel regions spaced apart from each other and a plurality of transmission regions disposed between the plurality of pixel regions; a plurality of pixels, the plurality of pixels being arranged in the plurality of pixel regions and each including a plurality of sub-pixels, the pixel regions of the plurality of pixel regions including a first sub-pixel and a second sub-pixel, the first sub-pixel and the second sub-pixel being configured to emit light of the same color, each of the first sub-pixel and the second sub-pixel including a first electrode; and A repair line is disposed adjacent to the pixel region, the first electrode of the first sub-pixel is connected to the repair line, and the first electrode of the second sub-pixel is not connected to the repair line.

17. The display device according to claim 16, wherein: The repair line extends in the transmissive region.

18. The display device of claim 16, comprising a scan line crossing the pixel area, the first sub-pixel being located at a first side of the scan line, and the second sub-pixel being located at a second side of the scan line opposite to the first side.

19. The display device according to claim 16, wherein: The repair line is connected to the first electrode of the first sub-pixel via a connection electrode located on the same layer as the repair line.

20. A structure comprising: a first semiconductor layer; a first electrode, the first electrode being located on the first semiconductor layer; a light-emitting layer, the light-emitting layer being located on the first semiconductor layer and on a side of the first electrode; a second semiconductor layer, wherein the second semiconductor layer is located on the light emitting layer and the second semiconductor layer is not located on the first electrode; a second electrode, the second electrode being located on the second semiconductor layer; a first connecting electrode, the first connecting electrode being in contact with the first electrode; as well as A second connecting electrode, the second connecting electrode is in contact with the second electrode, and the second connecting electrode is isolated from the first connecting electrode.

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